diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/stm32l471xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/stm32l471xx.h index bdb2d527de..fdd8cb3364 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/stm32l471xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/stm32l471xx.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file stm32l475xx.h + * @file stm32l471xx.h * @author MCD Application Team - * @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File. + * @brief CMSIS STM32L471xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -43,12 +27,12 @@ * @{ */ -/** @addtogroup stm32l475xx +/** @addtogroup stm32l471xx * @{ */ -#ifndef __STM32L475xx_H -#define __STM32L475xx_H +#ifndef __STM32L471xx_H +#define __STM32L471xx_H #ifdef __cplusplus extern "C" { @@ -93,7 +77,7 @@ typedef enum SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ @@ -159,7 +143,6 @@ typedef enum COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ @@ -786,7 +769,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -1001,124 +983,6 @@ typedef struct __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; -/** - * @brief USB_OTG_Core_register - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} USB_OTG_DeviceTypeDef; - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} USB_OTG_HostChannelTypeDef; - /** * @} */ @@ -1126,183 +990,166 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */ +#define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) - -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) - -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) - -/*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) - -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) +#define DBGMCU_BASE (0xE0042000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1328,7 +1175,7 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC1_BASE) @@ -1438,7 +1285,6 @@ typedef struct #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) /** * @} */ @@ -1468,72 +1314,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1551,1064 +1397,1064 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ #define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -2618,3475 +2464,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - #define STM32L471xx /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V1.3.1 - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/system_stm32l4xx.h deleted file mode 100755 index b2b77363ae..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/system_stm32l4xx.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/system_clock.c index ee5ac4b40c..a0d42da302 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings @@ -337,10 +295,7 @@ uint8_t SetSysClock_PLL_MSI(void) } /* Enable MSI Auto-calibration through LSE */ HAL_RCCEx_EnableMSIPLLMode(); - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c index c47c24bb84..94946fb792 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c @@ -44,7 +44,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -75,47 +74,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S index a2f127a539..5b19f2c256 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l432xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 ;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S index a2f127a539..5b19f2c256 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l432xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 ;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S index c272e19398..694383516e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32l432xx.s * @author MCD Application Team - * @version V1.1.1 - * @date 29-April-2016 * @brief STM32L432xx devices vector table for GCC toolchain. * This module performs: * - Set the initial SP @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -59,6 +41,11 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first @@ -91,6 +78,17 @@ LoopCopyDataInit: adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S index a3dd09c0dc..7fb52e69b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/startup_stm32l432xx.S @@ -1,8 +1,6 @@ -;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;/********************* COPYRIGHT(c) 2017 STMicroelectronics ******************** ;* File Name : startup_stm32l432xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 ;* Description : STM32L432xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h index 147f6a015a..9d99011285 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -93,7 +77,7 @@ typedef enum SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM3/PVM4 through EXTI Line detection Interrupts */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ @@ -707,7 +691,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -929,122 +912,122 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */ +#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */ -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1063,7 +1046,7 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) @@ -1161,72 +1144,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1244,926 +1227,926 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ @@ -2174,3475 +2157,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ -#define STM32L432xx /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h deleted file mode 100644 index 4954d5c579..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c index c47c24bb84..94946fb792 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c @@ -44,7 +44,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -75,47 +74,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S index e8397decd9..2db9285b9c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S @@ -1,9 +1,7 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** -;* File Name : startup_stm32l432xx.s +;******************************************************************************* +;* File Name : startup_stm32l433xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 -;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* Description : STM32L433xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S index e8397decd9..2db9285b9c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S @@ -1,9 +1,7 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** -;* File Name : startup_stm32l432xx.s +;******************************************************************************* +;* File Name : startup_stm32l433xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 -;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* Description : STM32L433xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S index df1beb6f77..174425974c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S @@ -1,10 +1,8 @@ /** ****************************************************************************** - * @file startup_stm32l432xx.s + * @file startup_stm32l433xx.s * @author MCD Application Team - * @version V1.1.1 - * @date 29-April-2016 - * @brief STM32L432xx devices vector table for GCC toolchain. + * @brief STM32L433xx devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -59,6 +41,11 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first @@ -91,6 +78,17 @@ LoopCopyDataInit: adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S index 8688b7e8a7..65bac5a9f7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S @@ -1,9 +1,7 @@ -;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l432xx.s +;******************************************************************************** +;* File Name : startup_stm32l433xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 -;* Description : STM32L432xx Ultra Low Power Devices vector +;* Description : STM32L433xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, @@ -15,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h index 0340da1510..4f6278fe7d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -93,7 +77,7 @@ typedef enum SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ @@ -727,7 +711,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -987,130 +970,130 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */ +#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */ -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1133,7 +1116,7 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) @@ -1235,72 +1218,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1318,926 +1301,926 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ @@ -2248,3475 +2231,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ -#define STM32L433xx /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h deleted file mode 100644 index 4954d5c579..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c index c47c24bb84..94946fb792 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c @@ -44,7 +44,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -75,47 +74,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/startup_stm32l443xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/startup_stm32l443xx.S index 2095fb2b03..52562fdc6d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/startup_stm32l443xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_ARM_STD/startup_stm32l443xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l443xx.s ;* Author : MCD Application Team -;* Version : V1.2.0 -;* Date : 28-October-2016 ;* Description : STM32L443xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l443xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l443xx.S index 76120d3911..9e684a529e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l443xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l443xx.S @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32l443xx.s * @author MCD Application Team - * @version V1.2.0 - * @date 28-October-2016 * @brief STM32L443xx devices vector table for GCC toolchain. * This module performs: * - Set the initial SP @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -59,6 +41,11 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first @@ -91,6 +78,17 @@ LoopCopyDataInit: adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit @@ -105,6 +103,9 @@ LoopCopyDataInit: bl _start bx lr +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_IAR/startup_stm32l443xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_IAR/startup_stm32l443xx.S index 68881da03b..f44b2ab3ef 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_IAR/startup_stm32l443xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/TOOLCHAIN_IAR/startup_stm32l443xx.S @@ -1,8 +1,6 @@ -;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;******************************************************************************** ;* File Name : startup_stm32l443xx.s ;* Author : MCD Application Team -;* Version : V1.2.0 -;* Date : 28-October-2016 ;* Description : STM32L443xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/stm32l443xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/stm32l443xx.h index 1d6c82e52e..6a18d62e38 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/stm32l443xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/stm32l443xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -93,7 +77,7 @@ typedef enum SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ @@ -728,7 +712,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -789,12 +772,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; @@ -1022,131 +1003,131 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */ +#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */ -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define AES_BASE (AHB2PERIPH_BASE + 0x08060000U) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1169,7 +1150,7 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) @@ -1272,72 +1253,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1355,926 +1336,926 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ @@ -2285,3475 +2266,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ -#define STM32L443xx /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V1.3.1 - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/system_stm32l4xx.h deleted file mode 100644 index 3f229fa3d0..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/device/system_stm32l4xx.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c index d71a36fb67..7dac0c38b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c index 3b748462ab..b2954650e2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c @@ -33,7 +33,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -64,47 +63,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S index f897a1f1d5..a34d61e2b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l475xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l475xx.s ;* Author : MCD Application Team -;* Version : V1.2.0 -;* Date : 28-October-2016 ;* Description : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,28 +13,14 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; ;******************************************************************************* __initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S index f897a1f1d5..a34d61e2b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/startup_stm32l475xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l475xx.s ;* Author : MCD Application Team -;* Version : V1.2.0 -;* Date : 28-October-2016 ;* Description : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,28 +13,14 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; ;******************************************************************************* __initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S index 0794ce33f9..5beef80051 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32l475xx.s * @author MCD Application Team - * @version V1.2.0 - * @date 28-October-2016 * @brief STM32L475xx devices vector table for GCC toolchain. * This module performs: * - Set the initial SP @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -59,6 +41,10 @@ defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss .equ BootRAM, 0xF1E0F85F /** @@ -92,6 +78,17 @@ LoopCopyDataInit: adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit @@ -104,8 +101,11 @@ LoopCopyDataInit: // starting main(). software_init_hook() is available and has to be called due // to initializsation when using rtos. bl _start - bx lr -.size Reset_Handler, .-Reset_Handler + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S index 63361dd6b8..d24ee5ca90 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/startup_stm32l475xx.S @@ -1,8 +1,6 @@ -;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;******************************************************************************** ;* File Name : startup_stm32l475xx.s ;* Author : MCD Application Team -;* Version : V1.2.0 -;* Date : 28-October-2016 ;* Description : STM32L475xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h index bdb2d527de..543e24514f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/stm32l475xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -786,7 +770,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -1015,24 +998,24 @@ typedef struct __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** @@ -1048,18 +1031,18 @@ typedef struct __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; /** @@ -1126,183 +1109,183 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */ +#define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) /*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1468,72 +1451,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1551,1064 +1534,1064 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ #define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -2618,3475 +2601,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ -#define STM32L475xx /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -#define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/system_stm32l4xx.h deleted file mode 100644 index 4bbc092679..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c index d71a36fb67..7dac0c38b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c index d71a36fb67..7dac0c38b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c index c5daf4963e..ec69543c09 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/system_clock.c @@ -33,7 +33,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -64,47 +63,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c index d71a36fb67..7dac0c38b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S index 9eba6e1686..0de4817cf9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l476xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 ;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,28 +13,14 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; ;******************************************************************************* __initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S index 9eba6e1686..0de4817cf9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_STD/startup_stm32l476xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l476xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 ;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,28 +13,14 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; ;******************************************************************************* __initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S index 8e825b181c..c2d33811e8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.S @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32l476xx.s * @author MCD Application Team - * @version V1.1.1 - * @date 29-April-2016 * @brief STM32L476xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S index 8548246832..b07e2994a5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_IAR/startup_stm32l476xx.S @@ -1,8 +1,6 @@ -;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;******************************************************************************** ;* File Name : startup_stm32l476xx.s ;* Author : MCD Application Team -;* Version : V1.1.1 -;* Date : 29-April-2016 ;* Description : STM32L476xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h index e862cba86d..c7d4f1a140 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -801,7 +785,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -1030,24 +1013,24 @@ typedef struct __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** @@ -1063,18 +1046,18 @@ typedef struct __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; /** @@ -1141,184 +1124,184 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */ +#define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) /*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1485,72 +1468,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1568,1064 +1551,1064 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ #define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -2635,3475 +2618,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ -#define STM32L476xx /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c index 2f32d14892..269c62cf00 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c index d71a36fb67..7dac0c38b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S index 525d3289e0..68eccdf2e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l486xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l486xx.s ;* Author : MCD Application Team -;* Version : V1.1.2 -;* Date : 12-September-2016 ;* Description : STM32L486xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,28 +13,14 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; ;******************************************************************************* __initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S index 525d3289e0..021aef1fc4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_STD/startup_stm32l486xx.S @@ -1,8 +1,6 @@ -;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l486xx.s ;* Author : MCD Application Team -;* Version : V1.1.2 -;* Date : 12-September-2016 ;* Description : STM32L486xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ; ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S index 7cb9d3aa2a..da287b271a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l486xx.S @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32l486xx.s * @author MCD Application Team - * @version V1.1.2 - * @date 12-September-2016 * @brief STM32L486xx devices vector table for GCC toolchain. * This module performs: * - Set the initial SP @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S index e6a79a84bb..c0016100b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_IAR/startup_stm32l486xx.S @@ -1,8 +1,6 @@ -;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;******************************************************************************** ;* File Name : startup_stm32l486xx.s ;* Author : MCD Application Team -;* Version : V1.1.2 -;* Date : 12-September-2016 ;* Description : STM32L486xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h index 5706fdd28c..0f7cf0ec44 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -802,7 +786,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -1063,24 +1046,24 @@ typedef struct __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** @@ -1096,18 +1079,18 @@ typedef struct __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; /** @@ -1174,185 +1157,185 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */ +#define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define AES_BASE (AHB2PERIPH_BASE + 0x08060000U) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) /*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1520,72 +1503,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1603,1064 +1586,1064 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ #define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -2670,3475 +2653,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - #define STM32L486xx /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h deleted file mode 100644 index 4954d5c579..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c index 97902d6886..736a6e4f42 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c index 97902d6886..736a6e4f42 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_error.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S index b233de792f..8797083d8c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;******************************************************************************* ;* File Name : startup_stm32l496xx.s ;* Author : MCD Application Team -;* Version : V1.7.0 -;* Date : 17-February-2017 ;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S index b233de792f..8797083d8c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;******************************************************************************* ;* File Name : startup_stm32l496xx.s ;* Author : MCD Application Team -;* Version : V1.7.0 -;* Date : 17-February-2017 ;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S index 1e5ac5b16f..c49ee80a76 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32l496xx.s * @author MCD Application Team - * @version V1.1.1 - * @date 29-April-2016 * @brief STM32L496xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP @@ -17,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S index 71698fcbb1..598390a104 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S @@ -1,4 +1,4 @@ -;/********************* COPYRIGHT(c) 2017 STMicroelectronics ******************** +;******************************************************************************** ;* File Name : startup_stm32l496xx.s ;* Author : MCD Application Team ;* Version : V1.7.0 @@ -15,27 +15,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h index 53617100dd..977163c633 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -873,7 +857,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -1103,24 +1086,24 @@ typedef struct __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** @@ -1136,18 +1119,18 @@ typedef struct __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; /** @@ -1214,190 +1197,190 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 256 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 256 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(64 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x00040000U) /*!< maximum SRAM1 size (up to 256 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */ +#define SRAM1_SIZE_MAX (0x00040000UL) /*!< maximum SRAM1 size (up to 256 KBytes) */ +#define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) -#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) -#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000UL) -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U) +#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) /*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1570,72 +1553,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1653,1072 +1636,1072 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_DFSDMCFG_Pos (2U) -#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ #define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC_SMPR1_SMPPLUS_Pos (31U) -#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ #define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -2728,3478 +2711,3478 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - #define STM32L496xx /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h deleted file mode 100644 index 4bbc092679..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c index 2943dc51cc..efd64c6602 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32l4r5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32l4r5xx.S index 4524787e37..4e20eb89e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32l4r5xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32l4r5xx.S @@ -1,4 +1,4 @@ -;********************** COPYRIGHT(c) 2017 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l4r5xx.s ;* Author : MCD Application Team ;* Description : STM32L4R5xx Ultra Low Power devices vector table for MDK-ARM toolchain. @@ -13,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_STD/startup_stm32l4r5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_STD/startup_stm32l4r5xx.S index 4524787e37..4e20eb89e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_STD/startup_stm32l4r5xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_ARM_STD/startup_stm32l4r5xx.S @@ -1,4 +1,4 @@ -;********************** COPYRIGHT(c) 2017 STMicroelectronics ****************** +;******************************************************************************* ;* File Name : startup_stm32l4r5xx.s ;* Author : MCD Application Team ;* Description : STM32L4R5xx Ultra Low Power devices vector table for MDK-ARM toolchain. @@ -13,27 +13,13 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_GCC_ARM/startup_stm32l4r5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_GCC_ARM/startup_stm32l4r5xx.S index 1df9ca41c3..aa64c12260 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_GCC_ARM/startup_stm32l4r5xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_GCC_ARM/startup_stm32l4r5xx.S @@ -15,29 +15,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_IAR/startup_stm32l4r5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_IAR/startup_stm32l4r5xx.S index bc63151de4..f9c95d715e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_IAR/startup_stm32l4r5xx.S +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/TOOLCHAIN_IAR/startup_stm32l4r5xx.S @@ -1,4 +1,4 @@ -;/********************* COPYRIGHT(c) 2017 STMicroelectronics ******************** +;******************************************************************************** ;* File Name : startup_stm32l4r5xx.s ;* Author : MCD Application Team ;* Description : STM32L4R5xx Ultra Low Power Devices vector @@ -13,27 +13,13 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/stm32l4r5xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/stm32l4r5xx.h index 20327ca110..1aae860b2f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/stm32l4r5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/stm32l4r5xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -911,7 +895,6 @@ typedef struct __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; - /** * @brief Serial Audio Interface */ @@ -1128,24 +1111,24 @@ typedef struct __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** @@ -1161,18 +1144,18 @@ typedef struct __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ } USB_OTG_DeviceTypeDef; /** @@ -1239,211 +1222,211 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 2 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 192 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */ -#define SRAM3_BASE ((uint32_t)0x20040000U) /*!< SRAM3(384 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define OCTOSPI1_BASE ((uint32_t)0x90000000U) /*!< OCTOSPI1 memories accessible over AHB base address */ -#define OCTOSPI2_BASE ((uint32_t)0x70000000U) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 2 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(64 KB) base address */ +#define SRAM3_BASE (0x20040000UL) /*!< SRAM3(384 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define OCTOSPI1_R_BASE ((uint32_t)0xA0001000U) /*!< OCTOSPI1 control registers base address */ -#define OCTOSPI2_R_BASE ((uint32_t)0xA0001400U) /*!< OCTOSPI2 control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE (0xA0001000UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE (0xA0001400UL) /*!< OCTOSPI2 control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX ((uint32_t)0x00030000U) /*!< maximum SRAM1 size (up to 192 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */ -#define SRAM3_SIZE ((uint32_t)0x00060000U) /*!< SRAM3 size (384 KBytes) */ +#define SRAM1_SIZE_MAX (0x00030000UL) /*!< maximum SRAM1 size (up to 192 KBytes) */ +#define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ +#define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) /*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) -#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004) -#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008) -#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000C) -#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010) -#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014) -#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018) -#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001C) -#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020) -#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024) -#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028) -#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002C) -#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030) -#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) -#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100) -#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104) -#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108) -#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010C) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) -#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080) -#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140) +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) /*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) -#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U) +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000UL) -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U) +#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) -#define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00U) -#define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400U) +#define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00UL) +#define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400UL) /*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) /* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) +#define DBGMCU_BASE (0xE0042000UL) /*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ @@ -1470,7 +1453,7 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define I2C4 ((I2C_TypeDef *) I2C4_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) @@ -1634,72 +1617,72 @@ typedef struct /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /* Legacy defines */ @@ -1717,934 +1700,934 @@ typedef struct /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_DFSDMCFG_Pos (2U) -#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ #define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ #define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC_SMPR1_SMPPLUS_Pos (31U) -#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ #define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ #define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ #define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************************************************************************/ @@ -2655,3475 +2638,3475 @@ typedef struct /*!*/ #define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) -#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - #define STM32L4R5xx /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - #define USE_HAL_DRIVER -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/system_stm32l4xx.h deleted file mode 100644 index 4bbc092679..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c index 2943dc51cc..efd64c6602 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/system_clock.c @@ -31,7 +31,6 @@ **/ #include "stm32l4xx.h" -#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -62,47 +61,6 @@ uint8_t SetSysClock_PLL_MSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4r9xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4r9xx.h index 3535e9875a..d74bbda280 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4r9xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4r9xx.h @@ -1615,7 +1615,7 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define I2C4 ((I2C_TypeDef *) I2C4_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) @@ -7208,9 +7208,9 @@ typedef struct #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */ /***************** Bit definition for DFSDM_FLTICR register *******************/ -#define DFSDM_FLTICR_CLRSCSDF_Pos (24U) -#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */ -#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */ +#define DFSDM_FLTICR_CLRSCDF_Pos (24U) +#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */ +#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCDF[7:0] Clear the short circuit detector flag */ #define DFSDM_FLTICR_CLRCKABF_Pos (16U) #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */ #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */ @@ -21161,10 +21161,6 @@ typedef struct #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */ #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */ -//+ MBED -#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE_Pos /*!< RXNE Interrupt Enable */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE Interrupt Enable */ -//- MBED #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ @@ -21356,11 +21352,6 @@ typedef struct #define USART_CR3_WUFIE_Pos (22U) #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ -/* MBED */ -#define USART_CR3_UCESM_Pos (23U) -#define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */ -#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */ -/* MBED */ #define USART_CR3_TXFTIE_Pos (23U) #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x02000000 */ #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/system_stm32l4xx.h deleted file mode 100644 index 4bbc092679..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/system_stm32l4xx.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h index 540311f1da..a811603806 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h @@ -35,12 +35,15 @@ #include "PeripheralNames.h" #include "PinNames.h" #include "stm32l4xx_ll_usart.h" +#include "stm32l4xx_ll_lpuart.h" #include "stm32l4xx_ll_tim.h" +#include "stm32l4xx_ll_rtc.h" #ifdef __cplusplus extern "C" { #endif + struct pwmout_s { PWMName pwm; PinName pin; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h index 0ae9d0b248..cafb816219 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h @@ -7,36 +7,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { @@ -110,6 +94,10 @@ #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ /** * @} */ @@ -248,6 +236,16 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE +#if defined(STM32G4) +#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) +#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + /** * @} */ @@ -274,7 +272,100 @@ #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE +#if defined(STM32L4) +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#endif /* STM32H7 */ /** * @} @@ -355,6 +446,38 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ /** * @} @@ -373,6 +496,13 @@ #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ /** * @} */ @@ -386,7 +516,7 @@ #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 @@ -427,16 +557,25 @@ #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -456,78 +595,6 @@ * @} */ -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) - #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE - #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE - #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET - #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET - #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE - #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - - #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX - #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 - #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 - #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - - #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT - #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING - #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING - #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - - -#endif /* STM32H7 */ - - -/** - * @} - */ - - /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -549,6 +616,13 @@ #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ /** * @} */ @@ -688,6 +762,12 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + /** * @} */ @@ -696,6 +776,15 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif @@ -820,6 +909,21 @@ #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + /** * @} */ @@ -887,6 +991,33 @@ #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + /** * @} */ @@ -1047,8 +1178,9 @@ * @} */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ @@ -1072,7 +1204,7 @@ /** * @} */ -#endif /* STM32L4 || STM32F7*/ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -1164,6 +1296,28 @@ #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ /** * @} */ @@ -1243,6 +1397,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ /** * @} */ @@ -1456,10 +1618,17 @@ #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT @@ -1725,6 +1894,10 @@ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + /** * @} */ @@ -2350,12 +2523,28 @@ #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET @@ -2688,6 +2877,15 @@ #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET @@ -2804,7 +3002,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -2932,7 +3130,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3048,7 +3246,7 @@ #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef @@ -3064,6 +3262,7 @@ #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback #endif /** * @} @@ -3291,6 +3490,31 @@ * @} */ +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ @@ -3303,7 +3527,7 @@ } #endif -#endif /* ___STM32_HAL_LEGACY */ +#endif /* STM32_HAL_LEGACY */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx.h similarity index 77% rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4xx.h rename to targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx.h index 91d9b0f1bc..db8edb02ff 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx.h @@ -16,29 +16,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -73,11 +57,14 @@ application */ -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ +#if !defined (STM32L412xx) && !defined (STM32L422xx) && \ + !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) + /* #define STM32L412xx */ /*!< STM32L412xx Devices */ + /* #define STM32L422xx */ /*!< STM32L422xx Devices */ /* #define STM32L431xx */ /*!< STM32L431xx Devices */ /* #define STM32L432xx */ /*!< STM32L432xx Devices */ /* #define STM32L433xx */ /*!< STM32L433xx Devices */ @@ -110,15 +97,15 @@ In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ - #define USE_HAL_DRIVER + /*#define USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */ /** * @brief CMSIS Device version number */ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ @@ -133,7 +120,11 @@ * @{ */ -#if defined(STM32L431xx) +#if defined(STM32L412xx) + #include "stm32l412xx.h" +#elif defined(STM32L422xx) + #include "stm32l422xx.h" +#elif defined(STM32L431xx) #include "stm32l431xx.h" #elif defined(STM32L432xx) #include "stm32l432xx.h" @@ -201,8 +192,8 @@ typedef enum typedef enum { - ERROR = 0, - SUCCESS = !ERROR + SUCCESS = 0, + ERROR = !SUCCESS } ErrorStatus; /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c index 5e6dae988a..e2da4a74bc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c @@ -21,29 +21,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -67,17 +51,17 @@ /** * @brief STM32L4xx HAL Driver version number */ -#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32L4xx_HAL_VERSION_RC)) +#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define STM32L4XX_HAL_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */ +#define STM32L4XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ + |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ + |(STM32L4XX_HAL_VERSION_SUB2 << 8U)\ + |(STM32L4XX_HAL_VERSION_RC)) #if defined(VREFBUF) -#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */ +#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */ #endif /* VREFBUF */ /* ------------ SYSCFG registers bit address in the alias region ------------ */ @@ -85,20 +69,31 @@ /* --- MEMRMP Register ---*/ /* Alias word address of FB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET -#define FB_MODE_BitNumber ((uint8_t)0x8) -#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) +#define FB_MODE_BitNumber 8U +#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U)) /* --- SCSR Register ---*/ /* Alias word address of SRAM2ER bit */ -#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) -#define BRER_BitNumber ((uint8_t)0x0) -#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4)) +#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18U) +#define BRER_BitNumber 0U +#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -__IO uint32_t uwTick; - /* Private function prototypes -----------------------------------------------*/ + +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */ +uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions @@ -113,7 +108,7 @@ __IO uint32_t uwTick; ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the Flash interface the NVIC allocation and initial time base + (+) Initialize the Flash interface, the NVIC allocation and initial time base clock configuration. (+) De-initialize common part of the HAL. (+) Configure the time base source to have 1ms time base with a dedicated @@ -139,23 +134,25 @@ __IO uint32_t uwTick; /** * @brief Configure the Flash prefetch, the Instruction and Data caches, - * the time base source, NVIC and any required global low level hardware - * by calling the HAL_MspInit() callback function to be optionally defined in user file + * the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file * stm32l4xx_hal_msp.c. * - * @note HAL_Init() function is called at the beginning of program after reset and before + * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. - * + * * @note In the default implementation the System Timer (Systick) is used as source of time base. * The Systick configuration is based on MSI clock, as MSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. - * Once done, time base tick starts incrementing: the tick variable counter is incremented + * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { + HAL_StatusTypeDef status = HAL_OK; + /* Configure Flash prefetch, Instruction cache, Data cache */ /* Default configuration at reset is: */ /* - Prefetch disabled */ @@ -177,13 +174,18 @@ HAL_StatusTypeDef HAL_Init(void) HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -256,14 +258,36 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000); + HAL_StatusTypeDef status = HAL_OK; - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + if (uwTickFreq != 0U) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -301,7 +325,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) */ __weak void HAL_IncTick(void) { - uwTick++; + uwTick += uwTickFreq; } /** @@ -316,8 +340,49 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @param Freq tick frequency + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status == HAL_OK) + { + uwTickFreq = Freq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +uint32_t HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. @@ -334,8 +399,8 @@ __weak void HAL_Delay(uint32_t Delay) /* Add a period to guaranty minimum wait */ if (wait < HAL_MAX_DELAY) { - wait++; - } + wait += (uint32_t)(uwTickFreq); + } while((HAL_GetTick() - tickstart) < wait) { @@ -380,7 +445,7 @@ __weak void HAL_ResumeTick(void) */ uint32_t HAL_GetHalVersion(void) { - return __STM32L4xx_HAL_VERSION; + return STM32L4XX_HAL_VERSION; } /** @@ -389,7 +454,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); + return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); } /** @@ -398,7 +463,7 @@ uint32_t HAL_GetREVID(void) */ uint32_t HAL_GetDEVID(void) { - return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); + return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } /** @@ -407,7 +472,7 @@ uint32_t HAL_GetDEVID(void) */ uint32_t HAL_GetUIDw0(void) { - return(READ_REG(*((uint32_t *)UID_BASE))); + return(READ_REG(*((uint32_t *)UID_BASE))); } /** @@ -416,7 +481,7 @@ uint32_t HAL_GetUIDw0(void) */ uint32_t HAL_GetUIDw1(void) { - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** @@ -425,7 +490,7 @@ uint32_t HAL_GetUIDw1(void) */ uint32_t HAL_GetUIDw2(void) { - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** @@ -536,7 +601,7 @@ void HAL_SYSCFG_SRAM2Erase(void) SYSCFG->SKR = 0xCA; SYSCFG->SKR = 0x53; /* Starts a hardware SRAM2 erase operation*/ - *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001; + *(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL; } /** @@ -551,7 +616,7 @@ void HAL_SYSCFG_SRAM2Erase(void) */ void HAL_SYSCFG_EnableMemorySwappingBank(void) { - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE; + *(__IO uint32_t *)FB_MODE_BB = 0x00000001UL; } /** @@ -567,7 +632,7 @@ void HAL_SYSCFG_EnableMemorySwappingBank(void) void HAL_SYSCFG_DisableMemorySwappingBank(void) { - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE; + *(__IO uint32_t *)FB_MODE_BB = 0x00000000UL; } #if defined(VREFBUF) @@ -575,9 +640,9 @@ void HAL_SYSCFG_DisableMemorySwappingBank(void) * @brief Configure the internal voltage reference buffer voltage scale. * @param VoltageScaling specifies the output voltage to achieve * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. * @retval None */ @@ -585,7 +650,7 @@ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); } @@ -601,7 +666,7 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); - + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); } @@ -613,7 +678,7 @@ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); - + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); } @@ -623,22 +688,22 @@ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) */ HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) { - uint32_t tickstart = 0; - + uint32_t tickstart; + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait for VRR bit */ - while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET) + while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U) { if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } - + return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h index aafa7c351c..9643b494d4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h @@ -7,36 +7,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_H -#define __STM32L4xx_HAL_H +#ifndef STM32L4xx_HAL_H +#define STM32L4xx_HAL_H #ifdef __cplusplus extern "C" { @@ -55,6 +39,27 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +#define HAL_TICK_FREQ_10HZ 100U +#define HAL_TICK_FREQ_100HZ 10U +#define HAL_TICK_FREQ_1KHZ 1U +#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ + +/** + * @} + */ + +/** + * @} + */ + /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ @@ -62,7 +67,7 @@ /** @defgroup SYSCFG_BootMode Boot Mode * @{ */ -#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) +#define SYSCFG_BOOT_MAINFLASH 0U #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ @@ -72,7 +77,7 @@ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) @@ -188,8 +193,8 @@ /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale * @{ */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ /** * @} @@ -198,8 +203,8 @@ /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance * @{ */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ /** * @} @@ -222,7 +227,7 @@ */ /** @brief Fast-mode Plus driving capability on a specific GPIO - */ + */ #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) @@ -491,16 +496,16 @@ * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. */ #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) /** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__ This parameter can be a value of : + * @param __FASTMODEPLUS__ This parameter can be a value of : * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 - * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 */ @@ -517,6 +522,18 @@ */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ + +#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \ + ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \ + ((__FREQ__) == HAL_TICK_FREQ_1KHZ)) + +/** + * @} + */ + /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros * @{ */ @@ -533,7 +550,7 @@ ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) -#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) +#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) #if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ @@ -542,7 +559,7 @@ #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) -#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) #endif /* VREFBUF */ #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) @@ -566,6 +583,18 @@ * @} */ +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern uint32_t uwTickFreq; +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions @@ -579,8 +608,8 @@ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); /** @@ -592,17 +621,20 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); */ /* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); +uint32_t HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); /** * @} @@ -613,12 +645,12 @@ uint32_t HAL_GetUIDw2(void); */ /* DBGMCU Peripheral Control functions *****************************************/ -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} @@ -629,20 +661,20 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ /* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); -void HAL_SYSCFG_EnableMemorySwappingBank(void); -void HAL_SYSCFG_DisableMemorySwappingBank(void); +void HAL_SYSCFG_SRAM2Erase(void); +void HAL_SYSCFG_EnableMemorySwappingBank(void); +void HAL_SYSCFG_DisableMemorySwappingBank(void); #if defined(VREFBUF) -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); -void HAL_SYSCFG_DisableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); #endif /* VREFBUF */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); /** * @} @@ -664,6 +696,6 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); } #endif -#endif /* __STM32L4xx_HAL_H */ +#endif /* STM32L4xx_HAL_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c index a152b9e040..16117a181d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_adc.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions @@ -16,7 +16,7 @@ * + State functions * ++ ADC state machine management * ++ Interrupts and flags management - * Other functions (extended functions) are available in file + * Other functions (extended functions) are available in file * "stm32l4xx_hal_adc_ex.c". * @verbatim @@ -26,33 +26,33 @@ [..] (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - (+) Interrupt generation at the end of regular conversion and in case of + (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. - + (+) Single and continuous conversion modes. - + (+) Scan mode for conversion of several channels sequentially. - + (+) Data alignment with in-built data coherency. - + (+) Programmable sampling time (channel wise) - + (+) External trigger (timer or EXTI) with configurable polarity - + (+) DMA request generation for transfer of conversions data of regular group. - + (+) Configurable delay between conversions in Dual interleaved mode. - + (+) ADC channels selectable single/differential input. - + (+) ADC offset shared on 4 offset instances. (+) ADC calibration - + (+) ADC conversion of regular group. - + (+) ADC supply requirements: 1.62 V to 3.6 V. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). @@ -67,12 +67,12 @@ (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. - (++) Two clock settings are mandatory: + (++) Two clock settings are mandatory: (+++) ADC clock (core clock, also possibly conversion clock). (+++) ADC clock (conversions clock). Two possible clock sources: synchronous clock derived from APB clock - or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2 + or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2 running up to 80MHz. (+++) Example: @@ -98,8 +98,8 @@ (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: @@ -107,8 +107,8 @@ using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, group regular, channels parameters *** @@ -119,7 +119,7 @@ and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). - (#) Configure the channels for regular group parameters (channel number, + (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). @@ -141,22 +141,22 @@ (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion + (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() - (+++) Retrieve conversion results + (+++) Retrieve conversion results using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() - (++) ADC conversion by interruption: + (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) - (+++) Retrieve conversion results + (+++) Retrieve conversion results using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: @@ -167,7 +167,7 @@ (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() [..] @@ -210,36 +210,93 @@ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] - - @endverbatim + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -263,36 +320,28 @@ * @{ */ -#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES | ADC_CFGR_ALIGN |\ - ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ - ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated - when no regular conversion is on-going */ - -/* Delay to wait before setting ADEN once ADCAL has been reset - must be at least 4 ADC clock cycles. - Assuming lowest ADC clock (140 KHz according to DS), this - 4 ADC clock cycles duration is equal to - 4 / 140,000 = 0.028 ms. - ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure - the 4 ADC clock cycles have elapsed while waiting for ADRDY - to become 1 */ - #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ - #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ - +#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ + ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ + ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated + when no regular conversion is on-going */ +/* Timeout values for ADC operations (enable settling time, */ +/* disable settling time, ...). */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescalers. */ +#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ +#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ + /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ -/* - ADC clock with prescaler 256 */ -/* (from asynchronous clock, assuming clock frequency same as CPU for */ -/* this calculation) */ +/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ /* - ADC oversampling ratio 256 */ -/* Calculation: 653 * 256 * 256 = 42795008 CPU clock cycles max */ +/* Calculation: 653 * 4096 * 256 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ -#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 42795008) /*!< ADC conversion completion time-out value */ - +#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ /** @@ -311,19 +360,19 @@ /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief ADC Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. + (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** - * @brief Initialize the ADC peripheral and regular group according to + * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (refer to description of RCC configuration for ADC @@ -331,42 +380,47 @@ * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". - * @note Parameters related to common ADC registers (ADC clock mode) are set + * @note Parameters related to common ADC registers (ADC clock mode) are set * only if all ADCs are disabled. - * If this is not the case, these common parameters setting are + * If this is not the case, these common parameters setting are * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR = 0U; - __IO uint32_t wait_loop_index = 0; - + uint32_t tmpCFGR; + uint32_t tmp_adc_reg_is_conversion_on_going; + __IO uint32_t wait_loop_index = 0UL; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) assert_param(IS_ADC_DFSDMCFG_MODE(hadc)); +#endif assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); @@ -377,117 +431,141 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if(hadc->Init.DiscontinuousConvMode == ENABLE) + + if (hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } - + /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - + /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ - if(hadc->State == HAL_ADC_STATE_RESET) + if (hadc->State == HAL_ADC_STATE_RESET) { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } - + /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0U) + if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { - /* Disable ADC deep power down mode */ + /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); - + /* System was in deep power down mode, calibration must - be relaunched or a previously saved calibration factor - re-applied once the ADC voltage regulator is enabled */ + be relaunched or a previously saved calibration factor + re-applied once the ADC voltage regulator is enabled */ } - - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - - /* Delay for ADC stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while (wait_loop_index != 0UL) { wait_loop_index--; } } - + /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + tmp_hal_status = HAL_ERROR; } - - /* Configuration of ADC parameters if previous preliminary actions are */ + + /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ - if( (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - ) + tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) + ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Configuration of common ADC parameters */ - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { - /* Reset configuration of ADC common register CCR: */ - /* */ - /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ - /* according to adc->Init.ClockPrescaler. It selects the clock */ - /* source and sets the clock division factor. */ - /* */ - /* Some parameters of this register are not reset, since they are set */ - /* by other functions and must be kept in case of usage of this */ - /* function on the fly (update of a parameter of ADC_InitTypeDef */ - /* without needing to reconfigure all other ADC groups/channels */ - /* parameters): */ - /* - when multimode feature is available, multimode-related */ - /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ - /* HAL_ADCEx_MultiModeConfigChannel() ) */ - /* - internal measurement paths: Vbat, temperature sensor, Vref */ - /* (set into HAL_ADC_ConfigChannel() or */ - /* HAL_ADCEx_InjectedConfigChannel() ) */ - LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) + { + /* Reset configuration of ADC common register CCR: */ + /* */ + /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ + /* according to adc->Init.ClockPrescaler. It selects the clock */ + /* source and sets the clock division factor. */ + /* */ + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - when multimode feature is available, multimode-related */ + /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ + /* HAL_ADCEx_MultiModeConfigChannel() ) */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() or */ + /* HAL_ADCEx_InjectedConfigChannel() ) */ + LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); + } } - + /* Configuration of ADC: */ /* - resolution Init.Resolution */ /* - data alignment Init.DataAlign */ @@ -497,17 +575,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ - tmpCFGR = (ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) | - hadc->Init.Overrun | - hadc->Init.DataAlign | - hadc->Init.Resolution | - ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) ); - + tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + hadc->Init.Overrun | + hadc->Init.DataAlign | + hadc->Init.Resolution | + ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); + if (hadc->Init.DiscontinuousConvMode == ENABLE) { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); } - + /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ @@ -515,35 +593,39 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge ); } - + /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); - + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { - tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | - ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) | - ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); - - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); - + tmpCFGR = (ADC_CFGR_DFSDM(hadc) | + ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); + if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); - + /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ @@ -566,9 +648,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } - - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ - + + } + /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ @@ -587,7 +669,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); } - + /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); @@ -596,10 +678,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + tmp_hal_status = HAL_ERROR; } - + /* Return function status */ return tmp_hal_status; } @@ -607,41 +689,40 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. - * @note For devices with several ADCs: reset of ADC common registers is done + * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: * all ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). - * If this is not the case, reset of these common parameters reset is + * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behavior in - * case of reset of a single ADC while the other ADCs sharing the same + * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents + * this saves more power by reducing leakage currents * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { + HAL_StatusTypeDef tmp_hal_status; + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Note: No check on ADC_ConversionStop() return status, */ - /* if the conversion stop failed, it is up to */ - /* HAL_ADC_MspDeInit() to reset the ADC IP. */ - ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + + /* Stop potential conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ /* queue sequencer is enabled and ADC disabled. */ @@ -649,116 +730,129 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* internally disabled just after the completion of the last valid */ /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); - - /* Disable the ADC peripheral */ - /* No check on ADC_Disable() return status, if the ADC disabling process - failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */ - ADC_Disable(hadc); - - + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ + /* and disable return status. In case of status fail, attempt to */ + /* perform deinitialization anyway and it is up user code in */ + /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ + /* system RCC hard reset. */ + /* ========== Reset ADC registers ========== */ /* Reset register IER */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOSMP | ADC_IT_RDY ) ); - + ADC_IT_EOSMP | ADC_IT_RDY)); + /* Reset register ISR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | - ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); - + ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + /* Reset register CR */ - /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, - ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": - no direct reset applicable. - Update CR register to reset value where doable by software */ + /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, + ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": + no direct reset applicable. + Update CR register to reset value where doable by software */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); - SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - + SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); + /* Reset register CFGR */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + /* Reset register CFGR2 */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | - ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE ); - + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | + ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); + /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); - + CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); + /* Reset register SMPR2 */ - CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | - ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | - ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 ); - + CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | + ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | + ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); + /* Reset register TR1 */ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); - + /* Reset register TR2 */ - CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); - + CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); + /* Reset register TR3 */ - CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); - + CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); + /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | - ADC_SQR1_SQ1 | ADC_SQR1_L); - + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | + ADC_SQR1_SQ1 | ADC_SQR1_L); + /* Reset register SQR2 */ - CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | - ADC_SQR2_SQ6 | ADC_SQR2_SQ5); - + CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | + ADC_SQR2_SQ6 | ADC_SQR2_SQ5); + /* Reset register SQR3 */ - CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | - ADC_SQR3_SQ11 | ADC_SQR3_SQ10); - + CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | + ADC_SQR3_SQ11 | ADC_SQR3_SQ10); + /* Reset register SQR4 */ - CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - + CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); + /* Register JSQR was reset when the ADC was disabled */ - + /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ - + /* Reset register OFR1 */ - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); + CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); + CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); /* Reset register OFR3 */ - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); + CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ - + /* Reset register AWD2CR */ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); - + /* Reset register AWD3CR */ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); - + /* Reset register DIFSEL */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); - + /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); - - + + /* ========== Reset common ADC registers ========== */ - + /* Software is allowed to change common parameters only when all the other ADCs are disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: - clock mode: CKMODE, PRESCEN - - multimode related parameters (when this feature is available): MDMA, + - multimode related parameters (when this feature is available): MDMA, DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) - internal measurement paths: Vbat, temperature sensor, Vref (set into HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) @@ -766,34 +860,45 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); } - /* DeInit the low level hardware. - + /* DeInit the low level hardware. + For example: __HAL_RCC_ADC_FORCE_RESET(); __HAL_RCC_ADC_RELEASE_RESET(); __HAL_RCC_ADC_CLK_DISABLE(); - + Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - + the clock will reset all ADCs. + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware: RCC clock, NVIC */ HAL_ADC_MspDeInit(hadc); - +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Reset injected channel configuration parameters */ hadc->InjectionConfig.ContextQueue = 0; - hadc->InjectionConfig.ChannelCount = 0; - + hadc->InjectionConfig.ChannelCount = 0; + /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ - return HAL_OK; + return tmp_hal_status; } /** @@ -801,14 +906,14 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. - */ + */ } /** @@ -818,24 +923,268 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) * the core clock reset all ADC instances). * @retval None */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. - */ + */ } +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : + hadc->InjectedQueueOverflowCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = pCallback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : + hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions - * @brief ADC IO operation functions - * -@verbatim + * @brief ADC IO operation functions + * +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -857,29 +1206,32 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /** * @brief Enable ADC, start conversion of regular group. * @note Interruptions enabled in this function: None. - * @note Case of multimode enabled (when multimode feature is available): - * if ADC is Slave, ADC is enabled but conversion is not started, + * @note Case of multimode enabled (when multimode feature is available): + * if ADC is Slave, ADC is enabled but conversion is not started, * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_TypeDef *tmpADC_Master; - + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -889,37 +1241,41 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } +#endif /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else - { + { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -928,31 +1284,44 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { - /* Multimode feature is not available or ADC Instance is Independent or Master, - or is not Slave ADC with dual regular conversions enabled. - Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { + /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* if Master ADC JAUTO bit is set, update Slave State in setting + /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + } +#else + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); +#endif } else { @@ -964,39 +1333,39 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected channels in + * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential + * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1006,10 +1375,10 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1018,30 +1387,33 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * @brief Wait for regular group conversion to be completed. * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function, with an exception: - * if low power feature "LowPowerAutoWait" is enabled, flags are + * if low power feature "LowPowerAutoWait" is enabled, flags are * not cleared to not interfere with this feature until data register * is read using function HAL_ADC_GetValue(). - * @note This function cannot be used in a particular setup: ADC configured + * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still + * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { - uint32_t tickstart = 0U; - uint32_t tmp_Flag_End = 0U; - uint32_t tmp_cfgr = 0U; - ADC_TypeDef *tmpADC_Master; - + uint32_t tickstart; + uint32_t tmp_Flag_End; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { @@ -1056,10 +1428,14 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ - if(ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { - /* Check ADC DMA mode in independant mode */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) + /* Check ADC DMA mode in independent mode on ADC group regular */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; @@ -1071,8 +1447,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti } else { - /* Check ADC DMA mode in multimode */ - if(ADC_MULTIMODE_DMA_ENABLED(hadc)) + /* Check ADC DMA mode in multimode on ADC group regular */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; @@ -1082,82 +1458,104 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tmp_Flag_End = (ADC_FLAG_EOC); } } +#else + /* Check ADC DMA mode */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } +#endif } - + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) { /* Check whether end of sequence is reached */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } - + /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { /* Retrieve handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* Retrieve Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - +#else + /* Retrieve handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif + /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } - + /* Return function status */ return HAL_OK; } @@ -1175,130 +1573,131 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. - * Indeed, the latter is reset only if hadc->Init.Overrun field is set - * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten * by a new converted data as soon as OVR is cleared. * To reset OVR flag once the preserved data is retrieved, the user can resort - * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); - + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - - switch(EventType) + + switch (EventType) { - /* End Of Sampling event */ - case ADC_EOSMP_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - - /* Clear the End Of Sampling flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - - break; - - /* Analog watchdog (level out of window) event */ - /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of analog watchdog */ - /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ - /* For example: */ - /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ - /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ - /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */ - /* Check analog watchdog 1 flag */ - case ADC_AWD_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - - break; - - /* Check analog watchdog 2 flag */ - case ADC_AWD2_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - - break; - - /* Check analog watchdog 3 flag */ - case ADC_AWD3_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - - break; - - /* Injected context queue overflow event */ - case ADC_JQOVF_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - - /* Clear ADC Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - break; - - /* Overrun event */ - default: /* Case ADC_OVR_EVENT */ - /* If overrun is set to overwrite previous data, overrun event is not */ - /* considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - } - else - { - /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN - otherwise, data register is potentially overwritten by new converted data as soon - as OVR is cleared. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - break; + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Injected context queue overflow event */ + case ADC_JQOVF_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + + /* Set ADC error code to Injected context queue overflow */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + + /* Clear ADC Injected context queue overflow flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; } - + /* Return function status */ return HAL_OK; } @@ -1306,43 +1705,46 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /** * @brief Enable ADC, start conversion of regular group with interruption. * @note Interruptions enabled in this function according to initialization - * setting : EOC (end of conversion), EOS (end of sequence), + * setting : EOC (end of conversion), EOS (end of sequence), * OVR overrun. * Each of these interruptions has its dedicated callback function. - * @note Case of multimode enabled (when multimode feature is available): + * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Start_IT() must be called for ADC Slave first, then for * ADC Master. - * For ADC Slave, ADC is enabled only (conversion is not started). + * For ADC Slave, ADC is enabled only (conversion is not started). * For ADC Master, ADC is enabled and multimode conversion is started. * @note To guarantee a proper reset of all interruptions once all the needed - * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: - * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) - * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_TypeDef *tmpADC_Master; - + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1352,42 +1754,46 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - +#endif + /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); @@ -1397,129 +1803,158 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); break; } - + /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); } - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ + /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if(ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { - /* Multimode feature is not available or ADC Instance is Independent or Master, - or is not Slave ADC with dual regular conversions enabled. - Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - - /* Enable as well injected interruptions in case + + /* Enable as well injected interruptions in case HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This allows to start regular and injected conversions when JAUTO is set with a single call to HAL_ADC_Start_IT() */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; + break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; + break; } } - + /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { - /* hadc is the handle of a Slave ADC with dual regular conversions - enabled. Therefore, ADC_CR_ADSTART is NOT set */ + /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, Slave injected interruptions are enabled nevertheless (for same reason as above) */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { - /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit + /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Next, set Slave injected interruptions */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; + break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; + break; } } } +#else + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + + /* Enable as well injected interruptions in case + HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This + allows to start regular and injected conversions when JAUTO is + set with a single call to HAL_ADC_Start_IT() */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); +#endif } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } - + } else { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1529,10 +1964,10 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1540,36 +1975,44 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) /** * @brief Enable ADC, start conversion of regular group and transfer result through DMA. * @note Interruptions enabled in this function: - * overrun (if applicable), DMA half transfer, DMA transfer complete. + * overrun (if applicable), DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. - * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() - * is designed for single-ADC mode only. For multimode, the dedicated + * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() + * is designed for single-ADC mode only. For multimode, the dedicated * HAL_ADCEx_MultiModeStart_DMA() function must be used. * @param hadc ADC handle * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - - /* Ensure that dual regular conversions are not enabled or unavailable. */ + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ - if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) +#endif { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1579,61 +2022,65 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - +#endif + /* Check if a conversion is on going on ADC group injected */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else - { + { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - + /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ /* ADC start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - - /* With DMA, overrun event is always considered as an error even if - hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, + + /* With DMA, overrun event is always considered as an error even if + hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -1646,79 +2093,85 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Process unlocked */ __HAL_UNLOCK(hadc); } + } +#if defined(ADC_MULTIMODE_SUPPORT) else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); } +#endif } else { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on ADC group injected. If ADC group injected is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential ADC group regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ - /* in memory a potential failing status. */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { - ADC_Disable(hadc); + (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ @@ -1729,12 +2182,12 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1743,7 +2196,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS + * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent @@ -1758,15 +2211,15 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ + + /* Return ADC converted value */ return hadc->Instance->DR; } @@ -1775,153 +2228,185 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { - uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; uint32_t tmp_ier = hadc->Instance->IER; - uint32_t tmp_cfgr = 0x0; - ADC_TypeDef *tmpADC_Master; - + uint32_t tmp_adc_inj_is_trigger_source_sw_start; + uint32_t tmp_adc_reg_is_trigger_source_sw_start; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - + /* ========== Check End of Sampling flag for ADC group regular ========== */ - if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } - + /* End Of Sampling callback */ - HAL_ADCEx_EndOfSamplingCallback(hadc); - +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->EndOfSamplingCallback(hadc); +#else + HAL_ADCEx_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); } - + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ - if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) { /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) { /* check CONT bit directly in handle ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* else need to check Master ADC CONT bit */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif + /* Carry on if continuous mode is disabled */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) + if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) { /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - + /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } + } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } - + /* Conversion complete callback */ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ /* possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else HAL_ADC_ConvCpltCallback(hadc); - +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } - + /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ - if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) + if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || + (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) { /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - + + /* Retrieve ADC configuration */ + tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); + tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) { - tmp_cfgr = READ_REG(hadc->Instance->CFGR); + tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { - tmpADC_Master = ADC_MASTER_REGISTER(hadc); + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif + /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ @@ -1929,20 +2414,20 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -1950,64 +2435,83 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } - + /* Injected Conversion complete callback */ - /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to + /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether - interruption has been triggered by end of conversion or end of - sequence. */ + interruption has been triggered by end of conversion or end of + sequence. */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else HAL_ADCEx_InjectedConvCpltCallback(hadc); - +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } - + /* ========== Check Analog watchdog 1 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Level out of window 1 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else HAL_ADC_LevelOutOfWindowCallback(hadc); - /* Clear ADC analog watchdog flag */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } - + /* ========== Check analog watchdog 2 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - + /* Level out of window 2 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow2Callback(hadc); +#else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); - /* Clear ADC analog watchdog flag */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } - + /* ========== Check analog watchdog 3 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - + /* Level out of window 3 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow3Callback(hadc); +#else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); - /* Clear ADC analog watchdog flag */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } - + /* ========== Check Overrun flag ========== */ - if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) { /* If overrun is set to overwrite previous data (default setting), */ /* overrun event is not considered as an error. */ @@ -2015,69 +2519,78 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - overrun_error = 1; + overrun_error = 1UL; } else { /* Check DMA configuration */ - if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET) +#if defined(ADC_MULTIMODE_SUPPORT) + if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) { - /* Multimode not set or feature not available or ADC independent */ - if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) + /* Multimode (when feature is available) is enabled, + Common Control Register MDMA bits must be checked. */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { - overrun_error = 1; + overrun_error = 1UL; } } else +#endif { - /* Multimode (when feature is available) is enabled, - Common Control Register MDMA bits must be checked. */ - if (ADC_MULTIMODE_DMA_ENABLED(hadc)) + /* Multimode not set or feature not available or ADC independent */ + if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) { - overrun_error = 1; + overrun_error = 1UL; } } } - - if (overrun_error == 1) + + if (overrun_error == 1UL) { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - + /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - + /* Error callback */ /* Note: In case of overrun, ADC conversion data is preserved until */ /* flag OVR is reset. */ /* Therefore, old ADC conversion data can be retrieved in */ /* function "HAL_ADC_ErrorCallback()". */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - + /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - + /* ========== Check Injected context queue overflow flag ========== */ - if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) + if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { /* Change ADC state to overrun state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - + /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - + /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - /* Error callback */ + + /* Injected context queue overflow callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedQueueOverflowCallback(hadc); +#else HAL_ADCEx_InjectedQueueOverflowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - + } /** @@ -2085,7 +2598,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2100,7 +2613,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2115,7 +2628,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2128,8 +2641,8 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief ADC error callback in non-blocking mode * (ADC conversion with interruption or transfer by DMA). - * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" @@ -2152,16 +2665,16 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim + * @brief Peripheral Control functions + * +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog - + @endverbatim * @{ */ @@ -2170,7 +2683,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @brief Configure a channel to be assigned to ADC group regular. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function + * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into ADC group regular, @@ -2183,12 +2696,15 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; + uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; - + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); @@ -2196,34 +2712,34 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); - - /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + + /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); - + assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); + /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); + assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel)); } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { #if !defined (USE_FULL_ASSERT) - /* Correspondance for compatibility with legacy definition of */ - /* sequencer ranks in direct number format. This correspondance can */ + /* Correspondence for compatibility with legacy definition of */ + /* sequencer ranks in direct number format. This correspondence can */ /* be done only on ranks 1 to 5 due to literal values. */ /* Note: Sequencer ranks in direct number format are no more used */ /* and are detected by activating USE_FULL_ASSERT feature. */ @@ -2236,28 +2752,32 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break; case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break; /* case 1U */ - default: sConfig->Rank = ADC_REGULAR_RANK_1; + default: sConfig->Rank = ADC_REGULAR_RANK_1; break; } } #endif /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { #if defined(ADC_SMPR1_SMPPLUS) /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ - if(sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) + if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); - + /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } @@ -2265,7 +2785,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); - + /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } @@ -2273,18 +2793,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); #endif - + /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); - - if(sConfig->OffsetNumber != ADC_OFFSET_NONE) + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); + + if (sConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); - + } else { @@ -2308,22 +2828,25 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf } } } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - if (ADC_IS_ENABLE(hadc) == RESET) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); - + /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), + sConfig->SamplingTime); } - + } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ @@ -2332,53 +2855,55 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - /* Configuration of common ADC parameters */ - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) + if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { - /* Configuration of common ADC parameters (continuation) */ + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while (wait_loop_index != 0UL) { wait_loop_index--; } } } - else if (sConfig->Channel == ADC_CHANNEL_VBAT) + else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } + else + { + /* nothing to do */ + } } } - + /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ @@ -2386,13 +2911,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2400,12 +2925,12 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /** * @brief Configure the analog watchdog. * @note Possibility to update parameters on the fly: - * This function initializes the selected analog watchdog, successive - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting * the ADC. * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @note On this STM32 serie, analog watchdog thresholds cannot be modified * while ADC conversion is on going. @@ -2413,76 +2938,97 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted = 0U; - uint32_t tmpAWDLowThresholdShifted = 0U; - + uint32_t tmpAWDHighThresholdShifted; + uint32_t tmpAWDLowThresholdShifted; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) + + if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); } - /* Verify if threshold is within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + /* Verify thresholds range */ + if (hadc->Init.OversamplingMode == ENABLE) + { + /* Case of oversampling enabled: depending on ratio and shift configuration, + analog watchdog thresholds can be higher than ADC resolution. + Verify if thresholds are within maximum thresholds range. */ + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + } + else + { + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + } /* Process locked */ __HAL_LOCK(hadc); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { /* Analog watchdog configuration */ - if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ - switch(AnalogWDGConfig->WatchdogMode) + switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); break; - + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_INJECTED)); break; - + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR_INJECTED)); break; - + case ADC_ANALOGWATCHDOG_ALL_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); break; - + case ADC_ANALOGWATCHDOG_ALL_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); break; - + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; - + default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); break; } - + /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0 */ @@ -2494,15 +3040,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD1(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -2514,7 +3060,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch(AnalogWDGConfig->WatchdogMode) + switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: @@ -2523,25 +3069,25 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* several channels by successive calls of this function. */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } break; - + case ADC_ANALOGWATCHDOG_ALL_REG: case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; - + default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } - + /* Shift the thresholds in function of the selected ADC resolution */ /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); @@ -2554,15 +3100,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD2(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -2576,15 +3122,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG { /* Update state, clear previous result related to AWD3 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD3(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -2594,7 +3140,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG } } } - + } /* If a conversion is on going on ADC group regular or injected, no update */ /* could be done on neither of the AWD configuration structure parameters. */ @@ -2607,7 +3153,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG } /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2618,14 +3164,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief ADC Peripheral State functions - * + * @brief ADC Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral state and errors functions ##### =============================================================================== [..] - This subsection provides functions to get in run-time the status of the + This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @@ -2636,19 +3182,19 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /** * @brief Return the ADC handle state. - * @note ADC state machine is managed by bitfields, ADC status must be + * @note ADC state machine is managed by bitfields, ADC status must be * compared with states bits. - * For example: - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Return ADC handle state */ return hadc->State; } @@ -2662,7 +3208,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + return hadc->ErrorCode; } @@ -2688,19 +3234,26 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { - uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0; - uint32_t tickstart = 0; - uint32_t Conversion_Timeout_CPU_cycles = 0; + uint32_t tickstart; + uint32_t Conversion_Timeout_CPU_cycles = 0UL; + uint32_t conversion_group_reassigned = ConversionGroup; + uint32_t tmp_ADC_CR_ADSTART_JADSTART; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); - + /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular != 0UL) + || (tmp_adc_is_conversion_on_going_injected != 0UL) + ) { /* Particular case of continuous auto-injection mode combined with */ /* auto-delay mode. */ @@ -2708,93 +3261,96 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ - if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) - && (hadc->Init.ContinuousConvMode==ENABLE) - && (hadc->Init.LowPowerAutoWait==ENABLE)) + if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) + && (hadc->Init.ContinuousConvMode == ENABLE) + && (hadc->Init.LowPowerAutoWait == ENABLE) + ) { /* Use stop of regular group */ - ConversionGroup = ADC_REGULAR_GROUP; - + conversion_group_reassigned = ADC_REGULAR_GROUP; + /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET) + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) { - if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4)) + if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } Conversion_Timeout_CPU_cycles ++; } - + /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } - - /* Stop potential conversion on going on regular group */ - if (ConversionGroup != ADC_INJECTED_GROUP) + + /* Stop potential conversion on going on ADC group regular */ + if (conversion_group_reassigned != ADC_INJECTED_GROUP) { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && - HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { - /* Stop conversions on regular group */ - LL_ADC_REG_StopConversion(hadc->Instance); + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } } } - - /* Stop potential conversion on going on injected group */ - if (ConversionGroup != ADC_REGULAR_GROUP) + + /* Stop potential conversion on going on ADC group injected */ + if (conversion_group_reassigned != ADC_REGULAR_GROUP) { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && - HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { - /* Stop conversions on injected group */ - SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP); - } + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group injected conversion */ + LL_ADC_INJ_StopConversion(hadc->Instance); + } + } } - + /* Selection of start and stop bits with respect to the regular or injected group */ - switch(ConversionGroup) + switch (conversion_group_reassigned) { - case ADC_REGULAR_INJECTED_GROUP: + case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); break; - case ADC_INJECTED_GROUP: + case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; break; - /* Case ADC_REGULAR_GROUP only*/ - default: + /* Case ADC_REGULAR_GROUP only*/ + default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; break; } - + /* Wait for conversion effectively stopped */ - - tickstart = HAL_GetTick(); - - while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET) + + while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } - + } - + /* Return HAL status */ return HAL_OK; } @@ -2808,73 +3364,62 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { - uint32_t tickstart = 0; - __IO uint32_t wait_loop_index = 0; - + uint32_t tickstart; + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ - if (ADC_IS_ENABLE(hadc) == RESET) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ - if (ADC_ENABLING_CONDITIONS(hadc) == RESET) + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } - + /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - - /* Delay for ADC stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) - { - wait_loop_index--; - } /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) + + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the calibration logic. The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ - if(LL_ADC_IsEnabled(hadc->Instance) == 0) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_Enable(hadc->Instance); } - - if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } } - + /* Return HAL status */ return HAL_OK; } @@ -2886,17 +3431,20 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { - uint32_t tickstart = 0; - + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); + /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ - if (ADC_IS_ENABLE(hadc) != RESET) + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) { /* Check if conditions to disable the ADC are fulfilled */ - if (ADC_DISABLING_CONDITIONS(hadc) != RESET) + if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); @@ -2906,68 +3454,68 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } - + /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ + + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } } - + /* Return HAL status */ return HAL_OK; } /** - * @brief DMA transfer complete callback. + * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Update state machine on conversion status if not in error state */ - if(HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))) + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ - if(HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) + if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Is CONT bit set ? */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -2977,26 +3525,34 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } - + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else /* DMA and-or internal error occurred */ { - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) { /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { @@ -3007,17 +3563,21 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Half conversion callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** @@ -3028,16 +3588,20 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - + /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - + /* Error callback */ - HAL_ADC_ErrorCallback(hadc); +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h index 522b91304b..577a42e676 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_ADC_H -#define __STM32L4xx_HAL_ADC_H +#ifndef STM32L4xx_HAL_ADC_H +#define STM32L4xx_HAL_ADC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +44,7 @@ * @{ */ -/** +/** * @brief ADC group regular oversampling structure definition */ typedef struct @@ -76,13 +60,13 @@ typedef struct uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected - sequence interruption. - If oversampling is enabled on both regular and injected groups, this parameter - is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" - (the oversampling buffer is zeroed during injection sequence). - This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ + sequence interruption. + If oversampling is enabled on both regular and injected groups, this parameter + is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" + (the oversampling buffer is zeroed during injection sequence). + This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ -}ADC_OversamplingTypeDef; +} ADC_OversamplingTypeDef; /** * @brief Structure definition of ADC instance and ADC group regular. @@ -97,7 +81,7 @@ typedef struct * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter + * without error reporting (as it can be the expected behavior in case of intended action to update another parameter * (which fulfills the ADC state condition) on the fly). */ typedef struct @@ -105,15 +89,15 @@ typedef struct uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. - Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, + Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only - if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC + if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ - uint32_t Resolution; /*!< Configure the ADC resolution. + uint32_t Resolution; /*!< Configure the ADC resolution. This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). @@ -131,11 +115,11 @@ typedef struct uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of @ref ADC_EOCSelection. */ - uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun - for low frequency applications. + for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag to free the IRQ vector sequencer. @@ -143,17 +127,17 @@ typedef struct use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ - uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. - Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without + Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. @@ -167,12 +151,12 @@ typedef struct If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ - + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ @@ -180,15 +164,15 @@ typedef struct uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear - end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function + Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear + end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data + - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ - uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. + FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ @@ -201,7 +185,7 @@ typedef struct Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ #endif -}ADC_InitTypeDef; +} ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group @@ -222,7 +206,7 @@ typedef struct uint32_t Rank; /*!< Specify the rank in the regular group sequencer. This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by + Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. @@ -245,7 +229,7 @@ typedef struct Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t OffsetNumber; /*!< Select the offset number @@ -254,12 +238,12 @@ typedef struct uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ -}ADC_ChannelConfTypeDef; +} ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog @@ -284,21 +268,29 @@ typedef struct For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ - uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits + the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits - the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ -}ADC_AnalogWDGConfTypeDef; + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits + the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ +} ADC_AnalogWDGConfTypeDef; /** * @brief ADC group injected contexts queue configuration @@ -306,12 +298,12 @@ typedef struct */ typedef struct { - uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each + uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ - + uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ -}ADC_InjectionConfigTypeDef; +} ADC_InjectionConfigTypeDef; /** @defgroup ADC_States ADC States * @{ @@ -321,65 +313,102 @@ typedef struct * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. - * For example: - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ /** * @} */ -/** +/** * @brief ADC handle Structure definition */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else typedef struct +#endif { ADC_TypeDef *Instance; /*!< Register base address */ - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - __IO uint32_t ErrorCode; /*!< ADC Error code */ - ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ -}ADC_HandleTypeDef; +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ + void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ + void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ + void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ + void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ + HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} @@ -395,12 +424,15 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, - enable/disable, erroneous state, ...) */ -#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ @@ -424,10 +456,6 @@ typedef struct #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ - -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ /** * @} */ @@ -455,8 +483,8 @@ typedef struct /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ -#define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */ -#define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ /** * @} */ @@ -466,22 +494,22 @@ typedef struct */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ -#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -489,10 +517,10 @@ typedef struct /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ /** * @} */ @@ -611,7 +639,7 @@ typedef struct /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ @@ -689,17 +717,17 @@ typedef struct /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ -#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ -#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ -#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ +#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ @@ -749,15 +777,6 @@ typedef struct /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__ ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) - /** * @brief Return resolution bits in CFGR register RES[1:0] field. * @param __HANDLE__ ADC handle @@ -771,7 +790,7 @@ typedef struct * @param __HANDLE__ ADC handle * @retval None */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Verification of ADC state: enabled or disabled. @@ -786,7 +805,7 @@ typedef struct /** * @brief Check if conversion is on going on regular group. * @param __HANDLE__ ADC handle - * @retval SET (conversion is on going) or RESET (no conversion is on going) + * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) @@ -803,34 +822,31 @@ typedef struct /** * @brief Verify that a given value is aligned with the ADC resolution range. * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). - * @param __ADC_VALUE__ value checked against the resolution. + * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ -#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) ) +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) /** * @brief Verify the length of the scheduled regular conversions group. - * @param __LENGTH__ number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ -#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U))) +#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. - * @param NUMBER number of scheduled regular conversions in discontinuous mode. - * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large) + * @param NUMBER number of scheduled regular conversions in discontinuous mode. + * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) /** * @brief Verify the ADC clock setting. - * @param __ADC_CLOCK__ programmed ADC clock. + * @param __ADC_CLOCK__ programmed ADC clock. * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) */ #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ @@ -847,29 +863,29 @@ typedef struct ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) /** * @brief Verify the ADC resolution setting. - * @param __RESOLUTION__ programmed ADC resolution. + * @param __RESOLUTION__ programmed ADC resolution. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) - -/** + +/** * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. - * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. + * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) - */ + */ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) /** * @brief Verify the ADC converted data alignment. - * @param __ALIGN__ programmed ADC converted data alignment. + * @param __ALIGN__ programmed ADC converted data alignment. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) */ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ @@ -961,7 +977,7 @@ typedef struct /** * @brief Verify the ADC regular channel setting. - * @param __CHANNEL__ programmed ADC regular channel. + * @param __CHANNEL__ programmed ADC regular channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ @@ -999,7 +1015,7 @@ typedef struct /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ @@ -1026,8 +1042,17 @@ typedef struct * @param __HANDLE__ ADC handle * @retval None */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif /** * @brief Enable ADC interrupt. @@ -1044,7 +1069,7 @@ typedef struct * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1065,7 +1090,7 @@ typedef struct * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1085,28 +1110,28 @@ typedef struct * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) - + /** * @brief Check whether the specified ADC flag is set or not. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ @@ -1117,17 +1142,17 @@ typedef struct * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ @@ -1192,7 +1217,7 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) /** * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x @@ -1244,7 +1269,7 @@ typedef struct * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) /** * @brief Helper macro to determine whether the selected channel @@ -1305,7 +1330,7 @@ typedef struct * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) /** * @brief Helper macro to convert a channel defined from parameter @@ -1380,7 +1405,7 @@ typedef struct * @arg @ref ADC_CHANNEL_18 */ #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) /** * @brief Helper macro to determine whether the internal channel @@ -1417,7 +1442,7 @@ typedef struct * Value "1" if the internal channel selected is available on the ADC instance selected. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -1434,7 +1459,7 @@ typedef struct * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) + __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) #endif /** @@ -1448,7 +1473,7 @@ typedef struct * @retval ADC common register instance */ #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ - __LL_ADC_COMMON_INSTANCE((__ADCx__)) + __LL_ADC_COMMON_INSTANCE((__ADCx__)) /** * @brief Helper macro to check if all ADC instances sharing the same @@ -1468,7 +1493,7 @@ typedef struct * is enabled. */ #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) /** * @brief Helper macro to define the ADC conversion data full-scale digital @@ -1481,15 +1506,15 @@ typedef struct * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) + * @retval ADC conversion data full-scale digital value */ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted + * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B @@ -1507,9 +1532,9 @@ typedef struct #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ - __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ - (__ADC_RESOLUTION_CURRENT__),\ - (__ADC_RESOLUTION_TARGET__)) + __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ + (__ADC_RESOLUTION_CURRENT__), \ + (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -1530,9 +1555,9 @@ typedef struct #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ - (__ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -1561,8 +1586,8 @@ typedef struct */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1612,9 +1637,9 @@ typedef struct #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1666,12 +1691,12 @@ typedef struct __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ - (__TEMPSENSOR_TYP_CALX_V__),\ - (__TEMPSENSOR_CALX_TEMP__),\ - (__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ + (__TEMPSENSOR_TYP_CALX_V__), \ + (__TEMPSENSOR_CALX_TEMP__), \ + (__VREFANALOG_VOLTAGE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @} @@ -1694,10 +1719,17 @@ typedef struct * @{ */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ @@ -1709,39 +1741,39 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); /* IO operation functions *****************************************************/ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ + * @brief Peripheral Control functions + * @{ + */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} @@ -1751,7 +1783,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @@ -1766,9 +1798,9 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @addtogroup ADC_Private_Functions ADC Private Functions * @{ */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma); @@ -1790,6 +1822,6 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma); #endif -#endif /* __STM32L4xx_HAL_ADC_H */ +#endif /* STM32L4xx_HAL_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c index 249566e9a9..8b30389381 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_adc_ex.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions @@ -16,11 +16,11 @@ * ++ Channels configuration on ADC group injected * + State functions * ++ ADC group injected contexts queue management - * Other functions (generic functions) are available in file + * Other functions (generic functions) are available in file * "stm32l4xx_hal_adc.c". * @verbatim - [..] + [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32l4xx_hal_adc.c". [..] @@ -28,29 +28,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -76,21 +60,20 @@ * @{ */ -#define ADC_JSQR_FIELDS ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ - ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ - ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime - once the ADC is enabled */ - +#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ + ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ + ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime + once the ADC is enabled */ + /* Fixed timeout value for ADC calibration. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -/* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value */ -/* according to Data sheet), calibration_time MAX = 112 / f_ADC */ -/* 112 / 140,000 = 0.8 ms */ -/* At maximum CPU speed (80 MHz), this means */ -/* 0.8 ms * 80 MHz = 64000 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (64000U) /*!< ADC calibration time-out value */ - +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ +/* source PLL SAI 8MHz, ADC clock prescaler 256), CPU frequency 80MHz. */ +/* Calibration time max = 116 / fADC (refer to datasheet) */ +/* = 296 960 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (296960UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ + /** * @} */ @@ -112,7 +95,7 @@ ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: - + (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @@ -123,7 +106,7 @@ (+) Get result of ADC group injected channel conversion. (+) Start conversion of ADC group injected and enable interruptions. (+) Stop conversion of ADC group injected and disable interruptions. - + (+) When multimode feature is available, start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. @@ -143,57 +126,52 @@ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t WaitLoopIndex = 0; - + HAL_StatusTypeDef tmp_hal_status; + __IO uint32_t wait_loop_index = 0UL; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Calibration prerequisite: ADC must be disabled. */ - + /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Start ADC calibration in mode single-ended or differential */ + LL_ADC_StartCalibration(hadc->Instance, SingleDiff); - /* Select calibration mode single ended or differential ended */ - MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff); - - /* Start ADC calibration */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL); - /* Wait for calibration completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { - WaitLoopIndex++; - if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT) + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } } - + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, @@ -202,14 +180,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -222,21 +200,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + /* Return the selected ADC calibration value */ - if (SingleDiff == ADC_DIFFERENTIAL_ENDED) - { - return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); - } - else - { - return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S); - } + return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); } /** @@ -249,32 +220,32 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - assert_param(IS_ADC_CALFACT(CalibrationFactor)); - + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + assert_param(IS_ADC_CALFACT(CalibrationFactor)); + /* Process locked */ __HAL_LOCK(hadc); - + /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ - if ( (ADC_IS_ENABLE(hadc) != RESET) && - (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) ) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { /* Set the selected ADC calibration value */ - if (SingleDiff == ADC_DIFFERENTIAL_ENDED) - { - MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor)); - } - else - { - MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor); - } + LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); } else { @@ -282,14 +253,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Update ADC error code */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -297,414 +268,97 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 /** * @brief Enable ADC, start conversion of injected group. * @note Interruptions enabled in this function: None. - * @note Case of multimode enabled when multimode feature is available: - * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, - * then for ADC master. - * For ADC slave, ADC is enabled only (conversion is not started). + * @note Case of multimode enabled when multimode feature is available: + * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, + * then for ADC master. + * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_config_injected_queue; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) + + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { - - /* In case of software trigger detection enabled, JQDIS must be set + /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ - if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET) - && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET)) + tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + && (tmp_config_injected_queue == 0UL) + ) { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } - /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + +#if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - - /* Clear ADC group injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable conversion of injected group, if automatic injected conversion */ - /* is disabled. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ - /* if ADC is slave, */ - /* - ADC is enabled only (conversion is not started). */ - /* - if multimode only concerns regular conversion, ADC is enabled */ - /* and conversion is started. */ - /* If ADC is master or independent, */ - /* - ADC is enabled and conversion is started. */ - - /* Are injected conversions that of a dual Slave ? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) - { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - set ADSTART only if JAUTO is cleared */ - if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) - { - SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; - } - } - else - { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - ADSTART is not set */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - /* Return function status */ - return tmp_hal_status; - } -} - -/** - * @brief Stop conversion of injected channels. Disable ADC peripheral if - * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @note In case of multimode enabled (when multimode feature is available), - * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. - * For ADC master, conversion is stopped and ADC is disabled. - * For ADC slave, ADC is disabled only (conversion stop of ADC master - * has already stopped conversion of ADC slave). - * @param hadc ADC handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going on injected group only. */ - tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - - /* Disable ADC peripheral if injected conversions are effectively stopped */ - /* and if no conversion on regular group is on-going */ - if (tmp_hal_status == HAL_OK) - { - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - /* Conversion on injected group is stopped, but ADC not disabled since */ - /* conversion on regular group is still running. */ - else - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for injected group conversion to be completed. - * @param hadc ADC handle - * @param Timeout Timeout value in millisecond. - * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is - * checked and cleared depending on AUTDLY bit status. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - uint32_t tmp_Flag_End = 0U; - uint32_t tmp_cfgr = 0U; - ADC_TypeDef *tmpADC_Master; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* If end of sequence selected */ - if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) - { - tmp_Flag_End = ADC_FLAG_JEOS; - } - else /* end of conversion selected */ - { - tmp_Flag_End = ADC_FLAG_JEOC; - } - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait until End of Conversion or Sequence flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - /* Get relevant register CFGR in ADC instance of ADC master or slave */ - /* in function of multimode state (for devices with multimode */ - /* available). */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == SET) - { - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger or by automatic injected conversion */ - /* from group regular. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) - { - /* Check whether end of sequence is reached */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) - { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - } - } - - /* Clear polled flag */ - if (tmp_Flag_End == ADC_FLAG_JEOS) - { - /* Clear end of sequence JEOS flag of injected group if low power feature */ - /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ - /* For injected groups, no new conversion will start before JEOS is */ - /* cleared. */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) - { - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - } - } - else - { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - } - - /* Return API HAL status */ - return HAL_OK; -} - -/** - * @brief Enable ADC, start conversion of injected group with interruption. - * @note Interruptions enabled in this function according to initialization - * setting : JEOC (end of conversion) or JEOS (end of sequence) - * @note Case of multimode enabled (when multimode feature is enabled): - * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, - * then for ADC master. - * For ADC slave, ADC is enabled only (conversion is not started). - * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc ADC handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) - { - return HAL_BUSY; - } - else - { - /* In case of software trigger detection enabled, JQDIS must be set - (which can be done only if ADSTART and JADSTART are both cleared). - If JQDIS is not set at that point, returns an error - - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means - the queue is empty */ - if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET) - && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Check if a regular conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - } - else - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } +#endif /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - - /* Enable ADC Injected context queue overflow interrupt if this feature */ - /* is enabled. */ - if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) - { - __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); - } - - /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; - } - + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -717,80 +371,82 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ - - /* Are injected conversions that of a dual Slave ? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - set ADSTART only if JAUTO is cleared */ - if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { - SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; + LL_ADC_INJ_StartConversion(hadc->Instance); } } else { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - ADSTART is not set */ - SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } +#else + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + /* Start ADC group injected conversion */ + LL_ADC_INJ_StartConversion(hadc->Instance); + } +#endif + } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } } /** - * @brief Stop conversion of injected channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no regular conversion - * is on going. - * @note If ADC must be disabled and if conversion is on going on + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, - * then for ADC slave. - * For ADC master, conversion is stopped and ADC is disabled. + * @note In case of multimode enabled (when multimode feature is available), + * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. + * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). - * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. - * @param hadc ADC handle + * @param hadc ADC handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - + /* Disable ADC peripheral if injected conversions are effectively stopped */ - /* and if no conversion on the other group (regular group) is intended to */ - /* continue. */ + /* and if no conversion on regular group is on-going */ if (tmp_hal_status == HAL_OK) { - /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -811,7 +467,376 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Process unlocked */ __HAL_UNLOCK(hadc); - + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for injected group conversion to be completed. + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is + * checked and cleared depending on AUTDLY bit status. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_Flag_End; + uint32_t tmp_adc_inj_is_trigger_source_sw_start; + uint32_t tmp_adc_reg_is_trigger_source_sw_start; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of sequence selected */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_Flag_End = ADC_FLAG_JEOS; + } + else /* end of conversion selected */ + { + tmp_Flag_End = ADC_FLAG_JEOC; + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait until End of Conversion or Sequence flag is raised */ + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + /* Retrieve ADC configuration */ + tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); + tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger or by automatic injected conversion */ + /* from group regular. */ + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + { + /* Check whether end of sequence is reached */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + { + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + } + + /* Clear polled flag */ + if (tmp_Flag_End == ADC_FLAG_JEOS) + { + /* Clear end of sequence JEOS flag of injected group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ + /* For injected groups, no new conversion will start before JEOS is */ + /* cleared. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) + { + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + } + } + else + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + } + + /* Return API HAL status */ + return HAL_OK; +} + +/** + * @brief Enable ADC, start conversion of injected group with interruption. + * @note Interruptions enabled in this function according to initialization + * setting : JEOC (end of conversion) or JEOS (end of sequence) + * @note Case of multimode enabled (when multimode feature is enabled): + * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, + * then for ADC master. + * For ADC slave, ADC is enabled only (conversion is not started). + * For ADC master, ADC is enabled and multimode conversion is started. + * @param hadc ADC handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_config_injected_queue; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) + { + return HAL_BUSY; + } + else + { + /* In case of software trigger detection enabled, JQDIS must be set + (which can be done only if ADSTART and JADSTART are both cleared). + If JQDIS is not set at that point, returns an error + - since software trigger detection is disabled. User needs to + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + the queue is empty */ + tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + && (tmp_config_injected_queue == 0UL) + ) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Check if a regular conversion is ongoing */ + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) + { + /* Reset ADC error code field related to injected conversions only */ + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + } + else + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif + + /* Clear ADC group injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC Injected context queue overflow interrupt if this feature */ + /* is enabled. */ + if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); + } + + /* Enable ADC end of conversion interrupt */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + + /* Enable conversion of injected group, if automatic injected conversion */ + /* is disabled. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled (when multimode feature is available): */ + /* if ADC is slave, */ + /* - ADC is enabled only (conversion is not started), */ + /* - if multimode only concerns regular conversion, ADC is enabled */ + /* and conversion is started. */ + /* If ADC is master or independent, */ + /* - ADC is enabled and conversion is started. */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + LL_ADC_INJ_StartConversion(hadc->Instance); + } + } + else + { + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#else + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + /* Start ADC group injected conversion */ + LL_ADC_INJ_StartConversion(hadc->Instance); + } +#endif + + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; + } +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, + * then for ADC slave. + * For ADC master, conversion is stopped and ADC is disabled. + * For ADC slave, ADC is disabled only (conversion stop of ADC master + * has already stopped conversion of ADC slave). + * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going on injected group only. */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); + + /* Disable ADC peripheral if injected conversions are effectively stopped */ + /* and if no conversion on the other group (regular group) is intended to */ + /* continue. */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); + + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + /* Conversion on injected group is stopped, but ADC not disabled since */ + /* conversion on regular group is still running. */ + else + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + /* Return function status */ return tmp_hal_status; } @@ -819,22 +844,22 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. - * @note Multimode must have been previously configured using + * @note Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: - * overrun, DMA half transfer, DMA transfer complete. + * overrun, DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. - * @note State field of Slave ADC handle is not updated in this configuration: - * user should not rely on it for information related to Slave regular - * conversions. + * @note State field of Slave ADC handle is not updated in this configuration: + * user should not rely on it for information related to Slave regular + * conversions. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @param pData Destination Buffer address. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; ADC_Common_TypeDef *tmpADC_Common; @@ -843,8 +868,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) + + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } @@ -855,18 +880,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); @@ -874,7 +899,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t { tmp_hal_status = ADC_Enable(&tmphadcSlave); } - + /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) { @@ -882,40 +907,40 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - + /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; - + /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); - + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -928,7 +953,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Process unlocked */ __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } @@ -937,113 +962,120 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /** * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. * @note Multimode is kept enabled after this function. MultiMode DMA bits - * (MDMA and DMACFG bits of common CCR register) are maintained. To disable - * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be + * (MDMA and DMACFG bits of common CCR register) are maintained. To disable + * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can * resort to HAL_ADCEx_DisableMultiMode() API. - * @note In case of DMA configured in circular mode, function + * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; - + uint32_t tmphadcSlave_conversion_on_going; + HAL_StatusTypeDef tmphadcSlave_disable_status; + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - - + + /* 1. Stop potential multimode conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) - { + { /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ - - /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ - tickstart = HAL_GetTick(); - - while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || - ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) + + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ + tickstart = HAL_GetTick(); + + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } + + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADC_Stop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_ERROR) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripherals: master and slave */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { - /* Check if ADC are effectively disabled */ - if ((ADC_Disable(hadc) == HAL_OK) && - (ADC_Disable(&tmphadcSlave) == HAL_OK) ) + tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave); + if ((ADC_Disable(hadc) == HAL_OK) && + (tmphadcSlave_disable_status == HAL_OK)) { tmp_hal_status = HAL_OK; } } else { - ADC_Disable(hadc); - ADC_Disable(&tmphadcSlave); + /* In case of error, attempt to disable ADC master and slave without status assert */ + (void) ADC_Disable(hadc); + (void) ADC_Disable(&tmphadcSlave); } - + /* Set ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1053,16 +1085,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { - ADC_Common_TypeDef *tmpADC_Common; - + const ADC_Common_TypeDef *tmpADC_Common; + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ + UNUSED(hadc); + /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - + /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } @@ -1072,7 +1108,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). - * @note This function does not clear ADC flag JEOS + * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent @@ -1083,9 +1119,9 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). - * To clear this flag, either use function: + * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADCEx_InjectedPollForConversion() + * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. @@ -1096,24 +1132,24 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { - uint32_t tmp_jdr = 0; - + uint32_t tmp_jdr; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - + /* Get ADC converted value */ - switch(InjectedRank) - { + switch (InjectedRank) + { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; - case ADC_INJECTED_RANK_3: + case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; - case ADC_INJECTED_RANK_2: + case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: @@ -1121,8 +1157,8 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa tmp_jdr = hadc->Instance->JDR1; break; } - - /* Return ADC converted value */ + + /* Return ADC converted value */ return tmp_jdr; } @@ -1131,11 +1167,11 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ @@ -1150,11 +1186,11 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ @@ -1165,11 +1201,11 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ @@ -1180,11 +1216,11 @@ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ @@ -1196,48 +1232,48 @@ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } /** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral if no + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if regular conversions are effectively stopped + + /* Disable ADC peripheral if regular conversions are effectively stopped and if no injected conversions are on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1254,10 +1290,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1271,32 +1307,32 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Disable all regular-related interrupts */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* 2. Disable ADC peripheral if no injected conversions are on-going */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) - { + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { tmp_hal_status = ADC_Disable(hadc); /* if no issue reported */ if (tmp_hal_status == HAL_OK) @@ -1312,76 +1348,76 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral if no conversion is on going * on injected group. - * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. - * For multimode (when multimode feature is available), + * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. + * For multimode (when multimode feature is available), * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + HAL_StatusTypeDef tmp_hal_status; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped + + /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ + /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ - /* memory a potential failing status. */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) - { + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { - ADC_Disable(hadc); + (void)ADC_Disable(hadc); } - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1393,13 +1429,13 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) } else { - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1408,124 +1444,129 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits - * (MDMA and DMACFG bits of common CCR register) are maintained. To disable - * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be + * (MDMA and DMACFG bits of common CCR register) are maintained. To disable + * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can - * resort to HAL_ADCEx_DisableMultiMode() API. - * @note In case of DMA configured in circular mode, function + * resort to HAL_ADCEx_DisableMultiMode() API. + * @note In case of DMA configured in circular mode, function * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; - + uint32_t tmphadcSlave_conversion_on_going; + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - - + + /* 1. Stop potential multimode conversion on going, on regular groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ - - /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ - tickstart = HAL_GetTick(); - - while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || - ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) + + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ + tickstart = HAL_GetTick(); + + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } + + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADCEx_RegularStop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripherals: master and slave if no injected */ /* conversion is on-going. */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) - { - tmp_hal_status = ADC_Disable(hadc); - if (tmp_hal_status == HAL_OK) - { - if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET) - { - tmp_hal_status = ADC_Disable(&tmphadcSlave); - } - } - } - - if (tmp_hal_status == HAL_OK) - { - /* Both Master and Slave ADC's could be disabled. Update Master State */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); - } - else - { - /* injected (Master or Slave) conversions are still on-going, - no Master State change */ - } + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(hadc); + if (tmp_hal_status == HAL_OK) + { + if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(&tmphadcSlave); + } + } + } + + if (tmp_hal_status == HAL_OK) + { + /* Both Master and Slave ADC's could be disabled. Update Master State */ + /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + } + else + { + /* injected (Master or Slave) conversions are still on-going, + no Master State change */ + } } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1538,7 +1579,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions * @brief ADC Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== @@ -1548,7 +1589,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) (+) Enable or Disable Injected Queue (+) Disable ADC voltage regulator (+) Enter ADC deep-power-down mode - + @endverbatim * @{ */ @@ -1556,45 +1597,48 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Configure a channel to be assigned to ADC group injected. * @note Possibility to update parameters on the fly: - * This function initializes injected group, following calls to this + * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_InjectionConfTypeDef". * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function + * These internal paths can be disabled using function * HAL_ADC_DeInit(). - * @note Caution: For Injected Context Queue use, a context must be fully - * defined before start of injected conversion. All channels are configured - * consecutively for the same ADC instance. Therefore, the number of calls to - * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter + * @note Caution: For Injected Context Queue use, a context must be fully + * defined before start of injected conversion. All channels are configured + * consecutively for the same ADC instance. Therefore, the number of calls to + * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter * InjectedNbrOfConversion for each context. - * - Example 1: If 1 context is intended to be used (or if there is no use of the - * Injected Queue Context feature) and if the context contains 3 injected ranks - * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be - * called once for each channel (i.e. 3 times) before starting a conversion. - * This function must not be called to configure a 4th injected channel: + * - Example 1: If 1 context is intended to be used (or if there is no use of the + * Injected Queue Context feature) and if the context contains 3 injected ranks + * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be + * called once for each channel (i.e. 3 times) before starting a conversion. + * This function must not be called to configure a 4th injected channel: * it would start a new context into context queue. - * - Example 2: If 2 contexts are intended to be used and each of them contains - * 3 injected ranks (InjectedNbrOfConversion = 3), - * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and - * for each context (3 channels x 2 contexts = 6 calls). Conversion can - * start once the 1st context is set, that is after the first three + * - Example 2: If 2 contexts are intended to be used and each of them contains + * 3 injected ranks (InjectedNbrOfConversion = 3), + * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and + * for each context (3 channels x 2 contexts = 6 calls). Conversion can + * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; - uint32_t wait_loop_index = 0U; - + uint32_t tmp_config_internal_channel; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + __IO uint32_t wait_loop_index = 0; + uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); @@ -1606,38 +1650,38 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } - - - /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + + + /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); - + assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); + /* JDISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - + assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + /* DISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + /* Verification of channel number */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel)); } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Configuration of injected group sequencer: */ /* Hardware constraint: Must fully define injected context register JSQR */ /* before make it entering into injected sequencer queue. */ @@ -1658,9 +1702,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ - + if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1U) ) + (sConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1668,7 +1712,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - external trigger to start conversion */ /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ - + if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ @@ -1678,20 +1722,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } - - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); + + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; - + } } else @@ -1703,10 +1747,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* calls of this function, for each injected channel rank: */ /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger. */ - + /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ - if (hadc->InjectionConfig.ChannelCount == 0U) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ @@ -1714,13 +1758,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ - hadc->InjectionConfig.ContextQueue = 0x00000000U; - + hadc->InjectionConfig.ContextQueue = 0x00000000U; + /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ /* - external trigger to start conversion */ /* - external trigger polarity */ - + /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ @@ -1728,39 +1772,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); } - + } - + /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); - + /* Set the JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); - + /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; - + /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() - call, aggregate the setting to those already built during the previous + call, aggregate the setting to those already built during the previous HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; - + /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) { - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } } @@ -1771,25 +1815,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* enable (context decremented, up to 2 contexts queued) */ /* - Injected discontinuous mode: can be enabled only if auto-injected */ /* mode is disabled. */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* If auto-injected mode is disabled: no constraint */ if (sConfigInjected->AutoInjectedConv == DISABLE) - { - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) ); + { + MODIFY_REG(hadc->Instance->CFGR, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) ); + MODIFY_REG(hadc->Instance->CFGR, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); } } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -1797,21 +1843,26 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* external triggers are disabled. */ /* - Channel sampling time */ /* - Channel offset */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } - else - { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } + if (sConfigInjected->AutoInjectedConv == ENABLE) + { + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } + else + { + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } } /* If Automatic injected conversion was intended to be set and could not */ /* due to injected group external triggers enabled, error is reported. */ @@ -1821,77 +1872,78 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } else { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } - + if (sConfigInjected->InjecOversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); - + /* JOVSE must be reset in case of triggered regular mode */ - assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS))); - + assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); + /* Configuration of Injected Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ - + /* Enable OverSampling mode */ - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_JOVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS, - ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift - ); + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + sConfigInjected->InjecOversampling.Ratio | + sConfigInjected->InjecOversampling.RightBitShift + ); } else { /* Disable Regular OverSampling */ - CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } - + #if defined(ADC_SMPR1_SMPPLUS) - /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ - if(sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); - - /* Set ADC sampling time common configuration */ - LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); - } - else - { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); - - /* Set ADC sampling time common configuration */ - LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); - } -#else + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); + } + else + { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); + } +#else + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); #endif - + /* Configure the offset: offset enable/disable, channel, offset value */ - + /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); - - if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + + if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); - + LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, + tmpOffsetShifted); + } else { @@ -1899,110 +1951,101 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* If this is the case, the corresponding offset number is disabled. */ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } } - + } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ - if (ADC_IS_ENABLE(hadc) == RESET) + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); - + /* Configuration of differential mode */ + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); } - - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ - /* internal measurement paths enable: If internal channel selected, */ - /* enable dedicated internal buffers and path. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit(). */ - /* Configuration of common ADC parameters */ + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit(). */ + + if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) + if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { - /* Configuration of common ADC parameters (continuation) */ - /* Software is allowed to change common parameters only when all ADCs */ - /* of the common group are disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while (wait_loop_index != 0UL) { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) - { - wait_loop_index--; - } - } + wait_loop_index--; } - else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) - { - if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } - } - else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) - { - if (ADC_VREFINT_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } - } - } - /* If the requested internal measurement path has already been enabled */ - /* and other ADC of the common group are enabled, internal */ - /* measurement paths cannot be enabled. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; } } - + else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + { + if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); + } + } + else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + if (ADC_VREFINT_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + } + else + { + /* nothing to do */ + } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2011,12 +2054,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: - * This function initializes multimode parameters, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_MultiModeTypeDef" on the fly, without resetting + * This function initializes multimode parameters, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_MultiModeTypeDef" on the fly, without resetting * the ADCs. * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). @@ -2024,57 +2067,59 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I * @param multimode Structure of ADC multimode configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { - HAL_StatusTypeDef tmp_hal_status = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSlave; - + uint32_t tmphadcSlave_conversion_on_going; + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MULTIMODE(multimode->Mode)); - if(multimode->Mode != ADC_MODE_INDEPENDENT) + if (multimode->Mode != ADC_MODE_INDEPENDENT) { assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } - + /* Process locked */ __HAL_LOCK(hadc); - + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ - if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) ) + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + && (tmphadcSlave_conversion_on_going == 0UL)) { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - - /* If multimode is selected, configure all multimode paramaters. */ + + /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ - if(multimode->Mode != ADC_MODE_INDEPENDENT) + if (multimode->Mode != ADC_MODE_INDEPENDENT) { - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, + MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, multimode->DMAAccessMode | - ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests)); - + ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ @@ -2085,26 +2130,24 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { - MODIFY_REG(tmpADC_Common->CCR, - ADC_CCR_DUAL | - ADC_CCR_DELAY, - multimode->Mode | - multimode->TwoSamplingDelay - ); + MODIFY_REG(tmpADC_Common->CCR, + ADC_CCR_DUAL | + ADC_CCR_DELAY, + multimode->Mode | + multimode->TwoSamplingDelay + ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); - + /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); } @@ -2116,119 +2159,161 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; -} +} #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable Injected Queue * @note This function resets CFGR register JQDIS bit in order to enable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) { - /* Parameter can be set only if no conversion is on-going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + /* Parameter can be set only if no conversion is on-going */ + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - + /* Update state, clear previous result related to injected queue overflow */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - return HAL_OK; + + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** * @brief Disable Injected Queue * @note This function sets CFGR register JQDIS bit in order to disable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) { - /* Parameter can be set only if no conversion is on-going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + /* Parameter can be set only if no conversion is on-going */ + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) { - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - return HAL_OK; + LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE); + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** * @brief Disable ADC voltage regulator. * @note Disabling voltage regulator allows to save power. This operation can * be carried out only when ADC is disabled. - * @note To enable again the voltage regulator, the user is expected to - * resort to HAL_ADC_Init() API. + * @note To enable again the voltage regulator, the user is expected to + * resort to HAL_ADC_Init() API. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) { - /* ADVREGEN can be written only when the ADC is disabled */ - if (ADC_IS_ENABLE(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { - CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN); - return HAL_OK; + LL_ADC_DisableInternalRegulator(hadc->Instance); + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** * @brief Enter ADC deep-power-down mode - * @note This mode is achieved in setting DEEPPWD bit and allows to save power - * in reducing leakage currents. It is particularly interesting before + * @note This mode is achieved in setting DEEPPWD bit and allows to save power + * in reducing leakage currents. It is particularly interesting before * entering stop modes. * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the * ADC voltage regulator. This means that this API encompasses * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal - * calibration is lost. - * @note To exit the ADC deep-power-down mode, the user is expected to + * calibration is lost. + * @note To exit the ADC deep-power-down mode, the user is expected to * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) { - /* DEEPPWD can be written only when the ADC is disabled */ - if (ADC_IS_ENABLE(hadc) == RESET) + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { - SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - return HAL_OK; + LL_ADC_EnableDeepPowerDown(hadc->Instance); + tmp_hal_status = HAL_OK; } else { - return HAL_ERROR; + tmp_hal_status = HAL_ERROR; } + + return tmp_hal_status; } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h index 042c3b7548..82b0d86a2b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_ADC_EX_H -#define __STM32L4xx_HAL_ADC_EX_H +#ifndef STM32L4xx_HAL_ADC_EX_H +#define STM32L4xx_HAL_ADC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,26 +34,26 @@ /** @addtogroup ADCEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types * @{ */ -/** +/** * @brief ADC Injected Conversion Oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ - + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ -}ADC_InjOversamplingTypeDef; +} ADC_InjOversamplingTypeDef; -/** +/** * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset @@ -80,20 +64,20 @@ typedef struct * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. - * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going + * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * on ADC groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ -typedef struct +typedef struct { uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. - This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS. - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by + This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. + Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. @@ -116,7 +100,7 @@ typedef struct Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. @@ -127,27 +111,27 @@ typedef struct Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. + Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one - This parameter can be set to ENABLE or DISABLE. + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one + This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. @@ -155,14 +139,14 @@ typedef struct Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. + FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a - new injected context is set when queue is full, error is triggered by interruption and through function + new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ @@ -175,27 +159,27 @@ typedef struct uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADC_injected_external_trigger_edge. If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. + Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -}ADC_InjectionConfTypeDef; +} ADC_InjectionConfTypeDef; #if defined(ADC_MULTIMODE_SUPPORT) -/** +/** * @brief Structure definition of ADC multimode * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). * Both Master and Slave ADCs must be disabled. */ typedef struct { - uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. + uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: @@ -204,10 +188,10 @@ typedef struct uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. - Delay range depends on selected resolution: + Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ -}ADC_MultiModeTypeDef; +} ADC_MultiModeTypeDef; #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -225,22 +209,22 @@ typedef struct */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -248,10 +232,10 @@ typedef struct /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ @@ -277,7 +261,7 @@ typedef struct * @} */ -/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks +/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ @@ -304,7 +288,7 @@ typedef struct /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ -#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** @@ -366,7 +350,7 @@ typedef struct /** * @} */ - + /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ @@ -374,7 +358,7 @@ typedef struct #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ - ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) + ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) #else #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ @@ -385,7 +369,7 @@ typedef struct * @} */ -/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields +/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion @@ -403,7 +387,7 @@ typedef struct /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} @@ -421,16 +405,16 @@ typedef struct * @{ */ -/** @brief Force ADC instance in multimode mode independant (multimode disable). +/** @brief Force ADC instance in multimode mode independent (multimode disable). * @note This macro must be used only in case of transition from multimode * to mode independent and in case of unknown previous state, * to ensure ADC configuration is in mode independent. * @note Standard way of multimode configuration change is done from * HAL ADC handle of ADC master using function * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". - * Usage of this macro is not the Standard way of multimode - * configuration and can lead to have HAL ADC handles status - * misaligned. Usage of this macro must be limited to cases + * Usage of this macro is not the Standard way of multimode + * configuration and can lead to have HAL ADC handles status + * misaligned. Usage of this macro must be limited to cases * mentionned above. * @param __HANDLE__ ADC handle. * @retval None @@ -458,21 +442,21 @@ typedef struct * @retval SET (software start) or RESET (external trigger). */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) + (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) /** * @brief Check if conversion is on going on regular or injected groups. * @param __HANDLE__ ADC handle. * @retval SET (conversion is on going) or RESET (no conversion is on going). */ -#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ +#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ + (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ ) ? RESET : SET) /** * @brief Check if conversion is on going on injected group. * @param __HANDLE__ ADC handle. - * @retval SET (conversion is on going) or RESET (no conversion is on going). + * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) @@ -480,7 +464,7 @@ typedef struct /** * @brief Check whether or not ADC is independent. * @param __HANDLE__ ADC handle. - * @note When multimode feature is not available, the macro always returns SET. + * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) @@ -493,12 +477,14 @@ typedef struct ) #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) +#elif defined (STM32L412xx) || defined (STM32L422xx) +#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) #endif /** * @brief Set the selected injected Channel rank. * @param __CHANNELNB__ Channel number. - * @param __RANKNB__ Rank number. + * @param __RANKNB__ Rank number. * @retval None */ #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) @@ -529,7 +515,7 @@ typedef struct * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. * @retval None */ -#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos) +#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. @@ -564,7 +550,7 @@ typedef struct * @param __CHANNEL__ ADC Channel. * @retval None */ -#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) +#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) /** * @brief Configure calibration factor in differential mode to be set into calibration register. @@ -585,7 +571,7 @@ typedef struct * @param __THRESHOLD__ Threshold value. * @retval None */ -#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16) +#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -595,48 +581,9 @@ typedef struct */ #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) #endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @brief Enable the ADC peripheral. - * @param __HANDLE__ ADC handle. - * @retval None - */ -#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) /** - * @brief Verification of hardware constraints before ADC can be enabled. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) - */ -#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \ - ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ - ) == RESET \ - ) ? SET : RESET) - -/** - * @brief Disable the ADC peripheral. - * @param __HANDLE__ ADC handle. - * @retval None - */ -#define ADC_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ - __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ - } while(0) - -/** - * @brief Verification of hardware constraints before ADC can be disabled. - * @param __HANDLE__ ADC handle. - * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) - */ -#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ - ) ? SET : RESET) - -/** - * @brief Shift the offset with respect to the selected ADC resolution. + * @brief Shift the offset with respect to the selected ADC resolution. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. @@ -648,8 +595,7 @@ typedef struct * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ - ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) - + ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. @@ -664,7 +610,7 @@ typedef struct * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) + ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. @@ -677,29 +623,11 @@ typedef struct * @param __THRESHOLD__ Value to be shifted * @retval None */ -#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ - ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ - ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ - (__THRESHOLD__) << 2 ) - -/** - * @brief Report Master Instance. - * @param __HANDLE__ ADC handle. - * @note Return same instance if ADC of input handle is independent ADC or if - * multimode feature is not available. - * @retval Master Instance - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_MASTER_REGISTER(__HANDLE__) \ - ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ - )? \ - ((__HANDLE__)->Instance) \ - : \ - (ADC1) \ +#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ + ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ + ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ + ((__THRESHOLD__) << 2UL) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance) -#endif /** * @brief Clear Common Control Register. @@ -707,150 +635,27 @@ typedef struct * @retval None */ #if defined(ADC_MULTIMODE_SUPPORT) -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ - ADC_CCR_PRESC | \ - ADC_CCR_VBATEN | \ - ADC_CCR_TSEN | \ - ADC_CCR_VREFEN | \ - ADC_CCR_MDMA | \ - ADC_CCR_DMACFG | \ - ADC_CCR_DELAY | \ - ADC_CCR_DUAL ) +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ + ADC_CCR_CKMODE | \ + ADC_CCR_PRESC | \ + ADC_CCR_VBATEN | \ + ADC_CCR_TSEN | \ + ADC_CCR_VREFEN | \ + ADC_CCR_MDMA | \ + ADC_CCR_DMACFG | \ + ADC_CCR_DELAY | \ + ADC_CCR_DUAL) #else -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ - ADC_CCR_PRESC | \ - ADC_CCR_VBATEN | \ - ADC_CCR_TSEN | \ - ADC_CCR_VREFEN ) +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ + ADC_CCR_CKMODE | \ + ADC_CCR_PRESC | \ + ADC_CCR_VBATEN | \ + ADC_CCR_TSEN | \ + ADC_CCR_VREFEN) #endif /* ADC_MULTIMODE_SUPPORT */ -/** - * @brief Check whether or not dual conversions are enabled. - * @param __HANDLE__ ADC handle. - * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. - * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) - */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \ - ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ - )? \ - ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \ - : \ - RESET \ - ) -#else -#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET) -#endif - -/** - * @brief Check whether or not dual regular conversions are enabled. - * @param __HANDLE__ ADC handle. - * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. - * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) - */ -#if defined(ADC_MULTIMODE_SUPPORT) -#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ - ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ - )? \ - ( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ - (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ - (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ - : \ - RESET \ - ) -#else -#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET) -#endif - -/** - * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master. - * @param __HANDLE__ ADC handle. - * @note Return SET if multimode feature is not available. - * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ - )? \ - SET \ - : \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ - ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET) -#endif - -/** - * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. - * @param __HANDLE__ ADC handle. - * @note Return SET if multimode feature is not available. - * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ - )? \ - SET \ - : \ - ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined( STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET) -#endif - -/** - * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. - * @param __HANDLE__ ADC handle. - * @note Return SET if multimode feature is not available. - * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ - )? \ - SET \ - : \ - ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET) -#endif - -/** - * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter. - * @param __INSTANCE__ ADC instance. - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \ - (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ - ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ - ) ? SET : RESET) - -/** - * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle. - * @param __HANDLE__ ADC handle. - * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_ANY_OTHER_ENABLED(__HANDLE__) \ - ( ( ((__HANDLE__)->Instance == ADC1) \ - )? \ - (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ - : \ - ( ( ((__HANDLE__)->Instance == ADC2) \ - )? \ - (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ - : \ - ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \ - ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET) -#endif - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -860,28 +665,15 @@ typedef struct */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ - -/** - * @brief Check whether or not multimode is configured in DMA mode. - * @param __HANDLE__ ADC handle. - * @note Return RESET if multimode feature is not available. - * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \ - ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \ - || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS)) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET) -#endif +#endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ + /** * @brief Verify the ADC instance connected to the temperature sensor. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* The temperature sensor measurement path (channel 17) is available on ADC1 */ #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) @@ -894,7 +686,7 @@ typedef struct * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* The battery voltage measurement path (channel 18) is available on ADC1 */ #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) @@ -912,7 +704,7 @@ typedef struct /** * @brief Verify the length of scheduled injected conversions group. - * @param __LENGTH__ number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) @@ -928,7 +720,7 @@ typedef struct /** * @brief Verify the ADC channel setting. * @param __HANDLE__ ADC handle. - * @param __CHANNEL__ programmed ADC channel. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) @@ -956,7 +748,43 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) -#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#elif defined (STM32L412xx) || defined (STM32L422xx) +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ + ((((__HANDLE__)->Instance) == ADC2) && \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) ))) +#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -1022,10 +850,10 @@ typedef struct /** * @brief Verify the ADC channel setting in differential mode. * @param __HANDLE__ ADC handle. - * @param __CHANNEL__ programmed ADC channel. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1078,7 +906,7 @@ typedef struct /** * @brief Verify the ADC single-ended input or differential mode setting. - * @param __SING_DIFF__ programmed channel setting. + * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ @@ -1086,24 +914,24 @@ typedef struct /** * @brief Verify the ADC offset management setting. - * @param __OFFSET_NUMBER__ ADC offset management. + * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) + ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) /** * @brief Verify the ADC injected channel setting. - * @param __CHANNEL__ programmed ADC injected channel. + * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ - ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) + ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) /** * @brief Verify the ADC injected conversions external trigger. @@ -1133,26 +961,26 @@ typedef struct * @brief Verify the ADC edge trigger setting for injected group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ -#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) + */ +#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Verify the ADC multimode setting. * @param __MODE__ programmed ADC multimode setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ - ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INTERL) || \ - ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) + */ +#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INTERL) || \ + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) /** * @brief Verify the ADC multimode DMA access setting. @@ -1161,7 +989,7 @@ typedef struct */ #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ - ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) + ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) /** * @brief Verify the ADC multimode delay setting. @@ -1179,7 +1007,7 @@ typedef struct ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -1189,7 +1017,7 @@ typedef struct */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) /** * @brief Verify the ADC analog watchdog mode setting. @@ -1202,31 +1030,31 @@ typedef struct ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @brief Verify the ADC conversion (regular or injected or both). * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ -#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ - ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ - ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) +#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ + ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ + ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) /** * @brief Verify the ADC event type. * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ -#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ - ((__EVENT__) == ADC_AWD_EVENT) || \ - ((__EVENT__) == ADC_AWD2_EVENT) || \ - ((__EVENT__) == ADC_AWD3_EVENT) || \ - ((__EVENT__) == ADC_OVR_EVENT) || \ - ((__EVENT__) == ADC_JQOVF_EVENT) ) +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ + ((__EVENT__) == ADC_AWD_EVENT) || \ + ((__EVENT__) == ADC_AWD2_EVENT) || \ + ((__EVENT__) == ADC_AWD3_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT) || \ + ((__EVENT__) == ADC_JQOVF_EVENT) ) /** - * @brief Verify the ADC oversampling ratio. + * @brief Verify the ADC oversampling ratio. * @param __RATIO__ programmed ADC oversampling ratio. * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) */ @@ -1240,7 +1068,7 @@ typedef struct ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) /** - * @brief Verify the ADC oversampling shift. + * @brief Verify the ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) */ @@ -1255,48 +1083,48 @@ typedef struct ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) /** - * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__ programmed ADC oversampling triggered mode. + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ - ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** - * @brief Verify the ADC oversampling regular conversion resumed or continued mode. - * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. + * @brief Verify the ADC oversampling regular conversion resumed or continued mode. + * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ - ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) + ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) /** - * @brief Verify the DFSDM mode configuration. - * @param __HANDLE__ ADC handle. + * @brief Verify the DFSDM mode configuration. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. + * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) -#else +#else #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) #endif /** * @brief Return the DFSDM configuration mode. - * @param __HANDLE__ ADC handle. - * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). + * @param __HANDLE__ ADC handle. + * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. + * directly. * @retval DFSDM configuration mode */ #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) #else -#define ADC_CFGR_DFSDM(__HANDLE__) (0x0) +#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) #endif /** @@ -1315,42 +1143,43 @@ typedef struct /* IO operation functions *****************************************************/ /* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, + uint32_t CalibrationFactor); /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); /* ADC group regular conversions stop */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /** @@ -1361,14 +1190,14 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* ADC_MULTIMODE_SUPPORT */ -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); /** * @} @@ -1390,7 +1219,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* h } #endif -#endif /* __STM32L4xx_HAL_ADC_EX_H */ +#endif /* STM32L4xx_HAL_ADC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c index a78181d858..13188adad8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c @@ -126,33 +126,85 @@ (++) When a start of Rx CAN frame is detected by the CAN peripheral, if automatic wake up mode is enabled. + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example @ref HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() + or @ref HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -221,7 +273,7 @@ */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check CAN handle */ if (hcan == NULL) @@ -243,11 +295,40 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else if (hcan->State == HAL_CAN_STATE_RESET) { /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Exit from sleep mode */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); @@ -256,7 +337,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -277,7 +358,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -387,10 +468,21 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); /* Stop the CAN module */ - HAL_CAN_Stop(hcan); + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /* Reset the CAN peripheral */ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); @@ -437,6 +529,284 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) */ } +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callabck is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /** * @} @@ -467,11 +837,12 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t filternbrbitpos = 0U; + uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check the parameters */ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); @@ -481,7 +852,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); #if defined(CAN2) /* CAN1 and CAN2 are dual instances with 28 common filters banks */ @@ -508,7 +879,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe #endif /* Convert filter number into bit position */ - filternbrbitpos = (1U) << sFilterConfig->FilterBank; + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); /* Filter Deactivation */ CLEAR_BIT(can_ip->FA1R, filternbrbitpos); @@ -573,7 +944,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe } /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) { SET_BIT(can_ip->FA1R, filternbrbitpos); } @@ -632,7 +1003,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe */ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_READY) { @@ -646,7 +1017,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) @@ -684,7 +1055,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) */ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hcan->State == HAL_CAN_STATE_LISTENING) { @@ -695,7 +1066,7 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) @@ -739,8 +1110,10 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) */ HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) { - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Request Sleep mode */ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); @@ -770,9 +1143,10 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) { __IO uint32_t count = 0; uint32_t timeout = 1000000U; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Wake up request */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); @@ -780,8 +1154,11 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) /* Wait sleep mode is exited */ do { + /* Increment counter */ + count++; + /* Check if timeout is reached */ - if (++count > timeout) + if (count > timeout) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; @@ -789,7 +1166,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) return HAL_ERROR; } } - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); /* Return function status */ return HAL_OK; @@ -814,12 +1191,13 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) { uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check Sleep mode */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { status = 1U; } @@ -844,6 +1222,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); /* Check the parameters */ assert_param(IS_CAN_IDTYPE(pHeader->IDE)); @@ -859,19 +1239,28 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType } assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check that all the Tx mailboxes are not full */ - if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || - ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || - ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) { /* Select an empty transmit mailbox */ - transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + + return HAL_ERROR; + } /* Store the Tx mailbox */ - *pTxMailbox = 1U << transmitmailbox; + *pTxMailbox = (uint32_t)1 << transmitmailbox; /* Set up the Id */ if (pHeader->IDE == CAN_ID_STD) @@ -940,28 +1329,30 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType */ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { + HAL_CAN_StateTypeDef state = hcan->State; + /* Check function parameters */ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 */ - if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) { /* Add cancellation request for Tx Mailbox 0 */ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); } /* Check Tx Mailbox 1 */ - if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) { /* Add cancellation request for Tx Mailbox 1 */ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); } /* Check Tx Mailbox 2 */ - if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) { /* Add cancellation request for Tx Mailbox 2 */ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); @@ -988,24 +1379,25 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check Tx Mailbox 0 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) { freelevel++; } /* Check Tx Mailbox 1 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) { freelevel++; } /* Check Tx Mailbox 2 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) { freelevel++; } @@ -1030,12 +1422,13 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; /* Check function parameters */ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check pending transmission request on the selected Tx Mailboxes */ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) @@ -1062,12 +1455,13 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { uint32_t timestamp = 0U; uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; /* Check function parameters */ assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Select the Tx mailbox */ transmitmailbox = POSITION_VAL(TxMailbox); @@ -1093,16 +1487,18 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) */ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { + HAL_CAN_StateTypeDef state = hcan->State; + assert_param(IS_CAN_RX_FIFO(RxFifo)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check the Rx FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ { /* Check that the Rx FIFO 0 is not empty */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; @@ -1110,10 +1506,10 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, return HAL_ERROR; } } - else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + else /* Rx element is assigned to Rx FIFO 1 */ { /* Check that the Rx FIFO 1 is not empty */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; @@ -1138,14 +1534,14 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; /* Get the data */ - aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; - aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; - aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; - aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; - aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; - aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; - aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; - aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); /* Release the FIFO */ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ @@ -1153,7 +1549,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, /* Release RX FIFO 0 */ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); } - else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + else /* Rx element is assigned to Rx FIFO 1 */ { /* Release RX FIFO 1 */ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); @@ -1182,12 +1578,13 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) { uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; /* Check function parameters */ assert_param(IS_CAN_RX_FIFO(RxFifo)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { if (RxFifo == CAN_RX_FIFO0) { @@ -1233,11 +1630,13 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) */ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { + HAL_CAN_StateTypeDef state = hcan->State; + /* Check function parameters */ assert_param(IS_CAN_IT(ActiveITs)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Enable the selected interrupts */ __HAL_CAN_ENABLE_IT(hcan, ActiveITs); @@ -1264,11 +1663,13 @@ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t */ HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) { + HAL_CAN_StateTypeDef state = hcan->State; + /* Check function parameters */ assert_param(IS_CAN_IT(InactiveITs)); - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Disable the selected interrupts */ __HAL_CAN_DISABLE_IT(hcan, InactiveITs); @@ -1302,28 +1703,33 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) uint32_t esrflags = READ_REG(hcan->Instance->ESR); /* Transmit Mailbox empty interrupt management *****************************/ - if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) { /* Transmit Mailbox 0 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP0) != RESET) + if ((tsrflags & CAN_TSR_RQCP0) != 0U) { /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - if ((tsrflags & CAN_TSR_TXOK0) != RESET) + if ((tsrflags & CAN_TSR_TXOK0) != 0U) { /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { - if ((tsrflags & CAN_TSR_ALST0) != RESET) + if ((tsrflags & CAN_TSR_ALST0) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST0; } - else if ((tsrflags & CAN_TSR_TERR0) != RESET) + else if ((tsrflags & CAN_TSR_TERR0) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR0; @@ -1331,32 +1737,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) else { /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } } /* Transmit Mailbox 1 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP1) != RESET) + if ((tsrflags & CAN_TSR_RQCP1) != 0U) { /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - if ((tsrflags & CAN_TSR_TXOK1) != RESET) + if ((tsrflags & CAN_TSR_TXOK1) != 0U) { /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { - if ((tsrflags & CAN_TSR_ALST1) != RESET) + if ((tsrflags & CAN_TSR_ALST1) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST1; } - else if ((tsrflags & CAN_TSR_TERR1) != RESET) + else if ((tsrflags & CAN_TSR_TERR1) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR1; @@ -1364,32 +1780,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) else { /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } } /* Transmit Mailbox 2 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP2) != RESET) + if ((tsrflags & CAN_TSR_RQCP2) != 0U) { /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - if ((tsrflags & CAN_TSR_TXOK2) != RESET) + if ((tsrflags & CAN_TSR_TXOK2) != 0U) { /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } else { - if ((tsrflags & CAN_TSR_ALST2) != RESET) + if ((tsrflags & CAN_TSR_ALST2) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_ALST2; } - else if ((tsrflags & CAN_TSR_TERR2) != RESET) + else if ((tsrflags & CAN_TSR_TERR2) != 0U) { /* Update error code */ errorcode |= HAL_CAN_ERROR_TX_TERR2; @@ -1397,17 +1823,22 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) else { /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } } } /* Receive FIFO 0 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) { - if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) { /* Set CAN error code to Rx Fifo 0 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV0; @@ -1418,35 +1849,45 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Receive FIFO 0 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) { - if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) { /* Clear FIFO 0 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 0 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) { /* Check if message is still pending */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) { /* Receive FIFO 0 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) { - if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) { /* Set CAN error code to Rx Fifo 1 overrun error */ errorcode |= HAL_CAN_ERROR_RX_FOV1; @@ -1457,67 +1898,87 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Receive FIFO 1 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) { - if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) { /* Clear FIFO 1 full Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Receive FIFO 1 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) { /* Check if message is still pending */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) { /* Receive FIFO 1 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Sleep interrupt management *********************************************/ - if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) { - if ((msrflags & CAN_MSR_SLAKI) != RESET) + if ((msrflags & CAN_MSR_SLAKI) != 0U) { /* Clear Sleep interrupt Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* WakeUp interrupt management *********************************************/ - if ((interrupts & CAN_IT_WAKEUP) != RESET) + if ((interrupts & CAN_IT_WAKEUP) != 0U) { - if ((msrflags & CAN_MSR_WKUI) != RESET) + if ((msrflags & CAN_MSR_WKUI) != 0U) { /* Clear WakeUp Flag */ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } /* Error interrupts management *********************************************/ - if ((interrupts & CAN_IT_ERROR) != RESET) + if ((interrupts & CAN_IT_ERROR) != 0U) { - if ((msrflags & CAN_MSR_ERRI) != RESET) + if ((msrflags & CAN_MSR_ERRI) != 0U) { /* Check Error Warning Flag */ - if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && - ((esrflags & CAN_ESR_EWGF) != RESET)) + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) { /* Set CAN error code to Error Warning */ errorcode |= HAL_CAN_ERROR_EWG; @@ -1526,8 +1987,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Check Error Passive Flag */ - if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && - ((esrflags & CAN_ESR_EPVF) != RESET)) + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) { /* Set CAN error code to Error Passive */ errorcode |= HAL_CAN_ERROR_EPV; @@ -1536,8 +1997,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Check Bus-off Flag */ - if (((interrupts & CAN_IT_BUSOFF) != RESET) && - ((esrflags & CAN_ESR_BOFF) != RESET)) + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) { /* Set CAN error code to Bus-Off */ errorcode |= HAL_CAN_ERROR_BOF; @@ -1546,8 +2007,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) } /* Check Last Error Code Flag */ - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && - ((esrflags & CAN_ESR_LEC) != RESET)) + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) { switch (esrflags & CAN_ESR_LEC) { @@ -1595,8 +2056,13 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) hcan->ErrorCode |= errorcode; /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ } } @@ -1881,21 +2347,25 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Check sleep mode acknowledge flag */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { /* Sleep mode is active */ state = HAL_CAN_STATE_SLEEP_ACTIVE; } /* Check sleep mode request flag */ - else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) { /* Sleep mode request is pending */ state = HAL_CAN_STATE_SLEEP_PENDING; } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } } /* Return CAN state */ @@ -1923,9 +2393,10 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; - if ((hcan->State == HAL_CAN_STATE_READY) || - (hcan->State == HAL_CAN_STATE_LISTENING)) + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) { /* Reset CAN error code */ hcan->ErrorCode = 0U; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h index 87a0fb0ba8..8cd92066c4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -151,7 +135,7 @@ typedef struct This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be set to ENABLE or DISABLE. */ + This parameter can be a value of @ref CAN_filter_activation */ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. For single CAN instances, this parameter is meaningless. @@ -233,8 +217,58 @@ typedef struct __CAN_HandleTypeDef __IO uint32_t ErrorCode; /*!< CAN Error code. This parameter can be a value of @ref CAN_Error_Code */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ } CAN_HandleTypeDef; +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ /** * @} */ @@ -272,6 +306,11 @@ typedef struct __CAN_HandleTypeDef #define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ #define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + /** * @} */ @@ -364,6 +403,15 @@ typedef struct __CAN_HandleTypeDef * @} */ +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ @@ -496,7 +544,15 @@ typedef struct __CAN_HandleTypeDef * @param __HANDLE__ CAN handle. * @retval None */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ /** * @brief Enable the specified CAN interrupts. @@ -587,6 +643,12 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ /** * @} */ @@ -732,12 +794,16 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) #define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#if defined(CAN2) #define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#endif #define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) #define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c index 3b88ba4f2f..41fb96f657 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c @@ -3,15 +3,15 @@ * @file stm32l4xx_hal_can.c * @author MCD Application Team * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions * + Peripheral State and Error functions * @verbatim - ============================================================================== + ============================================================================== ##### User NOTE ##### ============================================================================== [..] @@ -21,86 +21,70 @@ ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using + [..] + (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. - + (#) CAN pins configuration (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (++) Connect and configure the involved CAN pins using the - following function HAL_GPIO_Init(); - - (#) Initialize and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or + __HAL_RCC_GPIOx_CLK_ENABLE(); + (++) Connect and configure the involved CAN pins using the + following function HAL_GPIO_Init(); + + (#) Initialize and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or HAL_CAN_Transmit_IT() function. - + (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. *** Polling mode IO operation *** ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation using HAL_CAN_Transmit(), at this stage user can specify the value of timeout according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation + (+) Start the CAN peripheral reception and wait the end of this operation using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** + according to his end application + + *** Interrupt mode IO operation *** =================================== - [..] + [..] (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_CAN_ErrorCallback - + *** CAN HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in CAN HAL driver. - + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN Legacy HAL driver header file for more useful macros - + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + @endverbatim - + ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -112,7 +96,7 @@ * @{ */ -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED #ifdef HAL_CAN_MODULE_ENABLED /* Select HAL CAN module in stm32l4xx_hal_conf.h file: (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations @@ -127,9 +111,9 @@ /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ + */ + - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants @@ -157,33 +141,33 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + @endverbatim * @{ */ - + /** - * @brief Initialize the CAN peripheral according to the specified parameters + * @brief Initialize the CAN peripheral according to the specified parameters * in the CAN_InitStruct structure and initialize the associated handle. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ uint32_t tickstart = 0; - + /* Check CAN handle */ if(hcan == NULL) { @@ -203,7 +187,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_BS1(hcan->Init.BS1)); assert_param(IS_CAN_BS2(hcan->Init.BS2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - + if(hcan->State == HAL_CAN_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -212,10 +196,10 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /* Init the low level hardware */ HAL_CAN_MspInit(hcan); } - + /* Initialize the CAN state*/ hcan->State = HAL_CAN_STATE_BUSY; - + /* Exit from sleep mode */ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); @@ -312,7 +296,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { @@ -331,15 +315,15 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) status = CAN_INITSTATUS_SUCCESS; } } - + if(status == CAN_INITSTATUS_SUCCESS) { /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - + /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -365,7 +349,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { uint32_t filternbrbitpos = 0; - + /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); @@ -381,7 +365,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* Initialisation mode for the filter */ CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; - + #if defined(CAN2) /* Select the start slave bank */ CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); @@ -399,13 +383,13 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); } @@ -415,11 +399,11 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* 32-bit scale for the filter */ CAN1->FS1R |= filternbrbitpos; /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); } @@ -448,7 +432,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* FIFO 1 assignation for the filter */ CAN1->FFA1R |= (uint32_t)filternbrbitpos; } - + /* Filter activation */ if (sFilterConfig->FilterActivation == ENABLE) { @@ -457,15 +441,15 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* Leave the initialisation mode for the filter */ CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CAN peripheral registers to their default reset values. + * @brief DeInitialize the CAN peripheral registers to their default reset values. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) @@ -475,16 +459,16 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - + /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY; - + /* DeInit the low level hardware */ HAL_CAN_MspDeInit(hcan); - + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; @@ -498,7 +482,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) /** * @brief Initialize the CAN MSP. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) @@ -508,13 +492,13 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) /* NOTE : This function should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitialize the CAN MSP. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval None */ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) @@ -524,7 +508,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) /* NOTE : This function should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ } /** @@ -532,18 +516,18 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) */ /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + * @brief I/O operation functions * -@verbatim +@verbatim ============================================================================== ##### IO operation functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Transmit a CAN frame message. (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. + (+) Enter CAN peripheral in sleep mode. (+) Wake up the CAN peripheral from sleep mode. - + @endverbatim * @{ */ @@ -551,7 +535,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) /** * @brief Initiate and transmit a CAN frame message. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @param Timeout: Timeout duration. * @retval HAL status */ @@ -564,11 +548,11 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - + /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX_RX; @@ -578,7 +562,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; } - + /* Select one empty transmit mailbox */ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { @@ -599,7 +583,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (hcan->pTxMsg->IDE == CAN_ID_STD) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ hcan->pTxMsg->RTR); } @@ -610,27 +594,27 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) hcan->pTxMsg->IDE | \ hcan->pTxMsg->RTR); } - + /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | ((uint32_t)hcan->pTxMsg->Data[6] << 16) | ((uint32_t)hcan->pTxMsg->Data[5] << 8) | ((uint32_t)hcan->pTxMsg->Data[4])); /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check End of transmission flag */ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) { @@ -646,7 +630,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) } } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; @@ -656,18 +640,18 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; } - + /* Process unlocked */ __HAL_UNLOCK(hcan); - + /* Return function status */ return HAL_OK; } else { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - + hcan->State = HAL_CAN_STATE_ERROR; + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -679,7 +663,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /** * @brief Initiate and transmit a CAN frame message in Interrupt mode. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) @@ -690,12 +674,12 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) { /* Process Locked */ __HAL_LOCK(hcan); - + /* Select one empty transmit mailbox */ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { @@ -716,7 +700,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if(hcan->pTxMsg->IDE == CAN_ID_STD) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ hcan->pTxMsg->RTR); } @@ -727,23 +711,23 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) hcan->pTxMsg->IDE | \ hcan->pTxMsg->RTR); } - + /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | ((uint32_t)hcan->pTxMsg->Data[6] << 16) | ((uint32_t)hcan->pTxMsg->Data[5] << 8) | ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX_RX; @@ -753,13 +737,13 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; } - + /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hcan); - + /* Enable interrupts: */ /* - Enable Error warning Interrupt */ /* - Enable Error passive Interrupt */ @@ -773,7 +757,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) CAN_IT_LEC | CAN_IT_ERR | CAN_IT_TME ); - + /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } @@ -782,14 +766,14 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) { return HAL_BUSY; } - + return HAL_OK; } /** * @brief Receive a correct CAN frame. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @param FIFONumber: FIFO number. * @param Timeout: Timeout duration. * @retval HAL status @@ -797,14 +781,14 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { uint32_t tickstart = 0; - + /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - + /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX_RX; @@ -814,10 +798,10 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; } - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check pending message */ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) { @@ -833,7 +817,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u } } } - + /* Get the Id */ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; if (hcan->pRxMsg->IDE == CAN_ID_STD) @@ -844,7 +828,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u { hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); } - + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; @@ -859,7 +843,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - + /* Release the FIFO */ if(FIFONumber == CAN_FIFO0) { @@ -871,8 +855,8 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Release FIFO1 */ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; @@ -882,7 +866,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; } - + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -893,7 +877,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u /** * @brief Receive a correct CAN frame in Interrupt mode. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @param FIFONumber: FIFO number. * @retval HAL status */ @@ -901,13 +885,13 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber { /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) { /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX_RX; @@ -917,10 +901,10 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; } - + /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; - + /* Enable interrupts: */ /* - Enable Error warning Interrupt */ /* - Enable Error passive Interrupt */ @@ -946,13 +930,13 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber /* Enable FIFO 1 overrun and message pending Interrupt */ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - + } else { return HAL_BUSY; } - + /* Return function status */ return HAL_OK; } @@ -966,16 +950,16 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) { uint32_t tickstart = 0; - + /* Process locked */ __HAL_LOCK(hcan); - + /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - + hcan->State = HAL_CAN_STATE_BUSY; + /* Request Sleep mode */ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - + /* Sleep mode status */ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) { @@ -985,10 +969,10 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) /* Return function status */ return HAL_ERROR; } - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait the acknowledge */ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) { @@ -1000,13 +984,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_TIMEOUT; } } - + /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hcan); - + /* Return function status */ return HAL_OK; } @@ -1021,13 +1005,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) { uint32_t tickstart = 0; - + /* Process locked */ __HAL_LOCK(hcan); - + /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - + hcan->State = HAL_CAN_STATE_BUSY; + /* Wake up request */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; @@ -1053,13 +1037,13 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) /* Return function status */ return HAL_ERROR; } - + /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - + hcan->State = HAL_CAN_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcan); - + /* Return function status */ return HAL_OK; } @@ -1107,7 +1091,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) CAN_Transmit_IT(hcan); } } - + /* Check End of reception flag for FIFO0 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) @@ -1115,7 +1099,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO0); } - + /* Check End of reception flag for FIFO1 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) @@ -1123,10 +1107,10 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO1); } - + /* Set error code in handle */ hcan->ErrorCode |= errorcode; - + /* Check Error Warning Flag */ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && @@ -1136,7 +1120,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) hcan->ErrorCode |= HAL_CAN_ERROR_EWG; /* No need for clear of Error Warning Flag as read-only */ } - + /* Check Error Passive Flag */ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && @@ -1144,9 +1128,9 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { /* Set CAN error code to EPV error */ hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ + /* No need for clear of Error Passive Flag as read-only */ } - + /* Check Bus-Off Flag */ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && @@ -1156,7 +1140,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) hcan->ErrorCode |= HAL_CAN_ERROR_BOF; /* No need for clear of Bus-Off Flag as read-only */ } - + /* Check Last error code Flag */ if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && @@ -1192,7 +1176,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) break; } - /* Clear Last error code Flag */ + /* Clear Last error code Flag */ hcan->Instance->ESR &= ~(CAN_ESR_LEC); } @@ -1226,10 +1210,10 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) CAN_IT_FMP1| CAN_IT_FOV1| CAN_IT_TME ); - + /* Call Error callback function */ HAL_CAN_ErrorCallback(hcan); - } + } } /** @@ -1285,9 +1269,9 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions + * @brief CAN Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== @@ -1295,7 +1279,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) This subsection provides functions allowing to : (+) Check the CAN state. (+) Check CAN Errors detected during interrupt process. - + @endverbatim * @{ */ @@ -1337,16 +1321,16 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) /** * @brief Initiate and transmit a CAN frame message. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) { /* Disable Transmit mailbox empty Interrupt */ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - + if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { + { /* Disable interrupts: */ /* - Disable Error warning Interrupt */ /* - Disable Error passive Interrupt */ @@ -1359,8 +1343,8 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) CAN_IT_LEC | CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; @@ -1370,18 +1354,18 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; } - - /* Transmission complete callback */ + + /* Transmission complete callback */ HAL_CAN_TxCpltCallback(hcan); - + return HAL_OK; } /** * @brief Receive a correct CAN frame. * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number + * the configuration information for the specified CAN. + * @param FIFONumber: Specify the FIFO number * @retval HAL status */ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) @@ -1396,7 +1380,7 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum { hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); } - + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; @@ -1416,19 +1400,19 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum if (FIFONumber == CAN_FIFO0) { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - + /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - + /* Disable FIFO 1 overrun and message pending Interrupt */ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - + if(hcan->State == HAL_CAN_STATE_BUSY_RX) { /* Disable interrupts: */ @@ -1443,8 +1427,8 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum CAN_IT_LEC | CAN_IT_ERR ); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) { /* Disable CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; @@ -1455,7 +1439,7 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum hcan->State = HAL_CAN_STATE_READY; } - /* Receive complete callback */ + /* Receive complete callback */ HAL_CAN_RxCpltCallback(hcan); /* Return function status */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h index 08fd1017dc..b221774204 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -154,7 +138,7 @@ typedef struct This parameter can be set to ENABLE or DISABLE */ uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ }CAN_FilterConfTypeDef; @@ -596,7 +580,7 @@ typedef struct * @retval None */ #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) +((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) /** * @brief Cancel a transmit request. @@ -612,29 +596,29 @@ typedef struct /** * @brief Enable or disable the DBG Freeze for CAN. * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. + * @param __NEWSTATE__: new state of the CAN peripheral. * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFO can still be accessed/controlled normally) + * during debug. Reception FIFO can still be accessed/controlled normally) * or DISABLE (CAN is working during debug). * @retval None */ #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) /** * @} - */ - -/* Exported functions --------------------------------------------------------*/ + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @{ */ -/* addtogroup and de-initialization functions *****************************/ +/* addtogroup and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); @@ -642,10 +626,10 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); /** * @} - */ - + */ + /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + * @brief I/O operation functions * @{ */ /* IO operation functions *****************************************************/ @@ -661,10 +645,10 @@ void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); /** * @} - */ - + */ + /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions + * @brief CAN Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ @@ -672,11 +656,11 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} - */ + */ /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c index a6d00340ee..7528b21cf4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c @@ -3,14 +3,14 @@ * @file stm32l4xx_hal_comp.c * @author MCD Application Team * @brief COMP HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: * + Initialization and de-initialization functions * + Start/Stop operation functions in polling mode * + Start/Stop operation functions in interrupt mode (through EXTI interrupt) * + Peripheral control functions * + Peripheral state functions - * + * @verbatim ================================================================================ ##### COMP Peripheral features ##### @@ -18,22 +18,25 @@ [..] The STM32L4xx device family integrates two analog comparators instances: - COMP1, COMP2. + COMP1, COMP2 except for the STM32L412xx/STM32L422xx products that embed only + one: COMP1. + In the rest of the file, all comments related to a pair of comparators are not + applicable to STM32L412xx or STM32L422xx. (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). - + (#) Comparators output level is available using HAL_COMP_GetOutputLevel() and can be redirected to other peripherals: GPIO pins (in mode alternate functions for comparator), timers. (refer to GPIO list in reference manual). - + (#) The comparators have interrupt capability through the EXTI controller with wake-up from sleep and stop modes. - + (#) Pairs of comparators instances can be combined in window mode (2 consecutive instances odd and even COMP and COMP). - + From the corresponding IRQ handler, the right interrupt source can be retrieved using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). @@ -42,18 +45,18 @@ [..] This driver provides functions to configure and program the comparator instances of STM32L4xx devices. - + To use the comparator, perform the following steps: - + (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode using HAL_GPIO_Init(). (++) If needed, configure the GPIO connected to comparator output in alternate function mode using HAL_GPIO_Init(). - (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and + (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator interrupt vector using HAL_NVIC_EnableIRQ() function. - + (#) Configure the comparator using HAL_COMP_Init() function: (++) Select the input minus (inverting input) (++) Select the input plus (non-inverting input) @@ -62,101 +65,143 @@ (++) Select the output polarity (++) Select the power mode (++) Select the window mode - + -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() to enable internal control clock of the comparators. However, this is a legacy strategy. In future STM32 families, COMP clock enable must be implemented by user in "HAL_COMP_MspInit()". - Therefore, for compatibility anticipation, it is recommended to + Therefore, for compatibility anticipation, it is recommended to implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()". - + (#) Reconfiguration on-the-fly of comparator can be done by calling again function HAL_COMP_Init() with new input structure parameters values. - + (#) Enable the comparator using HAL_COMP_Start() function. - + (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions to manage comparator outputs (events and output level). - + (#) Disable the comparator using HAL_COMP_Stop() function. - + (#) De-initialize the comparator using HAL_COMP_DeInit() function. - + (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. The only way to unlock the comparator is a device hardware reset. - + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_COMP_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + + By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET + all callbacks are set to the corresponding weak functions: + example @ref HAL_COMP_TriggerCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit() + or @ref HAL_COMP_Init() function. + [..] + + When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** Table 1. COMP inputs and output for STM32L4xx devices - +---------------------------------------------------------+ - | | | COMP1 | COMP2 | - |----------------|----------------|-----------|-----------| - | | IO1 | PC5 | PB4 | - | Input plus | IO2 | PB2 | PB6 | - | | IO3 (3) | PA1 | PA3 | - |----------------|----------------|-----------------------| - | | 1/4 VrefInt | Available | Available | - | | 1/2 VrefInt | Available | Available | - | | 3/4 VrefInt | Available | Available | - | Input minus | VrefInt | Available | Available | - | | DAC1 channel 1 | Available | Available | - | | DAC1 channel 2 | Available | Available | - | | IO1 | PB1 | PB3 | - | | IO2 | PC4 | PB7 | - | | IO3 (3) | PA0 | PA2 | - | | IO4 (3) | PA4 | PA4 | - | | IO5 (3) | PA5 | PA5 | - +---------------------------------------------------------+ - | Output | | PB0 (1) | PB5 (1) | - | | | PB10 (1) | PB11 (1) | - | | | TIM (2) | TIM (2) | - +---------------------------------------------------------+ + +-----------------------------------------------------------------+ + | | | COMP1 | COMP2 (4) | + |----------------|----------------|---------------|---------------+ + | | IO1 | PC5 | PB4 | + | Input plus | IO2 | PB2 | PB6 | + | | IO3 (3) | PA1 | PA3 | + |----------------|----------------|---------------|---------------+ + | | 1/4 VrefInt | Available | Available | + | | 1/2 VrefInt | Available | Available | + | | 3/4 VrefInt | Available | Available | + | Input minus | VrefInt | Available | Available | + | | DAC1 channel 1 | Available | Available (4) | + | | DAC1 channel 2 | Available | Available (4) | + | | IO1 | PB1 | PB3 | + | | IO2 | PC4 | PB7 | + | | IO3 (3) | PA0 | PA2 | + | | IO4 (3) | PA4 | PA4 | + | | IO5 (3) | PA5 | PA5 | + +----------------|----------------|---------------|---------------+ + | Output | | PB0 (1) | PB5 (1) | + | | | PB10 (1) | PB11 (1) | + | | | TIM (2) | TIM (2) | + +-----------------------------------------------------------------+ (1) GPIO must be set to alternate function for comparator (2) Comparators output to timers is set in timers instances. (3) Only STM32L43x/L44x + (4) Not applicable to STM32L412x/L422x ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#ifdef HAL_COMP_MODULE_ENABLED - -#if defined (COMP1) || defined (COMP2) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#ifdef HAL_COMP_MODULE_ENABLED + +#if defined (COMP1) || defined (COMP2) + /** @defgroup COMP COMP * @brief COMP HAL module driver * @{ @@ -173,15 +218,15 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US (80U) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART_SCALER"). */ /* Unit: us */ -#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200U) /*!< Delay for COMP voltage scaler stabilization time */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */ -#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /** * @} @@ -196,14 +241,14 @@ * @{ */ -/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and de-initialization functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This section provides functions to initialize and de-initialize comparators + [..] This section provides functions to initialize and de-initialize comparators @endverbatim * @{ @@ -219,14 +264,18 @@ */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { - uint32_t tmp_csr = 0U; - uint32_t exti_line = 0U; - uint32_t comp_voltage_scaler_not_initialized = 0U; - __IO uint32_t wait_loop_index = 0U; + uint32_t tmp_csr; + uint32_t exti_line; + uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ + __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -239,15 +288,20 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode)); assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); - assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); + assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); +#if defined(COMP2) assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); - +#endif + if(hcomp->State == HAL_COMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; - + + /* Set COMP error code to none */ + COMP_CLEAR_ERRORCODE(hcomp); + /* Init SYSCFG and the low level hardware to access comparators */ /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE() */ /* to enable internal control clock of the comparators. */ @@ -258,14 +312,27 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* to implement __HAL_RCC_SYSCFG_CLK_ENABLE() */ /* in "HAL_COMP_MspInit()". */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + /* Init the COMP Callback settings */ + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + + if (hcomp->MspInitCallback == NULL) + { + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hcomp->MspInitCallback(hcomp); +#else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } - + /* Memorize voltage scaler state before initialization */ - comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) == 0); - + comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN); + /* Set COMP parameters */ tmp_csr = ( hcomp->Init.NonInvertingInput | hcomp->Init.InvertingInput @@ -274,16 +341,25 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) | hcomp->Init.OutputPol | hcomp->Init.Mode ); - + /* Set parameters in COMP register */ /* Note: Update all bits except read-only, lock and enable bits */ #if defined (COMP_CSR_INMESEL) +#if defined (COMP_CSR_WINMODE) MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST | COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, tmp_csr ); +#else + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | + COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, + tmp_csr + ); +#endif #else MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | @@ -292,7 +368,8 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) tmp_csr ); #endif - + +#if defined(COMP2) /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ @@ -305,30 +382,32 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); } - +#endif /* COMP2 */ + /* Delay for COMP scaler bridge voltage stabilization */ - /* Apply the delay if voltage scaler bridge is enabled for the first time */ - if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0U) && - (comp_voltage_scaler_not_initialized != 0U) ) + /* Apply the delay if voltage scaler bridge is required and not already enabled */ + if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) && + (comp_voltage_scaler_initialized == 0UL) ) { /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2U))); - while(wait_loop_index != 0U) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } } - + /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); - + /* Manage EXTI settings */ - if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET) + if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) { /* Configure EXTI rising edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) { LL_EXTI_EnableRisingTrig_0_31(exti_line); } @@ -336,9 +415,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { LL_EXTI_DisableRisingTrig_0_31(exti_line); } - + /* Configure EXTI falling edge */ - if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) { LL_EXTI_EnableFallingTrig_0_31(exti_line); } @@ -346,12 +425,12 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { LL_EXTI_DisableFallingTrig_0_31(exti_line); } - + /* Clear COMP EXTI pending bit (if any) */ LL_EXTI_ClearFlag_0_31(exti_line); - + /* Configure EXTI event mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) { LL_EXTI_EnableEvent_0_31(exti_line); } @@ -359,9 +438,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { LL_EXTI_DisableEvent_0_31(exti_line); } - + /* Configure EXTI interrupt mode */ - if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET) + if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) { LL_EXTI_EnableIT_0_31(exti_line); } @@ -374,11 +453,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { /* Disable EXTI event mode */ LL_EXTI_DisableEvent_0_31(exti_line); - + /* Disable EXTI interrupt mode */ LL_EXTI_DisableIT_0_31(exti_line); } - + /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ @@ -387,7 +466,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) hcomp->State = HAL_COMP_STATE_READY; } } - + return status; } @@ -401,9 +480,13 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -411,20 +494,30 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + /* Set COMP_CSR register to reset value */ - WRITE_REG(hcomp->Instance->CSR, 0x00000000U); - - /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ + WRITE_REG(hcomp->Instance->CSR, 0x00000000UL); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + if (hcomp->MspDeInitCallback == NULL) + { + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ + hcomp->MspDeInitCallback(hcomp); +#else + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ HAL_COMP_MspDeInit(hcomp); - +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hcomp); } - + return status; } @@ -437,7 +530,7 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_MspInit could be implemented in the user file */ @@ -452,23 +545,183 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_MspDeInit could be implemented in the user file */ } +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User COMP Callback + * To be used instead of the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = pCallback; + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a COMP Callback + * COMP callback is redirected to the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions - * @brief Start-Stop operation functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start a comparator instance. (+) Stop a comparator instance. @@ -484,11 +737,15 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { - __IO uint32_t wait_loop_index = 0U; + __IO uint32_t wait_loop_index = 0UL; HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -501,16 +758,17 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); - + /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; - + /* Delay for COMP startup time */ /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U))); - while(wait_loop_index != 0U) + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) { wait_loop_index--; } @@ -532,9 +790,13 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -542,9 +804,10 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - - if((hcomp->State == HAL_COMP_STATE_BUSY) || - (hcomp->State == HAL_COMP_STATE_READY) ) + + /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ + /* (all states except HAL_COMP_STATE_RESET and except locked status. */ + if(hcomp->State != HAL_COMP_STATE_RESET) { /* Disable the selected comparator */ CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); @@ -557,7 +820,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) status = HAL_ERROR; } } - + return status; } @@ -570,10 +833,11 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { /* Get the EXTI line corresponding to the selected COMP instance */ uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); - + /* Check COMP EXTI flag */ - if(LL_EXTI_IsActiveFlag_0_31(exti_line) != RESET) + if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) { +#if defined(COMP2) /* Check whether comparator is in independent or window mode */ if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != RESET) { @@ -587,13 +851,18 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else +#endif /* COMP2 */ { /* Clear COMP EXTI line pending bit */ LL_EXTI_ClearFlag_0_31(exti_line); } - + /* COMP trigger user callback */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->TriggerCallback(hcomp); +#else HAL_COMP_TriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } } @@ -601,15 +870,15 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions. + * +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the comparators. + This subsection provides a set of functions allowing to control the comparators. @endverbatim * @{ @@ -626,9 +895,13 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the COMP handle allocation and lock status */ - if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp))) + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) { status = HAL_ERROR; } @@ -636,22 +909,33 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + /* Set HAL COMP handle state */ - hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK)); + switch(hcomp->State) + { + case HAL_COMP_STATE_RESET: + hcomp->State = HAL_COMP_STATE_RESET_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: /* HAL_COMP_STATE_BUSY */ + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + } } - + if(status == HAL_OK) { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } - - return status; + + return status; } /** - * @brief Return the output level (high or low) of the selected comparator. + * @brief Return the output level (high or low) of the selected comparator. * The output level depends on the selected polarity. * If the polarity is not inverted: * - Comparator output is low when the input plus is at a lower @@ -664,22 +948,22 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * - Comparator output is low when the input plus is at a higher * voltage than the input minus * @param hcomp COMP handle - * @retval Returns the selected comparator output level: + * @retval Returns the selected comparator output level: * @arg COMP_OUTPUT_LEVEL_LOW * @arg COMP_OUTPUT_LEVEL_HIGH - * + * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - + return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE) >> COMP_OUTPUT_LEVEL_BITOFFSET_POS); } /** - * @brief Comparator callback. + * @brief Comparator trigger callback. * @param hcomp COMP handle * @retval None */ @@ -687,7 +971,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcomp); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_COMP_TriggerCallback should be implemented in the user file */ @@ -698,13 +982,13 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permit to get in run-time the status of the peripheral. @@ -733,8 +1017,17 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) } /** - * @} + * @brief Return the COMP error code. + * @param hcomp COMP handle + * @retval COMP error code */ +uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return hcomp->ErrorCode; +} /** * @} @@ -752,4 +1045,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) #endif /* HAL_COMP_MODULE_ENABLED */ +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h index 142639e679..24afa97fbd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h @@ -6,43 +6,25 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_COMP_H -#define __STM32L4xx_HAL_COMP_H +#ifndef STM32L4xx_HAL_COMP_H +#define STM32L4xx_HAL_COMP_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined (COMP1) || defined (COMP2) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" #include "stm32l4xx_ll_exti.h" @@ -50,29 +32,32 @@ /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined (COMP1) || defined (COMP2) /** @addtogroup COMP * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup COMP_Exported_Types COMP Exported Types * @{ */ -/** - * @brief COMP Init structure definition +/** + * @brief COMP Init structure definition */ typedef struct { +#if defined(COMP2) uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP and COMP). Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ +#endif /* COMP2 */ uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. - Note: For the characteritics of comparator power modes + Note: For the characteristics of comparator power modes (propagation delay and power consumption), refer to device datasheet. This parameter can be a value of @ref COMP_PowerMode */ @@ -94,7 +79,7 @@ typedef struct uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI). This parameter can be a value of @ref COMP_EXTI_TriggerMode */ -}COMP_InitTypeDef; +} COMP_InitTypeDef; /** * @brief HAL COMP state machine: HAL COMP states definition @@ -108,19 +93,47 @@ typedef enum HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ -}HAL_COMP_StateTypeDef; +} HAL_COMP_StateTypeDef; -/** +/** * @brief COMP Handle Structure definition */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +typedef struct __COMP_HandleTypeDef +#else typedef struct +#endif { COMP_TypeDef *Instance; /*!< Register base address */ COMP_InitTypeDef Init; /*!< COMP required parameters */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ + __IO uint32_t ErrorCode; /*!< COMP error code */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */ + void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */ + void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } COMP_HandleTypeDef; +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL COMP Callback ID enumeration definition + */ +typedef enum +{ + HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */ + HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */ + HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */ +} HAL_COMP_CallbackIDTypeDef; + +/** + * @brief HAL COMP Callback pointer definition + */ +typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */ + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + /** * @} */ @@ -130,22 +143,35 @@ typedef struct * @{ */ -/** @defgroup COMP_WindowMode COMP Window Mode +/** @defgroup COMP_Error_Code COMP Error Code * @{ */ -#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ -#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** * @} */ +#if defined(COMP2) +/** @defgroup COMP_WindowMode COMP Window Mode + * @{ + */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +/** + * @} + */ +#endif + /** @defgroup COMP_PowerMode COMP power mode * @{ */ -/* Note: For the characteritics of comparator power modes */ +/* Note: For the characteristics of comparator power modes */ /* (propagation delay and power consumption), */ /* refer to device datasheet. */ -#define COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< High Speed */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ #define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ #define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */ /** @@ -155,7 +181,7 @@ typedef struct /** @defgroup COMP_InputPlus COMP input plus (non-inverting input) * @{ */ -#define COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -189,7 +215,7 @@ typedef struct /** @defgroup COMP_Hysteresis COMP hysteresis * @{ */ -#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ #define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ @@ -200,7 +226,7 @@ typedef struct /** @defgroup COMP_OutputPolarity COMP output Polarity * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ #define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ /** * @} @@ -209,7 +235,7 @@ typedef struct /** @defgroup COMP_BlankingSrce COMP blanking source * @{ */ -#define COMP_BLANKINGSRC_NONE (0x00000000U) /*!State = HAL_COMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) +#endif + +/** + * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). + * @param __HANDLE__ COMP handle + * @retval None + */ +#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) /** * @brief Enable the specified comparator. @@ -346,7 +387,7 @@ typedef struct /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ @@ -394,6 +435,7 @@ typedef struct */ #define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1) +#if defined(COMP2) /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None @@ -478,6 +520,7 @@ typedef struct */ #define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2) +#endif /* COMP2 */ /** * @} */ @@ -497,7 +540,9 @@ typedef struct * @{ */ #define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output */ +#if defined(COMP2) #define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output */ +#endif /* COMP2 */ /** * @} */ @@ -505,10 +550,10 @@ typedef struct /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ -#define COMP_EXTI_IT (0x01U) /*!< EXTI line event with interruption */ -#define COMP_EXTI_EVENT (0x02U) /*!< EXTI line event only (without interruption) */ -#define COMP_EXTI_RISING (0x10U) /*!< EXTI line event on rising edge */ -#define COMP_EXTI_FALLING (0x20U) /*!< EXTI line event on falling edge */ +#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */ /** * @} */ @@ -522,7 +567,7 @@ typedef struct * @{ */ -/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators +/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators * @{ */ /** @@ -530,8 +575,12 @@ typedef struct * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ -#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ - : COMP_EXTI_LINE_COMP2) +#if defined(COMP2) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) +#else +#define COMP_GET_EXTI_LINE(__INSTANCE__) COMP_EXTI_LINE_COMP1 +#endif /* COMP2 */ /** * @} */ @@ -539,8 +588,10 @@ typedef struct /** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters * @{ */ +#if defined(COMP2) #define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) ) +#endif #define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ @@ -609,6 +660,7 @@ typedef struct #define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \ ((__POL__) == COMP_OUTPUTPOL_INVERTED)) +#if defined(COMP2) #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ @@ -618,7 +670,24 @@ typedef struct || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ ) +#else +#if defined(TIM3) +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + ) +#else +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + ) +#endif /* TIM3 */ +#endif /* COMP2 */ +#if defined(COMP2) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ @@ -631,7 +700,22 @@ typedef struct ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - +#else +#if defined(TIM3) + #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) +#else + #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) )) +#endif /* TIM3 */ +#endif /* COMP2 */ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ @@ -664,9 +748,16 @@ typedef struct /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); -HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** * @} */ @@ -699,6 +790,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); * @{ */ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); /** * @} */ @@ -710,7 +802,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); /** * @} */ - +#endif /* COMP1 || COMP2 */ /** * @} */ @@ -719,8 +811,6 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); } #endif -#endif /* COMP1 || COMP2 */ - -#endif /* __STM32L4xx_HAL_COMP_H */ +#endif /* STM32L4xx_HAL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h index ae27ce2da1..ef6b90e3a9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h @@ -8,36 +8,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H +#ifndef STM32L4xx_HAL_CONF_H +#define STM32L4xx_HAL_CONF_H #ifdef __cplusplus extern "C" { @@ -65,21 +49,22 @@ #define HAL_DMA_MODULE_ENABLED #define HAL_DMA2D_MODULE_ENABLED #define HAL_DSI_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_FIREWALL_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_GFXMMU_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED -#define HAL_NAND_MODULE_ENABLED -#define HAL_NOR_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_IRDA_MODULE_ENABLED #define HAL_IWDG_MODULE_ENABLED #define HAL_LCD_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED #define HAL_LTDC_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED #define HAL_OPAMP_MODULE_ENABLED #define HAL_OSPI_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED @@ -93,6 +78,7 @@ #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED #define HAL_SWPMI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_TSC_MODULE_ENABLED @@ -108,11 +94,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)200U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -120,7 +106,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** @@ -129,7 +115,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -140,7 +126,7 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -148,8 +134,8 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ /** @@ -157,11 +143,11 @@ * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -170,7 +156,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -179,7 +165,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -189,8 +175,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U @@ -203,6 +189,51 @@ */ /* #define USE_FULL_ASSERT 1U */ +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l4xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver @@ -277,6 +308,14 @@ #include "stm32l4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -289,22 +328,18 @@ #include "stm32l4xx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED #include "stm32l4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + #ifdef HAL_IWDG_MODULE_ENABLED #include "stm32l4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ @@ -321,6 +356,18 @@ #include "stm32l4xx_hal_ltdc.h" #endif /* HAL_LTDC_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ @@ -329,6 +376,10 @@ #include "stm32l4xx_hal_ospi.h" #endif /* HAL_OSPI_MODULE_ENABLED */ +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -353,6 +404,10 @@ #include "stm32l4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + #ifdef HAL_SMBUS_MODULE_ENABLED #include "stm32l4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ @@ -361,6 +416,10 @@ #include "stm32l4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + #ifdef HAL_SWPMI_MODULE_ENABLED #include "stm32l4xx_hal_swpmi.h" #endif /* HAL_SWPMI_MODULE_ENABLED */ @@ -381,30 +440,10 @@ #include "stm32l4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - #ifdef HAL_WWDG_MODULE_ENABLED #include "stm32l4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_GFXMMU_MODULE_ENABLED - #include "stm32l4xx_hal_gfxmmu.h" -#endif /* HAL_GFXMMU_MODULE_ENABLED */ - /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /* ALL MBED targets use same stm32_assert.h */ @@ -417,7 +456,7 @@ } #endif -#endif /* __STM32L4xx_HAL_CONF_H */ +#endif /* STM32L4xx_HAL_CONF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c index 99afff61e4..ee9ada55b0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c @@ -67,7 +67,7 @@ The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - + ========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== @@ -76,43 +76,27 @@ -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bit for subpriority - -------------------------------------------------------------------------------------------------------------------------- + -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bit for subpriority + | | | 0 bit for subpriority ========================================================================================================================== ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -225,7 +209,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } @@ -241,7 +225,7 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } @@ -257,7 +241,7 @@ void HAL_NVIC_SystemReset(void) } /** - * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. @@ -444,15 +428,15 @@ void HAL_MPU_Disable(void) /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - + /* Disable the MPU and clear the control register*/ MPU->CTRL = 0U; } /** * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI @@ -464,10 +448,10 @@ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - + /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - + /* Ensure MPU settings take effects */ __DSB(); __ISB(); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h index f3eea8a70c..4f550803f9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -63,26 +47,26 @@ */ typedef struct { - uint8_t Enable; /*!< Specifies the status of the region. + uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. + uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. + uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. + uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** @@ -228,7 +212,7 @@ typedef struct * @} */ -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) @@ -275,7 +259,7 @@ typedef struct * @{ */ -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @{ */ @@ -291,7 +275,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); * @} */ -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @{ */ @@ -319,7 +303,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); * @} */ -/* Private types -------------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c index ffa5acb034..b530e4605e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c @@ -4,7 +4,7 @@ * @author MCD Application Team * @brief CRC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the CRC peripheral: + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * + Peripheral State functions @@ -16,8 +16,8 @@ [..] (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); (+) Initialize CRC calculator - (++) specify generating polynomial (IP default or non-default one) - (++) specify initialization value (IP default or non-default one) + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) (++) specify input data format (++) specify input or output data inversion mode if any (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the @@ -31,29 +31,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -113,13 +97,13 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @brief Initialize the CRC according to the specified * parameters in the CRC_InitTypeDef and create the associated handle. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == NULL) + if (hcrc == NULL) { return HAL_ERROR; } @@ -127,11 +111,10 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - if(hcrc->State == HAL_CRC_STATE_RESET) + if (hcrc->State == HAL_CRC_STATE_RESET) { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -143,13 +126,13 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) { - /* initialize IP with default generating polynomial */ + /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); } else { - /* initialize CRC IP with generating polynomial defined by user */ + /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) { return HAL_ERROR; @@ -190,13 +173,13 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /** * @brief DeInitialize the CRC peripheral. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == NULL) + if (hcrc == NULL) { return HAL_ERROR; } @@ -205,7 +188,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); /* Check the CRC peripheral state */ - if(hcrc->State == HAL_CRC_STATE_BUSY) + if (hcrc->State == HAL_CRC_STATE_BUSY) { return HAL_BUSY; } @@ -217,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -234,7 +217,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -249,7 +232,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) /** * @brief DeInitialize the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -275,7 +258,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) =============================================================================== [..] This section provides functions allowing to: (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - using the combination of the previous CRC value and the new one + using combination of the previous CRC value and the new one. [..] or @@ -289,10 +272,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -303,11 +286,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - - /* Process locked */ - __HAL_LOCK(hcrc); + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; @@ -316,7 +296,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for (index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -324,13 +304,12 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ break; case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; - default: break; } @@ -338,21 +317,17 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - /* Return the CRC computed value */ return temp; } - /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -363,11 +338,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - - /* Process locked */ - __HAL_LOCK(hcrc); + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; @@ -380,7 +352,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for (index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -389,12 +361,12 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); break; case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: @@ -404,9 +376,6 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - /* Return the CRC computed value */ return temp; } @@ -431,7 +400,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** * @brief Return the CRC handle state. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) @@ -448,84 +417,85 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @} */ -/** @defgroup CRC_Private_Functions CRC Private Functions +/** @addtogroup CRC_Private_Functions * @{ */ /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i; /* input data buffer index */ uint16_t data; __IO uint16_t *pReg; - /* Processing time optimization: 4 bytes are entered in a row with a single word write, - * last bytes must be carefully fed to the CRC calculator to ensure a correct type - * handling by the IP */ - for(i = 0; i < (BufferLength/4); i++) - { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; - } - /* last bytes specific handling */ - if ((BufferLength%4) != 0) - { - if (BufferLength%4 == 1) - { - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i]; - } - if (BufferLength%4 == 2) - { - data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); - *pReg = data; - } - if (BufferLength%4 == 3) - { - data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); - *pReg = data; + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i+2]; - } - } + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } /* Return the CRC computed value */ return hcrc->Instance->DR; } - - /** * @brief Enter 16-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i; /* input data buffer index */ __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure - * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; } - if ((BufferLength%2) != 0) + if ((BufferLength % 2U) != 0U) { - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); - *pReg = pBuffer[2*i]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; } /* Return the CRC computed value */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h index 035242c9dc..342427d8b1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CRC_H -#define __STM32L4xx_HAL_CRC_H +#ifndef STM32L4xx_HAL_CRC_H +#define STM32L4xx_HAL_CRC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,48 +34,45 @@ /** @addtogroup CRC * @{ - */ - -/* Exported types ------------------------------------------------------------*/ + */ +/* Exported types ------------------------------------------------------------*/ /** @defgroup CRC_Exported_Types CRC Exported Types * @{ */ -/** - * @brief CRC HAL State Structure definition - */ +/** + * @brief CRC HAL State Structure definition + */ typedef enum -{ - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ -}HAL_CRC_StateTypeDef; +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; - - -/** - * @brief CRC Init Structure definition - */ +/** + * @brief CRC Init Structure definition + */ typedef struct { - uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. - If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ - uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, + respectively equal to 7, 8, 16 or 32. This field is written in normal representation, e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. - No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of @@ -99,49 +80,45 @@ typedef struct @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ - - uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse - is set to DEFAULT_INIT_VALUE_ENABLE. */ - - uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. - Can be either one of the following values + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ - + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. - Can be either - @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ -}CRC_InitTypeDef; + Can be either + @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ +} CRC_InitTypeDef; - - -/** - * @brief CRC Handle Structure definition - */ +/** + * @brief CRC Handle Structure definition + */ typedef struct { - CRC_TypeDef *Instance; /*!< Register base address */ - + CRC_TypeDef *Instance; /*!< Register base address */ + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ - + HAL_LockTypeDef Lock; /*!< CRC Locking object */ - + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ - - uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. - Can be either + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) - + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error - must occur if InputBufferFormat is not one of the three values listed above */ -}CRC_HandleTypeDef; - - + must occur if InputBufferFormat is not one of the three values listed above */ +} CRC_HandleTypeDef; /** * @} */ @@ -170,28 +147,28 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ /** * @} */ - + /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ - */ + */ #define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ #define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ /** * @} */ -/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral * @{ */ -#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */ -#define CRC_POLYLENGTH_16B (CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ -#define CRC_POLYLENGTH_8B (CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ -#define CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ +#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ /** * @} */ @@ -199,29 +176,29 @@ typedef struct /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ -#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ -#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ -#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ -#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ /** * @} - */ + */ /** @defgroup CRC_Input_Buffer_Format Input Buffer Format * @{ */ /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but - * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set - * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for - * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ -#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ -#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ -#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ -/** + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ +/** * @} */ - + /** @defgroup CRC_Aliases CRC API aliases * @{ */ @@ -235,45 +212,44 @@ typedef struct * @} */ - /* Exported macros -----------------------------------------------------------*/ /** @defgroup CRC_Exported_Macros CRC Exported Macros * @{ */ /** @brief Reset CRC handle state. - * @param __HANDLE__: CRC handle. + * @param __HANDLE__ CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Reset CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Set CRC INIT non-default value - * @param __HANDLE__: CRC handle - * @param __INIT__: 32-bit initial value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value * @retval None */ -#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** * @brief Store data in the Independent Data (ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: Value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Return the data stored in the Independent Data (ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval Value of the ID register */ @@ -284,25 +260,25 @@ typedef struct /* Private macros --------------------------------------------------------*/ -/** @addtogroup CRC_Private_Macros CRC Private Macros +/** @defgroup CRC_Private_Macros CRC Private Macros * @{ */ #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - + #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ - ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) - + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + #define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ ((LENGTH) == CRC_POLYLENGTH_16B) || \ ((LENGTH) == CRC_POLYLENGTH_8B) || \ - ((LENGTH) == CRC_POLYLENGTH_7B)) + ((LENGTH) == CRC_POLYLENGTH_7B)) -#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ - ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) /** * @} @@ -319,9 +295,9 @@ typedef struct /* Initialization and de-initialization functions ****************************/ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions * @{ - */ + */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); -HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); /** @@ -353,7 +329,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); /** * @} - */ + */ /** * @} @@ -363,6 +339,6 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); } #endif -#endif /* __STM32L4xx_HAL_CRC_H */ +#endif /* STM32L4xx_HAL_CRC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c index cc30ffe074..cc8ee03568 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c @@ -3,9 +3,9 @@ * @file stm32l4xx_hal_crc_ex.c * @author MCD Application Team * @brief Extended CRC HAL module driver. - * This file provides firmware functions to manage the extended - * functionalities of the CRC peripheral. - * + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * @verbatim ================================================================================ ##### How to use this driver ##### @@ -18,31 +18,15 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -73,7 +57,7 @@ /** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions * @brief Extended Initialization and Configuration functions. * -@verbatim +@verbatim =============================================================================== ##### Extended configuration functions ##### =============================================================================== @@ -81,7 +65,7 @@ (+) Configure the generating polynomial (+) Configure the input data inversion (+) Configure the output data inversion - + @endverbatim * @{ */ @@ -89,123 +73,129 @@ /** * @brief Initialize the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long). + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). * This parameter is written in normal representation, e.g. - * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 - * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. * This parameter can be one of the following values: * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) - * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { - uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - + /* check polynomial definition vs polynomial size: * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is + * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while (((Pol & (1U << msb)) == 0) && (msb-- > 0)) {} + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } switch (PolyLength) { case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) + if (msb >= HAL_CRC_LENGTH_7B) { - return HAL_ERROR; + status = HAL_ERROR; } break; case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) { - return HAL_ERROR; - } + status = HAL_ERROR; + } break; case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) { - return HAL_ERROR; - } + status = HAL_ERROR; + } break; + case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ - break; + break; default: - return HAL_ERROR; + status = HAL_ERROR; + break; } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); - /* set generating polynomial */ - WRITE_REG(hcrc->Instance->POL, Pol); - - /* set generating polynomial size */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); - + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } /* Return function status */ - return HAL_OK; + return status; } /** * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. * This parameter can be one of the following values: * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal - * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) -{ +{ /* Check the parameters */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; /* set input data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. * This parameter can be one of the following values: * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) - * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) { /* Check the parameters */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; /* set output data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); - + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h index 4e20acf7f8..11dad827db 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CRC_EX_H -#define __STM32L4xx_HAL_CRC_EX_H +#ifndef STM32L4xx_HAL_CRC_EX_H +#define STM32L4xx_HAL_CRC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,21 +34,21 @@ /** @addtogroup CRCEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants +/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants * @{ */ /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */ -#define CRC_INPUTDATA_INVERSION_BYTE (CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_HALFWORD (CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_WORD (CRC_CR_REV_IN) /*!< Word-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ /** * @} */ @@ -72,39 +56,39 @@ /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */ -#define CRC_OUTPUTDATA_INVERSION_ENABLE (CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ /** * @} */ -/** +/** * @} */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros +/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros * @{ */ - + /** * @brief Set CRC output reversal - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ -#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) /** * @brief Unset CRC output reversal - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ -#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) /** * @brief Set CRC non-default polynomial - * @param __HANDLE__: CRC handle - * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial * @retval None */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) @@ -114,18 +98,17 @@ */ /* Private macros --------------------------------------------------------*/ -/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros +/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros * @{ */ - -#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) - #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ - ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) /** * @} @@ -133,14 +116,13 @@ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions +/** @addtogroup CRCEx_Exported_Functions * @{ */ - -/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + +/** @addtogroup CRCEx_Exported_Functions_Group1 * @{ */ - /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); @@ -148,24 +130,24 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ /** * @} - */ - -/** - * @} - */ - -/** - * @} - */ + */ /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_CRC_EX_H */ +#endif /* STM32L4xx_HAL_CRC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c index 0be7c96a57..405ffa4ffa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c @@ -3,21 +3,21 @@ * @file stm32l4xx_hal_cryp.c * @author MCD Application Team * @brief CRYP HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: * + Initialization and de-initialization functions * + Processing functions using polling mode * + Processing functions using interrupt mode * + Processing functions using DMA mode * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The CRYP HAL driver can be used as follows: - + (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): (++) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE() (++) In case of using interrupts (e.g. HAL_CRYP_AES_IT()) @@ -25,7 +25,7 @@ (+++) Enable the AES IRQ handler using HAL_NVIC_EnableIRQ() (+++) In AES IRQ handler, call HAL_CRYP_IRQHandler() (++) In case of using DMA to control data transfer (e.g. HAL_CRYPEx_AES_DMA()) - (+++) Enable the DMA2 interface clock using + (+++) Enable the DMA2 interface clock using __HAL_RCC_DMA2_CLK_ENABLE() (+++) Configure and enable two DMA channels one for managing data transfer from memory to peripheral (input channel) and another channel for managing data @@ -36,14 +36,14 @@ interrupt on the two DMA channels. The output channel should have higher priority than the input channel. Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - + (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures: (++) The data type: 1-bit, 8-bit, 16-bit and 32-bit (++) The AES operating mode (encryption, key derivation and/or decryption) - (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC when applicable, CCM when applicable) + (++) The AES chaining mode (ECB, CBC, CTR, GCM, GMAC, CMAC when applicable, CCM when applicable) (++) The encryption/decryption key if so required (++) The initialization vector or nonce if applicable (not used in ECB mode). - + (#)Three processing (encryption/decryption) functions are available: (++) Polling mode: encryption and decryption APIs are blocking functions i.e. they process the data and wait till the processing is finished @@ -51,46 +51,81 @@ i.e. they process the data under interrupt (++) DMA mode: encryption and decryption APIs are not blocking functions i.e. the data transfer is ensured by DMA - + (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_CRYP_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + (+) InCpltCallback : callback for input DMA transfer completion. + (+) OutCpltCallback : callback for output DMA transfer completion. + (+) CompCpltCallback : callback for computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) InCpltCallback : callback for input DMA transfer completion. + (+) OutCpltCallback : callback for output DMA transfer completion. + (+) CompCpltCallback : callback for computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + + (#) By default, after the @ref HAL_CRYP_Init and if the state is HAL_CRYP_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_CRYP_InCpltCallback(), @ref HAL_CRYP_ErrorCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_CRYP_Init + and @ref HAL_CRYP_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init and @ref HAL_CRYP_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CRYP_RegisterCallback before calling @ref HAL_CRYP_DeInit + or @ref HAL_¨CRYP_Init function. + + When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(AES) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -127,92 +162,92 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); * @{ */ -/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions - * @brief Initialization and Configuration functions. +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim ============================================================================== ##### Initialization and deinitialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize the CRYP according to the specified parameters + (+) Initialize the CRYP according to the specified parameters in the CRYP_InitTypeDef and creates the associated handle (+) DeInitialize the CRYP peripheral (+) Initialize the CRYP MSP (MCU Specific Package) (+) De-Initialize the CRYP MSP - + [..] (@) Specific care must be taken to format the key and the Initialization Vector IV! - - [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where - b127 is the MSB and b0 the LSB, the key must be stored in MCU memory + + [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where + b127 is the MSB and b0 the LSB, the key must be stored in MCU memory (+) as a sequence of words where the MSB word comes first (occupies the - lowest memory address) + lowest memory address) (+) where each word is byte-swapped: (++) address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120 (++) address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88 (++) address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56 - (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24 + (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24 [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}. - The 4 32-bit words that make the key must be stored as follows in MCU memory: + The 4 32-bit words that make the key must be stored as follows in MCU memory: (+) address n+0 : 0x B12 B13 B14 B15 (+) address n+4 : 0x B8 B9 B10 B11 (+) address n+8 : 0x B4 B5 B6 B7 - (+) address n+C : 0x B0 B1 B2 B3 - [..] which leads to the expected setting - (+) AES_KEYR3 = 0x B15 B14 B13 B12 - (+) AES_KEYR2 = 0x B11 B10 B9 B8 - (+) AES_KEYR1 = 0x B7 B6 B5 B4 - (+) AES_KEYR0 = 0x B3 B2 B1 B0 - - [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. + (+) address n+C : 0x B0 B1 B2 B3 + [..] which leads to the expected setting + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. The 8 32-bit words that make the key must be stored as follows in MCU memory: (+) address n+00 : 0x B28 B29 B30 B31 (+) address n+04 : 0x B24 B25 B26 B27 (+) address n+08 : 0x B20 B21 B22 B23 - (+) address n+0C : 0x B16 B17 B18 B19 + (+) address n+0C : 0x B16 B17 B18 B19 (+) address n+10 : 0x B12 B13 B14 B15 (+) address n+14 : 0x B8 B9 B10 B11 (+) address n+18 : 0x B4 B5 B6 B7 - (+) address n+1C : 0x B0 B1 B2 B3 - [..] which leads to the expected setting - (+) AES_KEYR7 = 0x B31 B30 B29 B28 - (+) AES_KEYR6 = 0x B27 B26 B25 B24 - (+) AES_KEYR5 = 0x B23 B22 B21 B20 - (+) AES_KEYR4 = 0x B19 B18 B17 B16 - (+) AES_KEYR3 = 0x B15 B14 B13 B12 - (+) AES_KEYR2 = 0x B11 B10 B9 B8 - (+) AES_KEYR1 = 0x B7 B6 B5 B4 - (+) AES_KEYR0 = 0x B3 B2 B1 B0 - - [..] Initialization Vector IV (4 32-bit words) format must follow the same as - that of a 128-bit long key. - - [..] - + (+) address n+1C : 0x B0 B1 B2 B3 + [..] which leads to the expected setting + (+) AES_KEYR7 = 0x B31 B30 B29 B28 + (+) AES_KEYR6 = 0x B27 B26 B25 B24 + (+) AES_KEYR5 = 0x B23 B22 B21 B20 + (+) AES_KEYR4 = 0x B19 B18 B17 B16 + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Initialization Vector IV (4 32-bit words) format must follow the same as + that of a 128-bit long key. + + [..] + @endverbatim * @{ */ /** * @brief Initialize the CRYP according to the specified - * parameters in the CRYP_InitTypeDef and initialize the associated handle. - * @note Specific care must be taken to format the key and the Initialization Vector IV - * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations - * hereabove. + * parameters in the CRYP_InitTypeDef and initialize the associated handle. + * @note Specific care must be taken to format the key and the Initialization Vector IV + * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations + * hereabove. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) -{ +{ /* Check the CRYP handle allocation */ if(hcryp == NULL) { return HAL_ERROR; } - + /* Check the instance */ assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance)); - + /* Check the parameters */ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); @@ -223,42 +258,62 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode)); } assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag)); - + /*========================================================*/ /* Check the proper operating/chaining modes combinations */ - /*========================================================*/ + /*========================================================*/ /* Check the proper chaining when the operating mode is key derivation and decryption */ #if defined(AES_CR_NPBLB) if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\ ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM))) -#else +#else if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\ ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \ || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))) -#endif - { - return HAL_ERROR; - } - /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */ -#if defined(AES_CR_NPBLB) - if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) - && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) -#else - if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) - && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) -#endif +#endif { return HAL_ERROR; } - - + /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */ +#if defined(AES_CR_NPBLB) + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) +#else + if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) + && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) +#endif + { + return HAL_ERROR; + } + + /*================*/ /* Initialization */ - /*================*/ + /*================*/ /* Initialization start */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + if (hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + /* Reset Callback pointers in HAL_CRYP_STATE_RESET only */ + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak (surcharged) input DMA transfer completion callback */ + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak (surcharged) output DMA transfer completion callback */ + hcryp->CompCpltCallback = HAL_CRYPEx_ComputationCpltCallback; /* Legacy weak (surcharged) computation completion callback */ + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak (surcharged) error callback */ + if(hcryp->MspInitCallback == NULL) + { + hcryp->MspInitCallback = HAL_CRYP_MspInit; + } + + /* Init the low level hardware */ + hcryp->MspInitCallback(hcryp); + } +#else if(hcryp->State == HAL_CRYP_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -267,33 +322,34 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /* Init the low level hardware */ HAL_CRYP_MspInit(hcryp); } - +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - + hcryp->State = HAL_CRYP_STATE_BUSY; + /* Disable the Peripheral */ __HAL_CRYP_DISABLE(hcryp); - + /*=============================================================*/ - /* AES initialization common to all operating modes */ + /* AES initialization common to all operating modes */ /*=============================================================*/ /* Set the Key size selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize); - + /* Set the default CRYP phase when this parameter is not used. Phase is updated below in case of GCM/GMAC(/CMAC)(/CCM) setting. */ hcryp->Phase = HAL_CRYP_PHASE_NOT_USED; - - + + /*=============================================================*/ - /* Carry on the initialization based on the AES operating mode */ + /* Carry on the initialization based on the AES operating mode */ /*=============================================================*/ - /* Key derivation */ + /* Key derivation */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION); - + /* Configure the Key registers */ if (CRYP_SetKey(hcryp) != HAL_OK) { @@ -302,46 +358,46 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } else /* Encryption / Decryption (with or without key derivation) / authentication */ - { -#if !defined(AES_CR_NPBLB) + { +#if !defined(AES_CR_NPBLB) /* Set data type, operating and chaining modes. In case of GCM or GMAC, data type is forced to 0b00 */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode); } - - /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), + + /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), Galois message authentication code (GMAC), cipher message authentication code (CMAC) when applicable or Counter with Cipher Mode (CCM) when applicable */ -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) #else if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase); hcryp->Phase = HAL_CRYP_PHASE_START; } - + /* Configure the Key registers if no need to bypass this step */ if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE) { if (CRYP_SetKey(hcryp) != HAL_OK) { return HAL_ERROR; - } + } } - + /* If applicable, configure the Initialization Vector */ if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB) { @@ -351,34 +407,34 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } } } - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* Clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif +#endif /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; hcryp->CrypOutCount = 0; - + /* Reset ErrorCode field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; - + /* Reset Mode suspension request */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Enable the Peripheral */ __HAL_CRYP_ENABLE(hcryp); - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CRYP peripheral. + * @brief DeInitialize the CRYP peripheral. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status @@ -390,29 +446,39 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { return HAL_ERROR; } - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Set the default CRYP phase */ hcryp->Phase = HAL_CRYP_PHASE_READY; - + /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; hcryp->CrypOutCount = 0; - + /* Disable the CRYP Peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); - + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + if(hcryp->MspDeInitCallback == NULL) + { + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + } + + /* DeInit the low level hardware */ + hcryp->MspDeInitCallback(hcryp); +#else /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_CRYP_MspDeInit(hcryp); - +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hcryp); - + /* Return function status */ return HAL_OK; } @@ -453,13 +519,13 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @} */ -/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions - * @brief Processing functions. +/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions + * @brief Processing functions. * -@verbatim +@verbatim ============================================================================== ##### AES processing functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Encrypt plaintext using AES algorithm in different chaining modes (+) Decrypt cyphertext using AES algorithm in different chaining modes @@ -471,8 +537,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) @endverbatim * @{ */ - - + + /** * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains @@ -480,9 +546,9 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -502,7 +568,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); } - + /** * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. @@ -513,11 +579,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * @param pCypherData: Pointer to the cyphertext buffer * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) -{ +{ /* Re-initialize AES IP with proper parameters */ if (HAL_CRYP_DeInit(hcryp) != HAL_OK) { @@ -530,7 +596,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP { return HAL_ERROR; } - + return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout); } @@ -542,9 +608,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -566,16 +632,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP } /** - * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, + * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -597,16 +663,16 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC } /** - * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, + * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -623,12 +689,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC { return HAL_ERROR; } - + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); } /** - * @brief Decrypt pCypherData in AES CTR decryption mode, + * @brief Decrypt pCypherData in AES CTR decryption mode, * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module @@ -637,7 +703,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * @param pPlainData: Pointer to the plaintext buffer * @param Timeout: Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -653,8 +719,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout); } @@ -667,7 +733,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -683,21 +749,21 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); } /** * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -714,21 +780,21 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); } - + /** * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -745,20 +811,20 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData); } /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -775,20 +841,20 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -805,20 +871,20 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). + * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -834,14 +900,14 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData); } /** * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer @@ -849,7 +915,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -866,15 +932,15 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); } - - + + /** * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer @@ -882,7 +948,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @param pCypherData: Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -899,13 +965,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData); } /** * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, - * the cypher data are available in pCypherData. + * the cypher data are available in pCypherData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer @@ -913,7 +979,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @param pCypherData: Pointer to the cyphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -936,15 +1002,15 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -961,13 +1027,13 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer @@ -975,7 +1041,7 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -992,21 +1058,21 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { return HAL_ERROR; } - + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); } /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, - * the decyphered data are available in pPlainData. + * the decyphered data are available in pPlainData. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. * @param pPlainData: Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly - * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). - * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). + * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1022,8 +1088,8 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t if (HAL_CRYP_Init(hcryp) != HAL_OK) { return HAL_ERROR; - } - + } + return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData); } @@ -1032,13 +1098,13 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @} */ -/** @defgroup CRYP_Exported_Functions_Group3 Callback functions - * @brief Callback functions. +/** @defgroup CRYP_Exported_Functions_Group3 Callback functions + * @brief Callback functions. * -@verbatim +@verbatim ============================================================================== ##### Callback functions ##### - ============================================================================== + ============================================================================== [..] This section provides Interruption and DMA callback functions: (+) DMA Input data transfer complete (+) DMA Output data transfer complete @@ -1096,17 +1162,206 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) */ } +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User CRYP Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hcryp CRYP handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUTCPLT_CB_ID CRYP input DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_OUTPUTCPLT_CB_ID CRYP output DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_COMPCPLT_CB_ID CRYP computation completion Callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID CRYP error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID CRYP MspDeInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID CRYP MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hcryp); + + if(HAL_CRYP_STATE_READY == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_INPUTCPLT_CB_ID : + hcryp->InCpltCallback = pCallback; + break; + + case HAL_CRYP_OUTPUTCPLT_CB_ID : + hcryp->OutCpltCallback = pCallback; + break; + + case HAL_CRYP_COMPCPLT_CB_ID : + hcryp->CompCpltCallback = pCallback; + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = pCallback; + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_CRYP_STATE_RESET == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return status; +} + +/** + * @brief Unregister a CRYP Callback + * CRYP Callback is redirected to the weak (surcharged) predefined callback + * @param hcryp CRYP handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUTCPLT_CB_ID CRYP input DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_OUTPUTCPLT_CB_ID CRYP output DMA transfer completion Callback ID + * @arg @ref HAL_CRYP_COMPCPLT_CB_ID CRYP computation completion Callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID CRYP error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID CRYP MspDeInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID CRYP MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hcryp); + + if(HAL_CRYP_STATE_READY == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_INPUTCPLT_CB_ID : + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak (surcharged) input DMA transfer completion callback */ + break; + + case HAL_CRYP_OUTPUTCPLT_CB_ID : + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak (surcharged) output DMA transfer completion callback */ + break; + + case HAL_CRYP_COMPCPLT_CB_ID : + hcryp->CompCpltCallback = HAL_CRYPEx_ComputationCpltCallback; /* Legacy weak (surcharged) computation completion callback */ + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak (surcharged) error callback */ + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_CRYP_STATE_RESET == hcryp->State) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return status; +} +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler +/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler * @brief AES IRQ handler. * -@verbatim +@verbatim ============================================================================== ##### AES IRQ handler management ##### - ============================================================================== + ============================================================================== [..] This section provides AES IRQ handler function. @endverbatim @@ -1136,47 +1391,68 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) hcryp->ErrorCode |= HAL_CRYP_READ_ERROR; hcryp->State = HAL_CRYP_STATE_ERROR; } - + /* If an error has been reported */ if (hcryp->State == HAL_CRYP_STATE_ERROR) - { + { /* Disable Error and Computation Complete Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Clear all Interrupt flags */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR|CRYP_CCF_CLEAR); - + /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - + __HAL_UNLOCK(hcryp); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); - - return; +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + return; } } - - /* Check if computation complete interrupt is enabled + + /* Check if computation complete interrupt is enabled and if the computation complete flag is raised */ - if((__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)) - { + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) + { + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + { #if defined(AES_CR_NPBLB) - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) - || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) -#else - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) - || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) -#endif - { - /* To ensure proper suspension requests management, CCF flag - is reset in CRYP_AES_Auth_IT() according to the current - phase under handling */ - CRYP_AES_Auth_IT(hcryp); - } - else - { - /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - CRYP_AES_IT(hcryp); + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)) +#else + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) + || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)) +#endif + { + /* To ensure proper suspension requests management, CCF flag + is reset in CRYP_AES_Auth_IT() according to the current + phase under handling */ + if (CRYP_AES_Auth_IT(hcryp) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear Computation Complete Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + if (CRYP_AES_IT(hcryp) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } } } } @@ -1185,13 +1461,13 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * @} */ -/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions. * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### - ============================================================================== + ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -1215,7 +1491,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) * @brief Return the CRYP peripheral error. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @note The returned error is a bit-map combination of possible errors + * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map */ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) @@ -1237,62 +1513,62 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) /** - * @brief Write the Key in KeyRx registers. + * @brief Write the Key in KeyRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) -{ - uint32_t keyaddr = 0x0; - - if ((uint32_t)(hcryp->Init.pKey == NULL)) +{ + uint32_t keyaddr; + + if (hcryp->Init.pKey == NULL) { return HAL_ERROR; } - - + + keyaddr = (uint32_t)(hcryp->Init.pKey); - + if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - } - + keyaddr+=4U; + } + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); - + keyaddr+=4U; + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + return HAL_OK; } /** - * @brief Write the InitVector/InitCounter in IVRx registers. + * @brief Write the InitVector/InitCounter in IVRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) { - uint32_t ivaddr = 0x0; - + uint32_t ivaddr; + #if !defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { hcryp->Instance->IVR3 = 0; hcryp->Instance->IVR2 = 0; - hcryp->Instance->IVR1 = 0; + hcryp->Instance->IVR1 = 0; hcryp->Instance->IVR0 = 0; } else @@ -1301,16 +1577,16 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) if (hcryp->Init.pInitVect == NULL) { return HAL_ERROR; - } - + } + ivaddr = (uint32_t)(hcryp->Init.pInitVect); - + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } return HAL_OK; @@ -1318,7 +1594,7 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) -/** +/** * @brief Handle CRYP block input/output data handling under interruption. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_IT(). @@ -1328,64 +1604,68 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t inputaddr = 0; - uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + uint32_t inputaddr; + uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; if(hcryp->State == HAL_CRYP_STATE_BUSY) { if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) - { + { /* Read the last available output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - + hcryp->CrypOutCount -= 16U; + } else { /* Read the derived key from the Key registers */ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) - { + { *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); - outputaddr+=4; + outputaddr+=4U; } - + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); } - + /* In case of ciphering or deciphering, check if all output text has been retrieved; In case of key derivation, stop right there */ - if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)) + if ((hcryp->CrypOutCount == 0U) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)) { /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } /* If suspension flag has been raised, suspend processing */ @@ -1393,44 +1673,44 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { /* reset ModeSuspend */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; - + /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else /* Process the rest of input data */ { /* Get the Intput data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - + hcryp->CrypInCount -= 16U; + /* Write the next input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - - return HAL_OK; + + return HAL_OK; } } else { - return HAL_BUSY; + return HAL_BUSY; } } - + @@ -1447,8 +1727,8 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /** * @} */ - -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ + +#endif /* AES */ #endif /* HAL_CRYP_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h index dcb2f5d66a..c1ac07e222 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_CRYP_H @@ -41,8 +25,6 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -50,6 +32,8 @@ * @{ */ +#if defined(AES) + /** @addtogroup CRYP * @{ */ @@ -59,7 +43,7 @@ * @{ */ -/** +/** * @brief CRYP Configuration Structure definition */ typedef struct @@ -67,36 +51,36 @@ typedef struct uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ - uint32_t KeySize; /*!< 128 or 256-bit key length. + uint32_t KeySize; /*!< 128 or 256-bit key length. This parameter can be a value of @ref CRYP_Key_Size */ - - uint32_t OperatingMode; /*!< AES operating mode. + + uint32_t OperatingMode; /*!< AES operating mode. This parameter can be a value of @ref CRYP_AES_OperatingMode */ - - uint32_t ChainingMode; /*!< AES chaining mode. + + uint32_t ChainingMode; /*!< AES chaining mode. This parameter can be a value of @ref CRYP_AES_ChainingMode */ - - uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption. - This parameter can be a value of @ref CRYP_Key_Write */ - - uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM), - Galois Message Authentication Code (GMAC), Cipher Message - Authentication Code (CMAC) (when applicable) or Counter with Cipher + + uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption. + This parameter can be a value of @ref CRYP_Key_Write */ + + uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM), + Galois Message Authentication Code (GMAC), Cipher Message + Authentication Code (CMAC) (when applicable) or Counter with Cipher Mode (CCM) (when applicable). - This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */ + This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */ uint8_t* pKey; /*!< Encryption/Decryption Key */ - uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable) + uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */ uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (when applicable) and CCM (when applicable) modes */ uint64_t HeaderSize; /*!< Header size in bytes */ - + }CRYP_InitTypeDef; -/** +/** * @brief HAL CRYP State structures definition */ typedef enum @@ -109,47 +93,65 @@ typedef enum HAL_CRYP_STATE_SUSPENDED = 0x05 /*!< CRYP suspended */ }HAL_CRYP_STATETypeDef; -/** +/** * @brief HAL CRYP phase structures definition */ typedef enum { HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */ HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */ - HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but + HAL_CRYP_PHASE_START = 0x03, /*!< CRYP peripheral has been initialized but GCM/GMAC(/CMAC)(/CCM) initialization phase has not started */ - HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out */ - HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out */ - HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */ + HAL_CRYP_PHASE_INIT_OVER = 0x04, /*!< GCM/GMAC(/CMAC)(/CCM) init phase has been carried out */ + HAL_CRYP_PHASE_HEADER_OVER = 0x05, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been carried out */ + HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06, /*!< GCM(/CCM) payload phase has been carried out */ HAL_CRYP_PHASE_FINAL_OVER = 0x07, /*!< GCM/GMAC(/CMAC)(/CCM) final phase has been carried out */ HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08, /*!< GCM/GMAC(/CMAC)(/CCM) header phase has been suspended */ - HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */ - HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */ + HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09, /*!< GCM(/CCM) payload phase has been suspended */ + HAL_CRYP_PHASE_NOT_USED = 0x0a /*!< Phase is irrelevant to the current chaining mode */ }HAL_PhaseTypeDef; -/** +/** * @brief HAL CRYP mode suspend definitions */ typedef enum { HAL_CRYP_SUSPEND_NONE = 0x00, /*!< CRYP peripheral suspension not requested */ - HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */ + HAL_CRYP_SUSPEND = 0x01 /*!< CRYP peripheral suspension requested */ }HAL_SuspendTypeDef; -/** - * @brief HAL CRYP Error Codes definition - */ +/** + * @brief HAL CRYP Error Codes definition + */ #define HAL_CRYP_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_CRYP_WRITE_ERROR ((uint32_t)0x00000001) /*!< Write error */ #define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */ -#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */ -#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */ +#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */ +#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -/** +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL CRYP common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CRYP_INPUTCPLT_CB_ID = 0x01U, /*!< CRYP input DMA transfer completion callback ID */ + HAL_CRYP_OUTPUTCPLT_CB_ID = 0x02U, /*!< CRYP output DMA transfer completion callback ID */ + HAL_CRYP_COMPCPLT_CB_ID = 0x03U, /*!< CRYP computation completion callback ID */ + HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP error callback ID */ + HAL_CRYP_MSPINIT_CB_ID = 0x05U, /*!< CRYP MspInit callback ID */ + HAL_CRYP_MSPDEINIT_CB_ID = 0x06U, /*!< CRYP MspDeInit callback ID */ +}HAL_CRYP_CallbackIDTypeDef; +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +/** * @brief CRYP handle Structure definition - */ -typedef struct + */ +typedef struct __CRYP_HandleTypeDef { AES_TypeDef *Instance; /*!< Register base address */ @@ -159,7 +161,7 @@ typedef struct uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */ - uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining + uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining number of bytes to process */ uint32_t CrypOutCount; /*!< Output data size in bytes */ @@ -176,13 +178,35 @@ typedef struct HAL_LockTypeDef Lock; /*!< CRYP locking object */ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ - - HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ + + HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + void (* InCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP input DMA transfer completion callback */ + + void (* OutCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP output DMA transfer completion callback */ + + void (* CompCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP computation completion callback */ + + void (* ErrorCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP error callback */ + + void (* MspInitCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */ + + void (* MspDeInitCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */ + +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ }CRYP_HandleTypeDef; -/** + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL CRYP Callback pointer definition + */ +typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a CRYP common callback functions */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +/** * @} */ @@ -195,8 +219,8 @@ typedef struct /** @defgroup CRYP_Key_Size Key size selection * @{ */ -#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */ -#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ +#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000) /*!< 128-bit long key */ +#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ /** * @} */ @@ -211,19 +235,19 @@ typedef struct /** * @} */ - + /** @defgroup CRYP_AES_State AES Enable state * @{ - */ + */ #define CRYP_AES_DISABLE ((uint32_t)0x00000000) /*!< Disable AES */ #define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */ /** * @} - */ - + */ + /** @defgroup CRYP_AES_OperatingMode AES operating mode * @{ - */ + */ #define CRYP_ALGOMODE_ENCRYPT ((uint32_t)0x00000000) /*!< Encryption mode */ #define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */ #define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */ @@ -231,11 +255,11 @@ typedef struct #define CRYP_ALGOMODE_TAG_GENERATION ((uint32_t)0x00000000) /*!< GMAC or CMAC (when applicable) authentication tag generation */ /** * @} - */ + */ /** @defgroup CRYP_AES_ChainingMode AES chaining mode * @{ - */ + */ #define CRYP_CHAINMODE_AES_ECB ((uint32_t)0x00000000) /*!< Electronic codebook chaining algorithm */ #define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ #define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ @@ -245,19 +269,19 @@ typedef struct #else #define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */ #endif -/** - * @} - */ - -/** @defgroup CRYP_Key_Write AES decryption key write-up flag - * @{ - */ -#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */ -#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */ /** * @} - */ - + */ + +/** @defgroup CRYP_Key_Write AES decryption key write-up flag + * @{ + */ +#define CRYP_KEY_WRITE_ENABLE ((uint32_t)0x00000000) /*!< Enable decryption key writing */ +#define CRYP_KEY_WRITE_DISABLE ((uint32_t)0x00000001) /*!< Disable decryption key writing */ +/** + * @} + */ + /** @defgroup CRYP_DMAIN DMA Input phase management enable state * @{ */ @@ -266,7 +290,7 @@ typedef struct /** * @} */ - + /** @defgroup CRYP_DMAOUT DMA Output phase management enable state * @{ */ @@ -274,22 +298,22 @@ typedef struct #define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */ /** * @} - */ - - + */ + + /** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CCM/CMAC (when applicable) processing phase selection * @{ */ -#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */ -#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC/CCM/CMAC header phase */ -#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM/CCM payload phase */ -#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC/CCM/CMAC final phase */ -/* Definitions duplication for code readibility's sake: +#define CRYP_GCM_INIT_PHASE ((uint32_t)0x00000000) /*!< GCM/GMAC (or CCM) init phase */ +#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC/CCM/CMAC header phase */ +#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM/CCM payload phase */ +#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC/CCM/CMAC final phase */ +/* Definitions duplication for code readibility's sake: supported or not supported chain modes are not specified for each phase */ -#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */ -#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */ -#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */ -#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */ +#define CRYP_INIT_PHASE ((uint32_t)0x00000000) /*!< Init phase */ +#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */ +#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */ +#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */ /** * @} */ @@ -305,7 +329,7 @@ typedef struct /** * @} */ - + /** @defgroup CRYP_Clear_Flags AES clearing flags * @{ */ @@ -318,7 +342,7 @@ typedef struct /** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits * @{ - */ + */ #define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */ #define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */ /** @@ -348,49 +372,57 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @retval None */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /** * @brief Enable the CRYP AES peripheral. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN) /** * @brief Disable the CRYP AES peripheral. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN) /** * @brief Set the algorithm operating mode. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @param __OPERATING_MODE__: specifies the operating mode * This parameter can be one of the following values: - * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption - * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation - * @arg @ref CRYP_ALGOMODE_DECRYPT decryption - * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption + * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption + * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation + * @arg @ref CRYP_ALGOMODE_DECRYPT decryption + * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption * @retval None */ -#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__)) +#define __HAL_CRYP_SET_OPERATINGMODE(__HANDLE__, __OPERATING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_MODE, (__OPERATING_MODE__)) /** * @brief Set the algorithm chaining mode. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @param __CHAINING_MODE__: specifies the chaining mode * This parameter can be one of the following values: - * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook - * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining + * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook + * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining * @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode - * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code + * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code * @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable) * @retval None */ -#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__)) +#define __HAL_CRYP_SET_CHAININGMODE(__HANDLE__, __CHAINING_MODE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_CHMOD, (__CHAINING_MODE__)) @@ -398,10 +430,10 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden - * @arg @ref CRYP_IT_WRERR Write Error - * @arg @ref CRYP_IT_RDERR Read Error - * @arg @ref CRYP_IT_CCF Computation Complete + * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden + * @arg @ref CRYP_IT_WRERR Write Error + * @arg @ref CRYP_IT_RDERR Read Error + * @arg @ref CRYP_IT_CCF Computation Complete * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) @@ -412,7 +444,7 @@ typedef struct * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear - * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear + * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear * @retval None */ #define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__)) @@ -424,7 +456,7 @@ typedef struct * @param __INTERRUPT__: CRYP interrupt source to check * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt * @retval State of interruption (TRUE or FALSE). */ #define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) @@ -434,9 +466,9 @@ typedef struct * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: specifies the interrupt to check. * This parameter can be one of the following values: - * @arg @ref CRYP_IT_WRERR Write Error - * @arg @ref CRYP_IT_RDERR Read Error - * @arg @ref CRYP_IT_CCF Computation Complete + * @arg @ref CRYP_IT_WRERR Write Error + * @arg @ref CRYP_IT_RDERR Read Error + * @arg @ref CRYP_IT_CCF Computation Complete * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) @@ -448,19 +480,19 @@ typedef struct * @param __INTERRUPT__: specifies the IT to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear - * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear + * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear * @retval None */ #define __HAL_CRYP_CLEAR_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** - * @brief Enable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. + * @brief Enable the CRYP interrupt. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt * @retval None */ #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) @@ -468,11 +500,11 @@ typedef struct /** * @brief Disable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt * @retval None */ #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) @@ -488,9 +520,9 @@ typedef struct /** * @brief Verify the key size length. - * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. + * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid) - */ + */ #define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \ ((__KEYSIZE__) == CRYP_KEYSIZE_256B)) @@ -498,7 +530,7 @@ typedef struct * @brief Verify the input data type. * @param __DATATYPE__: Ciphering/deciphering algorithm input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) - */ + */ #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \ ((__DATATYPE__) == CRYP_DATATYPE_16B) || \ ((__DATATYPE__) == CRYP_DATATYPE_8B) || \ @@ -508,45 +540,45 @@ typedef struct * @brief Verify the CRYP AES IP running mode. * @param __MODE__: CRYP AES IP running mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \ - ((__MODE__) == CRYP_AES_ENABLE)) + ((__MODE__) == CRYP_AES_ENABLE)) /** * @brief Verify the selected CRYP algorithm. * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid) - */ + */ #define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \ ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \ ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \ ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \ - ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT)) + ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT)) /** * @brief Verify the selected CRYP chaining algorithm. * @param __CHAINMODE__: Selected CRYP chaining algorithm. * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid) - */ + */ #if defined(AES_CR_NPBLB) #define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \ - ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM)) + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM)) #else #define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \ ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \ - ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC)) -#endif + ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC)) +#endif /** * @brief Verify the deciphering key write option. * @param __WRITE__: deciphering key write option. * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid) - */ + */ #define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \ ((__WRITE__) == CRYP_KEY_WRITE_DISABLE)) @@ -554,28 +586,28 @@ typedef struct * @brief Verify the CRYP input data DMA mode. * @param __MODE__: CRYP input data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \ - ((__MODE__) == CRYP_DMAIN_ENABLE)) + ((__MODE__) == CRYP_DMAIN_ENABLE)) /** * @brief Verify the CRYP output data DMA mode. * @param __MODE__: CRYP output data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \ - ((__MODE__) == CRYP_DMAOUT_ENABLE)) + ((__MODE__) == CRYP_DMAOUT_ENABLE)) /** * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase. * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase. * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid) - */ + */ #define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_INIT_PHASE) || \ ((__PHASE__) == CRYP_HEADER_PHASE) || \ ((__PHASE__) == CRYP_PAYLOAD_PHASE) || \ ((__PHASE__) == CRYP_FINAL_PHASE)) - + /** * @} */ @@ -587,11 +619,11 @@ typedef struct /** @addtogroup CRYP_Exported_Functions CRYP Exported Functions * @{ */ - + /** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions * @{ */ - + /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); @@ -603,10 +635,10 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); /** * @} */ - -/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions + +/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions * @{ - */ + */ /* AES encryption/decryption processing functions ****************************/ @@ -637,22 +669,27 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uin /** * @} */ - + /** @addtogroup CRYP_Exported_Functions_Group3 Callback functions * @{ - */ + */ /* CallBack functions ********************************************************/ void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); - +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /** * @} */ - -/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler + +/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler * @{ - */ + */ /* AES interrupt handling function *******************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); @@ -660,8 +697,8 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); /** * @} */ - -/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions + +/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions * @{ */ @@ -675,17 +712,17 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); /** * @} - */ + */ /** * @} - */ + */ + +#endif /* AES */ /** * @} - */ - -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c index 586dd48ed2..694be0f879 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c @@ -4,44 +4,28 @@ * @author MCD Application Team * @brief CRYPEx HAL module driver. * This file provides firmware functions to manage the extended - * functionalities of the Cryptography (CRYP) peripheral. - * + * functionalities of the Cryptography (CRYP) peripheral. + * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(AES) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -83,8 +67,8 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout); static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAError(DMA_HandleTypeDef *hdma); @@ -100,13 +84,13 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ */ -/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function - * @brief Extended callback functions. +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function + * @brief Extended callback functions. * -@verbatim +@verbatim =============================================================================== ##### Extended callback functions ##### - =============================================================================== + =============================================================================== [..] This section provides callback function: (+) Computation completed. @@ -128,20 +112,20 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) /* NOTE : This function should not be modified; when the callback is needed, the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions - * @brief Extended processing functions. +/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions + * @brief Extended processing functions. * -@verbatim +@verbatim ============================================================================== ##### AES extended processing functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes. Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated @@ -149,14 +133,14 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) (++) Polling mode (++) Interrupt mode (++) DMA mode - (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES + (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES algorithm in different chaining modes. - Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase - so that steps can be skipped if so required. Functions are only differentiated based on the processing type. + Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase + so that steps can be skipped if so required. Functions are only differentiated based on the processing type. Three processing types are available: (++) Polling mode (++) Interrupt mode - (++) DMA mode + (++) DMA mode @endverbatim * @{ @@ -164,19 +148,19 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Carry out in polling mode the ciphering or deciphering operation according to - * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and + * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in polling mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * Parameter is meaningless in case of key derivation. + * Parameter is meaningless in case of key derivation. * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * Parameter is meaningless in case of key derivation. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in - * case of key derivation only. - * @param Timeout: Specify Timeout value + * case of key derivation only. + * @param Timeout: Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -187,25 +171,25 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, /* Check parameters setting */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { - if (pOutputData == NULL) + if (pOutputData == NULL) { return HAL_ERROR; } } else { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U)) { return HAL_ERROR; } } - + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Call CRYP_ReadKey() API if the operating mode is set to key derivation, CRYP_ProcessData() otherwise */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) @@ -213,7 +197,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK) { return HAL_TIMEOUT; - } + } } else { @@ -222,17 +206,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, return HAL_TIMEOUT; } } - + /* If the state has not been set to SUSPENDED, set it to READY, otherwise keep it as it is */ if (hcryp->State != HAL_CRYP_STATE_SUSPENDED) { hcryp->State = HAL_CRYP_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else @@ -245,44 +229,44 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, /** * @brief Carry out in interrupt mode the ciphering or deciphering operation according to - * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and + * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * Parameter is meaningless in case of key derivation. + * Parameter is meaningless in case of key derivation. * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of - * decryption/key derivation+decryption, or pointer to the derivative keys in - * case of key derivation only. + * Parameter is meaningless in case of key derivation. + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * decryption/key derivation+decryption, or pointer to the derivative keys in + * case of key derivation only. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - + uint32_t inputaddr; + if(hcryp->State == HAL_CRYP_STATE_READY) { /* Check parameters setting */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { - if (pOutputData == NULL) + if (pOutputData == NULL) { return HAL_ERROR; } } else { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U)) { return HAL_ERROR; } } /* Process Locked */ __HAL_LOCK(hcryp); - + /* If operating mode is not limited to key derivation only, get the buffers addresses and sizes */ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) @@ -299,50 +283,50 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD (will point at derivated key) */ hcryp->pCrypOutBuffPtr = pOutputData; } - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Enable Computation Complete Flag and Error Interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); - - - /* If operating mode is key derivation only, the input data have + + + /* If operating mode is key derivation only, the input data have already been entered during the initialization process. For - the other operating modes, they are fed to the CRYP hardware + the other operating modes, they are fed to the CRYP hardware block at this point. */ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION) { - /* Initiate the processing under interrupt in entering + /* Initiate the processing under interrupt in entering the first input data */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; /* Write the first input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } - + /* Return function status */ return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - - - + + + /** @@ -351,140 +335,144 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption - * or key derivation+decryption. + * or key derivation+decryption. * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption. - * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. - * @note Supported operating modes are encryption, decryption and key derivation with decryption. - * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx - * registers must be done by software. - * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx + * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. + * @note Supported operating modes are encryption, decryption and key derivation with decryption. + * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx + * registers must be done by software. + * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs. - * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - uint32_t outputaddr = 0; - + uint32_t inputaddr; + uint32_t outputaddr; + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Check parameters setting */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) { - /* no DMA channel is provided for key derivation operating mode, + /* no DMA channel is provided for key derivation operating mode, access to AES_KEYRx registers must be done by software */ return HAL_ERROR; } else { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U)) { return HAL_ERROR; } } - - + + /* Process Locked */ __HAL_LOCK(hcryp); - + inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the input and output addresses and start DMA transfer */ + + /* Set the input and output addresses and start DMA transfer */ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Return function status */ return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - + /** - * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering - * operation according to hcryp->Init structure fields. + * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: - * - pointer to payload data in GCM or CCM payload phase, + * @param pInputData: + * - pointer to payload data in GCM or CCM payload phase, * - pointer to B0 block in CMAC header phase, - * - pointer to C block in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. - * @param Size: + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. + * @param Size: * - length of the input payload data buffer in bytes in GCM or CCM payload phase, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CCM final phase. - * - Parameter is message length in bytes in case of GCM final phase. - * - Parameter must be set to zero in case of GMAC final phase. - * @param pOutputData: - * - pointer to plain or cipher text in GCM/CCM payload phase, + * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. + * - Parameter is meaningless in case of CCM final phase. + * - Parameter is message length in bytes in case of GCM final phase. + * - Parameter must be set to zero in case of GMAC final phase. + * @param pOutputData: + * - pointer to plain or cipher text in GCM/CCM payload phase, * - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CMAC header phase. - * @param Timeout: Specify Timeout value + * - Parameter is meaningless in case of CMAC header phase. + * @param Timeout: Specify Timeout value * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. - * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes - * can be skipped by the user if so required. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout) { - uint32_t index = 0; - uint32_t inputaddr = 0; - uint32_t outputaddr = 0; - uint32_t tagaddr = 0; - uint64_t headerlength = 0; - uint64_t inputlength = 0; - uint64_t payloadlength = 0; + uint32_t index ; + uint32_t inputaddr ; + uint32_t outputaddr ; + uint32_t tagaddr ; + uint64_t headerlength ; + uint64_t inputlength ; + uint64_t payloadlength ; uint32_t difflength = 0; - uint32_t addhoc_process = 0; - + uint32_t addhoc_process = 0; + if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ - if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { - if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) || - ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0))) + /* No processing required */ + } + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U)) || + ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0U))) { return HAL_ERROR; } #if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif +#endif { /* In case of CMAC or CCM (when applicable) header phase resumption, we can have pInputData = NULL and Size = 0 */ - if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U))) { return HAL_ERROR; } } } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) - { - if (((pInputData == NULL) && (Size != 0)) || \ - ((pInputData != NULL) && (Size == 0)) || \ - ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))) + { + if (((pInputData == NULL) && (Size != 0U)) || \ + ((pInputData != NULL) && (Size == 0U)) || \ + ((pInputData != NULL) && (Size != 0U) && (pOutputData == NULL))) { return HAL_ERROR; } @@ -495,37 +483,42 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput { return HAL_ERROR; } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) { return HAL_ERROR; } -#endif +#endif } - - + else + { + /* Unspecified Phase */ + return HAL_ERROR; + } + + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /*==============================================*/ /* GCM/GMAC (or CCM when applicable) init phase */ /*==============================================*/ - /* In case of init phase, the input data (Key and Initialization Vector) have + /* In case of init phase, the input data (Key and Initialization Vector) have already been entered during the initialization process. Therefore, the API just waits for the CCF flag to be set. */ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { /* just wait for hash computation */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Mark that the initialization phase is over */ @@ -535,54 +528,56 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* GCM/GMAC or (CCM / CMAC when applicable) header phase */ /*=======================================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) - { -#if !defined(AES_CR_NPBLB) + { +#if !defined(AES_CR_NPBLB) /* Set header phase; for GCM or GMAC, set data-byte at this point */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); } - + /* Enable the Peripheral */ __HAL_CRYP_ENABLE(hcryp); - -#if !defined(AES_CR_NPBLB) + +#if !defined(AES_CR_NPBLB) /* in case of CMAC, enter B0 block in header phase, before the header itself. */ /* If Size = 0 (possible case of resumption after CMAC header phase suspension), skip these steps and go directly to header buffer feeding to the HW */ - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0)) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0U)) { - inputaddr = (uint32_t)pInputData; - - for( ; (index < Size); index += 16) + uint64_t index_test; + inputaddr = (uint32_t)pInputData; + + for(index=0U ; (index < Size); index += 16U) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + inputaddr+=4U; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size)) + to end, suspend processing */ + index_test = (uint64_t)index + 16U; + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && (index_test < Size)) { /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -590,55 +585,57 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - /* Save the total number of bytes (B blocks + header) that remain to be + /* Save the total number of bytes (B blocks + header) that remain to be processed at this point */ - hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16); - + hcryp->CrypInCount = (uint32_t) (hcryp->Init.HeaderSize + Size - index_test); + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } - } /* for(index=0; (index < Size); index += 16) */ + } + } /* for(index=0; (index < Size); index += 16) */ } -#endif /* !defined(AES_CR_NPBLB) */ - - /* Enter header */ - inputaddr = (uint32_t)hcryp->Init.Header; +#endif /* !defined(AES_CR_NPBLB) */ + + /* Enter header */ + inputaddr = (uint32_t)hcryp->Init.Header; /* Local variable headerlength is a number of bytes multiple of 128 bits, remaining header data (if any) are handled after this loop */ - headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; - if ((hcryp->Init.HeaderSize % 16) != 0) + headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ; + if ((hcryp->Init.HeaderSize % 16U) != 0U) { - difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength); + difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength); } - for(index=0; index < headerlength; index += 16) + for(index=0U ; index < headerlength; index += 16U) { + uint64_t index_temp; /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + inputaddr+=4U; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength)) + to end, suspend processing */ + index_temp = (uint64_t)index + 16U; + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && (index_temp < headerlength)) { /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -646,26 +643,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the total number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16); - + hcryp->CrypInCount = (uint32_t) (hcryp->Init.HeaderSize - index_temp); + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } + } } - + /* Case header length is not a multiple of 16 bytes */ - if (difflength != 0) + if (difflength != 0U) { hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); - } - + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } + /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; } @@ -674,161 +671,163 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /*============================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); - + /* if the header phase has been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - + /* Enter payload */ /* Specific handling to manage payload last block size less than 128 bits */ - if ((Size % 16) != 0) + if ((Size % 16U) != 0U) { - payloadlength = (Size/16) * 16; + payloadlength = (Size/16U) * 16U; difflength = (uint32_t) (Size - payloadlength); addhoc_process = 1; } else { - payloadlength = Size; + payloadlength = Size; } - - /* Feed payload */ - for( ; index < payloadlength; index += 16) + + /* Feed payload */ + for(index=0U ; index < payloadlength; index += 16U) { + uint64_t index_temp; /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + inputaddr+=4U; + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Retrieve output data: read the output block + + /* Retrieve output data: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; - + outputaddr+=4U; + /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength)) + to end, suspend processing */ + index_temp = (uint64_t)index + 16U; + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && (index_temp < payloadlength)) { /* no flag waiting under IRQ handling */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { /* Ensure that Busy flag is reset */ - if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - } + } /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = Size - (index+16); - + hcryp->CrypInCount = (uint32_t) (Size - index_temp); + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } - + } + } - - /* Additional processing to manage GCM(/CCM) encryption and decryption cases when + + /* Additional processing to manage GCM(/CCM) encryption and decryption cases when payload last block size less than 128 bits */ - if (addhoc_process == 1) + if (addhoc_process == 1U) { - + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; - CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); - + hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } /* (addhoc_process == 1) */ - + /* Mark that the payload phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ - else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) - { + else + { tagaddr = (uint32_t)pOutputData; - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* By default, clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif - +#endif + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* if the header and payload phases have been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* input length in bits */ - -#if !defined(AES_CR_NPBLB) + headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */ + inputlength = Size * 8U; /* input length in bits */ + +#if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DINR = __RBIT((headerlength)>>32); - hcryp->Instance->DINR = __RBIT(headerlength); - hcryp->Instance->DINR = __RBIT((inputlength)>>32); - hcryp->Instance->DINR = __RBIT(inputlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)headerlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DINR = __REV((headerlength)>>32); - hcryp->Instance->DINR = __REV(headerlength); - hcryp->Instance->DINR = __REV((inputlength)>>32); - hcryp->Instance->DINR = __REV(inputlength); - } + hcryp->Instance->DINR = __REV((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)headerlength); + hcryp->Instance->DINR = __REV((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)inputlength); + } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); - hcryp->Instance->DINR = __ROR(headerlength, 16); - hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(headerlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(inputlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -837,46 +836,56 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } -#else + else + { + /* Unspecified Data Type */ + return HAL_ERROR; + } +#else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); -#endif +#endif } -#if !defined(AES_CR_NPBLB) - else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) +#if !defined(AES_CR_NPBLB) + else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { inputaddr = (uint32_t)pInputData; /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } -#endif - - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + else + { + /* Unspecified Chaining Mode */ + return HAL_ERROR; + } +#endif + + + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Read the Auth TAG in the Data Out register */ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - + tagaddr+=4U; + *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -885,22 +894,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /* Disable the Peripheral */ __HAL_CRYP_DISABLE(hcryp); } - /*=================================================*/ - /* case incorrect hcryp->Init.GCMCMACPhase setting */ - /*=================================================*/ - else - { - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else @@ -913,76 +913,82 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /** - * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering - * operation according to hcryp->Init structure fields. + * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: - * - pointer to payload data in GCM or CCM payload phase, + * @param pInputData: + * - pointer to payload data in GCM or CCM payload phase, * - pointer to B0 block in CMAC header phase, - * - pointer to C block in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. - * @param Size: + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. + * @param Size: * - length of the input payload data buffer in bytes in GCM or CCM payload phase, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CCM final phase. - * - Parameter is message length in bytes in case of GCM final phase. - * - Parameter must be set to zero in case of GMAC final phase. - * @param pOutputData: - * - pointer to plain or cipher text in GCM/CCM payload phase, + * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. + * - Parameter is meaningless in case of CCM final phase. + * - Parameter is message length in bytes in case of GCM final phase. + * - Parameter must be set to zero in case of GMAC final phase. + * @param pOutputData: + * - pointer to plain or cipher text in GCM/CCM payload phase, * - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CMAC header phase. + * - Parameter is meaningless in case of CMAC header phase. * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC. - * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes - * can be skipped by the user if so required. + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * can be skipped by the user if so required. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - uint64_t headerlength = 0; - uint64_t inputlength = 0; - uint32_t index = 0; - uint32_t addhoc_process = 0; + uint32_t inputaddr ; + uint64_t headerlength ; + uint64_t inputlength ; + uint32_t index ; + uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ - {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ - uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; - + uint32_t mask[4][3]; + + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + + mask[0][0] = 0xFF000000U; mask[0][1] = 0xFFFF0000U; mask[0][2] = 0xFFFFFF00U; /* 32-bit data */ + mask[1][0] = 0x0000FF00U; mask[1][1] = 0x0000FFFFU; mask[1][2] = 0xFF00FFFFU; /* 16-bit data */ + mask[2][0] = 0x000000FFU; mask[2][1] = 0x0000FFFFU; mask[2][2] = 0x00FFFFFFU; /* 8-bit data */ + mask[3][0] = 0x000000FFU; mask[3][1] = 0x0000FFFFU; mask[3][2] = 0x00FFFFFFU; /* Bit data */ if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ - if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { - if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) || - ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0))) + /* No processing required */ + } + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + if (((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U)) || + ((hcryp->Init.Header == NULL) && (hcryp->Init.HeaderSize != 0U))) { return HAL_ERROR; } -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif +#endif { /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ - if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U))) { return HAL_ERROR; } - } + } } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) - { - if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)) + { + if ((pInputData != NULL) && (Size != 0U) && (pOutputData == NULL)) { return HAL_ERROR; } @@ -993,24 +999,29 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn { return HAL_ERROR; } -#if !defined(AES_CR_NPBLB) - if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) +#if !defined(AES_CR_NPBLB) + if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) { return HAL_ERROR; } #endif } - - + else + { + /* Unspecified Phase */ + return HAL_ERROR; + } + + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Enable Computation Complete Flag and Error Interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); @@ -1020,95 +1031,95 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* GCM/GMAC (or CCM when applicable) init phase */ /*==============================================*/ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) - { - /* In case of init phase, the input data (Key and Initialization Vector) have + { + /* In case of init phase, the input data (Key and Initialization Vector) have already been entered during the initialization process. Therefore, the software just waits for the CCF interrupt to be raised and which will be handled by CRYP_AES_Auth_IT() API. */ } /*===================================*/ /* GCM/GMAC/CCM or CMAC header phase */ - /*===================================*/ + /*===================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif +#endif { /* In case of CMAC, B blocks are first entered, before the header. Therefore, B blocks and the header are entered back-to-back - as if it was only one single block. + as if it was only one single block. However, in case of resumption after suspension, if all the B blocks have been entered (in that case, Size = 0), only the remainder of the non-processed header bytes are entered. */ - if (Size != 0) + if (Size != 0U) { - hcryp->CrypInCount = Size + hcryp->Init.HeaderSize; + hcryp->CrypInCount = (uint32_t)(Size + hcryp->Init.HeaderSize); hcryp->pCrypInBuffPtr = pInputData; } else { - hcryp->CrypInCount = hcryp->Init.HeaderSize; + hcryp->CrypInCount = (uint32_t)hcryp->Init.HeaderSize; hcryp->pCrypInBuffPtr = hcryp->Init.Header; } } else { /* Get the header addresses and sizes */ - hcryp->CrypInCount = hcryp->Init.HeaderSize; + hcryp->CrypInCount = (uint32_t)hcryp->Init.HeaderSize; hcryp->pCrypInBuffPtr = hcryp->Init.Header; - } - + } + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) /* Set header phase; for GCM or GMAC, set data-byte at this point */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); } - + /* Enable the Peripheral */ __HAL_CRYP_ENABLE(hcryp); - + /* Increment/decrement instance pointer/counter */ - if (hcryp->CrypInCount == 0) + if (hcryp->CrypInCount == 0U) { /* Case of no header */ - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; - return HAL_OK; + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + return HAL_OK; } - else if (hcryp->CrypInCount < 16) + else if (hcryp->CrypInCount < 16U) { hcryp->CrypInCount = 0; - addhoc_process = 1; + addhoc_process = 1; difflength = (uint32_t) (hcryp->Init.HeaderSize); - difflengthmod4 = difflength%4; + difflengthmod4 = difflength%4U; } else { hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; + hcryp->CrypInCount -= 16U; } - - -#if defined(AES_CR_NPBLB) + + +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif - { +#endif + { if (hcryp->CrypInCount == hcryp->Init.HeaderSize) { /* All B blocks will have been entered after the next @@ -1116,43 +1127,43 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn the next iteration */ hcryp->pCrypInBuffPtr = hcryp->Init.Header; } - } - + } + /* Enter header first block to initiate the process in the Data Input register */ - if (addhoc_process == 0) - { - /* Header has size equal or larger than 128 bits */ + if (addhoc_process == 0U) + { + /* Header has size equal or larger than 128 bits */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } else { - /* Header has size less than 128 bits */ + /* Header has size less than 128 bits */ /* Enter complete words when possible */ - for( ; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } - /* Enter incomplete word padded with zeroes if applicable + /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ - if (difflengthmod4 != 0) - { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + if (difflengthmod4 != 0U) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); + } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; - } - + } + } } /*============================================*/ @@ -1161,152 +1172,152 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { /* Get the buffer addresses and sizes */ - hcryp->CrypInCount = Size; + hcryp->CrypInCount = (uint32_t)Size; hcryp->pCrypInBuffPtr = pInputData; hcryp->pCrypOutBuffPtr = pOutputData; - hcryp->CrypOutCount = Size; - + hcryp->CrypOutCount = (uint32_t)Size; + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); - + /* if the header phase has been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + /* No payload case */ if (pInputData == NULL) { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; /* Process Unlocked */ __HAL_UNLOCK(hcryp); - - return HAL_OK; - } - + + return HAL_OK; + } + /* Specific handling to manage payload size less than 128 bits */ - if (Size < 16) + if (Size < 16U) { difflength = (uint32_t) (Size); -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) { - if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) - || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + uint32_t cr_temp = hcryp->Instance->CR; + + if (((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_ALGOMODE_ENCRYPT)) + || ((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_CCM|CRYP_ALGOMODE_DECRYPT))) { - /* Set NPBLB field in writing the number of padding bytes + /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16U - difflength) << AES_POSITION_CR_NPBLB); } } #else - /* Software workaround applied to GCM encryption only */ + /* Software workaround applied to GCM encryption only */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { - /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR); - } -#endif + } +#endif - /* Set hcryp->CrypInCount to 0 (no more data to enter) */ - hcryp->CrypInCount = 0; + /* Set hcryp->CrypInCount to 0 (no more data to enter) */ + hcryp->CrypInCount = 0; - /* Insert the last block (which size is inferior to 128 bits) padded with zeroes, - to have a complete block of 128 bits */ - difflengthmod4 = difflength%4; - /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes, to have a complete block of 128 bits */ - for(index=0; index < (difflength/4); index ++) + difflengthmod4 = difflength%4U; + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + to have a complete block of 128 bits */ + for(index=0U; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* If required, manage input data size not multiple of 32 bits */ - if (difflengthmod4 != 0) - { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + if (difflengthmod4 != 0U) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); + } /* Wrap-up in padding with zero-words if applicable */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; - } + } } else - { + { /* Increment/decrement instance pointer/counter */ hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - + hcryp->CrypInCount -= 16U; + /* Enter payload first block to initiate the process in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ - else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + else { hcryp->pCrypOutBuffPtr = pOutputData; - -#if defined(AES_CR_NPBLB) + +#if defined(AES_CR_NPBLB) /* By default, clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif - +#endif + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* if the header and payload phases have been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) - { - headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* Input length in bits */ + { + headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */ + inputlength = Size * 8U; /* Input length in bits */ /* Write the number of bits in the header on 64 bits followed by the number of bits in the payload on 64 bits as well */ - -#if !defined(AES_CR_NPBLB) + +#if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DINR = __RBIT((headerlength)>>32); - hcryp->Instance->DINR = __RBIT(headerlength); - hcryp->Instance->DINR = __RBIT((inputlength)>>32); - hcryp->Instance->DINR = __RBIT(inputlength); + hcryp->Instance->DINR = __RBIT((uint32_t)((headerlength)>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)headerlength); + hcryp->Instance->DINR = __RBIT((uint32_t)((inputlength)>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DINR = __REV((headerlength)>>32); - hcryp->Instance->DINR = __REV(headerlength); - hcryp->Instance->DINR = __REV((inputlength)>>32); - hcryp->Instance->DINR = __REV(inputlength); + hcryp->Instance->DINR = __REV((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)headerlength); + hcryp->Instance->DINR = __REV((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); - hcryp->Instance->DINR = __ROR(headerlength, 16); - hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)((headerlength)>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)((inputlength)>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -1315,38 +1326,40 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } + else + { + /* Unspecified Data Type */ + return HAL_ERROR; + } #else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); -#endif +#endif } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { inputaddr = (uint32_t)pInputData; /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } -#endif + else + { + /* Unspecified Chaining Mode */ + return HAL_ERROR; + } +#endif } - /*=================================================*/ - /* case incorrect hcryp->Init.GCMCMACPhase setting */ - /*=================================================*/ - else - { - hcryp->State = HAL_CRYP_STATE_ERROR; - return HAL_ERROR; - } - + return HAL_OK; } else @@ -1359,75 +1372,79 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /** - * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering - * operation according to hcryp->Init structure fields. + * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering + * operation according to hcryp->Init structure fields. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: - * - pointer to payload data in GCM or CCM payload phase, + * @param pInputData: + * - pointer to payload data in GCM or CCM payload phase, * - pointer to B0 block in CMAC header phase, - * - pointer to C block in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. - * @param Size: + * - pointer to C block in CMAC final phase. + * - Parameter is meaningless in case of GCM/GMAC/CCM init, header and final phases. + * @param Size: * - length of the input payload data buffer in bytes in GCM or CCM payload phase, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. - * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CCM final phase. - * - Parameter is message length in bytes in case of GCM final phase. - * - Parameter must be set to zero in case of GMAC final phase. - * @param pOutputData: - * - pointer to plain or cipher text in GCM/CCM payload phase, + * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. + * - Parameter is meaningless in case of CCM final phase. + * - Parameter is message length in bytes in case of GCM final phase. + * - Parameter must be set to zero in case of GMAC final phase. + * @param pOutputData: + * - pointer to plain or cipher text in GCM/CCM payload phase, * - pointer to authentication tag in GCM/GMAC/CCM/CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC/CCM init and header phases. - * - Parameter is meaningless in case of CMAC header phase. + * - Parameter is meaningless in case of CMAC header phase. * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC. - * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes + * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes * can be skipped by the user if so required. - * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. + * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData) { - uint32_t inputaddr = 0; - uint32_t outputaddr = 0; - uint32_t tagaddr = 0; - uint64_t headerlength = 0; - uint64_t inputlength = 0; - uint64_t payloadlength = 0; - - + uint32_t inputaddr ; + uint32_t outputaddr ; + uint32_t tagaddr ; + uint64_t headerlength ; + uint64_t inputlength ; + uint64_t payloadlength ; + + if (hcryp->State == HAL_CRYP_STATE_READY) { /* input/output parameters check */ - if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { - if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0)) + /* No processing required */ + } + else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) + { + if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U)) { return HAL_ERROR; } -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) { /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ - if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) - { - return HAL_ERROR; - } - } -#else - if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) - { - if ((pInputData == NULL) || (Size == 0)) + if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U))) { return HAL_ERROR; } } -#endif +#else + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) + { + if ((pInputData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + } +#endif } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) - { - if ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)) + { + if ((pInputData != NULL) && (Size != 0U) && (pOutputData == NULL)) { return HAL_ERROR; } @@ -1438,38 +1455,43 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI { return HAL_ERROR; } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL)) { return HAL_ERROR; } #endif } - - + else + { + /* Unspecified Phase */ + return HAL_ERROR; + } + + /* Process Locked */ __HAL_LOCK(hcryp); - + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /*==============================================*/ /* GCM/GMAC (or CCM when applicable) init phase */ /*==============================================*/ - /* In case of init phase, the input data (Key and Initialization Vector) have + /* In case of init phase, the input data (Key and Initialization Vector) have already been entered during the initialization process. No DMA transfer is - required at that point therefore, the software just waits for the CCF flag + required at that point therefore, the software just waits for the CCF flag to be raised. */ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { /* just wait for hash computation */ - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Mark that the initialization phase is over */ @@ -1478,98 +1500,98 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } /*====================================*/ /* GCM/GMAC/ CCM or CMAC header phase */ - /*====================================*/ + /*====================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) - { -#if !defined(AES_CR_NPBLB) + { +#if !defined(AES_CR_NPBLB) /* Set header phase; for GCM or GMAC, set data-byte at this point */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType); } else -#endif +#endif { MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE); } - + /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - -#if !defined(AES_CR_NPBLB) + +#if !defined(AES_CR_NPBLB) /* enter first B0 block in polling mode (no DMA transfer for B0) */ if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { inputaddr = (uint32_t)pInputData; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } -#endif - +#endif + /* No header case */ if (hcryp->Init.Header == NULL) { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; /* Process Unlocked */ __HAL_UNLOCK(hcryp); - - return HAL_OK; + + return HAL_OK; } - + inputaddr = (uint32_t)hcryp->Init.Header; - if ((hcryp->Init.HeaderSize % 16) != 0) + if ((hcryp->Init.HeaderSize % 16U) != 0U) { - if (hcryp->Init.HeaderSize < 16) - { - hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; - CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF); - - hcryp->State = HAL_CRYP_STATE_READY; + if (hcryp->Init.HeaderSize < 16U) + { + hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; + CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF); + + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; - - /* CCF flag indicating header phase AES processing completion + hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; + + /* CCF flag indicating header phase AES processing completion will be checked at the start of the next phase: - payload phase (GCM / CCM when applicable) - - final phase (GMAC or CMAC when applicable). */ + - final phase (GMAC or CMAC when applicable). */ } else { /* Local variable headerlength is a number of bytes multiple of 128 bits, remaining header data (if any) are handled after this loop */ - headerlength = (((hcryp->Init.HeaderSize)/16)*16) ; + headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ; /* Store the ending transfer point */ hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength; hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */ - - /* Set the input and output addresses and start DMA transfer */ + + /* Set the input and output addresses and start DMA transfer */ /* (incomplete DMA transfer, will be wrapped up after completion of the first one (initiated here) with data padding */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, headerlength, 0); - } + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)headerlength, 0); + } } else { hcryp->CrypInCount = 0; - /* Set the input address and start DMA transfer */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0); + /* Set the input address and start DMA transfer */ + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)hcryp->Init.HeaderSize, 0); } } /*============================================*/ @@ -1577,16 +1599,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /*============================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - /* Coming from header phase, wait for CCF flag to be raised + /* Coming from header phase, wait for CCF flag to be raised if header present and fed to the IP in the previous phase */ if (hcryp->Init.Header != NULL) - { - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; - } + } } else { @@ -1594,129 +1616,135 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI __HAL_CRYP_ENABLE(hcryp); } /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE); - + /* No payload case */ if (pInputData == NULL) { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; /* Process Unlocked */ __HAL_UNLOCK(hcryp); - - return HAL_OK; + + return HAL_OK; } - - - /* Specific handling to manage payload size less than 128 bits */ - if ((Size % 16) != 0) + + + /* Specific handling to manage payload size less than 128 bits */ + if ((Size % 16U) != 0U) { inputaddr = (uint32_t)pInputData; - outputaddr = (uint32_t)pOutputData; - if (Size < 16) + outputaddr = (uint32_t)pOutputData; + if (Size < 16U) { /* Block is now entered in polling mode, no actual gain in resorting to DMA */ hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; - - CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); - + + CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->OutCpltCallback(hcryp); +#else HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - payloadlength = (Size/16) * 16; - + payloadlength = (Size/16U) * 16U; + /* Store the ending transfer points */ - hcryp->pCrypInBuffPtr = pInputData + payloadlength; - hcryp->pCrypOutBuffPtr = pOutputData + payloadlength; + hcryp->pCrypInBuffPtr = pInputData; + hcryp->pCrypInBuffPtr += payloadlength; + hcryp->pCrypOutBuffPtr = pOutputData; + hcryp->pCrypOutBuffPtr += payloadlength; hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */ - - /* Set the input and output addresses and start DMA transfer */ - /* (incomplete DMA transfer, will be wrapped up with data padding + + /* Set the input and output addresses and start DMA transfer */ + /* (incomplete DMA transfer, will be wrapped up with data padding after completion of the one initiated here) */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr); + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)payloadlength, outputaddr); } } else - { - hcryp->CrypInCount = 0; + { + hcryp->CrypInCount = 0; inputaddr = (uint32_t)pInputData; outputaddr = (uint32_t)pOutputData; - - /* Set the input and output addresses and start DMA transfer */ - CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - } + + /* Set the input and output addresses and start DMA transfer */ + CRYP_Authentication_SetDMAConfig(hcryp, inputaddr, (uint16_t)Size, outputaddr); + } } /*==================================*/ /* GCM/GMAC/CCM or CMAC final phase */ /*==================================*/ - else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) + else { - /* If coming from header phase (GMAC or CMAC case when applicable), + /* If coming from header phase (GMAC or CMAC case when applicable), wait for CCF flag to be raised */ if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE) - { - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + { + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - + } + tagaddr = (uint32_t)pOutputData; -#if defined(AES_CR_NPBLB) +#if defined(AES_CR_NPBLB) /* By default, clear NPBLB field */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB); -#endif +#endif MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* if the header and payload phases have been bypassed, AES must be enabled again */ if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER) { - __HAL_CRYP_ENABLE(hcryp); + __HAL_CRYP_ENABLE(hcryp); } - + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) { - headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */ - inputlength = Size * 8; /* input length in bits */ + headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */ + inputlength = Size * 8U; /* input length in bits */ /* Write the number of bits in the header on 64 bits followed by the number of bits in the payload on 64 bits as well */ -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) if(hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DINR = __RBIT((headerlength)>>32); - hcryp->Instance->DINR = __RBIT(headerlength); - hcryp->Instance->DINR = __RBIT((inputlength)>>32); - hcryp->Instance->DINR = __RBIT(inputlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)headerlength); + hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __RBIT((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DINR = __REV((headerlength)>>32); - hcryp->Instance->DINR = __REV(headerlength); - hcryp->Instance->DINR = __REV((inputlength)>>32); - hcryp->Instance->DINR = __REV(inputlength); + hcryp->Instance->DINR = __REV((uint32_t)(headerlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)headerlength); + hcryp->Instance->DINR = __REV((uint32_t)(inputlength>>32)); + hcryp->Instance->DINR = __REV((uint32_t)inputlength); } else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DINR = __ROR((headerlength)>>32, 16); - hcryp->Instance->DINR = __ROR(headerlength, 16); - hcryp->Instance->DINR = __ROR((inputlength)>>32, 16); - hcryp->Instance->DINR = __ROR(inputlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(headerlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16); + hcryp->Instance->DINR = __ROR((uint32_t)(inputlength>>32), 16); + hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16); } else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) { @@ -1725,52 +1753,62 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); } + else + { + /* Unspecified Data Type */ + return HAL_ERROR; + } #else hcryp->Instance->DINR = (uint32_t)(headerlength>>32); hcryp->Instance->DINR = (uint32_t)(headerlength); hcryp->Instance->DINR = (uint32_t)(inputlength>>32); hcryp->Instance->DINR = (uint32_t)(inputlength); -#endif +#endif } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + inputaddr = (uint32_t)pInputData; /* Enter the last block made of a 128-bit value formatted from the original B0 packet. */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } -#endif - - /* No DMA transfer is required at that point therefore, the software + else + { + /* Unspecified Chaining Mode */ + return HAL_ERROR; + } +#endif + + /* No DMA transfer is required at that point therefore, the software just waits for the CCF flag to be raised. */ - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Read the Auth TAG in the IN FIFO */ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4; + tagaddr+=4U; *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - + /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Mark that the final phase is over */ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; hcryp->State = HAL_CRYP_STATE_READY; @@ -1778,19 +1816,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI __HAL_CRYP_DISABLE(hcryp); } - /*=================================================*/ - /* case incorrect hcryp->Init.GCMCMACPhase setting */ - /*=================================================*/ - else - { - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; } else @@ -1803,18 +1832,18 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI * @} */ -/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions - * @brief Extended processing functions. +/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions + * @brief Extended processing functions. * -@verbatim +@verbatim ============================================================================== ##### AES extended suspension and resumption functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) save in memory the Initialization Vector, the Key registers, the Control register or the Suspend registers when a process is suspended by a higher priority message (+) write back in CRYP hardware block the saved values listed above when the suspended - lower priority message processing is resumed. + lower priority message processing is resumed. @endverbatim * @{ @@ -1822,26 +1851,26 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /** - * @brief In case of message processing suspension, read the Initialization Vector. + * @brief In case of message processing suspension, read the Initialization Vector. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Output: Pointer to the buffer containing the saved Initialization Vector. * @note This value has to be stored for reuse by writing the AES_IVRx registers * as soon as the interrupted processing has to be resumed. - * Applicable to all chaining modes. - * @note AES must be disabled when reading or resetting the IV values. + * Applicable to all chaining modes. + * @note AES must be disabled when reading or resetting the IV values. * @retval None */ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { uint32_t outputaddr = (uint32_t)Output; - + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0); } @@ -1849,204 +1878,208 @@ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) * @brief In case of message processing resumption, rewrite the Initialization * Vector in the AES_IVRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved Initialization Vector to - * write back in the CRYP hardware block. - * @note Applicable to all chaining modes. - * @note AES must be disabled when reading or resetting the IV values. + * write back in the CRYP hardware block. + * @note Applicable to all chaining modes. + * @note AES must be disabled when reading or resetting the IV values. * @retval None */ void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) { uint32_t ivaddr = (uint32_t)Input; - + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } /** - * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, + * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, * read the Suspend Registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Output: Pointer to the buffer containing the saved Suspend Registers. * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers - * as soon as the interrupted processing has to be resumed. + * as soon as the interrupted processing has to be resumed. * @retval None */ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { uint32_t outputaddr = (uint32_t)Output; - + /* In case of GCM payload phase encryption, check that suspension can be carried out */ - if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT)) + if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT)) { /* Ensure that Busy flag is reset */ - if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) - { + if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK) + { hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR; hcryp->State = HAL_CRYP_STATE_ERROR; - + /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - + __HAL_UNLOCK(hcryp); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ return ; } - } - + } + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); - outputaddr+=4; - *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R); + outputaddr+=4U; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); + outputaddr+=4U; + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Suspend * Registers in the AES_SUSPxR registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved suspend registers to - * write back in the CRYP hardware block. + * write back in the CRYP hardware block. * @retval None */ void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) { uint32_t ivaddr = (uint32_t)Input; - + hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; + ivaddr+=4U; hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr)); - ivaddr+=4; - hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr)); + ivaddr+=4U; + hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr)); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, read the Key Registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Key Registers. + * the configuration information for CRYP module. + * @param Output: Pointer to the buffer containing the saved Key Registers. * @param KeySize: Indicates the key size (128 or 256 bits). * @note These values have to be stored for reuse by writing back the AES_KEYRx registers - * as soon as the interrupted processing has to be resumed. + * as soon as the interrupted processing has to be resumed. * @retval None */ void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize) { uint32_t keyaddr = (uint32_t)Output; - + if (KeySize == CRYP_KEYSIZE_256B) { *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4); - keyaddr+=4; - } - + keyaddr+=4U; + } + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2); - keyaddr+=4; + keyaddr+=4U; *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1); - keyaddr+=4; - *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); + keyaddr+=4U; + *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key * Registers in the AES_KEYRx registers. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved key registers to - * write back in the CRYP hardware block. - * @param KeySize: Indicates the key size (128 or 256 bits) + * write back in the CRYP hardware block. + * @param KeySize: Indicates the key size (128 or 256 bits) * @retval None */ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) -{ +{ uint32_t keyaddr = (uint32_t)Input; - + if (KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - } - + keyaddr+=4U; + } + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4U; + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing suspension, read the Control Register. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Output: Pointer to the buffer containing the saved Control Register. * @note This values has to be stored for reuse by writing back the AES_CR register - * as soon as the interrupted processing has to be resumed. + * as soon as the interrupted processing has to be resumed. * @retval None */ void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) { - *(uint32_t*)(Output) = hcryp->Instance->CR; + *(uint32_t*)(void *)(Output) = hcryp->Instance->CR; /* Derogation MisraC2012 R.11.5 */ } /** * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Control * Registers in the AES_CR register. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Input: Pointer to the buffer containing the saved Control Register to - * write back in the CRYP hardware block. + * write back in the CRYP hardware block. * @retval None */ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) -{ - hcryp->Instance->CR = *(uint32_t*)(Input); - /* At the same time, set handle state back to READY to be able to resume the AES calculations +{ + hcryp->Instance->CR = *(uint32_t*)(void *)(Input); /* Derogation MisraC2012 R.11.5 */ + /* At the same time, set handle state back to READY to be able to resume the AES calculations without the processing APIs returning HAL_BUSY when called. */ hcryp->State = HAL_CRYP_STATE_READY; } @@ -2054,15 +2087,15 @@ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** * @brief Request CRYP processing suspension when in polling or interruption mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @note Set the handle field SuspendRequest to the appropriate value so that - * the on-going CRYP processing is suspended as soon as the required + * the configuration information for CRYP module. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going CRYP processing is suspended as soon as the required * conditions are met. - * @note It is advised not to suspend the CRYP processing when the DMA controller - * is managing the data transfer + * @note It is advised not to suspend the CRYP processing when the DMA controller + * is managing the data transfer * @retval None */ -void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) +void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) { /* Set Handle Suspend Request field */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND; @@ -2086,79 +2119,86 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) * @note Specific setting of hcryp fields are required only * in the case of header phase where no output data DMA * transfer is on-going (only input data transfer is enabled - * in such a case). + * in such a case). * @param hdma: DMA handle. * @retval None */ -static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) +static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma) { - uint32_t difflength = 0; - - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + uint32_t difflength; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ + /* Disable the DMA transfer for input request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) - { - - if (hcryp->CrypInCount != 0) + { + + if (hcryp->CrypInCount != 0U) { /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; - - CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF); + + CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF); } - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; } - /* CCF flag indicating header phase AES processing completion + /* CCF flag indicating header phase AES processing completion will be checked at the start of the next phase: - payload phase (GCM or CCM when applicable) - final phase (GMAC or CMAC). This allows to avoid the Wait on Flag within the IRQ handling. */ - + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->InCpltCallback(hcryp); +#else HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** * @brief DMA CRYP Output Data process complete callback * for GCM, GMAC, CCM or CMAC chaining modes. - * @note This callback is called only in the payload phase. + * @note This callback is called only in the payload phase. * @param hdma: DMA handle. * @retval None */ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) { - uint32_t difflength = 0; - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + uint32_t difflength; + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ + /* Disable the DMA transfer for output request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Initiate additional transfer to wrap-up data feeding to the IP */ - if (hcryp->CrypInCount != 0) + if (hcryp->CrypInCount != 0U) { /* Last block is now entered in polling mode, no actual gain in resorting to DMA */ difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; - - CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); - } - + + CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); + } + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->OutCpltCallback(hcryp); +#else HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** @@ -2169,46 +2209,52 @@ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ + hcryp->State= HAL_CRYP_STATE_ERROR; hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Clear Error Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); } -/** +/** * @brief Handle CRYP block input/output data handling under interruption - * for GCM, GMAC, CCM or CMAC chaining modes. + * for GCM, GMAC, CCM or CMAC chaining modes. * @note The function is called under interruption only, once - * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). + * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t inputaddr = 0x0; - uint32_t outputaddr = 0x0; - uint32_t index = 0x0; - uint32_t addhoc_process = 0; + uint32_t inputaddr ; + uint32_t outputaddr ; + uint32_t index ; + uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ - {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ - uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; - uint32_t intermediate_data[4] = {0}; - + uint32_t mask[4][3] ; + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + uint32_t intermediate_data[4] = {0}; + + mask[0][0] = 0xFF000000U; mask[0][1] = 0xFFFF0000U; mask[0][2] = 0xFFFFFF00U; /* 32-bit data */ + mask[1][0] = 0x0000FF00U; mask[1][1] = 0x0000FFFFU; mask[1][2] = 0xFF00FFFFU; /* 16-bit data */ + mask[2][0] = 0x000000FFU; mask[2][1] = 0x0000FFFFU; mask[2][2] = 0x00FFFFFFU; /* 8-bit data */ + mask[3][0] = 0x000000FFU; mask[3][1] = 0x0000FFFFU; mask[3][2] = 0x00FFFFFFU; /* Bit data */ + if(hcryp->State == HAL_CRYP_STATE_BUSY) { /*===========================*/ /* GCM/GMAC(/CCM) init phase */ - /*===========================*/ + /*===========================*/ if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE) { /* Clear Computation Complete Flag */ @@ -2217,23 +2263,27 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Mark that the initialization phase is over */ hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ return HAL_OK; } /*========================================*/ /* GCM/GMAC (or CCM or CMAC) header phase */ - /*========================================*/ + /*========================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE) { /* Check if all input header data have been entered */ - if (hcryp->CrypInCount == 0) + if (hcryp->CrypInCount == 0U) { /* Clear Computation Complete Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2243,13 +2293,17 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } /* If suspension flag has been raised, suspend processing */ @@ -2257,7 +2311,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) { /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ @@ -2266,39 +2320,39 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the header phase is suspended */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } + } else /* Carry on feeding input data to the CRYP hardware block */ { /* Clear Computation Complete Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Get the last Input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + /* Increment/decrement instance pointer/counter */ - if (hcryp->CrypInCount < 16) + if (hcryp->CrypInCount < 16U) { - difflength = hcryp->CrypInCount; + difflength = hcryp->CrypInCount; hcryp->CrypInCount = 0; - addhoc_process = 1; - difflengthmod4 = difflength%4; + addhoc_process = 1; + difflengthmod4 = difflength%4U; } else { hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - -#if defined(AES_CR_NPBLB) + hcryp->CrypInCount -= 16U; + } + +#if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) -#else +#else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif - { +#endif + { if (hcryp->CrypInCount == hcryp->Init.HeaderSize) { /* All B blocks will have been entered after the next @@ -2306,193 +2360,200 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) the next iteration */ hcryp->pCrypInBuffPtr = hcryp->Init.Header; } - } - + } + /* Write the Input block in the Data Input register */ - if (addhoc_process == 0) - { + if (addhoc_process == 0U) + { hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); } else { - /* Header remainder has size less than 128 bits */ + /* Header remainder has size less than 128 bits */ /* Enter complete words when possible */ - for( ; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } - /* Enter incomplete word padded with zeroes if applicable + /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ - if (difflengthmod4 != 0) - { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + if (difflengthmod4 != 0U) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); + } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; - } + } } - - return HAL_OK; + + return HAL_OK; } } /*=======================*/ /* GCM/CCM payload phase */ - /*=======================*/ + /*=======================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { /* Get the last output data address */ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - + /* Specific handling to manage payload size less than 128 bits when GCM (or CCM when applicable) encryption or decryption is selected. Check here if the last block output data are read */ -#if defined(AES_CR_NPBLB) - if ((hcryp->CrypOutCount < 16) && \ - (hcryp->CrypOutCount > 0)) -#else +#if defined(AES_CR_NPBLB) + if ((hcryp->CrypOutCount < 16U) && \ + (hcryp->CrypOutCount > 0U)) +#else if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \ - (hcryp->CrypOutCount < 16) && \ - (hcryp->CrypOutCount > 0)) -#endif + (hcryp->CrypOutCount < 16U) && \ + (hcryp->CrypOutCount > 0U)) +#endif { - addhoc_process = 1; difflength = hcryp->CrypOutCount; - difflengthmod4 = difflength%4; - hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */ + difflengthmod4 = difflength%4U; + hcryp->CrypOutCount = 0; /* mark that no more output data will be needed */ /* Retrieve intermediate data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } /* Retrieve last words of cyphered data */ /* First, retrieve complete output words */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { *(uint32_t*)(outputaddr) = intermediate_data[index]; - outputaddr+=4; - } + outputaddr+=4U; + } /* Next, retrieve partial output word if applicable; - at the same time, start masking intermediate data + at the same time, start masking intermediate data with a mask of zeros of same size than the padding - applied to the last block of payload */ - if (difflengthmod4 != 0) + applied to the last block of payload */ + if (difflengthmod4 != 0U) { - intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; - *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; - } - -#if !defined(AES_CR_NPBLB) + intermediate_data[difflength/4U] &= mask[mask_index][difflengthmod4-1U]; + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U]; + } + +#if !defined(AES_CR_NPBLB) if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) - { + { /* Change again CHMOD configuration to GCM mode */ - __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); - + __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); + /* Select FINAL phase */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); + /* Before inserting the intermediate data, carry on masking operation with a mask of zeros of same size than the padding applied to the last block of payload */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { - intermediate_data[(difflength+3)/4+index] = 0; - } - + intermediate_data[((difflength+3U)/4U)+index] = 0; + } + /* Insert intermediate data to trigger an additional DOUTR reading round */ /* Clear Computation Complete Flag before entering new block */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { - hcryp->Instance->DINR = intermediate_data[index]; + hcryp->Instance->DINR = intermediate_data[index]; } } else -#endif +#endif { /* Payload phase is now over */ /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } return HAL_OK; } - else - { - if (hcryp->CrypOutCount != 0) - { - /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ + else + { + if (hcryp->CrypOutCount != 0U) + { + /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ /* Retrieve the last block available from the CRYP hardware block: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - + /* Increment/decrement instance pointer/counter */ hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; + hcryp->CrypOutCount -= 16U; } -#if !defined(AES_CR_NPBLB) +#if !defined(AES_CR_NPBLB) else - { + { /* Software work-around: additional DOUTR reading round to discard the data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } } -#endif - } - +#endif + } + /* Check if all output text has been retrieved */ - if (hcryp->CrypOutCount == 0) + if (hcryp->CrypOutCount == 0U) { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the payload phase is over */ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } /* If suspension flag has been raised, suspend processing */ else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) - { + { /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; /* Disable Computation Complete Flag and Errors Interrupts */ @@ -2501,151 +2562,157 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_SUSPENDED; /* Mark that the payload phase is suspended */ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_SUSPENDED; - + /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + return HAL_OK; - } + } else /* Output data are still expected, carry on feeding the CRYP hardware block with input data */ { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Get the last Input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - + /* Usual input data feeding case */ - if (hcryp->CrypInCount < 16) + if (hcryp->CrypInCount < 16U) { difflength = (uint32_t) (hcryp->CrypInCount); - difflengthmod4 = difflength%4; - hcryp->CrypInCount = 0; - -#if defined(AES_CR_NPBLB) + difflengthmod4 = difflength%4U; + hcryp->CrypInCount = 0; + +#if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ - if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) - || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) - { - /* Set NPBLB field in writing the number of padding bytes - for the last block of payload */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); - } -#else - /* Software workaround applied to GCM encryption only */ + { + uint32_t cr_temp = hcryp->Instance->CR; + + if (((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_ALGOMODE_ENCRYPT)) + || ((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_CCM|CRYP_ALGOMODE_DECRYPT))) + { + /* Set NPBLB field in writing the number of padding bytes + for the last block of payload */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16U - difflength) << AES_POSITION_CR_NPBLB); + } + } +#else + /* Software workaround applied to GCM encryption only */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { - /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR); - } -#endif - - /* Insert the last block (which size is inferior to 128 bits) padded with zeroes + } +#endif + + /* Insert the last block (which size is inferior to 128 bits) padded with zeroes to have a complete block of 128 bits */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } /* If required, manage input data size not multiple of 32 bits */ - if (difflengthmod4 != 0) - { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + if (difflengthmod4 != 0U) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); + } /* Wrap-up in padding with zero-words if applicable */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; - } - + } + } else { hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - } - - - return HAL_OK; + inputaddr+=4U; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + } + + + return HAL_OK; } } /*=======================================*/ /* GCM/GMAC (or CCM or CMAC) final phase */ - /*=======================================*/ + /*=======================================*/ else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE) { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Get the last output data address */ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - + /* Retrieve the last expected data from the CRYP hardware block: read the output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - + /* Disable Computation Complete Flag and Errors Interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; /* Mark that the header phase is over */ hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER; - + /* Disable the Peripheral */ __HAL_CRYP_DISABLE(hcryp); /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Call computation complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->CompCpltCallback(hcryp); +#else HAL_CRYPEx_ComputationCpltCallback(hcryp); - +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + return HAL_OK; } else { /* Clear Computation Complete Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - hcryp->State = HAL_CRYP_STATE_ERROR; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + hcryp->State = HAL_CRYP_STATE_ERROR; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } - - - -/** + + + +/** * @brief Set the DMA configuration and start the DMA transfer - * for GCM, GMAC, CCM or CMAC chaining modes. + * for GCM, GMAC, CCM or CMAC chaining modes. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param inputaddr: Address of the Input buffer. * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream - * has to be configured. + * has to be configured. * @retval None */ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -2655,34 +2722,48 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->hdmain->XferCpltCallback = CRYP_Authentication_DMAInCplt; /* Set the DMA error callback */ hcryp->hdmain->XferErrorCallback = CRYP_Authentication_DMAError; - - if (outputaddr != 0) - { + + if (outputaddr != 0U) + { /* Set the output CRYP DMA transfer complete callback */ hcryp->hdmaout->XferCpltCallback = CRYP_Authentication_DMAOutCplt; /* Set the DMA error callback */ hcryp->hdmaout->XferErrorCallback = CRYP_Authentication_DMAError; } - + /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - + /* Enable the DMA input stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); - + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Enable the DMA input request */ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - - if (outputaddr != 0) - { + + if (outputaddr != 0U) + { /* Enable the DMA output stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); - + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Enable the DMA output request */ SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); } -} +} @@ -2693,69 +2774,69 @@ static void CRYP_Authentication_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t * @param Input: Pointer to the Input buffer. * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Timeout: Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) { - uint32_t index = 0; + uint32_t index; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; - - for(index=0; (index < Ilength); index += 16) + + for(index=0U ; (index < Ilength); index += 16U) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - + inputaddr+=4U; + /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } - + /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Read the Output block from the Data Output Register */ *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; - outputaddr+=4; - + outputaddr+=4U; + /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength)) + if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < Ilength)) { /* Reset SuspendRequest */ hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; - + /* Save current reading and writing locations of Input and Output buffers */ hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr; hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hcryp->CrypInCount = Ilength - (index+16); - + hcryp->CrypInCount = Ilength - (index+16U); + /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - + return HAL_OK; } - - + + } /* Return function status */ return HAL_OK; @@ -2772,45 +2853,45 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Timeout: Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) { uint32_t outputaddr = (uint32_t)Output; - - /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + + /* Wait for CCF flag to be raised */ + if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); return HAL_TIMEOUT; } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Read the derivative key from the AES_KEYRx registers */ if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B) - { + { *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4); - outputaddr+=4; + outputaddr+=4U; } - + *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1); - outputaddr+=4; + outputaddr+=4U; *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0); - + /* Return function status */ return HAL_OK; } @@ -2830,21 +2911,35 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; /* Set the DMA error callback */ hcryp->hdmain->XferErrorCallback = CRYP_DMAError; - + /* Set the CRYP DMA transfer complete callback */ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; /* Set the DMA error callback */ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; /* Enable the DMA input stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Enable the DMA output stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, ((uint32_t)Size)/4U) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Enable In and Out DMA requests */ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); - + /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } @@ -2853,57 +2948,57 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Timeout: Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart; + /* Get timeout */ tickstart = HAL_GetTick(); - + while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) - { + { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart ) > Timeout) - { + { return HAL_TIMEOUT; } } } - return HAL_OK; + return HAL_OK; } /** - * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. + * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param Timeout: Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef const * const hcryp, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart; + /* Get timeout */ tickstart = HAL_GetTick(); - + while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)) - { + { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart ) > Timeout) - { + { return HAL_TIMEOUT; } } } - return HAL_OK; + return HAL_OK; } @@ -2912,15 +3007,19 @@ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uin * @param hdma: DMA handle. * @retval None */ -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ + /* Disable the DMA transfer for input request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->InCpltCallback(hcryp); +#else HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** @@ -2929,117 +3028,131 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - +{ + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ + /* Disable the DMA transfer for output request */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - + /* Disable CRYP */ __HAL_CRYP_DISABLE(hcryp); - + /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; - + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->OutCpltCallback(hcryp); +#else HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /** - * @brief DMA CRYP communication error callback. + * @brief DMA CRYP communication error callback. * @param hdma: DMA handle. * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Derogation MisraC2012 R.11.5 */ + hcryp->State= HAL_CRYP_STATE_ERROR; - hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; + hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Clear Error Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); } /** - * @brief Last header or payload block padding when size is not a multiple of 128 bits. + * @brief Last header or payload block padding when size is not a multiple of 128 bits. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. + * the configuration information for CRYP module. * @param difflength: size remainder after having fed all complete 128-bit blocks. * @param polling: specifies whether or not polling on CCF must be done after having - * entered a complete block. + * entered a complete block. * @retval None */ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling) { - uint32_t index = 0; - uint32_t difflengthmod4 = difflength%4; - uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ - {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ - {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ - uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; - + uint32_t index; + uint32_t difflengthmod4 = difflength%4U; + uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + uint32_t mask[4][3]; + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + uint32_t intermediate_data[4] = {0}; - -#if defined(AES_CR_NPBLB) + + mask[0][0] = 0xFF000000U; mask[0][1] = 0xFFFF0000U; mask[0][2] = 0xFFFFFF00U; /* 32-bit data */ + mask[1][0] = 0x0000FF00U; mask[1][1] = 0x0000FFFFU; mask[1][2] = 0xFF00FFFFU; /* 16-bit data */ + mask[2][0] = 0x000000FFU; mask[2][1] = 0x0000FFFFU; mask[2][2] = 0x00FFFFFFU; /* 8-bit data */ + mask[3][0] = 0x000000FFU; mask[3][1] = 0x0000FFFFU; mask[3][2] = 0x00FFFFFFU; /* Bit data */ + +#if defined(AES_CR_NPBLB) /* In case of GCM encryption or CCM decryption, specify the number of padding bytes in last block of payload */ if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE) { - if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT)) - || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM) - && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT))) + uint32_t cr_temp = hcryp->Instance->CR; + + if (((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_GCM_GMAC|CRYP_ALGOMODE_ENCRYPT)) + || ((cr_temp & (AES_CR_CHMOD|AES_CR_MODE)) == (CRYP_CHAINMODE_AES_CCM|CRYP_ALGOMODE_DECRYPT))) { - /* Set NPBLB field in writing the number of padding bytes + /* Set NPBLB field in writing the number of padding bytes for the last block of payload */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16 - difflength) << AES_POSITION_CR_NPBLB); + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, (16U - difflength) << AES_POSITION_CR_NPBLB); } } #else /* Software workaround applied to GCM encryption only */ - if ((hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) && + if ((hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) && (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)) { - /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ + /* Change the mode configured in CHMOD bits of CR register to select CTR mode */ __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_CTR); - } -#endif - + } +#endif + /* Wrap-up entering header or payload data */ /* Enter complete words when possible */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; + inputaddr+=4U; } - /* Enter incomplete word padded with zeroes if applicable + /* Enter incomplete word padded with zeroes if applicable (case of header length not a multiple of 32-bits) */ - if (difflengthmod4 != 0) - { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); - } + if (difflengthmod4 != 0U) + { + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1U]); + } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { hcryp->Instance->DINR = 0; - } + } - if (polling == CRYP_POLLING_ON) + if (polling == (uint32_t)CRYP_POLLING_ON) { - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + hcryp->ErrorCallback(hcryp); +#else HAL_CRYP_ErrorCallback(hcryp); - } +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3048,71 +3161,71 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /* if payload */ if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - + /* Retrieve intermediate data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } /* Retrieve last words of cyphered data */ /* First, retrieve complete output words */ - for(index=0; index < (difflength/4); index ++) + for(index=0U ; index < (difflength/4U); index ++) { *(uint32_t*)(outputaddr) = intermediate_data[index]; - outputaddr+=4; - } + outputaddr+=4U; + } /* Next, retrieve partial output word if applicable; - at the same time, start masking intermediate data + at the same time, start masking intermediate data with a mask of zeros of same size than the padding - applied to the last block of payload */ - if (difflengthmod4 != 0) + applied to the last block of payload */ + if (difflengthmod4 != 0U) { - intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; - *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; - } - - -#if !defined(AES_CR_NPBLB) + intermediate_data[difflength/4U] &= mask[mask_index][difflengthmod4-1U]; + *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U]; + } + + +#if !defined(AES_CR_NPBLB) /* Software workaround applied to GCM encryption only, - applicable for AES IP v2 version (where NPBLB is not defined) */ + applicable for AES IP v2 version (where NPBLB is not defined) */ if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) { /* Change again CHMOD configuration to GCM mode */ - __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); - + __HAL_CRYP_SET_CHAININGMODE(hcryp, CRYP_CHAINMODE_AES_GCM_GMAC); + /* Select FINAL phase */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE); - + /* Before inserting the intermediate data, carry on masking operation with a mask of zeros of same size than the padding applied to the last block of payload */ - for(index=0; index < (4 - ((difflength+3)/4)); index ++) + for(index=0U ; index < (4U - ((difflength+3U)/4U)); index ++) { - intermediate_data[(difflength+3)/4+index] = 0; - } + intermediate_data[((difflength+3U)/4U)+index] = 0; + } /* Insert intermediate data */ - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { - hcryp->Instance->DINR = intermediate_data[index]; - } - - /* Wait for completion, and read data on DOUT. This data is to discard. */ - if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; + hcryp->Instance->DINR = intermediate_data[index]; + } + + /* Wait for completion, and read data on DOUT. This data is to discard. */ + if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); HAL_CRYP_ErrorCallback(hcryp); - } - - /* Read data to discard */ + } + + /* Read data to discard */ /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for(index=0; index < 4; index ++) + for(index=0U ; index < 4U; index ++) { - intermediate_data[index] = hcryp->Instance->DOUTR; - } + intermediate_data[index] = hcryp->Instance->DOUTR; + } } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */ -#endif /* !defined(AES_CR_NPBLB) */ +#endif /* !defined(AES_CR_NPBLB) */ } /* if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) */ } @@ -3129,7 +3242,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ +#endif /* AES */ #endif /* HAL_CRYP_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h index 19f83a6519..db3c1a2af9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_CRYP_EX_H @@ -41,8 +25,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - +#if defined(AES) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -53,9 +36,9 @@ /** @addtogroup CRYPEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -72,7 +55,7 @@ void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); /** * @} - */ + */ /** @addtogroup CRYPEx_Exported_Functions_Group2 * @{ @@ -90,7 +73,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /** * @} - */ + */ /** @addtogroup CRYPEx_Exported_Functions_Group3 * @{ @@ -109,13 +92,13 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp); /** * @} - */ - + */ + /** * @} - */ - + */ + /* Private functions -----------------------------------------------------------*/ /** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions * @{ @@ -125,18 +108,18 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp); /** * @} */ - + /** * @} - */ + */ /** * @} - */ - -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ - + */ + +#endif /* AES */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c index e9b7187443..fba511a5d9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c @@ -3,148 +3,146 @@ * @file stm32l4xx_hal_dac.c * @author MCD Application Team * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + Peripheral State and Errors functions - * + * + Peripheral State and Errors functions * - @verbatim + * + @verbatim ============================================================================== ##### DAC Peripheral features ##### ============================================================================== - [..] + [..] *** DAC Channels *** - ==================== - [..] - STM32L4 devices integrate one or two 12-bit Digital Analog Converters + ==================== + [..] + STM32L4 devices integrate one or two 12-bit Digital Analog Converters (i.e. one or 2 channel(s)) 1 channel : STM32L451xx STM32L452xx STM32L462xx 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx - STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx - STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx + STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx + STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx When 2 channels are available, the 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode): - (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip - peripherals (ex. OPAMPs, comparators). - (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output - or connected to on-chip peripherals (ex. OPAMPs, comparators). - + (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip + peripherals. + (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output + or connected to on-chip peripherals. + *** DAC Triggers *** ==================== [..] Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. - [..] + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] Digital to Analog conversion can be triggered by: (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. The used pin (GPIOx_PIN_9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 + + (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) - + (#) Software using DAC_TRIGGER_SOFTWARE - + *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. - To enable, the output buffer use + To enable, the output buffer use sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - [..] - (@) Refer to the device datasheet for more details about output + [..] + (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. *** DAC connect feature *** - =============================== - [..] - Each DAC channel can be connected internally. + =============================== + [..] + Each DAC channel can be connected internally. To connect, use sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; - + *** GPIO configurations guidelines *** ===================== - [..] - When a DAC channel is used (ex channel1 on PA4) and the other is not + [..] + When a DAC channel is used (ex channel1 on PA4) and the other is not (ex channel2 on PA5 is configured in Analog and disabled). Channel1 may disturb channel2 as coupling effect. Note that there is no coupling on channel2 as soon as channel2 is turned on. Coupling on adjacent channel could be avoided as follows: - when unused PA5 is configured as INPUT PULL-UP or DOWN. - PA5 is configured in ANALOG just before it is turned on. - + when unused PA5 is configured as INPUT PULL-UP or DOWN. + PA5 is configured in ANALOG just before it is turned on. + *** DAC Sample and Hold feature *** ======================== - [..] - For each converter, 2 modes are supported: normal mode and + [..] + For each converter, 2 modes are supported: normal mode and "sample and hold" mode (i.e. low power mode). - In the sample and hold mode, the DAC core converts data, then holds the - converted voltage on a capacitor. When not converting, the DAC cores and - buffer are completely turned off between samples and the DAC output is - tri-stated, therefore reducing the overall power consumption. A new + In the sample and hold mode, the DAC core converts data, then holds the + converted voltage on a capacitor. When not converting, the DAC cores and + buffer are completely turned off between samples and the DAC output is + tri-stated, therefore reducing the overall power consumption. A new stabilization period is needed before each new conversion. The sample and hold allow setting internal or external voltage @ - low power consumption cost (output value can be at any given rate either + low power consumption cost (output value can be at any given rate either by CPU or DMA). - The Sample and hold block and registers uses either LSI & run in - several power modes: run mode, sleep mode, low power run, low power sleep + The Sample and hold block and registers uses either LSI & run in + several power modes: run mode, sleep mode, low power run, low power sleep mode & stop1 mode. - + Low power stop1 mode allows only static conversion. - - To enable Sample and Hold mode + + To enable Sample and Hold mode Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters. Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE; & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, DAC_HoldTime & DAC_RefreshTime; - - *** DAC calibration feature *** - =================================== - [..] - (#) The 2 converters (channel1 & channel2) provide calibration capabilities. + =================================== + [..] + (#) The 2 converters (channel1 & channel2) provide calibration capabilities. (++) Calibration aims at correcting some offset of output buffer. - (++) The DAC uses either factory calibration settings OR user defined + (++) The DAC uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). - (++) The user defined settings can be figured out using self calibration + (++) The user defined settings can be figured out using self calibration handled by HAL_DACEx_SelfCalibrate. (++) HAL_DACEx_SelfCalibrate: (+++) Runs automatically the calibration. (+++) Enables the user trimming mode - (+++) Updates a structure with trimming values with fresh calibration - results. - The user may store the calibration results for larger - (ex monitoring the trimming as a function of temperature + (+++) Updates a structure with trimming values with fresh calibration + results. + The user may store the calibration results for larger + (ex monitoring the trimming as a function of temperature for instance) *** DAC wave generation feature *** - =================================== - [..] + =================================== + [..] Both DAC channels can be used to generate - (#) Noise wave + (#) Noise wave (#) Triangle wave - + *** DAC data format *** ======================= - [..] + [..] The DAC data format can be: (#) 8-bit right alignment using DAC_ALIGN_8B_R (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] + + *** DAC data value to voltage correspondence *** + ================================================ + [..] The analog output voltage on each DAC channel pin is determined by the following equation: [..] @@ -155,26 +153,43 @@ [..] e.g. To set DAC_OUT1 to 0.7V, use (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - + *** DMA requests *** ===================== [..] - A DMA1 request can be generated when an external trigger (but not a software trigger) - occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). - DMA requests are mapped as following: - (#) DAC channel1: mapped either on - (++) DMA1 request 6 channel3 - (++) or DMA2 request channel4 which must be already configured - (#) DAC channel2 (whenever present): mapped either on - (++) DMA1 request 5 channel4 - (++) or DMA2 request 3 channel5 which must be already configured + A DMA1 request can be generated when an external trigger (but not a software trigger) + occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). + DMA requests are mapped as following: + (#) When DMAMUX is NOT present: + DMA1 requests are mapped as following: + (+) DAC channel1 mapped on DMA1 request 6 / channel3 + (+) DAC channel2 mapped on DMA1 request 5 / channel4 + DMA2 requests are mapped as following: + (+) DAC channel1 mapped on DMA2 request 3 / channel4 + (+) DAC channel2 mapped on DMA2 request 3 / channel5 + (#) When DMAMUX is present: + (+) DAC channel1 mapped on DMA1/DMA2 request 6 (can be any DMA channel) + (+) DAC channel2 mapped on DMA1/DMA2 request 7 (can be any DMA channel) + + *** High frequency interface mode *** + ===================================== + [..] + The high frequency interface informs DAC instance about the bus frequency in use. + It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent) + provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function. + Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended + function figured out the correct setting. + The high frequency mode is same for all converters of a same DAC instance. Either same + parameter DAC_HighFrequency is used for all DAC converters or again self + DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter. + [..] - (@) For Dual mode and specific signal (Triangle and noise) generation please - refer to Extended Features Driver description - + (@) For Dual mode and specific signal (Triangle and noise) generation please + refer to Extended Features Driver description + ##### How to use this driver ##### ============================================================================== - [..] + [..] (+) DAC APB clock must be enabled to get write access to DAC registers using HAL_DAC_Init() (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. @@ -183,82 +198,122 @@ *** Calibration mode IO operation *** ====================================== - [..] + [..] (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset() - (+) Run the calibration using HAL_DACEx_SelfCalibrate() + (+) Run the calibration using HAL_DACEx_SelfCalibrate() (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming() *** Polling mode IO operation *** ================================= - [..] - (+) Start the DAC peripheral using HAL_DAC_Start() + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() - - *** DMA mode IO operation *** + + *** DMA mode IO operation *** ============================== - [..] - (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length of data to be transferred at each end of conversion - (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer + First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. - HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() - function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() - + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + (+) All Callbacks + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init + and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit + or @ref HAL_DAC_Init function. + + When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + *** DAC HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DAC HAL driver. - + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status - + [..] - (@) You can refer to the DAC HAL driver header file for more useful macros - - @endverbatim + (@) You can refer to the DAC HAL driver header file for more useful macros + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ - + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -267,12 +322,13 @@ * @{ */ - /** @defgroup DAC DAC - * @brief DAC driver modules - * @{ - */ - #ifdef HAL_DAC_MODULE_ENABLED +#if defined(DAC1) + + /** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -280,42 +336,33 @@ /** @addtogroup DAC_Private_Constants DAC Private Constants * @{ */ -#define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1 ms */ -#define HFSEL_ENABLE_THRESHOLD_80MHZ ((uint32_t)80000000) /* 80 mHz */ +#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */ +#define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */ + /** * @} - */ + */ -/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup DAC_Private_Functions DAC Private Functions - * @{ - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); -/** - * @} - */ /* Exported functions -------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC Exported Functions * @{ */ -/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the DAC. - (+) De-initialize the DAC. - + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + @endverbatim * @{ */ @@ -323,54 +370,77 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DAC peripheral according to the specified parameters * in the DAC_InitStruct and initialize the associated handle. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) -{ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) +{ /* Check DAC handle */ - if(hdac == NULL) + if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - if(hdac->State == HAL_DAC_STATE_RESET) - { + + if (hdac->State == HAL_DAC_STATE_RESET) + { +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the DAC Callback settings */ + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + + if (hdac->MspInitCallback == NULL) + { + hdac->MspInitCallback = HAL_DAC_MspInit; + } +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the low level hardware */ + hdac->MspInitCallback(hdac); +#else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } - + /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; - + /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; - + /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief Deinitialize the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { /* Check DAC handle */ - if(hdac == NULL) + if (hdac == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -379,8 +449,17 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + if (hdac->MspDeInitCallback == NULL) + { + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + } + /* DeInit the low level hardware */ + hdac->MspDeInitCallback(hdac); +#else /* DeInit the low level hardware */ HAL_DAC_MspDeInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; @@ -397,34 +476,34 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /** * @brief Initialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) -{ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +{ /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitialize the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file - */ + */ } /** @@ -432,52 +511,52 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) */ /** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. - + @endverbatim * @{ */ /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported) * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - if(Channel == DAC_CHANNEL_1) + if (Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ - if(((DAC_CR_TEN1 & ~(DAC_CR_TSEL1)) == (hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)))) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); @@ -486,7 +565,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) else { /* Check if software trigger enabled */ - if(((DAC_CR_TEN2 & ~(DAC_CR_TSEL2)) == (hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)))) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); @@ -500,7 +579,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) if(Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ - if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); @@ -509,15 +588,15 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) else { /* Check if software trigger enabled */ - if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2)) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ - /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ - +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /* Check if software trigger enabled */ @@ -529,84 +608,86 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) #endif /* STM32L451xx STM32L452xx STM32L462xx */ /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - + /* Return function status */ return HAL_OK; } -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /** - * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Disables DAC and stop conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment) { - uint32_t tmpreg = 0; - + HAL_StatusTypeDef status; + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - + /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - + /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - + /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - + /* Case of use of channel 1 */ - switch(Alignment) + switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ @@ -622,77 +703,86 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u break; default: break; - } - + } + /* Enable the DMA channel */ /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - + /* Enable the DMA channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + /* Process Unlocked */ __HAL_UNLOCK(hdac); - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } + /* Return function status */ - return HAL_OK; + return status; } -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - + /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment) { - uint32_t tmpreg = 0; - + HAL_StatusTypeDef status; + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - - if(Channel == DAC_CHANNEL_1) + + if (Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - + /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - + /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - + /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - + /* Case of use of channel 1 */ - switch(Alignment) + switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ @@ -714,18 +804,18 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - + /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; - + /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - + /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - + /* Case of use of channel 2 */ - switch(Alignment) + switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R2 address */ @@ -743,33 +833,40 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u break; } } - + /* Enable the DMA channel */ - if(Channel == DAC_CHANNEL_1) + if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - + /* Enable the DMA channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - } + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - + /* Enable the DMA channel */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } - + /* Process Unlocked */ __HAL_UNLOCK(hdac); - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } + /* Return function status */ - return HAL_OK; + return status; } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ @@ -777,27 +874,27 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { - HAL_StatusTypeDef status = HAL_OK; - + HAL_StatusTypeDef status; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); - + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - + /* Disable the DMA channel */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -807,7 +904,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); - + /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } @@ -815,7 +912,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle2); - + /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } @@ -826,11 +923,11 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); - + /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); -#endif /* STM32L451xx STM32L452xx STM32L462xx */ - +#endif /* STM32L451xx STM32L452xx STM32L462xx */ + /* Check if DMA Channel effectively disabled */ if (status != HAL_OK) { @@ -842,7 +939,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } - + /* Return function status */ return status; } @@ -854,32 +951,36 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Handles DAC interrupt request * This function uses the interruption of DMA - * underrun. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * underrun. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) - { + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + { /* Check underrun flag of DAC channel 1 */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - + /* Set DAC error code to chanel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); - + /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); + /* Disable the selected DAC channel1 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - - /* Error callback */ + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh1(hdac); +#else HAL_DAC_DMAUnderrunCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ @@ -887,23 +988,27 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { - /* Check underrun flag of DAC channel 1 */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + /* Check underrun flag of DAC channel 2 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - + /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); - + /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - - /* Disable the selected DAC channel1 DMA request */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel2 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - - /* Error callback */ + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh2(hdac); +#else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ @@ -913,31 +1018,31 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) -{ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ __IO uint32_t tmp = 0; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)hdac->Instance; - if(Channel == DAC_CHANNEL_1) + + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } @@ -948,18 +1053,18 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; - + /* Return function status */ return HAL_OK; } /** - * @brief Conversion complete callback in non-blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Conversion complete callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); @@ -970,12 +1075,12 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) } /** - * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); @@ -987,7 +1092,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1003,7 +1108,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -1020,41 +1125,44 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @} */ - + /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: - (+) Configure channels. + (+) Configure channels. (+) Set the specified data holding register value for DAC channel. - + @endverbatim * @{ */ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Returns the DAC channel data output register value */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Channel); + return hdac->Instance->DOR1; -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -1074,26 +1182,32 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @note By calling this function, the high frequency interface mode (HFSEL bits) + * will be set. This parameter scope is the DAC instance. As the function + * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig + * must be the same at each call. + * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect). + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present) * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0, tmpreg2 = 0; - uint32_t tickstart = 0; + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t tickstart = 0U; #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hclkfreq = 0; -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - - /* Check the DAC parameters */ + uint32_t hclkfreq; +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + + /* Check the DAC parameters */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); + assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); @@ -1101,37 +1215,37 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { - assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); + assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) { assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); - assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); + assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - - if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) - /* Sample on old configuration */ + + if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) + /* Sample on old configuration */ { /* SampleTime */ if (Channel == DAC_CHANNEL_1) { /* Get timeout */ tickstart = HAL_GetTick(); - - /* SHSR1 can be written when BWST1 equals RESET */ - while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET) + + /* SHSR1 can be written when BWST1 is cleared */ + while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) + if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); @@ -1145,15 +1259,15 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } -#if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) +#if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) else /* Channel 2 */ { - /* SHSR2 can be written when BWST2 equals RESET */ + /* SHSR2 can be written when BWST2 is cleared */ - while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET) + while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) + if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); @@ -1164,63 +1278,63 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf return HAL_TIMEOUT; } } - HAL_Delay(1); + HAL_Delay(1U); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } -#endif /* STM32L451xx STM32L452xx STM32L462xx */ - +#endif /* STM32L451xx STM32L452xx STM32L462xx */ + /* HoldTime */ - MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<DAC_SampleAndHoldConfig.DAC_HoldTime)<Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ - MODIFY_REG (hdac->Instance->SHRR, DAC_SHRR_TREFRESH1<DAC_SampleAndHoldConfig.DAC_RefreshTime)<Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } - - if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) + + if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; /* Clear trimming value */ - tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ - + /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; - /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */ - tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); + /* Clear DAC_MCR_MODEx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); /* Calculate MCR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; - + /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ - CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel); - + CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); + /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ - tmpreg2 = (sConfig->DAC_Trigger); + tmpreg2 = sConfig->DAC_Trigger; /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - if(DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency) + if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency) { tmpreg1 |= DAC_CR_HFSEL; } - else + else { if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE == sConfig->DAC_HighFrequency) { @@ -1229,8 +1343,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf else /* Automatic selection */ { hclkfreq = HAL_RCC_GetHCLKFreq(); - if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) - { + if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) + { /* High frequency enable when HCLK frequency higher than 80 */ tmpreg1 |= DAC_CR_HFSEL; } @@ -1241,21 +1355,20 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf } } } - -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; - /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); - + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } @@ -1265,28 +1378,28 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf */ /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Errors functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides functions allowing to (+) Check the DAC state. (+) Check the DAC Errors. - + @endverbatim * @{ */ /** * @brief return the DAC handle state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; @@ -1295,7 +1408,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ @@ -1304,6 +1417,243 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) return hdac->ErrorCode; } +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DAC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID + * + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdac); + + if (hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = pCallback; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = pCallback; + break; + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} + +/** + * @brief Unregister a User DAC Callback + * DAC Callback is redirected to the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdac); + + if (hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + break; + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + case HAL_DAC_ALL_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ @@ -1317,61 +1667,75 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) */ /** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DAC_ConvCpltCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; } /** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DAC_ErrorCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh1(hdac); +#else + HAL_DAC_ErrorCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; } /** * @} */ +/** + * @} + */ + +#endif /* DAC1 */ + #endif /* HAL_DAC_MODULE_ENABLED */ -/** - * @} - */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h index f19d72be8e..8a5558e758 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h @@ -6,49 +6,34 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DAC_H -#define __STM32L4xx_HAL_DAC_H +#ifndef STM32L4xx_HAL_DAC_H +#define STM32L4xx_HAL_DAC_H #ifdef __cplusplus extern "C" { #endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(DAC1) + /** @addtogroup DAC * @{ */ @@ -59,90 +44,132 @@ * @{ */ -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ - -}HAL_DAC_StateTypeDef; - -/** - * @brief DAC handle Structure definition - */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ + +} HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +typedef struct __DAC_HandleTypeDef +#else typedef struct +#endif { DAC_TypeDef *Instance; /*!< Register base address */ - + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ HAL_LockTypeDef Lock; /*!< DAC locking object */ - - DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ - - DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ - - __IO uint32_t ErrorCode; /*!< DAC Error code */ - -}DAC_HandleTypeDef; -/** - * @brief DAC Configuration sample and hold Channel structure definition - */ + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + + __IO uint32_t ErrorCode; /*!< DAC Error code */ + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +} DAC_HandleTypeDef; + +/** + * @brief DAC Configuration sample and hold Channel structure definition + */ typedef struct { uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. - This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. - This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel - This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. - This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ - - uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel - This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. - This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ -} -DAC_SampleAndHoldConfTypeDef; + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ -/** - * @brief DAC Configuration regular Channel structure definition - */ + uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ +} DAC_SampleAndHoldConfTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ typedef struct { #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode + uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode This parameter can be a value of @ref DAC_HighFrequency */ #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - + uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. This parameter can be a value of @ref DAC_SampleAndHold */ - + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ - + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ - - uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode - This parameter must be a value of @ref DAC_UserTrimming + + uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref DAC_UserTrimming DAC_UserTrimming is either factory or user trimming */ - - uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value - i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. + + uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value + i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ - -}DAC_ChannelConfTypeDef; + DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ + +} DAC_ChannelConfTypeDef; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DAC Callback ID enumeration definition + */ +typedef enum +{ + HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ + HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ + HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ + HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ + HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ + HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ + HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ +} HAL_DAC_CallbackIDTypeDef; + +/** + * @brief HAL DAC Callback pointer definition + */ +typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} @@ -157,11 +184,15 @@ typedef struct /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ -#define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ +#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ @@ -171,80 +202,79 @@ typedef struct */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ -#endif /* STM32L451xx STM32L452xx STM32L462xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ + +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T5_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */ +#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - + /** * @} - */ + */ /** @defgroup DAC_output_buffer DAC output buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) -#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1) +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U +#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) /** * @} */ - + /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_1 0x00000000U #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#define DAC_CHANNEL_2 0x00000010U +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -255,9 +285,9 @@ typedef struct /** @defgroup DAC_data_alignment DAC data alignment * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U /** * @} @@ -265,9 +295,9 @@ typedef struct /** @defgroup DAC_flags_definition DAC flags definition * @{ - */ -#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) + */ +#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) +#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /** * @} @@ -275,19 +305,19 @@ typedef struct /** @defgroup DAC_IT_definition DAC IT definition * @{ - */ -#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) + */ +#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) +#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) /** * @} */ - + /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000) -#define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0) +#define DAC_CHIPCONNECT_DISABLE 0x00000000U +#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) /** * @} @@ -296,36 +326,35 @@ typedef struct /** @defgroup DAC_UserTrimming DAC User Trimming * @{ */ +#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ +#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ -#define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ -#define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */ - /** * @} - */ + */ /** @defgroup DAC_SampleAndHold DAC power mode * @{ */ -#define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000) -#define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2) +#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U +#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) /** * @} */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -/** @defgroup DAC_HighFrequency DAC high frequency interface mode +/** @defgroup DAC_HighFrequency DAC high frequency interface mode * @{ */ -#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE ((uint32_t)0x00000000) /*!< High frequency interface mode disabled */ -#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ ((uint32_t)DAC_CR_HFSEL) /*!< High frequency interface mode enabled */ -#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC ((uint32_t)0x00000002) /*!< High frequency interface mode automatic */ - +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002U /*!< High frequency interface mode automatic */ + /** * @} */ -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + /** * @} */ @@ -337,48 +366,56 @@ typedef struct */ /** @brief Reset DAC handle state. - * @param __HANDLE__: specifies the DAC handle. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** @brief Enable the DAC channel. - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_Channel__: specifies the DAC channel + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) +((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Disable the DAC channel. - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_Channel__: specifies the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) - +((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + /** @brief Set DHR12R1 alignment. - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment. - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment. - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) /** @brief Enable the DAC interrupt. - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -387,8 +424,8 @@ typedef struct #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt. - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -397,8 +434,8 @@ typedef struct #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified DAC interrupt source is enabled or not. - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -407,8 +444,8 @@ typedef struct #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to get. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag @@ -417,8 +454,8 @@ typedef struct #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the DAC flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag @@ -428,7 +465,7 @@ typedef struct /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ @@ -443,30 +480,30 @@ typedef struct defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) -#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF) +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) /** * @} */ - -/* Include DAC HAL Extended module */ -#include "stm32l4xx_hal_dac_ex.h" -/* Exported functions --------------------------------------------------------*/ +/* Include DAC HAL Extended module */ +#include "stm32l4xx_hal_dac_ex.h" + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup DAC_Exported_Functions * @{ @@ -474,12 +511,12 @@ typedef struct /** @addtogroup DAC_Exported_Functions_Group1 * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); -void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); -void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /** * @} @@ -487,41 +524,50 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); /** @addtogroup DAC_Exported_Functions_Group2 * @{ - */ + */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); -void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); -void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering/unregistering */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ /** @addtogroup DAC_Exported_Functions_Group3 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ /** @addtogroup DAC_Exported_Functions_Group4 * @{ - */ + */ /* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); /** @@ -532,20 +578,32 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); * @} */ +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @} */ - + /** * @} */ - + +#endif /* DAC1 */ + +/** + * @} + */ + #ifdef __cplusplus } -#endif - +#endif -#endif /*__STM32L4xx_HAL_DAC_H */ + +#endif /*STM32L4xx_HAL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c index d139620350..1b12d22504 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c @@ -3,57 +3,47 @@ * @file stm32l4xx_hal_dac_ex.c * @author MCD Application Team * @brief DAC HAL module driver. - * This file provides firmware functions to manage the extended - * functionalities of the DAC peripheral. - * + * This file provides firmware functions to manage the extended + * functionalities of the DAC peripheral. * - @verbatim + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] + *** Dual mode IO operation *** + ============================== (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in + Channel 1 and Channel 2. + + *** Signal generation operation *** + =================================== (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel. (+) HAL_DACEx_SetUserTrimming to set user trimming value. - (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting - after reset, user setting if HAL_DACEx_SetUserTrimming have been used + (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting + after reset, user setting if HAL_DACEx_SetUserTrimming have been used at least one time after reset). - @endverbatim + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ @@ -63,12 +53,14 @@ * @{ */ +#ifdef HAL_DAC_MODULE_ENABLED + +#if defined(DAC1) + /** @defgroup DACEx DACEx * @brief DAC Extended HAL module driver * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -76,18 +68,18 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - + /** @defgroup DACEx_Exported_Functions DACEx Exported Functions * @{ */ /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions - * @brief Extended IO operation functions + * @brief Extended IO operation functions * -@verbatim +@verbatim ============================================================================== ##### Extended features functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. @@ -95,19 +87,20 @@ (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. (+) Get result of dual mode conversion. - + @endverbatim * @{ */ /** * @brief Enable or disable the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: - * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -120,78 +113,79 @@ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 - * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the triangle wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } /** * @brief Enable or disable the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: - * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. - * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation - * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the noise wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } @@ -202,55 +196,56 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) -{ - uint32_t data = 0, tmp = 0; - +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data; + uint32_t tmp; + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); - + /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8U) | Data1; } else { - data = ((uint32_t)Data2 << 16) | Data1; + data = ((uint32_t)Data2 << 16U) | Data1; } - + tmp = (uint32_t)hdac->Instance; tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; - + /* Return function status */ return HAL_OK; } /** * @brief Conversion complete callback in non-blocking mode for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); @@ -261,12 +256,12 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) } /** - * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); @@ -278,7 +273,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -294,7 +289,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -313,10 +308,10 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief Run the self calibration of one DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC channel configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC channel configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -325,23 +320,27 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) * @note Calibration runs about 7 ms. */ -HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) -{ +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +{ HAL_StatusTypeDef status = HAL_OK; - - __IO uint32_t tmp = 0; - uint32_t trimmingvalue = 0; + + __IO uint32_t tmp; + uint32_t trimmingvalue; uint32_t delta; - + /* store/restore channel configuration structure purpose */ - uint32_t oldmodeconfiguration = 0; - + uint32_t oldmodeconfiguration; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Check the DAC handle allocation */ /* Check if DAC running */ - if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY)) + if (hdac == NULL) + { + status = HAL_ERROR; + } + else if (hdac->State == HAL_DAC_STATE_BUSY) { status = HAL_ERROR; } @@ -349,19 +348,19 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC { /* Process locked */ __HAL_LOCK(hdac); - + /* Store configuration */ - oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel)); - + oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL))); + /* Disable the selected DAC channel */ - CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel)); - + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); + /* Set mode in MCR for calibration */ - MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0); - + MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); + /* Set DAC Channel1 DHR register to the middle value */ - tmp = (uint32_t)hdac->Instance; - + tmp = (uint32_t)hdac->Instance; + #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) @@ -376,30 +375,30 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); #endif /* STM32L451xx STM32L452xx STM32L462xx */ - *(__IO uint32_t *) tmp = 0x0800; - + *(__IO uint32_t *) tmp = 0x0800U; + /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ - SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel)); - - /* Init trimming counter */ + SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16; - delta = 8; - while (delta != 0) + trimmingvalue = 16U; + delta = 8U; + while (delta != 0U) { /* Set candidate trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + + /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ /* i.e. minimum time needed between two calibration steps */ HAL_Delay(1); - - if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) + { /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */ trimmingvalue -= delta; } @@ -407,67 +406,68 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC { /* DAC_SR_CAL_FLAGx is LOW try lower trimming */ trimmingvalue += delta; - } - delta >>= 1; + } + delta >>= 1U; } - + /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ /* Set candidate trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + + /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ /* i.e. minimum time needed between two calibration steps */ - HAL_Delay(1); - - if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) + { /* OPAMP_CSR_OUTCAL is actually one value more */ trimmingvalue++; /* Set right trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } - + /* Disable the selected DAC channel calibration */ /* i.e. clear DAC_CR_CENx bit */ - CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel)); - + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + sConfig->DAC_TrimmingValue = trimmingvalue; sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; - + /* Restore configuration */ - MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration); - + MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); + /* Process unlocked */ __HAL_UNLOCK(hdac); } - + return status; } /** * @brief Set the trimming mode and trimming value (user trimming mode applied). - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure updated with new DAC trimming value. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure updated with new DAC trimming value. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param NewTrimmingValue: DAC new trimming value + * @param NewTrimmingValue DAC new trimming value * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue) -{ +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, + uint32_t NewTrimmingValue) +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); - + /* Check the DAC handle allocation */ - if(hdac == NULL) + if (hdac == NULL) { status = HAL_ERROR; } @@ -475,14 +475,14 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe { /* Process locked */ __HAL_LOCK(hdac); - + /* Set new trimming */ - MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); + /* Update trimming mode */ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; sConfig->DAC_TrimmingValue = NewTrimmingValue; - + /* Process unlocked */ __HAL_UNLOCK(hdac); } @@ -491,34 +491,22 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /** * @brief Return the DAC trimming value. - * @param hdac : DAC handle - * @param Channel: The selected DAC channel. + * @param hdac DAC handle + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval Trimming value : range: 0->31 - * + * */ -uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) +uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) { - uint32_t trimmingvalue = 0; - - /* Check the DAC handle allocation */ - /* And not in Reset state */ - if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET)) - { - return HAL_ERROR; - } - else - { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(Channel)); /* Retrieve trimming */ - trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel); - } - return trimmingvalue; + return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); } /** @@ -527,37 +515,36 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: - (+) Configure channels. (+) Set the specified data holding register value for DAC channel. - + @endverbatim * @{ */ /** * @brief Return the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) { - uint32_t tmp = 0; - + uint32_t tmp = 0U; + tmp |= hdac->Instance->DOR1; - tmp |= hdac->Instance->DOR2 << 16; - + tmp |= hdac->Instance->DOR2 << 16U; + /* Returns the DAC channel data output register value */ return tmp; } @@ -566,7 +553,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) * @} */ -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -576,7 +563,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions @@ -585,49 +572,61 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) */ /** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DACEx_ConvCpltCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; } /** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DACEx_ErrorCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh2(hdac); +#else + HAL_DACEx_ErrorCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; } /** @@ -637,12 +636,14 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ +/** + * @} + */ + +#endif /* DAC1 */ + #endif /* HAL_DAC_MODULE_ENABLED */ -/** - * @} - */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h index f9c82155ee..796d5f7ffe 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h @@ -6,95 +6,81 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DAC_EX_H -#define __STM32L4xx_HAL_DAC_EX_H +#ifndef STM32L4xx_HAL_DAC_EX_H +#define STM32L4xx_HAL_DAC_EX_H #ifdef __cplusplus extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(DAC1) + /** @addtogroup DACEx * @{ */ /* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL State structures definition - */ + +/** + * @brief HAL State structures definition + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ - */ - + */ + /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ -#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ -#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ -#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ -#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ -#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ -#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ -#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ -#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ +#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ /** * @} - */ + */ /** * @} @@ -107,9 +93,9 @@ /** @defgroup DACEx_Private_Macros DACEx Private Macros * @{ - */ + */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ @@ -117,8 +103,8 @@ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ @@ -126,7 +112,7 @@ #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ @@ -134,41 +120,40 @@ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \ ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC)) - -#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - -#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF) -#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF) +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + +#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) + +#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) +#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) -#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) - -#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) +#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \ ((CONNECT) == DAC_CHIPCONNECT_ENABLE)) @@ -200,14 +185,11 @@ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) - - - /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /* Extended features functions ***********************************************/ /** @addtogroup DACEx_Exported_Functions @@ -216,16 +198,17 @@ /** @addtogroup DACEx_Exported_Functions_Group2 * @{ - */ + */ /* IO operation functions *****************************************************/ - + HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ @@ -240,8 +223,6 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue); /** * @} @@ -249,19 +230,13 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /** @addtogroup DACEx_Exported_Functions_Group3 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ - /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ - /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); - + /** * @} */ @@ -294,14 +269,16 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); * @} */ +#endif /* DAC1 */ + /** * @} */ #ifdef __cplusplus } -#endif +#endif -#endif /*__STM32L4xx_HAL_DAC_EX_H */ +#endif /*STM32L4xx_HAL_DAC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c index caa181294f..d718b0bda4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c @@ -3,135 +3,166 @@ * @file stm32l4xx_hal_dcmi.c * @author MCD Application Team * @brief DCMI HAL module driver - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - @verbatim + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - The sequence below describes how to use this driver to capture an image + The sequence below describes how to use this driver to capture images from a camera module connected to the DCMI Interface. This sequence does not take into account the configuration of the camera module, which should be made before configuring and enabling - the DCMI. + the DCMI to capture images. (#) Program the required configuration through the following parameters: horizontal and vertical polarity, pixel clock polarity, capture rate, synchronization mode, frame delimiter codes, data width, byte and line selection using HAL_DCMI_Init() function. - + (#) Optionally select JPEG mode; in that case, only the polarity - and the capture mode parameters need to be set. - + and the capture mode parameters need to be set. + (#) Capture mode can be either snapshot or continuous mode. - + (#) Configure the DMA_Handle to transfer data from DCMI DR register to the destination memory buffer. - + -@- In snapshot mode, the interface transfers a single frame through DMA. In continuous mode, the DMA must be set in circular mode to ensure a continuous - flow of images data samples. + flow of images data samples. (#) Program the transfer configuration through the following parameters: - DCMI mode, destination memory buffer address and data length then + DCMI mode, destination memory buffer address and data length then enable capture using HAL_DCMI_Start_DMA() function. - + (#) Whether in continuous or snapshot mode, data length parameter must be equal to the frame size. - - (#) When the frame size is unknown beforehand (e.g. JPEG case), data length must - be large enough to ensure the capture of a frame. - - (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), - (++) the DMA must be configured in circular mode, either for snapshot or continuous - capture mode, - (++) during capture, the driver copies the image data samples from DCMI DR register - at the end of the final destination buffer used as a work buffer, - (++) at each DMA half (respectively complete) transfer interrupt, the first - (resp. second) half of the work buffer is copied to the final destination thru - a second DMA channel. - (++) Parameters of this second DMA channel are contained in the memory to memory DMA - handle "DMAM2M_Handle", itself field of the DCMI handle structure. - (++) This memory to memory transfer has length half that of the work buffer and is - carried out in normal mode (not in circular mode). - (#) Optionally, configure and enable the CROP feature to select a - rectangular window from the received image using HAL_DCMI_ConfigCrop() + (#) When the frame size is unknown beforehand (e.g. JPEG case), data length must + be large enough to ensure the capture of a frame. + + (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), + (++) the DMA must be configured in circular mode, either for snapshot or continuous + capture mode, + (++) during capture, the driver copies the image data samples from DCMI DR register + at the end of the final destination buffer used as a work buffer, + (++) at each DMA half (respectively complete) transfer interrupt, the first + (resp. second) half of the work buffer is copied to the final destination thru + a second DMA channel. + (++) Parameters of this second DMA channel are contained in the memory to memory DMA + handle "DMAM2M_Handle", itself field of the DCMI handle structure. + (++) This memory to memory transfer has length half that of the work buffer and is + carried out in normal mode (not in circular mode). + + (#) Optionally, configure and enable the CROP feature to select a + rectangular window from the received image using HAL_DCMI_ConfigCrop() and HAL_DCMI_EnableCrop() functions. Use HAL_DCMI_DisableCrop() to disable this feature. (#) The capture can be stopped with HAL_DCMI_Stop() function. (#) To control the DCMI state, use the function HAL_DCMI_GetState(). - - (#) To read the DCMI error code, use the function HAL_DCMI_GetError(). - + + (#) To read the DCMI error code, use the function HAL_DCMI_GetError(). + [..] (@) When the frame size is less than the maximum DMA transfer length (i.e. 65535) and when in snapshot mode, user must make sure the FRAME interrupt is disabled. This allows to avoid corner cases where the FRAME interrupt might be triggered before the DMA transfer completion interrupt. In this specific configuration, - the driver checks the FRAME capture flag after the DMA transfer end and calls - HAL_DCMI_FrameEventCallback() if the flag is set. + the driver checks the FRAME capture flag after the DMA transfer end and calls + HAL_DCMI_FrameEventCallback() if the flag is set. *** DCMI HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DCMI HAL driver. - + (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral. (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral. (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags. (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags. (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts. (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts. - (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred - and that the interruption is enabled at the same time. - + (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not. + + *** Callback registration *** + ============================= + + The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback. + + Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks: + (+) FrameEventCallback : DCMI Frame Event. + (+) VsyncEventCallback : DCMI Vsync Event. + (+) LineEventCallback : DCMI Line Event. + (+) ErrorCallback : DCMI error. + (+) MspInitCallback : DCMI MspInit. + (+) MspDeInitCallback : DCMI MspDeInit. + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + This function allows to reset following callbacks: + (+) FrameEventCallback : DCMI Frame Event. + (+) VsyncEventCallback : DCMI Vsync Event. + (+) LineEventCallback : DCMI Line Event. + (+) ErrorCallback : DCMI error. + (+) MspInitCallback : DCMI MspInit. + (+) MspDeInitCallback : DCMI MspDeInit. + + By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init + and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit + or @ref HAL_DCMI_Init function. + + When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_DCMI_MODULE_ENABLED - -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined (DCMI) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -149,40 +180,19 @@ /** @defgroup DCMI_Stop_TimeOut DCMI Stop TimeOut * @{ - */ -#define DCMI_TIMEOUT_STOP ((uint32_t)1000) /*!< 1s */ + */ +#define DCMI_TIMEOUT_STOP ((uint32_t)1000U) /*!< 1s */ /** * @} */ -/** @defgroup DCMI_Shifts DCMI Shifts - * @{ - */ -#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */ -#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */ - -#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */ -#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */ -#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */ - -#define DCMI_POSITION_ESUR_LSU (uint32_t)POSITION_VAL(DCMI_ESUR_LSU) /*!< Required left shift to set line start delimiter unmask */ -#define DCMI_POSITION_ESUR_LEU (uint32_t)POSITION_VAL(DCMI_ESUR_LEU) /*!< Required left shift to set line end delimiter unmask */ -#define DCMI_POSITION_ESUR_FEU (uint32_t)POSITION_VAL(DCMI_ESUR_FEU) /*!< Required left shift to set frame end delimiter unmask */ -/** - * @} - */ - -#define NPRIME 16 +#define NPRIME 16U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -uint32_t PrimeArray[NPRIME] = { 1, 2, 3, 5, - 7, 11, 13, 17, - 19, 23, 29, 31, - 37, 41, 43, 47}; /* Private function prototypes -----------------------------------------------*/ /** @addtogroup DCMI_Private_Functions DCMI Private Functions * @{ @@ -203,38 +213,38 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize); /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DCMI - (+) De-initialize the DCMI + (+) De-initialize the DCMI @endverbatim * @{ */ - + /** * @brief Initialize the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @note By default, all interruptions are enabled (line end, frame end, overrun, - * VSYNC and embedded synchronization error interrupts). + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @note By default, all interruptions are enabled (line end, frame end, overrun, + * VSYNC and embedded synchronization error interrupts). * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) -{ +{ /* Check the DCMI peripheral state */ if(hdcmi == NULL) { return HAL_ERROR; } - + /* Check function parameters */ assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); - assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); + assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); @@ -246,27 +256,44 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); - + if(hdcmi->State == HAL_DCMI_STATE_RESET) { /* Allocate lock resource and initialize it */ hdcmi->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + + /* Init the DCMI Callback settings */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ + hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ + hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ + hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ + + if(hdcmi->MspInitCallback == NULL) + { + /* Legacy weak MspInit Callback */ + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + } + /* Initialize the low level hardware (MSP) */ + hdcmi->MspInitCallback(hdcmi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_DCMI_MspInit(hdcmi); - } - +#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */ + } + /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - + hdcmi->State = HAL_DCMI_STATE_BUSY; + /* Disable DCMI IP before setting the configuration register */ - __HAL_DCMI_DISABLE(hdcmi); - + __HAL_DCMI_DISABLE(hdcmi); + if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B) { - /* Byte select mode must be programmed to the reset value if the extended mode + /* Byte select mode must be programmed to the reset value if the extended mode is not set to 8-bit data capture on every pixel clock */ - hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL; - } + hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL; + } /* Set DCMI parameters */ hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ @@ -284,14 +311,14 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) { hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SynchroCode.FrameStartCode) |\ - ((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\ - ((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\ - ((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC)); + ((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\ + ((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\ + ((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_ESCR_FEC_Pos)); } /* By default, enable all interrupts. The user may disable the unwanted ones - in resorting to __HAL_DCMI_DISABLE_IT() macro before invoking HAL_DCMI_Start_DMA(). - Enabled interruptions are + in resorting to __HAL_DCMI_DISABLE_IT() macro before invoking HAL_DCMI_Start_DMA(). + Enabled interruptions are - end of line - end of frame - data reception overrun @@ -301,7 +328,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /* Update error code */ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - + /* Initialize the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -309,10 +336,10 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) } /** - * @brief De-initialize the DCMI peripheral, reset control registers to + * @brief De-initialize the DCMI peripheral, reset control registers to * their default values. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) @@ -323,16 +350,25 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) { if (HAL_DCMI_Stop(hdcmi) != HAL_OK) { - /* Issue when stopping DCMI IP */ + /* Issue when stopping DCMI IP */ return HAL_ERROR; } } - - /* DeInit the DCMI low level hardware */ - HAL_DCMI_MspDeInit(hdcmi); - + /* Reset DCMI control register */ - hdcmi->Instance->CR = 0; + hdcmi->Instance->CR = 0; + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + if(hdcmi->MspDeInitCallback == NULL) + { + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + } + /* De-Initialize the low level hardware (MSP) */ + hdcmi->MspDeInitCallback(hdcmi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_DCMI_MspDeInit(hdcmi); +#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */ /* Update error code */ hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; @@ -348,31 +384,31 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) /** * @brief Initialize the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_MspInit() callback can be implemented in the user file - */ + */ } /** * @brief De-initialize the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_MspDeInit() callback can be implemented in the user file */ @@ -382,65 +418,65 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) * @} */ -/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure destination address and data length, + (+) Configure destination address and data length, enable DCMI DMA request and DCMI capture. (+) Stop DCMI capture. (+) Handle DCMI interrupt request. - + [..] A set of callbacks is provided: (+) HAL_DCMI_ErrorCallback() (+) HAL_DCMI_LineEventCallback() (+) HAL_DCMI_VsyncEventCallback() (+) HAL_DCMI_FrameEventCallback() - + @endverbatim * @{ */ /** - * @brief Enable DCMI capture in DMA mode. - * @param hdcmi: Pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. - * @param pData: The destination memory buffer address. - * @param Length: The length of capture to be transferred (in 32-bit words). + * @brief Enable DCMI capture in DMA mode. + * @param hdcmi Pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. + * @param pData The destination memory buffer address. + * @param Length The length of capture to be transferred (in 32-bit words). * @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length), * the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA() * initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each * half and complete transfer interrupt triggers a copy from the work buffer to - * the final destination pData thru a second DMA channel. - * @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end, + * the final destination pData thru a second DMA channel. + * @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end, * frame end, overrun, VSYNC and embedded synchronization error interrupts). * User can disable unwanted interrupts thru __HAL_DCMI_DISABLE_IT() macro - * before invoking HAL_DCMI_Start_DMA(). - * @note For length less than 0xFFFF (DMA maximum transfer length) and in snapshot mode, + * before invoking HAL_DCMI_Start_DMA(). + * @note For length less than 0xFFFF (DMA maximum transfer length) and in snapshot mode, * frame interrupt is disabled before DMA transfer. FRAME capture flag is checked - * in DCMI_DMAXferCplt callback at the end of the DMA transfer. If flag is set, - * HAL_DCMI_FrameEventCallback() API is called. + * in DCMI_DMAXferCplt callback at the end of the DMA transfer. If flag is set, + * HAL_DCMI_FrameEventCallback() API is called. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) { - uint32_t circular_copy_length = 0; - + uint32_t circular_copy_length; + /* Check capture parameter */ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); /* Process Locked */ __HAL_LOCK(hdcmi); - + /* Lock the DCMI peripheral state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - + /* Configure the DCMI Mode and enable the DCMI IP at the same time */ MODIFY_REG(hdcmi->Instance->CR, (DCMI_CR_CM|DCMI_CR_ENABLE), (DCMI_Mode|DCMI_CR_ENABLE)); @@ -450,7 +486,10 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Set the DMA error callback */ hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; - if(Length <= 0xFFFF) + /* Set the dma abort callback */ + hdcmi->DMA_Handle->XferAbortCallback = NULL; + + if(Length <= 0xFFFFU) { hdcmi->XferCount = 0; /* Mark as direct transfer from DCMI_DR register to final destination buffer */ @@ -459,74 +498,74 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - + return HAL_ERROR; - } + } } else /* Capture length is longer than DMA maximum transfer size */ - { + { /* Set DMA in circular mode */ hdcmi->DMA_Handle->Init.Mode = DMA_CIRCULAR; - + /* Set the DMA half transfer complete callback */ hdcmi->DMA_Handle->XferHalfCpltCallback = DCMI_DMAHalfXferCplt; - + /* Initialize transfer parameters */ hdcmi->XferSize = Length; /* Store the complete transfer length in DCMI handle */ hdcmi->pBuffPtr = pData; /* Final destination buffer pointer */ - + circular_copy_length = DCMI_TransferSize(Length); /* Check if issue in intermediate length computation */ - if (circular_copy_length == 0) + if (circular_copy_length == 0U) { /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - - return HAL_ERROR; - } - + + return HAL_ERROR; + } + /* Store the number of half - intermediate buffer copies needed */ - hdcmi->XferCount = 2 * ((Length / circular_copy_length) - 1); + hdcmi->XferCount = 2U * ((Length / circular_copy_length) - 1U); /* Store the half-buffer copy length */ - hdcmi->HalfCopyLength = circular_copy_length / 2; - - /* DCMI DR samples in circular mode will be copied - at the end of the final buffer. + hdcmi->HalfCopyLength = circular_copy_length / 2U; + + /* DCMI DR samples in circular mode will be copied + at the end of the final buffer. Now compute the circular buffer start address. */ - /* Start by pointing at the final buffer */ + /* Start by pointing at the final buffer */ hdcmi->pCircularBuffer = pData; /* Update pCircularBuffer in "moving" at the end of the final - buffer, don't forger to convert in bytes to compute exact address */ - hdcmi->pCircularBuffer += 4 * (((Length / circular_copy_length) - 1) * circular_copy_length); - - /* Initiate the circular DMA transfer from DCMI IP to final buffer end */ + buffer, don't forger to convert in bytes to compute exact address */ + hdcmi->pCircularBuffer += 4U * (((Length / circular_copy_length) - 1U) * circular_copy_length); + + /* Initiate the circular DMA transfer from DCMI IP to final buffer end */ if ( HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)hdcmi->pCircularBuffer, circular_copy_length) != HAL_OK) - { + { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Set state back to Ready */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - + return HAL_ERROR; - } + } } /* Enable Capture */ - SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); + SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); /* Release Lock */ __HAL_UNLOCK(hdcmi); @@ -536,14 +575,15 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo } /** - * @brief Disable DCMI capture in DMA mode. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status + * @brief Disable DCMI capture in DMA mode. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) { - uint32_t tickstart = 0; + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdcmi); @@ -552,32 +592,30 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) hdcmi->State = HAL_DCMI_STATE_BUSY; /* Disable Capture */ - CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); + CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DCMI capture is effectively disabled */ - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U) { if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP) - { + { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_TIMEOUT; + + status = HAL_TIMEOUT; + break; } } - + /* Disable the DMA */ - HAL_DMA_Abort(hdcmi->DMA_Handle); - + if (HAL_DMA_Abort(hdcmi->DMA_Handle) != HAL_OK) + { + DCMI_DMAError(hdcmi->DMA_Handle); + } + /* Disable DCMI IP */ __HAL_DCMI_DISABLE(hdcmi); @@ -588,18 +626,18 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) __HAL_UNLOCK(hdcmi); /* Return function status */ - return HAL_OK; + return status; } /** - * @brief Suspend DCMI capture. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status + * @brief Suspend DCMI capture. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Process locked */ __HAL_LOCK(hdcmi); @@ -610,25 +648,25 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) hdcmi->State = HAL_DCMI_STATE_SUSPENDED; /* Disable Capture */ - CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); + CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DCMI capture is effectively disabled */ - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0) + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U) { if((HAL_GetTick() - tickstart ) > DCMI_TIMEOUT_STOP) - { + { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - + /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - + __HAL_UNLOCK(hdcmi); + return HAL_TIMEOUT; } } @@ -636,16 +674,16 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - + /* Return function status */ return HAL_OK; } /** - * @brief Resume DCMI capture. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status + * @brief Resume DCMI capture. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) { @@ -657,7 +695,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Enable Capture */ + /* Enable Capture */ SET_BIT(hdcmi->Instance->CR, DCMI_CR_CAPTURE); } @@ -669,16 +707,16 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) /** * @brief Handle DCMI interrupt request. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for the DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for the DCMI. * @retval None */ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) -{ +{ uint32_t misflags = READ_REG(hdcmi->Instance->MISR); - + /* Synchronization error interrupt management *******************************/ - if ((misflags & DCMI_MIS_ERR_MIS) != RESET) + if ((misflags & DCMI_MIS_ERR_MIS) != 0x0U) { /* Clear the Synchronization error flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); @@ -686,82 +724,97 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; } - + /* Overflow interrupt management ********************************************/ - if ((misflags & DCMI_MIS_OVR_MIS) != RESET) + if ((misflags & DCMI_MIS_OVR_MIS) != 0x0U) { /* Clear the Overflow flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; + hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; } - + if (hdcmi->ErrorCode != HAL_DCMI_ERROR_NONE) { /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; /* Set the overflow callback */ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; - - /* Abort the DMA Transfer */ - HAL_DMA_Abort_IT(hdcmi->DMA_Handle); - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); + /* Abort the DMA Transfer */ + if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK) + { + DCMI_DMAError(hdcmi->DMA_Handle); + } } - + /* Line Interrupt management ************************************************/ - if ((misflags & DCMI_MIS_LINE_MIS) != RESET) + if ((misflags & DCMI_MIS_LINE_MIS) != 0x0U) { - /* Clear the Line interrupt flag */ + /* Clear the Line interrupt flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); - /* Line interrupt Callback */ + /* Line interrupt Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI line event callback*/ + hdcmi->LineEventCallback(hdcmi); +#else HAL_DCMI_LineEventCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } - + /* VSYNC interrupt management ***********************************************/ - if ((misflags & DCMI_MIS_VSYNC_MIS) != RESET) + if ((misflags & DCMI_MIS_VSYNC_MIS) != 0x0U) { /* Clear the VSYNC flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); - /* VSYNC Callback */ + /* VSYNC Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI vsync event callback*/ + hdcmi->VsyncEventCallback(hdcmi); +#else HAL_DCMI_VsyncEventCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } - + /* End of Frame interrupt management ****************************************/ - if ((misflags & DCMI_MIS_FRAME_MIS) != RESET) + if ((misflags & DCMI_MIS_FRAME_MIS) != 0x0U) { /* Disable the Line interrupt when using snapshot mode */ if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) { __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE|DCMI_IT_VSYNC|DCMI_IT_ERR|DCMI_IT_OVR); /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; } /* Clear the End of Frame flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - /* End of Frame Callback */ + /* Frame Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI frame event callback*/ + hdcmi->FrameEventCallback(hdcmi); +#else HAL_DCMI_FrameEventCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } } /** * @brief Error DCMI callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_ErrorCallback() callback can be implemented in the user file. */ @@ -769,15 +822,15 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Line Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_LineEventCallback() callback can be implemented in the user file. */ @@ -785,15 +838,15 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief VSYNC Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_VsyncEventCallback() callback can be implemented in the user file. */ @@ -801,15 +854,15 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Frame Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval None */ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DCMI_FrameEventCallback() callback can be implemented in the user file. */ @@ -820,17 +873,17 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the crop feature. (+) Enable/Disable the crop feature. - (+) Configure the synchronization delimiters unmasks. - (+) Enable/Disable user-specified DCMI interrupts. + (+) Configure the synchronization delimiters unmasks. + (+) Enable/Disable user-specified DCMI interrupts. @endverbatim * @{ @@ -838,15 +891,15 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Configure the DCMI crop window coordinates. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param X0: DCMI window crop window X offset (number of pixels clocks to count before the capture). - * @param Y0: DCMI window crop window Y offset (image capture starts with this line number, previous - * line data are ignored). - * @param XSize: DCMI crop window horizontal size (in number of pixels per line). - * @param YSize: DCMI crop window vertical size (in lines count). - * @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line, - * YSize = 0x1 means 2 lines, ...) + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param X0 DCMI window crop window X offset (number of pixels clocks to count before the capture). + * @param Y0 DCMI window crop window Y offset (image capture starts with this line number, previous + * line data are ignored). + * @param XSize DCMI crop window horizontal size (in number of pixels per line). + * @param YSize DCMI crop window vertical size (in lines count). + * @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line, + * YSize = 0x1 means 2 lines, ...) * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) @@ -856,7 +909,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui assert_param(IS_DCMI_WINDOW_HEIGHT(Y0)); assert_param(IS_DCMI_WINDOW_COORDINATE(XSize)); assert_param(IS_DCMI_WINDOW_COORDINATE(YSize)); - + /* Process Locked */ __HAL_LOCK(hdcmi); @@ -864,8 +917,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui hdcmi->State = HAL_DCMI_STATE_BUSY; /* Configure CROP */ - MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE))); - MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST))); + MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos))); + MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_CWSTRT_VST_Pos))); /* Initialize the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -878,8 +931,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui /** * @brief Disable the crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) @@ -894,18 +947,18 @@ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) CLEAR_BIT(hdcmi->Instance->CR, DCMI_CR_CROP); /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - return HAL_OK; + return HAL_OK; } /** * @brief Enable the crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) @@ -917,7 +970,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) hdcmi->State = HAL_DCMI_STATE_BUSY; /* Enable DCMI Crop feature */ - SET_BIT(hdcmi->Instance->CR, DCMI_CR_CROP); + SET_BIT(hdcmi->Instance->CR, DCMI_CR_CROP); /* Change the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -925,15 +978,15 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - return HAL_OK; + return HAL_OK; } /** * @brief Set embedded synchronization delimiters unmasks. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param SyncUnmask: pointer to a DCMI_SyncUnmaskTypeDef structure that contains - * the embedded synchronization delimiters unmasks. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains + * the embedded synchronization delimiters unmasks. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) @@ -946,9 +999,9 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn /* Write DCMI embedded synchronization unmask register */ hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) |\ - ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_POSITION_ESUR_LSU)|\ - ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_POSITION_ESUR_LEU)|\ - ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_POSITION_ESUR_FEU)); + ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos)|\ + ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos)|\ + ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos)); /* Change the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -956,7 +1009,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - return HAL_OK; + return HAL_OK; } @@ -967,38 +1020,38 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn */ /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DCMI state. - (+) Get the specific DCMI error flag. + (+) Get the specific DCMI error flag. @endverbatim * @{ - */ + */ /** * @brief Return the DCMI state. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } /** -* @brief Return the DCMI error code. -* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains + * @brief Return the DCMI error code. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. -* @retval DCMI Error Code -*/ + * @retval DCMI Error Code + */ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; @@ -1007,141 +1060,319 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) /** * @} */ - + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +/** + * @brief DCMI Callback registering + * @param hdcmi dcmi handle + * @param CallbackID dcmi Callback ID + * @param hdcmi pointer to dcmi Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if(hdcmi->State == HAL_DCMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMI_FRAME_EVENT_CB_ID : + hdcmi->FrameEventCallback = pCallback; + break; + + case HAL_DCMI_VSYNC_EVENT_CB_ID : + hdcmi->VsyncEventCallback = pCallback; + break; + + case HAL_DCMI_LINE_EVENT_CB_ID : + hdcmi->LineEventCallback = pCallback; + break; + + case HAL_DCMI_ERROR_CB_ID : + hdcmi->ErrorCallback = pCallback; + break; + + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = pCallback; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hdcmi->State == HAL_DCMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = pCallback; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = pCallback; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief DCMI Callback Unregistering + * @param hdcmi dcmi handle + * @param CallbackID dcmi Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hdcmi->State == HAL_DCMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMI_FRAME_EVENT_CB_ID : + hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ + break; + + case HAL_DCMI_VSYNC_EVENT_CB_ID : + hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ + break; + + case HAL_DCMI_LINE_EVENT_CB_ID : + hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_DCMI_ERROR_CB_ID : + hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hdcmi->State == HAL_DCMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + /** * @} - */ - + */ + /* Private functions ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Functions DCMI Private Functions * @{ */ - - /** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @note When the size of the frame being captured by the DCMI peripheral is - * larger than 0xFFFF (DMA maximum transfer length), this API initiates - * another DMA transfer to copy the second half of the work buffer - * associated to the DCMI handle to the final destination buffer. + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @note When the size of the frame being captured by the DCMI peripheral is + * larger than 0xFFFF (DMA maximum transfer length), this API initiates + * another DMA transfer to copy the second half of the work buffer + * associated to the DCMI handle to the final destination buffer. * @retval None */ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { - uint32_t loop_length = 0; /* transfer length */ - uint32_t * tmpBuffer_Dest = NULL; - uint32_t * tmpBuffer_Orig = NULL; - + uint32_t loop_length; /* transfer length */ + uint32_t * tmpBuffer_Dest; + uint32_t * tmpBuffer_Orig; + uint32_t temp; + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if(hdcmi->XferCount != 0) + if(hdcmi->XferCount != 0U) { - /* Manage second half buffer copy in case of big transfer */ - + /* Manage second half buffer copy in case of big transfer */ + /* Decrement half-copies counter */ - hdcmi->XferCount--; - + hdcmi->XferCount--; + /* Point at DCMI final destination */ - tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; - + tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; + /* Point at DCMI circular buffer mid-location */ - tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; - tmpBuffer_Orig += hdcmi->HalfCopyLength; - + tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; + temp = (uint32_t) (tmpBuffer_Orig); + temp += hdcmi->HalfCopyLength; + tmpBuffer_Orig = (uint32_t *) temp; + /* copy half the buffer size */ loop_length = hdcmi->HalfCopyLength; - + /* Save next entry to write at next half DMA transfer interruption */ - hdcmi->pBuffPtr += (uint32_t) loop_length*4; - hdcmi->XferSize -= hdcmi->HalfCopyLength; - + hdcmi->pBuffPtr += (uint32_t) loop_length*4U; + hdcmi->XferSize -= hdcmi->HalfCopyLength; + /* Data copy from work buffer to final destination buffer */ /* Enable the DMA Channel */ if (HAL_DMA_Start_IT(hdcmi->DMAM2M_Handle, (uint32_t) tmpBuffer_Orig, (uint32_t) tmpBuffer_Dest, loop_length) != HAL_OK) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - + hdcmi->State = HAL_DCMI_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); - } + /* DCMI error Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); +#else + HAL_DCMI_ErrorCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + } } else { /* if End of frame IT is disabled */ - if((hdcmi->Instance->IER & DCMI_IT_FRAME) == RESET) + if((hdcmi->Instance->IER & DCMI_IT_FRAME) == 0x0U) { /* If End of Frame flag is set */ - if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET) + if(__HAL_DCMI_GET_FLAG(hdcmi, (uint32_t)DCMI_FLAG_FRAMERI) != 0x0UL) { /* Clear the End of Frame flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - + /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) - { + { /* Disable the Vsync, Error and Overrun interrupts */ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); - + hdcmi->State = HAL_DCMI_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); + __HAL_UNLOCK(hdcmi); } - - /* FRAME Callback */ + + /* Frame Event Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI frame event callback*/ + hdcmi->FrameEventCallback(hdcmi); +#else HAL_DCMI_FrameEventCallback(hdcmi); - } +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + } } } } - /** - * @brief DMA Half Transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @note When the size of the frame being captured by the DCMI peripheral is - * larger than 0xFFFF (DMA maximum transfer length), this API initiates - * another DMA transfer to copy the first half of the work buffer - * associated to the DCMI handle to the final destination buffer. +/** + * @brief DMA Half Transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @note When the size of the frame being captured by the DCMI peripheral is + * larger than 0xFFFF (DMA maximum transfer length), this API initiates + * another DMA transfer to copy the first half of the work buffer + * associated to the DCMI handle to the final destination buffer. * @retval None */ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma) { - uint32_t loop_length = 0; /* transfer length */ - uint32_t * tmpBuffer_Dest = NULL; - uint32_t * tmpBuffer_Orig = NULL; - + uint32_t loop_length; /* transfer length */ + uint32_t * tmpBuffer_Dest; + uint32_t * tmpBuffer_Orig; + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if(hdcmi->XferCount != 0) + + if(hdcmi->XferCount != 0U) { - /* Manage first half buffer copy in case of big transfer */ - + /* Manage first half buffer copy in case of big transfer */ + /* Decrement half-copies counter */ - hdcmi->XferCount--; - + hdcmi->XferCount--; + /* Point at DCMI final destination */ - tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; - + tmpBuffer_Dest = (uint32_t *)hdcmi->pBuffPtr; + /* Point at DCMI circular buffer start */ - tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; - + tmpBuffer_Orig = (uint32_t *)hdcmi->pCircularBuffer; + /* copy half the buffer size */ loop_length = hdcmi->HalfCopyLength; - + /* Save next entry to write at next DMA transfer interruption */ - hdcmi->pBuffPtr += (uint32_t) loop_length*4; - hdcmi->XferSize -= hdcmi->HalfCopyLength; + hdcmi->pBuffPtr += (uint32_t) loop_length*4U; + hdcmi->XferSize -= hdcmi->HalfCopyLength; /* Data copy from work buffer to final destination buffer */ /* Enable the DMA Channel */ @@ -1149,37 +1380,47 @@ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - + /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - + hdcmi->State = HAL_DCMI_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdcmi); - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); - } + /* DCMI error Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); +#else + HAL_DCMI_ErrorCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + } } } /** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) { - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Error Callback */ - HAL_DCMI_ErrorCallback(hdcmi); + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* DCMI error Callback */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); +#else + HAL_DCMI_ErrorCallback(hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } /** @@ -1188,21 +1429,25 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) * the tranfer from DCMI DR register to the final output buffer is carried out by a sequence * of intermediate sub-copies to temporary buffers of size less than 0xFFFF. * To optimize the number of DMA transfers, the API computes the temporary buffer - * size so that the latter is an even number less than 0xFFFF, that divides the final - * buffer size and is as high as possible. The API implements a sub-optimum solution for - * complexity's sake. - * @note InputSize MUST be even. - * @param InputSize: full buffer size (in 32-bit words) + * size so that the latter is an even number less than 0xFFFF, that divides the final + * buffer size and is as high as possible. The API implements a sub-optimum solution for + * complexity's sake. + * @note InputSize MUST be even. + * @param InputSize full buffer size (in 32-bit words) * @retval Transfer size (in 32-bit words) */ static uint32_t DCMI_TransferSize(uint32_t InputSize) -{ +{ uint32_t j = 1; uint32_t temp = InputSize; uint32_t aPrime[NPRIME] = {0}; uint32_t output = 2; /* Want a result which is an even number */ + uint32_t PrimeArray[NPRIME] = { 1UL, 2UL, 3UL, 5UL, + 7UL, 11UL, 13UL, 17UL, + 19UL, 23UL, 29UL, 31UL, + 37UL, 41UL, 43UL, 47UL}; + - /* Develop InputSize in product of prime numbers */ while (j < NPRIME) @@ -1211,43 +1456,43 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) { break; } - while ((temp % PrimeArray[j]) == 0) + while ((temp % PrimeArray[j]) == 0U) { - aPrime[j]++; - temp /= PrimeArray[j]; + aPrime[j]++; + temp /= PrimeArray[j]; } j++; - } - + } + /* Search for the biggest even divisor less or equal to 0xFFFE = 65534 */ - aPrime[1] -= 1; /* output is initialized to 2, so don't count dividor 2 twice */ + aPrime[1] -= 1U; /* output is initialized to 2, so don't count dividor 2 twice */ /* The algorithm below yields a sub-optimal solution but in an acceptable time. */ - j = NPRIME-1; - while ((j > 0) && (output <= 0xFFFE)) - { - while (aPrime[j] >0) + j = NPRIME-1U; + while ((j > 0U) && (output <= 0xFFFEU)) + { + while (aPrime[j] > 0U) { - if (output * PrimeArray[j] > 0xFFFE) + if ((output * PrimeArray[j]) > 0xFFFEU) { break; } else { - output *= PrimeArray[j]; + output *= PrimeArray[j]; aPrime[j]--; } } j--; } - - - + + + return output; } - + /** * @} */ @@ -1260,9 +1505,7 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) * @} */ -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* DCMI */ #endif /* HAL_DCMI_MODULE_ENABLED */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h index 278566e144..9d0a0607ac 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_DCMI_H @@ -41,12 +25,10 @@ extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#if defined (DCMI) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -55,15 +37,16 @@ /** @addtogroup DCMI DCMI * @brief DCMI HAL module driver * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DCMI_Exported_Types DCMI Exported Types * @{ */ -/** + +/** * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ + */ typedef struct { uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ @@ -73,9 +56,9 @@ typedef struct }DCMI_CodesInitTypeDef; -/** +/** * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ + */ typedef struct { uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */ @@ -85,52 +68,51 @@ typedef struct }DCMI_SyncUnmaskTypeDef; -/** +/** * @brief DCMI Init structure definition - */ + */ typedef struct { uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode. */ + This parameter can be a value of @ref DCMI_Synchronization_Mode */ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity. */ + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity. */ + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity. */ + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate. */ + This parameter can be a value of @ref DCMI_Capture_Rate */ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode. */ + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ DCMI_CodesInitTypeDef SynchroCode; /*!< Specifies the frame start delimiter codes. */ - uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. - This parameter can be a value of @ref DCMI_JPEG_Mode. */ + uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. + This parameter can be a value of @ref DCMI_MODE_JPEG */ - uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface. - This parameter can be a value of @ref DCMI_Byte_Select_Mode. */ - - uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd. - This parameter can be a value of @ref DCMI_Byte_Select_Start. */ + uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface + This parameter can be a value of @ref DCMI_Byte_Select_Mode */ - uint32_t LineSelectMode; /*!< Specifies the data line to be captured by the interface. - This parameter can be a value of @ref DCMI_Line_Select_Mode. */ - - uint32_t LineSelectStart; /*!< Specifies if the data line to be captured by the interface is even or odd. - This parameter can be a value of @ref DCMI_Line_Select_Start. */ - + uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd + This parameter can be a value of @ref DCMI_Byte_Select_Start */ + + uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface + This parameter can be a value of @ref DCMI_Line_Select_Mode */ + + uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd + This parameter can be a value of @ref DCMI_Line_Select_Start */ }DCMI_InitTypeDef; -/** +/** * @brief HAL DCMI State structures definition - */ + */ typedef enum { HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */ @@ -138,14 +120,14 @@ typedef enum HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */ HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ - HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ + HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ }HAL_DCMI_StateTypeDef; -/** +/** * @brief DCMI handle Structure definition */ -typedef struct +typedef struct __DCMI_HandleTypeDef { DCMI_TypeDef *Instance; /*!< DCMI Register base address */ @@ -164,17 +146,42 @@ typedef struct DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to DMA handler */ DMA_HandleTypeDef *DMAM2M_Handle; /*!< Pointer to DMA handler for memory to memory copy - (case picture size > maximum DMA transfer length) */ + (case picture size > maximum DMA transfer length) */ __IO uint32_t ErrorCode; /*!< DCMI Error code */ - - uint32_t pCircularBuffer; /*!< Pointer to intermediate copy buffer - (case picture size > maximum DMA transfer length) */ - + + uint32_t pCircularBuffer; /*!< Pointer to intermediate copy buffer + (case picture size > maximum DMA transfer length) */ + uint32_t HalfCopyLength; /*!< Intermediate copies length - (case picture size > maximum DMA transfer length) */ + (case picture size > maximum DMA transfer length) */ + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ + void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ + void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */ + void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */ + void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */ + void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */ +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ }DCMI_HandleTypeDef; + +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +typedef enum +{ + HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */ + HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */ + HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */ + HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */ + HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */ + HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */ + +}HAL_DCMI_CallbackIDTypeDef; + +typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ + /** * @} */ @@ -187,21 +194,24 @@ typedef struct /** @defgroup DCMI_Error_Code DCMI Error Code * @{ */ -#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun error */ -#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ -#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error */ +#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */ +#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */ +#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */ +#endif /** * @} */ /** @defgroup DCMI_Capture_Mode DCMI Capture Mode * @{ - */ -#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously + */ +#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously into the destination memory through the DMA */ -#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of +#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA */ /** * @} @@ -209,10 +219,10 @@ typedef struct /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode * @{ - */ -#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop) + */ +#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with +#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow */ /** @@ -222,17 +232,17 @@ typedef struct /** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity * @{ */ -#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ /** * @} */ - + /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity * @{ */ -#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */ +#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */ #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ /** @@ -241,8 +251,8 @@ typedef struct /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity * @{ - */ -#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */ + */ +#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */ #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ /** @@ -252,7 +262,7 @@ typedef struct /** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode * @{ */ -#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< JPEG mode disabled */ +#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< JPEG mode disabled */ #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< JPEG mode enabled */ /** @@ -262,7 +272,7 @@ typedef struct /** @defgroup DCMI_Capture_Rate DCMI Capture Rate * @{ */ -#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */ +#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */ #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ @@ -273,7 +283,7 @@ typedef struct /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode * @{ */ -#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ @@ -285,7 +295,7 @@ typedef struct /** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode * @{ */ -#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */ +#define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */ #define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */ #define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ #define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ @@ -296,8 +306,8 @@ typedef struct /** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start * @{ - */ -#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */ + */ +#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */ #define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */ /** @@ -307,7 +317,7 @@ typedef struct /** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode * @{ */ -#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */ +#define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */ #define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ /** @@ -316,8 +326,8 @@ typedef struct /** @defgroup DCMI_Line_Select_Start DCMI Line Select Start * @{ - */ -#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */ + */ +#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */ #define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */ /** @@ -341,57 +351,65 @@ typedef struct * @{ */ -/** +/** * @brief DCMI SR register - */ + */ #define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */ #define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */ #define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ -/** - * @brief DCMI RIS register - */ -#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Capture complete interrupt flag */ -#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */ -#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */ -#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */ -#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */ -/** - * @brief DCMI MIS register - */ -#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Capture complete masked interrupt status */ -#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ -#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ -#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ -#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ +/** + * @brief DCMI RIS register + */ +#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Capture complete interrupt flag */ +#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */ +#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */ +#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */ +#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */ +/** + * @brief DCMI MIS register + */ +#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Capture complete masked interrupt status */ +#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ +#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ +#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ +#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ /** * @} - */ + */ /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup DCMI_Exported_Macros DCMI Exported Macros * @{ */ - + /** @brief Reset DCMI handle state - * @param __HANDLE__: specifies the DCMI handle. + * @param __HANDLE__ specifies the DCMI handle. * @retval None */ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** * @brief Enable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) /** * @brief Disable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) @@ -399,32 +417,32 @@ typedef struct /* Interrupt & Flag management */ /** * @brief Get the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ Get the specified flag. * This parameter can be one of the following values (no combination allowed) - * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) - * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) - * @arg DCMI_FLAG_FNE: FIFO empty flag + * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) + * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) + * @arg DCMI_FLAG_FNE: FIFO empty flag * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag * @arg DCMI_FLAG_OVRRI: Overrun flag * @arg DCMI_FLAG_ERRRI: Synchronization error flag * @arg DCMI_FLAG_VSYNCRI: VSYNC flag * @arg DCMI_FLAG_LINERI: Line flag - * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status - * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status - * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status - * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status - * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status + * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status + * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status + * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status + * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status + * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status * @retval The state of FLAG. */ #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ -((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ - (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) + ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ + (((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) /** * @brief Clear the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag * @arg DCMI_FLAG_OVRRI: Overrun flag @@ -437,8 +455,8 @@ typedef struct /** * @brief Enable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt * @arg DCMI_IT_OVR: Overrun interrupt @@ -451,8 +469,8 @@ typedef struct /** * @brief Disable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt * @arg DCMI_IT_OVR: Overrun interrupt @@ -464,11 +482,11 @@ typedef struct #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) /** - * @brief Check whether or not the specified DCMI interrupt has occurred and that the interruption is enabled at the same time. - * @note A bit in MIS register is set if the corresponding enable bit in + * @brief Check whether the specified DCMI interrupt has occurred or not. + * @note A bit in MIS register is set if the corresponding enable bit in * DCMI_IER is set and the corresponding bit in DCMI_RIS is set. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt flag and source to check. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt flag and source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVR: Overrun interrupt mask @@ -482,29 +500,35 @@ typedef struct /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DCMI_Exported_Functions * @{ */ -/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions +/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions * @{ */ - + /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** * @} */ - -/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions + +/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions * @{ */ - + /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); @@ -518,8 +542,8 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); /** * @} */ - -/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions + +/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ @@ -530,8 +554,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ /** * @} */ - -/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions + +/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions * @{ */ /* Peripheral State functions *************************************************/ @@ -547,71 +571,71 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ /** @addtogroup DCMI_Private_Constants DCMI Private Constants * @{ */ - + /** @defgroup DCMI_Registers_Indices DCMI Registers Indices * @{ - */ -#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */ -#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */ + */ +#define DCMI_MIS_INDEX (0x1000U) /*!< DCMI MIS register index */ +#define DCMI_SR_INDEX (0x2000U) /*!< DCMI SR register index */ /** * @} - */ + */ /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate * @{ */ -#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */ +#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */ /** * @} */ /** @defgroup DCMI_Window_Height DCMI Window Height * @{ - */ -#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */ + */ +#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */ /** * @} */ /** * @} - */ - + */ + /* Private macro -------------------------------------------------------------*/ /** @defgroup DCMI_Private_Macros DCMI Private Macros * @{ */ #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \ ((MODE) == DCMI_MODE_SNAPSHOT)) - + #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ ((MODE) == DCMI_SYNCHRO_EMBEDDED)) - + #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \ ((POLARITY) == DCMI_PCKPOLARITY_RISING)) - + #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \ ((POLARITY) == DCMI_VSPOLARITY_HIGH)) - + #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \ ((POLARITY) == DCMI_HSPOLARITY_HIGH)) - + #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \ ((JPEG_MODE) == DCMI_JPEG_ENABLE)) - + #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) - + #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \ ((DATA) == DCMI_EXTEND_DATA_10B) || \ ((DATA) == DCMI_EXTEND_DATA_12B) || \ ((DATA) == DCMI_EXTEND_DATA_14B)) - + #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) @@ -620,18 +644,15 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); ((MODE) == DCMI_BSM_OTHER) || \ ((MODE) == DCMI_BSM_ALTERNATE_4) || \ ((MODE) == DCMI_BSM_ALTERNATE_2)) - + #define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \ ((POLARITY) == DCMI_OEBS_EVEN)) - + #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ ((MODE) == DCMI_LSM_ALTERNATE_2)) - + #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ - ((POLARITY) == DCMI_OELS_EVEN)) - -#define IS_DCMI_INTERRUPTS(INTERRUPTS) ((INTERRUPTS) <= DCMI_IER_INT_IE) - + ((POLARITY) == DCMI_OELS_EVEN)) /** * @} @@ -640,13 +661,12 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); /** * @} */ - + /** * @} - */ + */ -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DCMI */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h index fcee1d4eca..1db303b64f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h @@ -7,36 +7,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DEF -#define __STM32L4xx_HAL_DEF +#ifndef STM32L4xx_HAL_DEF_H +#define STM32L4xx_HAL_DEF_H #ifdef __cplusplus extern "C" { @@ -45,7 +29,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx.h" #include "stm32_hal_legacy.h" /* Aliases file for old names compatibility */ -#include +#include /* Exported types ------------------------------------------------------------*/ @@ -71,10 +55,12 @@ typedef enum /* Exported macros -----------------------------------------------------------*/ +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do{ \ @@ -82,8 +68,6 @@ typedef enum (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) -#define UNUSED(x) ((void)(x)) - /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. * @note This macro can be used for the following purpose: @@ -123,31 +107,6 @@ typedef enum }while (0) #endif /* USE_RTOS */ -// Added for MBED PR #3062 -#if defined (__CC_ARM) -#pragma diag_suppress 3731 -#endif - -// Added for MBED PR #3062 -static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) -{ - uint32_t newValue; - do { - newValue = (uint32_t)__LDREXW(ptr) | mask; - - } while (__STREXW(newValue, ptr)); -} - -// Added for MBED PR #3062 -static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) -{ - uint32_t newValue; - do { - newValue = (uint32_t)__LDREXW(ptr) &~mask; - - } while (__STREXW(newValue, ptr)); -} - #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) @@ -233,6 +192,6 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) } #endif -#endif /* ___STM32L4xx_HAL_DEF */ +#endif /* STM32L4xx_HAL_DEF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c index 3de4618edc..761a894f0e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: * + Initialization and configuration of channels and filters @@ -15,7 +15,7 @@ * + Extremes detector feature * + Clock absence detector feature * + Break generation on analog watchdog or short-circuit event - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -32,7 +32,7 @@ (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#) Configure the output clock, input, serial interface, analog watchdog, - offset and data right bit shift parameters for this channel using the + offset and data right bit shift parameters for this channel using the HAL_DFSDM_ChannelInit() function. *** Channel clock absence detector *** @@ -46,36 +46,36 @@ clock absence is detected. (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or HAL_DFSDM_ChannelCkabStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used + (#) Please note that the same mode (polling or interrupt) has to be used for all channels because the channels are sharing the same interrupt. (#) Please note also that in interrupt mode, if clock absence detector is stopped for one channel, interrupt will be disabled for all channels. *** Channel short circuit detector *** ====================================== - [..] + [..] (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or or HAL_DFSDM_ChannelScdStart_IT(). (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short circuit. - (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if + (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if short circuit is detected. (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or or HAL_DFSDM_ChannelScdStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used + (#) Please note that the same mode (polling or interrupt) has to be used for all channels because the channels are sharing the same interrupt. (#) Please note also that in interrupt mode, if short circuit detector is stopped for one channel, interrupt will be disabled for all channels. *** Channel analog watchdog value *** ===================================== - [..] + [..] (#) Get analog watchdog filter value of a channel using HAL_DFSDM_ChannelGetAwdValue(). *** Channel offset value *** ===================================== - [..] + [..] (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). *** Filter initialization *** @@ -94,21 +94,21 @@ *** Filter regular channel conversion *** ========================================= - [..] + [..] (#) Select regular channel and enable/disable continuous mode using HAL_DFSDM_FilterConfigRegChannel(). (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or HAL_DFSDM_FilterRegularMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect + (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect the end of regular conversion. (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called at the end of regular conversion. - (#) Get value of regular conversion and corresponding channel using + (#) Get value of regular conversion and corresponding channel using HAL_DFSDM_FilterGetRegularValue(). - (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and + (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that + half transfer and at the transfer complete. Please note that HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA circular mode. (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), @@ -121,15 +121,15 @@ (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or HAL_DFSDM_FilterInjectedMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect + (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect the end of injected conversion. (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called at the end of injected conversion. - (#) Get value of injected conversion and corresponding channel using + (#) Get value of injected conversion and corresponding channel using HAL_DFSDM_FilterGetInjectedValue(). - (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and + (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that + half transfer and at the transfer complete. Please note that HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA circular mode. (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), @@ -155,33 +155,111 @@ [..] (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue(). + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_DFSDM_Channel_RegisterCallback(), + HAL_DFSDM_Filter_RegisterCallback() or + HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback. + + [..] + Function HAL_DFSDM_Channel_RegisterCallback() allows to register + following callbacks: + (+) CkabCallback : DFSDM channel clock absence detection callback. + (+) ScdCallback : DFSDM channel short circuit detection callback. + (+) MspInitCallback : DFSDM channel MSP init callback. + (+) MspDeInitCallback : DFSDM channel MSP de-init callback. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Function HAL_DFSDM_Filter_RegisterCallback() allows to register + following callbacks: + (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. + (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. + (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback. + (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback. + (+) ErrorCallback : DFSDM filter error callback. + (+) MspInitCallback : DFSDM filter MSP init callback. + (+) MspDeInitCallback : DFSDM filter MSP de-init callback. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + For specific DFSDM filter analog watchdog callback use dedicated register callback: + HAL_DFSDM_Filter_RegisterAwdCallback(). + + [..] + Use functions HAL_DFSDM_Channel_UnRegisterCallback() or + HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default + weak function. + + [..] + HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + This function allows to reset following callbacks: + (+) CkabCallback : DFSDM channel clock absence detection callback. + (+) ScdCallback : DFSDM channel short circuit detection callback. + (+) MspInitCallback : DFSDM channel MSP init callback. + (+) MspDeInitCallback : DFSDM channel MSP de-init callback. + + [..] + HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + This function allows to reset following callbacks: + (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. + (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. + (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback. + (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback. + (+) ErrorCallback : DFSDM filter error callback. + (+) MspInitCallback : DFSDM filter MSP init callback. + (+) MspDeInitCallback : DFSDM filter MSP de-init callback. + + [..] + For specific DFSDM filter analog watchdog callback use dedicated unregister callback: + HAL_DFSDM_Filter_UnRegisterAwdCallback(). + + [..] + By default, after the call of init function and if the state is RESET + all callbacks are reset to the corresponding legacy weak functions: + examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak functions in the init and de-init only when these + callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the init and de-init keep and use + the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the init/de-init. + In that case first register the MspInit/MspDeInit user callbacks using + HAL_DFSDM_Channel_RegisterCallback() or + HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function. + + [..] + When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -202,7 +280,7 @@ /** @defgroup DFSDM DFSDM * @brief DFSDM HAL driver module * @{ - */ + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -227,8 +305,8 @@ /** @defgroup DFSDM_Private_Variables DFSDM Private Variables * @{ */ -__IO uint32_t v_dfsdm1ChannelCounter = 0; -DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; +static __IO uint32_t v_dfsdm1ChannelCounter = 0; +static DFSDM_Channel_HandleTypeDef *a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; /** * @} */ @@ -238,11 +316,11 @@ DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NUL * @{ */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance); static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); +static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma); static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma); static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma); @@ -258,7 +336,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); */ /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions - * @brief Channel initialization and de-initialization functions + * @brief Channel initialization and de-initialization functions * @verbatim ============================================================================== @@ -280,7 +358,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) + if (hdfsdm_channel == NULL) { return HAL_ERROR; } @@ -297,72 +375,85 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); - + /* Check that channel has not been already initialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) + if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) { return HAL_ERROR; } - + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; + hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback; + + /* Call MSP init function */ + if (hdfsdm_channel->MspInitCallback == NULL) + { + hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; + } + hdfsdm_channel->MspInitCallback(hdfsdm_channel); +#else /* Call MSP init function */ HAL_DFSDM_ChannelMspInit(hdfsdm_channel); - +#endif + /* Update the channel counter */ v_dfsdm1ChannelCounter++; - + /* Configure output serial clock and enable global DFSDM interface only for first channel */ - if(v_dfsdm1ChannelCounter == 1) + if (v_dfsdm1ChannelCounter == 1U) { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); /* Set the output serial clock source */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; - + /* Reset clock divider */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); - if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) + if (hdfsdm_channel->Init.OutputClock.Activation == ENABLE) { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ - DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << + DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) << DFSDM_CHCFGR1_CKOUTDIV_Pos); } - + /* enable the DFSDM global interface */ DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; } - + /* Set channel input parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | DFSDM_CHCFGR1_CHINSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | - hdfsdm_channel->Init.Input.DataPacking | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | + hdfsdm_channel->Init.Input.DataPacking | hdfsdm_channel->Init.Input.Pins); - + /* Set serial interface parameters */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | hdfsdm_channel->Init.SerialInterface.SpiClock); - + /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); - hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_AWFOSR_Pos)); + hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | + ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; - + /* Set DFSDM Channel to ready state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; /* Store channel handle in DFSDM channel handle table */ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; - + return HAL_OK; } @@ -374,34 +465,42 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) + if (hdfsdm_channel == NULL) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check that channel has not been already deinitialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) + if (a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) { return HAL_ERROR; } /* Disable the DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); - + /* Update the channel counter */ v_dfsdm1ChannelCounter--; - + /* Disable global DFSDM at deinit of last channel */ - if(v_dfsdm1ChannelCounter == 0) + if (v_dfsdm1ChannelCounter == 0U) { DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); } /* Call MSP deinit function */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + if (hdfsdm_channel->MspDeInitCallback == NULL) + { + hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; + } + hdfsdm_channel->MspDeInitCallback(hdfsdm_channel); +#else HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); +#endif /* Set DFSDM Channel in reset state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; @@ -421,7 +520,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_ChannelMspInit could be implemented in the user file. */ @@ -436,12 +535,150 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file. */ } +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user DFSDM channel callback + * to be used instead of the weak predefined callback. + * @param hdfsdm_channel DFSDM channel handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, + pDFSDM_Channel_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_CKAB_CB_ID : + hdfsdm_channel->CkabCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_SCD_CB_ID : + hdfsdm_channel->ScdCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = pCallback; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user DFSDM channel callback. + * DFSDM channel callback is redirected to the weak predefined callback. + * @param hdfsdm_channel DFSDM channel handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_CKAB_CB_ID : + hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; + break; + case HAL_DFSDM_CHANNEL_SCD_CB_ID : + hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback; + break; + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) + { + switch (CallbackID) + { + case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : + hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; + break; + case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : + hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ + /** * @} */ @@ -479,9 +716,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -495,12 +732,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) + while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) + if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT) { /* Set timeout status */ status = HAL_TIMEOUT; @@ -508,7 +745,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm } } - if(status == HAL_OK) + if (status == HAL_OK) { /* Start clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; @@ -524,17 +761,17 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; uint32_t channel; - + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ return HAL_ERROR; @@ -543,27 +780,27 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs { /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + /* Get timeout */ tickstart = HAL_GetTick(); /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) == 0) + while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; } } } - + /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + /* Return function status */ return HAL_OK; } @@ -581,9 +818,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -592,10 +829,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ { /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - + /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); } /* Return function status */ return status; @@ -618,9 +855,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -634,12 +871,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) + while ((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) + if ((HAL_GetTick() - tickstart) > DFSDM_CKAB_TIMEOUT) { /* Set timeout status */ status = HAL_TIMEOUT; @@ -647,7 +884,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf } } - if(status == HAL_OK) + if (status == HAL_OK) { /* Activate clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE; @@ -661,7 +898,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf } /** - * @brief Clock absence detection callback. + * @brief Clock absence detection callback. * @param hdfsdm_channel DFSDM channel handle. * @retval None */ @@ -669,7 +906,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file */ @@ -688,9 +925,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -699,10 +936,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs { /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - + /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); @@ -731,9 +968,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -743,8 +980,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ - Threshold); - + Threshold); + /* Start short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; } @@ -758,17 +995,17 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; uint32_t channel; - + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ return HAL_ERROR; @@ -777,27 +1014,27 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd { /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + /* Get timeout */ tickstart = HAL_GetTick(); /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0) + while (((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; } } } - + /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); - + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); + /* Return function status */ return HAL_OK; } @@ -815,9 +1052,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -826,10 +1063,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c { /* Stop short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - + /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); } /* Return function status */ return status; @@ -855,9 +1092,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -870,8 +1107,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ - Threshold); - + Threshold); + /* Start short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; } @@ -880,7 +1117,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs } /** - * @brief Short circuit detection callback. + * @brief Short circuit detection callback. * @param hdfsdm_channel DFSDM channel handle. * @retval None */ @@ -888,7 +1125,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_channel); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_ChannelScdCallback could be implemented in the user file */ @@ -907,9 +1144,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -918,10 +1155,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd { /* Stop short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - + /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); + DFSDM1_Filter0->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); /* Disable short circuit detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); @@ -955,9 +1192,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { /* Return error status */ status = HAL_ERROR; @@ -1005,7 +1242,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp */ /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions - * @brief Filter initialization and de-initialization functions + * @brief Filter initialization and de-initialization functions * @verbatim ============================================================================== @@ -1027,7 +1264,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check DFSDM Channel handle */ - if(hdfsdm_filter == NULL) + if (hdfsdm_filter == NULL) { return HAL_ERROR; } @@ -1045,9 +1282,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); /* Check parameters compatibility */ - if((hdfsdm_filter->Instance == DFSDM1_Filter0) && - ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || - (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) + if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && + ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || + (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) { return HAL_ERROR; } @@ -1057,13 +1294,30 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->InjectedChannelsNbr = 1; hdfsdm_filter->InjConvRemaining = 1; hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; - + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; + hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback; + hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback; + hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback; + hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback; + hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback; + + /* Call MSP init function */ + if (hdfsdm_filter->MspInitCallback == NULL) + { + hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; + } + hdfsdm_filter->MspInitCallback(hdfsdm_filter); +#else /* Call MSP init function */ HAL_DFSDM_FilterMspInit(hdfsdm_filter); +#endif /* Set regular parameters */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); - if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) + if (hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST; } @@ -1072,7 +1326,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST); } - if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) + if (hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN; } @@ -1083,14 +1337,14 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Set injected parameters */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL); - if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) + if (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) { assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger)); assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge)); hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger); } - if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) + if (hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN; } @@ -1099,7 +1353,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN); } - if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) + if (hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN; } @@ -1107,25 +1361,25 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); } - + /* Set filter parameters */ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_Pos) | - (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); + ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) | + (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U)); /* Store regular and injected triggers and injected scan mode*/ hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger; hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; - + /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; /* Set DFSDM filter to ready state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; - + return HAL_OK; } @@ -1137,19 +1391,27 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check DFSDM filter handle */ - if(hdfsdm_filter == NULL) + if (hdfsdm_filter == NULL) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Disable the DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + /* Call MSP deinit function */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + if (hdfsdm_filter->MspDeInitCallback == NULL) + { + hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; + } + hdfsdm_filter->MspDeInitCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterMspDeInit(hdfsdm_filter); +#endif /* Set DFSDM filter in reset state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET; @@ -1166,7 +1428,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_FilterMspInit could be implemented in the user file. */ @@ -1181,12 +1443,248 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the function is needed, the HAL_DFSDM_FilterMspDeInit could be implemented in the user file. */ } +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user DFSDM filter callback + * to be used instead of the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, + pDFSDM_Filter_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : + hdfsdm_filter->RegConvCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->RegConvHalfCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : + hdfsdm_filter->InjConvCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->InjConvHalfCpltCallback = pCallback; + break; + case HAL_DFSDM_FILTER_ERROR_CB_ID : + hdfsdm_filter->ErrorCallback = pCallback; + break; + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = pCallback; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = pCallback; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user DFSDM filter callback. + * DFSDM filter callback is redirected to the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID. + * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : + hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback; + break; + case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : + hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback; + break; + case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : + hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback; + break; + case HAL_DFSDM_FILTER_ERROR_CB_ID : + hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback; + break; + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) + { + switch (CallbackID) + { + case HAL_DFSDM_FILTER_MSPINIT_CB_ID : + hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; + break; + case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : + hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; + break; + default : + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Register a user DFSDM filter analog watchdog callback + * to be used instead of the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @param pCallback pointer to the DFSDM filter analog watchdog callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + pDFSDM_Filter_AwdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + hdfsdm_filter->AwdCallback = pCallback; + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user DFSDM filter analog watchdog callback. + * DFSDM filter AWD callback is redirected to the weak predefined callback. + * @param hdfsdm_filter DFSDM filter handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) + { + hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; + } + else + { + /* update the error code */ + hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ + /** * @} */ @@ -1220,30 +1718,30 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h uint32_t ContinuousMode) { HAL_StatusTypeDef status = HAL_OK; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { /* Configure channel and continuous mode for regular conversion */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT); - if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) + if (ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | - DFSDM_FLTCR1_RCONT); + hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)(((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | + DFSDM_FLTCR1_RCONT); } else { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); + hdfsdm_filter->Instance->FLTCR1 |= (uint32_t)((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); } /* Store continuous mode information */ hdfsdm_filter->RegularContMode = ContinuousMode; - } + } else { status = HAL_ERROR; @@ -1268,18 +1766,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { /* Configure channel for injected conversion */ - hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK); + hdfsdm_filter->Instance->FLTJCHGR = (uint32_t)(Channel & DFSDM_LSB_MASK); /* Store number of injected channels */ hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel); /* Update number of injected channels remaining */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } else { @@ -1325,7 +1823,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to start regular conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1338,8 +1836,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Start regular conversion */ DFSDM_RegConvStart(hdfsdm_filter); @@ -1368,8 +1866,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ return HAL_ERROR; @@ -1377,15 +1875,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe else { /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait end of regular conversion */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) + while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1393,18 +1891,22 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe } } /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) + if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) { /* Update error code and call error callback */ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif /* Clear regular overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; } /* Update DFSDM filter state only if not continuous conversion and SW trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; @@ -1428,8 +1930,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1445,7 +1947,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm /** * @brief This function allows to start regular conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1458,12 +1960,12 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Enable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - + /* Start regular conversion */ DFSDM_RegConvStart(hdfsdm_filter); } @@ -1489,8 +1991,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1499,7 +2001,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf { /* Disable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - + /* Stop regular conversion */ DFSDM_RegConvStop(hdfsdm_filter); } @@ -1509,7 +2011,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf /** * @brief This function allows to start regular conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least @@ -1529,42 +2031,42 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ + (Length != 1U)) { status = HAL_ERROR; } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMARegularHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1587,7 +2089,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to start regular conversion in DMA mode and to get * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. @@ -1606,42 +2108,42 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ + (Length != 1U)) { status = HAL_ERROR; } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMARegularHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1675,8 +2177,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1684,7 +2186,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd else { /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) + if (HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1709,19 +2211,22 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of data register for regular channel */ reg = hdfsdm_filter->Instance->FLTRDATAR; - + /* Extract channel and regular conversion value */ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); + /* Regular conversion value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTRDATAR_RDATA; + value = ((int32_t)reg) / 256; /* return regular conversion value */ return value; @@ -1729,7 +2234,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief This function allows to start injected conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1742,8 +2247,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Start injected conversion */ DFSDM_InjConvStart(hdfsdm_filter); @@ -1772,8 +2277,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ return HAL_ERROR; @@ -1781,15 +2286,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe else { /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait end of injected conversions */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) + while ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) { /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1797,11 +2302,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe } } /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) + if ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) { /* Update error code and call error callback */ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif /* Clear injected overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; @@ -1809,18 +2318,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) + if (hdfsdm_filter->InjConvRemaining == 0U) { /* Update DFSDM filter state only if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; } - + /* end of injected sequence, reset the value */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } /* Return function status */ @@ -1842,8 +2351,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1859,7 +2368,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to start injected conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -1872,12 +2381,12 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Enable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - + /* Start injected conversion */ DFSDM_InjConvStart(hdfsdm_filter); } @@ -1903,8 +2412,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -1913,7 +2422,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd { /* Disable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - + /* Stop injected conversion */ DFSDM_InjConvStop(hdfsdm_filter); } @@ -1923,7 +2432,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to start injected conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least @@ -1943,40 +2452,40 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ + (Length > hdfsdm_filter->InjConvRemaining)) { status = HAL_ERROR; } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMAInjectedHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -1999,7 +2508,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * /** * @brief This function allows to start injected conversion in DMA mode and to get * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. @@ -2018,40 +2527,40 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) + if ((pData == NULL) || (Length == 0U)) { status = HAL_ERROR; } /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) + else if ((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) { status = HAL_ERROR; } /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ + (Length > hdfsdm_filter->InjConvRemaining)) { status = HAL_ERROR; } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) + else if ((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ + (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) { status = HAL_ERROR; } /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) + else if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) { /* Set callbacks on DMA handler */ hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ + hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ? \ DFSDM_DMAInjectedHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \ + (uint32_t) pData, Length) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -2085,8 +2594,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) + if ((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ + (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) { /* Return error status */ status = HAL_ERROR; @@ -2094,7 +2603,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h else { /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) + if (HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) { /* Set DFSDM filter in error state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; @@ -2116,22 +2625,25 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of data register for injected channel */ reg = hdfsdm_filter->Instance->FLTJDATAR; - + /* Extract channel and injected conversion value */ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); + /* Injected conversion value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTJDATAR_JDATA; + value = ((int32_t)reg) / 256; /* return regular conversion value */ return value; @@ -2156,10 +2668,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2173,10 +2685,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /* Set thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ - awdParam->HighBreakSignal); + awdParam->HighBreakSignal); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ - awdParam->LowBreakSignal); + awdParam->LowBreakSignal); /* Set channels and interrupt for analog watchdog */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); @@ -2198,10 +2710,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2213,7 +2725,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /* Clear all analog watchdog flags */ hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); - + /* Reset thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); @@ -2240,10 +2752,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2252,7 +2764,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi { /* Set channels for extreme detector */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); } /* Return function status */ return status; @@ -2271,10 +2783,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ + (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) { /* Return error status */ status = HAL_ERROR; @@ -2286,7 +2798,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /* Clear extreme detector values */ reg1 = hdfsdm_filter->Instance->FLTEXMAX; - reg2 = hdfsdm_filter->Instance->FLTEXMIN; + reg2 = hdfsdm_filter->Instance->FLTEXMIN; UNUSED(reg1); /* To avoid GCC warning */ UNUSED(reg2); /* To avoid GCC warning */ } @@ -2304,19 +2816,22 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of extreme detector maximum register */ reg = hdfsdm_filter->Instance->FLTEXMAX; - + /* Extract channel and extreme detector maximum value */ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); + /* Extreme detector maximum value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTEXMAX_EXMAX; + value = ((int32_t)reg) / 256; /* return extreme detector maximum value */ return value; @@ -2332,19 +2847,22 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { - uint32_t reg = 0; - int32_t value = 0; - + uint32_t reg; + int32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); + assert_param(Channel != (void *)0); /* Get value of extreme detector minimum register */ reg = hdfsdm_filter->Instance->FLTEXMIN; - + /* Extract channel and extreme detector minimum value */ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); + /* Extreme detector minimum value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DFSDM_FLTEXMIN_EXMIN; + value = ((int32_t)reg) / 256; /* return extreme detector minimum value */ return value; @@ -2358,15 +2876,15 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter */ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { - uint32_t reg = 0; - uint32_t value = 0; - + uint32_t reg; + uint32_t value; + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Get value of conversion timer register */ reg = hdfsdm_filter->Instance->FLTCNVTIMR; - + /* Extract conversion time value */ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); @@ -2381,9 +2899,13 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil */ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { + /* Get FTLISR and FLTCR2 register values */ + const uint32_t temp_fltisr = hdfsdm_filter->Instance->FLTISR; + const uint32_t temp_fltcr2 = hdfsdm_filter->Instance->FLTCR2; + /* Check if overrun occurs during regular conversion */ - if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0)) + if (((temp_fltisr & DFSDM_FLTISR_ROVRF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_ROVRIE) != 0U)) { /* Clear regular overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; @@ -2392,11 +2914,15 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; /* Call error callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif } /* Check if overrun occurs during injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_JOVRF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_JOVRIE) != 0U)) { /* Clear injected overrun flag */ hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; @@ -2405,18 +2931,26 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; /* Call error callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif } /* Check if end of regular conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_REOCF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U)) { /* Call regular conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); +#endif /* End of conversion if mode is not continuous and software trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { /* Disable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE); @@ -2427,18 +2961,22 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } } /* Check if end of injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_JEOCF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U)) { /* Call injected conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); +#endif /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) + if (hdfsdm_filter->InjConvRemaining == 0U) { /* End of conversion if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { /* Disable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE); @@ -2449,60 +2987,68 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* end of injected sequence, reset the value */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } } /* Check if analog watchdog occurs */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0)) + else if (((temp_fltisr & DFSDM_FLTISR_AWDF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_AWDIE) != 0U)) { - uint32_t reg = 0; - uint32_t threshold = 0; + uint32_t reg; + uint32_t threshold; uint32_t channel = 0; - + /* Get channel and threshold */ reg = hdfsdm_filter->Instance->FLTAWSR; - threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; - if(threshold == DFSDM_AWD_HIGH_THRESHOLD) + threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; + if (threshold == DFSDM_AWD_HIGH_THRESHOLD) { reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; } - while((reg & 1) == 0) + while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U))) { channel++; reg = reg >> 1; } /* Clear analog watchdog flag */ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1 << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ - (1 << channel); + (1UL << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ + (1UL << channel); /* Call analog watchdog callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold); +#else HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold); +#endif } /* Check if clock absence occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0)) + else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ + ((temp_fltisr & DFSDM_FLTISR_CKABF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_CKABIE) != 0U)) { - uint32_t reg = 0; + uint32_t reg; uint32_t channel = 0; - + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); - while(channel < DFSDM1_CHANNEL_NUMBER) + while (channel < DFSDM1_CHANNEL_NUMBER) { /* Check if flag is set and corresponding channel is enabled */ - if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL)) + if (((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL)) { /* Check clock absence has been enabled for this channel */ - if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) + if ((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) { /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); + hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Call clock absence callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]); +#else HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); +#endif } } channel++; @@ -2510,31 +3056,35 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } } /* Check if short circuit detection occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0)) + else if ((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ + ((temp_fltisr & DFSDM_FLTISR_SCDF) != 0U) && \ + ((temp_fltcr2 & DFSDM_FLTCR2_SCDIE) != 0U)) { - uint32_t reg = 0; + uint32_t reg; uint32_t channel = 0; - + /* Get channel */ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); - while((reg & 1) == 0) + while (((reg & 1U) == 0U) && (channel < (DFSDM1_CHANNEL_NUMBER - 1U))) { channel++; reg = reg >> 1; } - + /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); + hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); /* Call short circuit detection callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]); +#else HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); +#endif } } /** - * @brief Regular conversion complete callback. + * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. * @param hdfsdm_filter DFSDM filter handle. @@ -2544,14 +3094,14 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file. */ } /** - * @brief Half regular conversion complete callback. + * @brief Half regular conversion complete callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -2559,14 +3109,14 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file. */ } /** - * @brief Injected conversion complete callback. + * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. * @param hdfsdm_filter DFSDM filter handle. @@ -2576,14 +3126,14 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file. */ } /** - * @brief Half injected conversion complete callback. + * @brief Half injected conversion complete callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -2591,14 +3141,14 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file. */ } /** - * @brief Filter analog watchdog callback. + * @brief Filter analog watchdog callback. * @param hdfsdm_filter DFSDM filter handle. * @param Channel Corresponding channel. * @param Threshold Low or high threshold has been reached. @@ -2611,14 +3161,14 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte UNUSED(hdfsdm_filter); UNUSED(Channel); UNUSED(Threshold); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. */ } /** - * @brief Error callback. + * @brief Error callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -2626,7 +3176,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil { /* Prevent unused argument(s) compilation warning */ UNUSED(hdfsdm_filter); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterErrorCallback could be implemented in the user file. */ @@ -2686,76 +3236,96 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) */ /** - * @brief DMA half transfer complete callback for regular conversion. + * @brief DMA half transfer complete callback for regular conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call regular half conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA transfer complete callback for regular conversion. + * @brief DMA transfer complete callback for regular conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call regular conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA half transfer complete callback for injected conversion. + * @brief DMA half transfer complete callback for injected conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call injected half conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA transfer complete callback for injected conversion. + * @brief DMA transfer complete callback for injected conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call injected conversion complete callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); +#endif } /** - * @brief DMA error callback. + * @brief DMA error callback. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; + DFSDM_Filter_HandleTypeDef *hdfsdm_filter = (DFSDM_Filter_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update error code */ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA; /* Call error callback */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + hdfsdm_filter->ErrorCallback(hdfsdm_filter); +#else HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); +#endif } /** @@ -2767,16 +3337,16 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) { uint32_t nbChannels = 0; uint32_t tmp; - + /* Get the number of channels from bitfield */ - tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); - while(tmp != 0) + tmp = (uint32_t)(Channels & DFSDM_LSB_MASK); + while (tmp != 0U) { - if((tmp & 1) != 0) + if ((tmp & 1U) != 0U) { nbChannels++; } - tmp = (uint32_t) (tmp >> 1); + tmp = (uint32_t)(tmp >> 1); } return nbChannels; } @@ -2786,47 +3356,51 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) * @param Instance DFSDM channel instance. * @retval Channel number. */ -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) { - uint32_t channel = 0xFF; - + uint32_t channel; + /* Get channel from instance */ - if(Instance == DFSDM1_Channel0) + if (Instance == DFSDM1_Channel0) { channel = 0; } - else if(Instance == DFSDM1_Channel1) + else if (Instance == DFSDM1_Channel1) { channel = 1; } - else if(Instance == DFSDM1_Channel2) + else if (Instance == DFSDM1_Channel2) { channel = 2; } - else if(Instance == DFSDM1_Channel3) + else if (Instance == DFSDM1_Channel3) { channel = 3; } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if(Instance == DFSDM1_Channel4) + else if (Instance == DFSDM1_Channel4) { channel = 4; } - else if(Instance == DFSDM1_Channel5) + else if (Instance == DFSDM1_Channel5) { channel = 5; } - else if(Instance == DFSDM1_Channel6) + else if (Instance == DFSDM1_Channel6) { channel = 6; } - else if(Instance == DFSDM1_Channel7) + else if (Instance == DFSDM1_Channel7) { channel = 7; } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + else + { + channel = 0; + } return channel; } @@ -2836,10 +3410,10 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check regular trigger */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) { /* Software start of regular conversion */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; @@ -2848,28 +3422,28 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + /* Set RSYNC bit in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) + if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; } /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } } /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ - HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; + HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; } /** @@ -2877,35 +3451,35 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) + if (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); } /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) + if (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; } /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; } - + /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; } /** @@ -2913,10 +3487,10 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Check injected trigger */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) { /* Software start of injected conversion */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; @@ -2925,8 +3499,8 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) + + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { /* Set JSYNC bit in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC; @@ -2936,13 +3510,13 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; } - + /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; } @@ -2957,39 +3531,43 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) * @param hdfsdm_filter DFSDM filter handle. * @retval None */ -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) +static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) + if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC); } - else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) + else if (hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) { /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN); } + else + { + /* Nothing to do */ + } /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) + if ((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ + (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) { hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; } /* Update remaining injected conversions */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; + hdfsdm_filter->InjectedChannelsNbr : 1U; /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; + HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h index 17de1fc91e..54d7e2bbc8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DFSDM_H -#define __STM32L4xx_HAL_DFSDM_H +#ifndef STM32L4xx_HAL_DFSDM_H +#define STM32L4xx_HAL_DFSDM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ @@ -55,26 +39,26 @@ /** @addtogroup DFSDM * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DFSDM_Exported_Types DFSDM Exported Types * @{ */ -/** - * @brief HAL DFSDM Channel states definition - */ +/** + * @brief HAL DFSDM Channel states definition + */ typedef enum { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ -}HAL_DFSDM_Channel_StateTypeDef; +} HAL_DFSDM_Channel_StateTypeDef; -/** - * @brief DFSDM channel output clock structure definition - */ +/** + * @brief DFSDM channel output clock structure definition + */ typedef struct { FunctionalState Activation; /*!< Output clock enable/disable */ @@ -82,11 +66,11 @@ typedef struct This parameter can be a value of @ref DFSDM_Channel_OuputClock */ uint32_t Divider; /*!< Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ -}DFSDM_Channel_OutputClockTypeDef; +} DFSDM_Channel_OutputClockTypeDef; -/** - * @brief DFSDM channel input structure definition - */ +/** + * @brief DFSDM channel input structure definition + */ typedef struct { uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. @@ -98,33 +82,33 @@ typedef struct This parameter can be a value of @ref DFSDM_Channel_DataPacking */ uint32_t Pins; /*!< Input pins are taken from same or following channel. This parameter can be a value of @ref DFSDM_Channel_InputPins */ -}DFSDM_Channel_InputTypeDef; +} DFSDM_Channel_InputTypeDef; -/** - * @brief DFSDM channel serial interface structure definition - */ +/** + * @brief DFSDM channel serial interface structure definition + */ typedef struct { uint32_t Type; /*!< SPI or Manchester modes. This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). This parameter can be a value of @ref DFSDM_Channel_SpiClock */ -}DFSDM_Channel_SerialInterfaceTypeDef; +} DFSDM_Channel_SerialInterfaceTypeDef; -/** - * @brief DFSDM channel analog watchdog structure definition - */ +/** + * @brief DFSDM channel analog watchdog structure definition + */ typedef struct { uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ -}DFSDM_Channel_AwdTypeDef; +} DFSDM_Channel_AwdTypeDef; -/** - * @brief DFSDM channel init structure definition - */ +/** + * @brief DFSDM channel init structure definition + */ typedef struct { DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ @@ -135,21 +119,49 @@ typedef struct This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ uint32_t RightBitShift; /*!< DFSDM channel right bit shift. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ -}DFSDM_Channel_InitTypeDef; +} DFSDM_Channel_InitTypeDef; -/** - * @brief DFSDM channel handle structure definition - */ +/** + * @brief DFSDM channel handle structure definition + */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +typedef struct __DFSDM_Channel_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ { DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ -}DFSDM_Channel_HandleTypeDef; +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ + void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ + void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ + void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ +#endif +} DFSDM_Channel_HandleTypeDef; -/** - * @brief HAL DFSDM Filter states definition - */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief DFSDM channel callback ID enumeration definition + */ +typedef enum +{ + HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ + HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ + HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ + HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ +} HAL_DFSDM_Channel_CallbackIDTypeDef; + +/** + * @brief DFSDM channel callback pointer definition + */ +typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +#endif + +/** + * @brief HAL DFSDM Filter states definition + */ typedef enum { HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ @@ -158,22 +170,22 @@ typedef enum HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ -}HAL_DFSDM_Filter_StateTypeDef; +} HAL_DFSDM_Filter_StateTypeDef; -/** - * @brief DFSDM filter regular conversion parameters structure definition - */ +/** + * @brief DFSDM filter regular conversion parameters structure definition + */ typedef struct { uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. This parameter can be a value of @ref DFSDM_Filter_Trigger */ FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ -}DFSDM_Filter_RegularParamTypeDef; +} DFSDM_Filter_RegularParamTypeDef; -/** - * @brief DFSDM filter injected conversion parameters structure definition - */ +/** + * @brief DFSDM filter injected conversion parameters structure definition + */ typedef struct { uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. @@ -184,11 +196,11 @@ typedef struct This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ -}DFSDM_Filter_InjectedParamTypeDef; +} DFSDM_Filter_InjectedParamTypeDef; -/** - * @brief DFSDM filter parameters structure definition - */ +/** + * @brief DFSDM filter parameters structure definition + */ typedef struct { uint32_t SincOrder; /*!< Sinc filter order. @@ -197,22 +209,26 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ uint32_t IntOversampling; /*!< Integrator oversampling ratio. This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ -}DFSDM_Filter_FilterParamTypeDef; +} DFSDM_Filter_FilterParamTypeDef; -/** - * @brief DFSDM filter init structure definition - */ +/** + * @brief DFSDM filter init structure definition + */ typedef struct { DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ -}DFSDM_Filter_InitTypeDef; +} DFSDM_Filter_InitTypeDef; -/** - * @brief DFSDM filter handle structure definition - */ +/** + * @brief DFSDM filter handle structure definition + */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +typedef struct __DFSDM_Filter_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ { DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ @@ -226,12 +242,23 @@ typedef struct uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ uint32_t InjConvRemaining; /*!< Injected conversions remaining */ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ - uint32_t ErrorCode; /*!< DFSDM filter error code */ -}DFSDM_Filter_HandleTypeDef; + uint32_t ErrorCode; /*!< DFSDM filter error code */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) + void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ + void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ + void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ + void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ + void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ + void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ + void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ + void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ +#endif +} DFSDM_Filter_HandleTypeDef; -/** - * @brief DFSDM filter analog watchdog parameters structure definition - */ +/** + * @brief DFSDM filter analog watchdog parameters structure definition + */ typedef struct { uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. @@ -246,11 +273,33 @@ typedef struct This parameter can be a values combination of @ref DFSDM_BreakSignals */ uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. This parameter can be a values combination of @ref DFSDM_BreakSignals */ -}DFSDM_Filter_AwdParamTypeDef; +} DFSDM_Filter_AwdParamTypeDef; + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/** + * @brief DFSDM filter callback ID enumeration definition + */ +typedef enum +{ + HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ + HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ + HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ + HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ + HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ + HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ + HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ +} HAL_DFSDM_Filter_CallbackIDTypeDef; + +/** + * @brief DFSDM filter callback pointer definition + */ +typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); +#endif /** * @} - */ + */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -261,7 +310,7 @@ typedef struct /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection * @{ */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ /** * @} @@ -270,7 +319,7 @@ typedef struct /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer * @{ */ -#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ +#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -284,7 +333,7 @@ typedef struct /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing * @{ */ -#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ +#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ /** @@ -294,7 +343,7 @@ typedef struct /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins * @{ */ -#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ +#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ /** * @} @@ -303,7 +352,7 @@ typedef struct /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type * @{ */ -#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ +#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ @@ -314,7 +363,7 @@ typedef struct /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection * @{ */ -#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ +#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ @@ -325,7 +374,7 @@ typedef struct /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order * @{ */ -#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ +#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ @@ -336,9 +385,9 @@ typedef struct /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger * @{ */ -#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ -#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ -#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ +#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ +#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ +#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ /** * @} */ @@ -347,7 +396,7 @@ typedef struct * @{ */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ @@ -355,7 +404,7 @@ typedef struct #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ @@ -371,7 +420,7 @@ typedef struct #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ #else -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ @@ -400,7 +449,7 @@ typedef struct /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order * @{ */ -#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ +#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ @@ -413,7 +462,7 @@ typedef struct /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source * @{ */ -#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ +#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ /** * @} @@ -421,11 +470,14 @@ typedef struct /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code * @{ - */ -#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ -#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ -#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ + */ +#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ +#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ +#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ +#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ +#endif /** * @} */ @@ -433,11 +485,11 @@ typedef struct /** @defgroup DFSDM_BreakSignals DFSDM break signals * @{ */ -#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ -#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ -#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ -#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ -#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ +#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ +#define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ +#define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ +#define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ +#define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ /** * @} */ @@ -451,22 +503,22 @@ typedef struct - in 16-bit MSB the channel number is set e.g. for channel 5 definition: - the channel mask is 0x00000020 (bit 5 is set) - - the channel number 5 is 0x00050000 + - the channel number 5 is 0x00050000 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) -#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) -#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) -#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) +#define DFSDM_CHANNEL_0 0x00000001U +#define DFSDM_CHANNEL_1 0x00010002U +#define DFSDM_CHANNEL_2 0x00020004U +#define DFSDM_CHANNEL_3 0x00030008U #else -#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) -#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) -#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) -#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) -#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) -#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) -#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) -#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) +#define DFSDM_CHANNEL_0 0x00000001U +#define DFSDM_CHANNEL_1 0x00010002U +#define DFSDM_CHANNEL_2 0x00020004U +#define DFSDM_CHANNEL_3 0x00030008U +#define DFSDM_CHANNEL_4 0x00040010U +#define DFSDM_CHANNEL_5 0x00050020U +#define DFSDM_CHANNEL_6 0x00060040U +#define DFSDM_CHANNEL_7 0x00070080U #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /** * @} @@ -475,8 +527,8 @@ typedef struct /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode * @{ */ -#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ -#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ +#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ +#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ /** * @} */ @@ -484,15 +536,15 @@ typedef struct /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold * @{ */ -#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ -#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ +#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ +#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ /** * @} */ /** * @} - */ + */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ @@ -504,13 +556,29 @@ typedef struct * @param __HANDLE__ DFSDM channel handle. * @retval None */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) +#endif /** @brief Reset DFSDM filter handle state. * @param __HANDLE__ DFSDM filter handle. * @retval None */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) +#endif /** * @} @@ -535,6 +603,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/* Channel callbacks register/unregister functions ****************************/ +HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, + pDFSDM_Channel_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, + HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); +#endif /** * @} */ @@ -582,6 +659,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); + +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) +/* Filter callbacks register/unregister functions ****************************/ +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, + pDFSDM_Filter_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, + pDFSDM_Filter_AwdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +#endif /** * @} */ @@ -618,15 +707,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef* awdParam); + DFSDM_Filter_AwdParamTypeDef *awdParam); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); @@ -665,7 +754,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe */ #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) -#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) +#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -676,8 +765,8 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/* STM32L496xx || STM32L4A6xx || */ +/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) @@ -695,10 +784,10 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) -#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) +#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) -#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) -#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) +#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) +#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ @@ -747,8 +836,8 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) -#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) -#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) +#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) +#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) @@ -758,7 +847,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_2) || \ ((CHANNEL) == DFSDM_CHANNEL_3)) -#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) +#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) #else #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \ @@ -768,31 +857,31 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CHANNEL) == DFSDM_CHANNEL_5) || \ ((CHANNEL) == DFSDM_CHANNEL_6) || \ ((CHANNEL) == DFSDM_CHANNEL_7)) -#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) +#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) /** * @} - */ + */ /* End of private macros -----------------------------------------------------*/ /** * @} - */ + */ /** * @} */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ +/* STM32L496xx || STM32L4A6xx || */ +/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_DFSDM_H */ +#endif /* STM32L4xx_HAL_DFSDM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c index 2304f97304..a96a941c95 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm_ex.c * @author MCD Application Team - * @brief DFSDM Extended HAL module driver. + * @brief DFSDM Extended HAL module driver. * This file provides firmware functions to manage the following * functionality of the DFSDM Peripheral Controller: * + Set and get pulses skipping on channel. @@ -10,32 +10,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -88,12 +72,12 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue) { HAL_StatusTypeDef status = HAL_OK; - + /* Check pulses value */ assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue)); - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) { /* Set new value of pulses skipping */ hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP); @@ -114,9 +98,9 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeD HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue) { HAL_StatusTypeDef status = HAL_OK; - + /* Check DFSDM channel state */ - if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) { /* Get value of remaining pulses to be skipped */ *PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h index ec26719449..564639f7bc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h @@ -6,46 +6,30 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DFSDM_EX_H -#define __STM32L4xx_HAL_DFSDM_EX_H +#ifndef STM32L4xx_HAL_DFSDM_EX_H +#define STM32L4xx_HAL_DFSDM_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -68,15 +52,15 @@ */ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue); -HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t* PulsesValue); +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue); /** * @} - */ + */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ @@ -88,11 +72,11 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD /** * @} - */ + */ /** * @} - */ + */ /** * @} @@ -104,6 +88,6 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD } #endif -#endif /* __STM32L4xx_HAL_DFSDM_EX_H */ +#endif /* STM32L4xx_HAL_DFSDM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c index 9963ae866e..6c9bf7220e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c @@ -3,8 +3,8 @@ * @file stm32l4xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions @@ -37,27 +37,27 @@ *** Polling mode IO operation *** ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. *** Interrupt mode IO operation *** =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** ============================================= - [..] + [..] Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. @@ -75,29 +75,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -162,13 +146,13 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + uint32_t tmp; /* Check the DMA handle allocation */ if(hdma == NULL) @@ -192,13 +176,13 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; hdma->DmaBaseAddress = DMA2; } @@ -222,7 +206,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; - #if defined(DMAMUX1) /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask @@ -241,7 +224,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask @@ -271,18 +254,18 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) if (DMA1 == hdma->DmaBaseAddress) { /* Reset request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); /* Configure request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); } else /* DMA2 */ { /* Reset request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); + DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); /* Configure request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); } } @@ -290,17 +273,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ /* STM32L496xx || STM32L4A6xx */ - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; + hdma->State = HAL_DMA_STATE_READY; /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; @@ -310,7 +287,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitialize the DMA peripheral. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -333,21 +310,21 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; hdma->DmaBaseAddress = DMA2; } /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; + hdma->Instance->CCR = 0U; /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #if !defined (DMAMUX1) @@ -355,12 +332,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) if (DMA1 == hdma->DmaBaseAddress) { /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); } else { /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); } #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ @@ -374,13 +351,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) DMA_CalcDMAMUXChannelBaseAndMask(hdma); /* Reset the DMAMUX channel that corresponds to the DMA channel */ - hdma->DMAmuxChannel->CCR = 0; + hdma->DMAmuxChannel->CCR = 0U; /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Reset Request generator parameters if any */ - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask @@ -393,13 +370,19 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } - + hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; #endif /* DMAMUX1 */ + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -437,11 +420,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Start the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -480,11 +463,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -556,7 +539,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Abort the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -564,54 +547,61 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; - /* Check the DMA peripheral handle */ - if(NULL == hdma) + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_ERROR; } - - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - -#if defined(DMAMUX1) - /* disable the DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; -#endif /* DMAMUX1 */ - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - -#if defined(DMAMUX1) - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) + else { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ - /* disable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } +#if defined(DMAMUX1) + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; +#endif /* DMAMUX1 */ + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + +#if defined(DMAMUX1) + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } #endif /* DMAMUX1 */ - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - return status; + return status; + } } /** * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ @@ -639,7 +629,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; @@ -656,7 +646,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) #else /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #endif /* DMAMUX1 */ /* Change the DMA state */ @@ -676,16 +666,16 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { uint32_t temp; - uint32_t tickstart = 0; + uint32_t tickstart; if(HAL_DMA_STATE_BUSY != hdma->State) { @@ -696,7 +686,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level } /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; @@ -706,25 +696,25 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); } else { /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); } /* Get tick */ tickstart = HAL_GetTick(); - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + while((hdma->DmaBaseAddress->ISR & temp) == 0U) { - if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) + if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; @@ -740,7 +730,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; @@ -788,7 +778,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ @@ -797,7 +787,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level else { /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); } /* Process unlocked */ @@ -808,7 +798,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /** * @brief Handle DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ @@ -818,21 +808,21 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ - if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ - if(hdma->XferHalfCpltCallback != NULL) + if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); @@ -840,18 +830,20 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Transfer Complete Interrupt management ***********************************/ - else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ /* Disable the transfer complete and error interrupt */ + /* if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU)); /* Process Unlocked */ __HAL_UNLOCK(hdma); @@ -864,7 +856,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Transfer Error Interrupt management **************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -872,7 +864,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; @@ -889,16 +881,20 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->XferErrorCallback(hdma); } } + else + { + /* Nothing To Do */ + } return; } /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -947,9 +943,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1026,8 +1022,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca */ /** - * @brief Return the DMA hande state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief Return the DMA handle state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ @@ -1062,11 +1058,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -1083,12 +1079,12 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t #endif /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ @@ -1097,7 +1093,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ @@ -1111,37 +1107,36 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t #if defined(DMAMUX1) /** - * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { - uint32_t channel_number = 0; - DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; + uint32_t channel_number; /* check if instance is not outside the DMA channel range */ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) { /* DMA1 */ - DMAMUX1_ChannelBase = DMAMUX1_Channel0; + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); } else { /* DMA2 */ - DMAMUX1_ChannelBase = DMAMUX1_Channel7; + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); } - channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; - hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); + + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - hdma->DMAmuxChannelStatusMask = 1U << channel_number; + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1CU); } /** * @brief Updates the DMA handle with the DMAMUX request generator params - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval None */ @@ -1154,7 +1149,8 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); } #endif /* DMAMUX1 */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h index c11a47ccae..3b5d8e0263 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_H -#define __STM32L4xx_HAL_DMA_H +#ifndef STM32L4xx_HAL_DMA_H +#define STM32L4xx_HAL_DMA_H #ifdef __cplusplus extern "C" { @@ -95,10 +79,10 @@ typedef struct */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ }HAL_DMA_StateTypeDef; /** @@ -106,8 +90,8 @@ typedef enum */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; @@ -116,12 +100,11 @@ typedef enum */ typedef enum { - HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ - + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ }HAL_DMA_CallbackIDTypeDef; /** @@ -129,42 +112,42 @@ typedef enum */ typedef struct __DMA_HandleTypeDef { - DMA_Channel_TypeDef *Instance; /*!< Register base address */ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ - DMA_InitTypeDef Init; /*!< DMA communication parameters */ + DMA_InitTypeDef Init; /*!< DMA communication parameters */ - HAL_LockTypeDef Lock; /*!< DMA locking object */ + HAL_LockTypeDef Lock; /*!< DMA locking object */ - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - void *Parent; /*!< Parent object state */ + void *Parent; /*!< Parent object state */ - void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - __IO uint32_t ErrorCode; /*!< DMA Error code */ + __IO uint32_t ErrorCode; /*!< DMA Error code */ - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - uint32_t ChannelIndex; /*!< DMA Channel Index */ + uint32_t ChannelIndex; /*!< DMA Channel Index */ #if defined(DMAMUX1) - DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ - DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ - uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ - DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ - DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ - uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ #endif /* DMAMUX1 */ @@ -182,13 +165,13 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ -#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ -#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ /** * @} @@ -199,14 +182,14 @@ typedef struct __DMA_HandleTypeDef */ #if !defined (DMAMUX1) -#define DMA_REQUEST_0 ((uint32_t)0x00000000) -#define DMA_REQUEST_1 ((uint32_t)0x00000001) -#define DMA_REQUEST_2 ((uint32_t)0x00000002) -#define DMA_REQUEST_3 ((uint32_t)0x00000003) -#define DMA_REQUEST_4 ((uint32_t)0x00000004) -#define DMA_REQUEST_5 ((uint32_t)0x00000005) -#define DMA_REQUEST_6 ((uint32_t)0x00000006) -#define DMA_REQUEST_7 ((uint32_t)0x00000007) +#define DMA_REQUEST_0 0U +#define DMA_REQUEST_1 1U +#define DMA_REQUEST_2 2U +#define DMA_REQUEST_3 3U +#define DMA_REQUEST_4 4U +#define DMA_REQUEST_5 5U +#define DMA_REQUEST_6 6U +#define DMA_REQUEST_7 7U #endif @@ -339,9 +322,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** * @} */ @@ -349,8 +332,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ +#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -358,8 +341,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ +#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -367,9 +350,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** * @} */ @@ -377,9 +360,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** * @} */ @@ -387,8 +370,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_mode DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ /** * @} */ @@ -396,10 +379,10 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Priority_level DMA Priority level * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ /** * @} */ @@ -408,9 +391,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE /** * @} */ @@ -418,34 +401,34 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL1 DMA_ISR_GIF1 +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 +#define DMA_FLAG_GL2 DMA_ISR_GIF2 +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 +#define DMA_FLAG_GL3 DMA_ISR_GIF3 +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 +#define DMA_FLAG_GL4 DMA_ISR_GIF4 +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 +#define DMA_FLAG_GL5 DMA_ISR_GIF5 +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 +#define DMA_FLAG_GL6 DMA_ISR_GIF6 +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 +#define DMA_FLAG_GL7 DMA_ISR_GIF7 +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /** * @} */ @@ -460,21 +443,21 @@ typedef struct __DMA_HandleTypeDef */ /** @brief Reset DMA handle state. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) @@ -484,7 +467,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ @@ -505,7 +488,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -525,7 +508,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -545,7 +528,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ @@ -565,8 +548,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -580,8 +563,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag @@ -595,8 +578,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -607,8 +590,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -619,8 +602,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Check whether the specified DMA Channel interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -631,7 +614,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the number of remaining data units in the current DMA Channel transfer. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) @@ -701,7 +684,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) @@ -761,6 +744,6 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); } #endif -#endif /* __STM32L4xx_HAL_DMA_H */ +#endif /* STM32L4xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c index d5088c5e7b..1a836d0ab9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c @@ -3,133 +3,168 @@ * @file stm32l4xx_hal_dma2d.c * @author MCD Application Team * @brief DMA2D HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions * - @verbatim + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - (#) Program the required configuration through the following parameters: - the transfer mode, the output color mode and the output offset using + (#) Program the required configuration through the following parameters: + the transfer mode, the output color mode and the output offset using HAL_DMA2D_Init() function. - (#) Program the required configuration through the following parameters: + (#) Program the required configuration through the following parameters: the input color mode, the input color, the input alpha value, the alpha mode, - the red/blue swap mode, the inverted alpha mode and the input offset using + the red/blue swap mode, the inverted alpha mode and the input offset using HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. - + *** Polling mode IO operation *** - ================================= - [..] - (#) Configure pdata parameter (explained hereafter), destination and data length - and enable the transfer using HAL_DMA2D_Start(). + ================================= + [..] + (#) Configure pdata parameter (explained hereafter), destination and data length + and enable the transfer using HAL_DMA2D_Start(). (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage user can specify the value of timeout according to his end application. - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (#) Configure pdata parameter, destination and data length and enable - the transfer using HAL_DMA2D_Start_IT(). + [..] + (#) Configure pdata parameter, destination and data length and enable + the transfer using HAL_DMA2D_Start_IT(). (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. - (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback (member - of DMA2D handle structure). - (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback - XferErrorCallback. + (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback (member + of DMA2D handle structure). + (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback + XferErrorCallback. -@- In Register-to-Memory transfer mode, pdata parameter is the register color, in Memory-to-memory or Memory-to-Memory with pixel format conversion pdata is the source address. - -@- Configure the foreground source address, the background source address, - the destination and data length then Enable the transfer using + -@- Configure the foreground source address, the background source address, + the destination and data length then Enable the transfer using HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() in interrupt mode. - + -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions are used if the memory to memory with blending transfer mode is selected. - + (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent(). - - (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two + + (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or - HAL_DMA2D_DisableDeadTime(). - + HAL_DMA2D_DisableDeadTime(). + (#) The transfer can be suspended, resumed and aborted using the following functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). - + (#) The CLUT loading can be suspended, resumed and aborted using the following - functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), - HAL_DMA2D_CLUTLoading_Abort(). - - (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). - - (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). + functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), + HAL_DMA2D_CLUTLoading_Abort(). + + (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). + + (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). *** DMA2D HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DMA2D HAL driver : - + (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. - (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. - - [..] + (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + + (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Exception as well for Transfer Completion and Transfer Error callbacks that are not defined + as weak (surcharged) functions. They must be defined by the user to be resorted to. + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit + or @ref HAL_DMA2D_Init function. + + When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" #ifdef HAL_DMA2D_MODULE_ENABLED - -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined (DMA2D) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -145,42 +180,12 @@ /** @defgroup DMA2D_Private_Constants DMA2D Private Constants * @{ */ - -/** @defgroup DMA2D_TimeOut DMA2D Time Out + +/** @defgroup DMA2D_TimeOut DMA2D Time Out * @{ - */ -#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */ -#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */ -/** - * @} */ - -/** @defgroup DMA2D_Shifts DMA2D Shifts - * @{ - */ -#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */ -#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */ - -#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */ -#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */ - -#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */ -#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */ -#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */ - -#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */ -#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */ -#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */ - -#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */ - -#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */ -#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */ - -#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */ -#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */ - -#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */ +#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */ +#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */ /** * @} */ @@ -210,27 +215,27 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DMA2D - (+) De-initialize the DMA2D + (+) De-initialize the DMA2D @endverbatim * @{ */ - + /** * @brief Initialize the DMA2D according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) -{ +{ /* Check the DMA2D peripheral state */ if(hdma2d == NULL) { @@ -242,11 +247,30 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap)); +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode)); +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap)); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + if (hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + if(hdma2d->MspInitCallback == NULL) + { + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; + } + + /* Init the low level hardware */ + hdma2d->MspInitCallback(hdma2d); + } +#else if(hdma2d->State == HAL_DMA2D_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -254,30 +278,30 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /* Init the low level hardware */ HAL_DMA2D_MspInit(hdma2d); } - +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + hdma2d->State = HAL_DMA2D_STATE_BUSY; /* DMA2D CR register configuration -------------------------------------------*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode); #else MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); #else MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ + MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); - /* DMA2D OOR register configuration ------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); - - /* DMA2D OPFCCR RBS and AI fields setting */ - MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), \ - ((hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI)|(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS))); /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; @@ -291,20 +315,20 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /** * @brief Deinitializes the DMA2D peripheral registers to their default reset * values. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { - + /* Check the DMA2D peripheral state */ if(hdma2d == NULL) { return HAL_ERROR; } - + /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) @@ -314,7 +338,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) { - /* Issue when aborting DMA2D transfer */ + /* Issue when aborting DMA2D transfer */ return HAL_ERROR; } } @@ -322,10 +346,10 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { /* Abort background CLUT loading if any */ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) - { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK) { - /* Issue when aborting background CLUT loading */ + /* Issue when aborting background CLUT loading */ return HAL_ERROR; } } @@ -334,43 +358,55 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Abort foreground CLUT loading if any */ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK) + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK) { - /* Issue when aborting foreground CLUT loading */ + /* Issue when aborting foreground CLUT loading */ return HAL_ERROR; - } + } } } } } - - /* Reset DMA2D control registers*/ - hdma2d->Instance->CR = 0; - hdma2d->Instance->IFCR = 0x3F; - hdma2d->Instance->FGOR = 0; - hdma2d->Instance->BGOR = 0; - hdma2d->Instance->FGPFCCR = 0; - hdma2d->Instance->BGPFCCR = 0; - hdma2d->Instance->OPFCCR = 0; + /* Reset DMA2D control registers*/ + hdma2d->Instance->CR = 0U; + hdma2d->Instance->IFCR = 0x3FU; + hdma2d->Instance->FGOR = 0U; + hdma2d->Instance->BGOR = 0U; + hdma2d->Instance->FGPFCCR = 0U; + hdma2d->Instance->BGPFCCR = 0U; + hdma2d->Instance->OPFCCR = 0U; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + + if(hdma2d->MspDeInitCallback == NULL) + { + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; + } + + /* DeInit the low level hardware */ + hdma2d->MspDeInitCallback(hdma2d); + +#else /* Carry on with de-initialization of low level hardware */ HAL_DMA2D_MspDeInit(hdma2d); - +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - + /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hdma2d); - + return HAL_OK; } /** * @brief Initializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -386,7 +422,7 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief DeInitializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -400,57 +436,248 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) */ } +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DMA2D Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdma2d); + + if(HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = pCallback; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = pCallback; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = pCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = pCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} + +/** + * @brief Unregister a DMA2D Callback + * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma2d); + + if(HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = NULL; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = NULL; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure the pdata, destination address and data size then + (+) Configure the pdata, destination address and data size then start the DMA2D transfer. - (+) Configure the source for foreground and background, destination address + (+) Configure the source for foreground and background, destination address and data size then start a MultiBuffer DMA2D transfer. - (+) Configure the pdata, destination address and data size then + (+) Configure the pdata, destination address and data size then start the DMA2D transfer with interrupt. - (+) Configure the source for foreground and background, destination address + (+) Configure the source for foreground and background, destination address and data size then start a MultiBuffer DMA2D transfer with interrupt. (+) Abort DMA2D transfer. (+) Suspend DMA2D transfer. - (+) Resume DMA2D transfer. - (+) Enable CLUT transfer. + (+) Resume DMA2D transfer. + (+) Enable CLUT transfer. (+) Configure CLUT loading then start transfer in polling mode. (+) Configure CLUT loading then start transfer in interrupt mode. (+) Abort DMA2D CLUT loading. (+) Suspend DMA2D CLUT loading. - (+) Resume DMA2D CLUT loading. + (+) Resume DMA2D CLUT loading. (+) Poll for transfer complete. (+) handle DMA2D interrupt request. (+) Transfer watermark callback. (+) CLUT Transfer Complete callback. - - + + @endverbatim * @{ */ /** * @brief Start the DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if - * Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -458,13 +685,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); assert_param(IS_DMA2D_PIXEL(Width)); - + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - + /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); @@ -476,15 +703,15 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /** * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if - * the Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * the Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -513,26 +740,26 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata /** * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - + assert_param(IS_DMA2D_PIXEL(Width)); + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure DMA2D Stream source2 address */ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); @@ -548,13 +775,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /** * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -562,22 +789,22 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); assert_param(IS_DMA2D_PIXEL(Width)); - + /* Process locked */ __HAL_LOCK(hdma2d); /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - + /* Configure DMA2D Stream source2 address */ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); /* Configure the source, destination address and the data size */ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - + /* Enable the transfer complete, transfer error and configuration error interrupts */ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); - + /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -586,66 +813,66 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /** * @brief Abort the DMA2D Transfer. - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Abort the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no - effect on START bitvalue). */ + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue) */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively disabled */ - while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } } /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); + __HAL_UNLOCK(hdma2d); return HAL_OK; } /** * @brief Suspend the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Suspend the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); @@ -653,29 +880,28 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively suspended */ - while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ - && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)) + while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + return HAL_TIMEOUT; } } - + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) - { + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; } else { - /* Make sure SUSP bit is cleared since it is meaningless + /* Make sure SUSP bit is cleared since it is meaningless when no tranfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); } @@ -685,8 +911,8 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /** * @brief Resume the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) @@ -700,9 +926,9 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /* Resume the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ - CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); return HAL_OK; } @@ -710,25 +936,25 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /** * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - if(LayerIdx == 0) + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Enable the background CLUT loading */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -736,47 +962,47 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay else { /* Enable the foreground CLUT loading */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - + return HAL_OK; } /** * @brief Start DMA2D CLUT Loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -786,54 +1012,54 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT { /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - + return HAL_OK; } /** * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); - + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -843,42 +1069,40 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC { /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); - + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } - + return HAL_OK; } /** * @brief Abort the DMA2D CLUT loading. - * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - uint32_t tickstart = 0; - __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */ - + uint32_t tickstart; + const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Abort the CLUT loading */ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); - - /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == 1) + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); } @@ -886,31 +1110,31 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 /* Get tick */ tickstart = HAL_GetTick(); - - /* Check if the CLUT loading is aborted */ - while((*reg & mask) != RESET) + + /* Check if the CLUT loading is aborted */ + while((*reg & DMA2D_BGPFCCR_START) != 0U) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } } /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); - + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma2d); @@ -919,98 +1143,104 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 /** * @brief Suspend the DMA2D CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - uint32_t tickstart = 0; - __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */ - + uint32_t tickstart; + uint32_t loadsuspended; + const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Suspend the CLUT loading */ - SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - - /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == 1) + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); - } + } /* Get tick */ tickstart = HAL_GetTick(); - + /* Check if the CLUT loading is suspended */ - while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ - && ((*reg & mask) == mask)) + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + while (loadsuspended == 0UL) { if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + return HAL_TIMEOUT; } + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ } - + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((*reg & mask) != RESET) - { + if ((*reg & DMA2D_BGPFCCR_START) != 0U) + { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; } else { - /* Make sure SUSP bit is cleared since it is meaningless + /* Make sure SUSP bit is cleared since it is meaningless when no tranfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - } + } return HAL_OK; } /** * @brief Resume the DMA2D CLUT loading. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { /* Check the SUSP and START bits for background or foreground CLUT loading */ - if(LayerIdx == 0) - { + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { /* Background CLUT loading suspension check */ - if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) { + if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ hdma2d->State = HAL_DMA2D_STATE_BUSY; } } + } else { /* Foreground CLUT loading suspension check */ - if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)) + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) { + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - } + } + } } /* Resume the CLUT loading */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); return HAL_OK; } @@ -1019,34 +1249,35 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint /** * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Timeout: Timeout duration + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) { - uint32_t tickstart = 0; - __IO uint32_t isrflags = 0x0; + uint32_t tickstart; + uint32_t layer_start; + __IO uint32_t isrflags = 0x0U; /* Polling for DMA2D transfer */ - if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) { - if ((isrflags & DMA2D_FLAG_CE) != RESET) + if ((isrflags & DMA2D_FLAG_CE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; } - if ((isrflags & DMA2D_FLAG_TE) != RESET) + if ((isrflags & DMA2D_FLAG_TE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; } /* Clear the transfer and configuration error flags */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); @@ -1056,116 +1287,117 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; /* Change the DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } - } + } } } /* Polling for CLUT loading (foreground or background) */ - if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || - ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET)) + layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; + layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; + if (layer_start != 0U) { /* Get tick */ tickstart = HAL_GetTick(); - - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) - { - if ((isrflags & DMA2D_FLAG_CAE) != RESET) + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + { + if ((isrflags & DMA2D_FLAG_CAE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - } - if ((isrflags & DMA2D_FLAG_CE) != RESET) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; } - if ((isrflags & DMA2D_FLAG_TE) != RESET) + if ((isrflags & DMA2D_FLAG_CE) != 0U) { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; } /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); - + /* Change DMA2D state */ hdma2d->State= HAL_DMA2D_STATE_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } + + return HAL_ERROR; + } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - + /* Change the DMA2D state */ hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_TIMEOUT; } - } + } } } /* Clear the transfer complete and CLUT loading flags */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); - + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdma2d); - + return HAL_OK; } /** * @brief Handle DMA2D interrupt request. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL status */ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) { uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); uint32_t crflags = READ_REG(hdma2d->Instance->CR); - + /* Transfer Error Interrupt management ***************************************/ - if ((isrflags & DMA2D_FLAG_TE) != RESET) + if ((isrflags & DMA2D_FLAG_TE) != 0U) { - if ((crflags & DMA2D_IT_TE) != RESET) + if ((crflags & DMA2D_IT_TE) != 0U) { /* Disable the transfer Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - + /* Clear the transfer error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); @@ -1173,8 +1405,8 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ @@ -1183,25 +1415,25 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } /* Configuration Error Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_CE) != RESET) + if ((isrflags & DMA2D_FLAG_CE) != 0U) { - if ((crflags & DMA2D_IT_CE) != RESET) - { + if ((crflags & DMA2D_IT_CE) != 0U) + { /* Disable the Configuration Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); - + /* Clear the Configuration error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ @@ -1210,104 +1442,113 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) } } /* CLUT access Error Interrupt management ***********************************/ - if ((isrflags & DMA2D_FLAG_CAE) != RESET) + if ((isrflags & DMA2D_FLAG_CAE) != 0U) { - if ((crflags & DMA2D_IT_CAE) != RESET) - { + if ((crflags & DMA2D_IT_CAE) != 0U) + { /* Disable the CLUT access error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); - + /* Clear the CLUT access error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); } } - } + } /* Transfer watermark Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_TW) != RESET) + if ((isrflags & DMA2D_FLAG_TW) != 0U) { - if ((crflags & DMA2D_IT_TW) != RESET) - { + if ((crflags & DMA2D_IT_TW) != 0U) + { /* Disable the transfer watermark interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); - - /* Clear the transfer watermark flag */ + + /* Clear the transfer watermark flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); /* Transfer watermark Callback */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->LineEventCallback(hdma2d); +#else HAL_DMA2D_LineEventCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + } - } + } /* Transfer Complete Interrupt management ************************************/ - if ((isrflags & DMA2D_FLAG_TC) != RESET) + if ((isrflags & DMA2D_FLAG_TC) != 0U) { - if ((crflags & DMA2D_IT_TC) != RESET) - { + if ((crflags & DMA2D_IT_TC) != 0U) + { /* Disable the transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); - - /* Clear the transfer complete flag */ + + /* Clear the transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + if(hdma2d->XferCpltCallback != NULL) { /* Transfer complete Callback */ hdma2d->XferCpltCallback(hdma2d); - } + } } } /* CLUT Transfer Complete Interrupt management ******************************/ - if ((isrflags & DMA2D_FLAG_CTC) != RESET) + if ((isrflags & DMA2D_FLAG_CTC) != 0U) { - if ((crflags & DMA2D_IT_CTC) != RESET) - { + if ((crflags & DMA2D_IT_CTC) != 0U) + { /* Disable the CLUT transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); - - /* Clear the CLUT transfer complete flag */ + + /* Clear the CLUT transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + /* CLUT Transfer complete Callback */ - HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->CLUTLoadingCpltCallback(hdma2d); +#else + HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ } - } - + } + } /** * @brief Transfer watermark callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1315,7 +1556,7 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_LineEventCallback can be implemented in the user file. */ @@ -1323,7 +1564,7 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief CLUT Transfer Complete callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1331,30 +1572,30 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); - + /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. */ -} +} /** * @} */ /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the DMA2D foreground or background layer parameters. (+) Configure the DMA2D CLUT transfer. (+) Configure the line watermark (+) Configure the dead time value. - (+) Enable or disable the dead time value functionality. - + (+) Enable or disable the dead time value functionality. + @endverbatim * @{ @@ -1363,163 +1604,156 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure the DMA2D Layer according to the specified * parameters in the DMA2D_HandleTypeDef. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - DMA2D_LayerCfgTypeDef *LayerCfg = &hdma2d->LayerCfg[LayerIdx]; - uint32_t tmp = 0; - +{ + DMA2D_LayerCfgTypeDef *pLayerCfg; + uint32_t regMask, regValue; + /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_OFFSET(LayerCfg->InputOffset)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); if(hdma2d->Init.Mode != DMA2D_R2M) - { - assert_param(IS_DMA2D_INPUT_COLOR_MODE(LayerCfg->InputColorMode)); + { + assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); if(hdma2d->Init.Mode != DMA2D_M2M) { - assert_param(IS_DMA2D_ALPHA_MODE(LayerCfg->AlphaMode)); + assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); } } - assert_param(IS_DMA2D_ALPHA_INVERTED(LayerCfg->AlphaInverted)); - assert_param(IS_DMA2D_RB_SWAP(LayerCfg->RedBlueSwap)); - + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); + /* Process locked */ __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the background DMA2D layer */ - if(LayerIdx == 0) - { - /* DMA2D BGPFCR register configuration -----------------------------------*/ - /* Prepare the value to be written to the BGPFCCR register */ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (LayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA)); - } - else - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (LayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA)); - } - - /* Write DMA2D BGPFCCR register */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS), \ - (tmp | (LayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI) |(LayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS))); - - /* DMA2D BGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->BGOR, LayerCfg->InputOffset); - - /* DMA2D BGCOLR register configuration -------------------------------------*/ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - WRITE_REG(hdma2d->Instance->BGCOLR, LayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); - } + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + + /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\ + (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); + regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); + + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + } + + /* Configure the background DMA2D layer */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); + } } /* Configure the foreground DMA2D layer */ else { - /* DMA2D FGPFCR register configuration -----------------------------------*/ - /* Prepare the value to be written to the FGPFCCR register */ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_FGPFCCR_AM) | (LayerCfg->InputAlpha & DMA2D_FGPFCCR_ALPHA)); - } - else - { - tmp = (LayerCfg->InputColorMode | (LayerCfg->AlphaMode << DMA2D_POSITION_FGPFCCR_AM) | (LayerCfg->InputAlpha << DMA2D_POSITION_FGPFCCR_ALPHA)); - } - - /* Write DMA2D FGPFCCR register */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_RBS), \ - (tmp | (LayerCfg->AlphaInverted << DMA2D_POSITION_FGPFCCR_AI) |(LayerCfg->RedBlueSwap << DMA2D_POSITION_FGPFCCR_RBS))); - + + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + /* DMA2D FGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->FGOR, LayerCfg->InputOffset); - - /* DMA2D FGCOLR register configuration -------------------------------------*/ - if ((LayerCfg->InputColorMode == DMA2D_INPUT_A4) || (LayerCfg->InputColorMode == DMA2D_INPUT_A8)) + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - WRITE_REG(hdma2d->Instance->FGCOLR, LayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); - } - } + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + } + } /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + return HAL_OK; } /** * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: - * 0(background) / 1(foreground) + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - + /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - + hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == 0) + if(LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); } /* Configure the CLUT of the foreground DMA2D layer */ else { /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - + /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); } - + /* Set the DMA2D state to Ready*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + return HAL_OK; } /** * @brief Configure the line watermark. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param Line: Line Watermark configuration (maximum 16-bit long value expected). + * @param Line Line Watermark configuration (maximum 16-bit long value expected). * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. * @note The transfer watermark interrupt is disabled once it has occurred. * @retval HAL status @@ -1529,38 +1763,38 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32 { /* Check the parameters */ assert_param(IS_DMA2D_LINEWATERMARK(Line)); - + if (Line > DMA2D_LWR_LW) { - return HAL_ERROR; + return HAL_ERROR; } else - { + { /* Process locked */ __HAL_LOCK(hdma2d); - + /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - + /* Sets the Line watermark configuration */ WRITE_REG(hdma2d->Instance->LWR, Line); - + /* Enable the Line interrupt */ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); - + /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - + __HAL_UNLOCK(hdma2d); + return HAL_OK; - } + } } /** * @brief Enable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1583,7 +1817,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) /** * @brief Disable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1606,21 +1840,21 @@ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure dead time. - * @note The dead time value represents the guaranteed minimum number of cycles between + * @note The dead time value represents the guaranteed minimum number of cycles between * two consecutive transactions on the AHB bus. - * @param hdma2d: DMA2D handle. - * @param DeadTime: dead time value. + * @param hdma2d DMA2D handle. + * @param DeadTime dead time value. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) { /* Process Locked */ - __HAL_LOCK(hdma2d); - + __HAL_LOCK(hdma2d); + hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Set DMA2D_AMTCR DT field */ - MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT)); + MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos)); hdma2d->State = HAL_DMA2D_STATE_READY; @@ -1633,38 +1867,38 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t /** * @} */ - + /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @brief Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides functions allowing to : + This subsection provides functions allowing to: (+) Get the DMA2D state - (+) Get the DMA2D error code + (+) Get the DMA2D error code @endverbatim * @{ - */ + */ /** * @brief Return the DMA2D state - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. * @retval HAL state */ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) -{ +{ return hdma2d->State; } /** * @brief Return the DMA2D error code - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for DMA2D. * @retval DMA2D Error Code */ @@ -1676,10 +1910,10 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @} */ - + /** * @} - */ + */ /** @defgroup DMA2D_Private_Functions DMA2D Private Functions @@ -1688,36 +1922,36 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @brief Set the DMA2D transfer parameters. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the specified DMA2D. - * @param pdata: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the specified DMA2D. + * @param pdata The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. * @retval HAL status */ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - uint32_t tmp = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t tmp4 = 0; - +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; + uint32_t tmp4; + /* Configure DMA2D data size */ - MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); - + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); + /* Configure DMA2D destination address */ WRITE_REG(hdma2d->Instance->OMAR, DstAddress); - + /* Register to memory DMA2D mode selected */ if (hdma2d->Init.Mode == DMA2D_R2M) - { + { tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; tmp2 = pdata & DMA2D_OCOLR_RED_1; tmp3 = pdata & DMA2D_OCOLR_GREEN_1; tmp4 = pdata & DMA2D_OCOLR_BLUE_1; - + /* Prepare the value to be written to the OCOLR register according to the color mode */ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) { @@ -1725,45 +1959,45 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) { - tmp = (tmp3 | tmp2 | tmp4); + tmp = (tmp3 | tmp2 | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) { - tmp2 = (tmp2 >> 19); - tmp3 = (tmp3 >> 10); - tmp4 = (tmp4 >> 3 ); - tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 10U); + tmp4 = (tmp4 >> 3U ); + tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) - { - tmp1 = (tmp1 >> 31); - tmp2 = (tmp2 >> 19); - tmp3 = (tmp3 >> 11); - tmp4 = (tmp4 >> 3 ); - tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); - } + { + tmp1 = (tmp1 >> 31U); + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 11U); + tmp4 = (tmp4 >> 3U ); + tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); + } else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ { - tmp1 = (tmp1 >> 28); - tmp2 = (tmp2 >> 20); - tmp3 = (tmp3 >> 12); - tmp4 = (tmp4 >> 4 ); - tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); - } + tmp1 = (tmp1 >> 28U); + tmp2 = (tmp2 >> 20U); + tmp3 = (tmp3 >> 12U); + tmp4 = (tmp4 >> 4U ); + tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); + } /* Write to DMA2D OCOLR register */ - WRITE_REG(hdma2d->Instance->OCOLR, tmp); - } + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + } else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ { /* Configure DMA2D source address */ - WRITE_REG(hdma2d->Instance->FGMAR, pdata); + WRITE_REG(hdma2d->Instance->FGMAR, pdata); } } /** * @} */ - + /** * @} */ @@ -1771,10 +2005,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** * @} */ - -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* DMA2D */ #endif /* HAL_DMA2D_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h index cb389d6659..d126629f85 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h @@ -6,44 +6,26 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA2D_H -#define __STM32L4xx_HAL_DMA2D_H +#ifndef STM32L4xx_HAL_DMA2D_H +#define STM32L4xx_HAL_DMA2D_H #ifdef __cplusplus extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - +#if defined (DMA2D) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -60,9 +42,9 @@ /** @defgroup DMA2D_Exported_Types DMA2D Exported Types * @{ */ -#define MAX_DMA2D_LAYER 2U +#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ -/** +/** * @brief DMA2D color Structure definition */ typedef struct @@ -77,7 +59,7 @@ typedef struct This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ } DMA2D_ColorTypeDef; -/** +/** * @brief DMA2D CLUT Structure definition */ typedef struct @@ -87,11 +69,11 @@ typedef struct uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. This parameter can be one value of @ref DMA2D_CLUT_CM. */ - uint32_t Size; /*!< Configures the DMA2D CLUT size. + uint32_t Size; /*!< Configures the DMA2D CLUT size. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ } DMA2D_CLUTCfgTypeDef; -/** +/** * @brief DMA2D Init structure definition */ typedef struct @@ -102,29 +84,30 @@ typedef struct uint32_t ColorMode; /*!< Configures the color format of the output image. This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ - uint32_t OutputOffset; /*!< Specifies the Offset value. + uint32_t OutputOffset; /*!< Specifies the Offset value. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ - + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) for the output pixel format converter. - This parameter can be one value of @ref DMA2D_RB_Swap. */ + This parameter can be one value of @ref DMA2D_RB_Swap. */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). This parameter can be one value of @ref DMA2D_Bytes_Swap. */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ - uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ } DMA2D_InitTypeDef; -/** +/** * @brief DMA2D Layer structure definition */ typedef struct @@ -132,29 +115,30 @@ typedef struct uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. + uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ - uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. + uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. This parameter can be one value of @ref DMA2D_Alpha_Mode. */ - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. - @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between - Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where + @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between + Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where - InputAlpha[24:31] is the alpha value ALPHA[0:7] - InputAlpha[16:23] is the red value RED[0:7] - InputAlpha[8:15] is the green value GREEN[0:7] - InputAlpha[0:7] is the blue value BLUE[0:7]. */ - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ - + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). This parameter can be one value of @ref DMA2D_RB_Swap. */ + + } DMA2D_LayerCfgTypeDef; -/** +/** * @brief HAL DMA2D State structures definition */ typedef enum @@ -167,27 +151,45 @@ typedef enum HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ }HAL_DMA2D_StateTypeDef; -/** +/** * @brief DMA2D handle Structure definition */ typedef struct __DMA2D_HandleTypeDef { DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ - + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ - - void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ - - DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - HAL_LockTypeDef Lock; /*!< DMA2D lock. */ - + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ + + void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ + + void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ + + void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ + +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ + + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ - - __IO uint32_t ErrorCode; /*!< DMA2D error code. */ + + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ } DMA2D_HandleTypeDef; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D Callback pointer definition + */ +typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ /** * @} */ @@ -200,34 +202,38 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Error_Code DMA2D Error Code * @{ */ -#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */ -#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */ -#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ +#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ +#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup DMA2D_Mode DMA2D Mode +/** @defgroup DMA2D_Mode DMA2D Mode * @{ */ -#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ /** * @} */ -/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode +/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode * @{ */ -#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ @@ -239,17 +245,17 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode * @{ */ -#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */ -#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */ -#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */ -#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */ -#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */ -#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */ -#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */ -#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */ -#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */ -#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */ -#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */ +#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ +#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ +#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ +#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ +#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ +#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ +#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ +#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ +#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ +#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ +#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ /** * @} */ @@ -257,19 +263,19 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode * @{ */ -#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ -#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */ -#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value +#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ +#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value with original alpha channel value */ /** * @} - */ + */ /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion * @{ */ -#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ -#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */ +#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ /** * @} */ @@ -277,43 +283,47 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap * @{ */ -#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */ -#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */ +#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ +#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ /** * @} - */ + */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + + +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode * @{ */ -#define DMA2D_LOM_PIXELS ((uint32_t)0x00000000U) /*!< Line offsets expressed in pixels */ -#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ +#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ +#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ /** * @} */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap * @{ */ -#define DMA2D_BYTES_REGULAR ((uint32_t)0x00000000U) /*!< Bytes in regular order in output FIFO */ -#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ +#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ +#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ /** * @} - */ + */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode * @{ */ -#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */ -#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */ +#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ +#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ /** * @} */ -/** @defgroup DMA2D_Interrupts DMA2D Interrupts +/** @defgroup DMA2D_Interrupts DMA2D Interrupts * @{ */ #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ @@ -322,13 +332,13 @@ typedef struct __DMA2D_HandleTypeDef #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ -/** - * @} - */ - -/** @defgroup DMA2D_Flags DMA2D Flags - * @{ - */ +/** + * @} + */ + +/** @defgroup DMA2D_Flags DMA2D Flags + * @{ + */ #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ @@ -338,7 +348,7 @@ typedef struct __DMA2D_HandleTypeDef /** * @} */ - + /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ @@ -346,8 +356,23 @@ typedef struct __DMA2D_HandleTypeDef /** * @} */ - - + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D common Callback ID enumeration definition + */ +typedef enum +{ + HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ + HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ + HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ + HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ + HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ + HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ +}HAL_DMA2D_CallbackIDTypeDef; +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + /** * @} */ @@ -357,14 +382,23 @@ typedef struct __DMA2D_HandleTypeDef */ /** @brief Reset DMA2D handle state - * @param __HANDLE__: specifies the DMA2D handle. + * @param __HANDLE__ specifies the DMA2D handle. * @retval None */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + /** * @brief Enable the DMA2D. - * @param __HANDLE__: DMA2D handle + * @param __HANDLE__ DMA2D handle * @retval None. */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) @@ -373,38 +407,38 @@ typedef struct __DMA2D_HandleTypeDef /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: flag to check. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag * @arg DMA2D_FLAG_CAE: CLUT access error flag * @arg DMA2D_FLAG_TW: Transfer Watermark flag * @arg DMA2D_FLAG_TC: Transfer complete flag - * @arg DMA2D_FLAG_TE: Transfer error flag + * @arg DMA2D_FLAG_TE: Transfer error flag * @retval The state of FLAG. */ #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** * @brief Clear the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag * @arg DMA2D_FLAG_CAE: CLUT access error flag * @arg DMA2D_FLAG_TW: Transfer Watermark flag * @arg DMA2D_FLAG_TC: Transfer complete flag - * @arg DMA2D_FLAG_TE: Transfer error flag + * @arg DMA2D_FLAG_TE: Transfer error flag * @retval None */ #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) /** * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -418,8 +452,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -433,8 +467,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -445,25 +479,30 @@ typedef struct __DMA2D_HandleTypeDef * @retval The state of INTERRUPT source. */ #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) - + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions * @{ */ /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions * @{ - */ - + */ + /* Initialization and de-initialization functions *******************************/ -HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ /** * @} @@ -473,7 +512,7 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions * @{ */ - + /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); @@ -529,94 +568,106 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); * @} */ -/* Private constants ---------------------------------------------------------*/ - +/* Private constants ---------------------------------------------------------*/ + /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants * @{ - */ + */ -/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark +/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark * @{ */ #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ /** * @} */ - + /** @defgroup DMA2D_Color_Value DMA2D Color Value * @{ */ -#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ +#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ /** * @} - */ + */ /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers * @{ - */ -#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */ + */ +#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ /** * @} - */ - -/** @defgroup DMA2D_Offset DMA2D Offset + */ + +/** @defgroup DMA2D_Layers DMA2D Layers * @{ */ -#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ +#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ +#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ /** * @} - */ - -/** @defgroup DMA2D_Size DMA2D Size + */ + +/** @defgroup DMA2D_Offset DMA2D Offset * @{ */ -#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ -#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ +#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ /** * @} - */ - + */ + +/** @defgroup DMA2D_Size DMA2D Size + * @{ + */ +#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ +#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ +/** + * @} + */ + /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size * @{ */ -#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */ +#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ /** * @} - */ - + */ + /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA2D_Private_Macros DMA2D Private Macros * @{ */ -#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) +#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) #else #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) + #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) + #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ ((INPUT_CM) == DMA2D_INPUT_A4)) + #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ ((AlphaMode) == DMA2D_COMBINE_ALPHA)) @@ -627,14 +678,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ ((RB_Swap) == DMA2D_RB_SWAP)) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ ((LOM) == DMA2D_LOM_BYTES)) +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) @@ -651,19 +704,19 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); /** * @} - */ + */ /** * @} */ -#endif /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DMA2D */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_DMA2D_H */ +#endif /* STM32L4xx_HAL_DMA2D_H */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c index 50b09d5908..0a8f922e05 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c @@ -25,33 +25,23 @@ called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -106,8 +96,8 @@ /** * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters * @retval HAL status */ @@ -133,8 +123,8 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy MODIFY_REG( hdma->DMAmuxChannel->CCR, \ (~DMAMUX_CxCR_DMAREQ_ID) , \ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ - pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ - (pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); /* Process UnLocked */ __HAL_UNLOCK(hdma); @@ -150,8 +140,8 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy /** * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : * contains the request generator parameters. * @@ -175,9 +165,9 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, /* Process Locked */ __HAL_LOCK(hdma); - /* Set the request generator new parameters*/ + /* Set the request generator new parameters */ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ - ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ pRequestGeneratorConfig->Polarity; /* Process UnLocked */ __HAL_UNLOCK(hdma); @@ -192,8 +182,8 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, /** * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) @@ -220,8 +210,8 @@ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) /** * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) @@ -248,8 +238,8 @@ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) /** * @brief Handles DMAMUX interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. * @retval None */ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h index 0ce4b2ae20..b6ff416f6f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_EX_H -#define __STM32L4xx_HAL_DMA_EX_H +#ifndef STM32L4xx_HAL_DMA_EX_H +#define STM32L4xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { @@ -152,9 +136,9 @@ typedef struct * @{ */ #define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ -#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ -#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ -#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ +#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ /** * @} @@ -164,32 +148,32 @@ typedef struct * @{ */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ +#define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ +#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ +#define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ /** * @} @@ -198,10 +182,10 @@ typedef struct /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection * @{ */ -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ -#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ /** * @} @@ -253,9 +237,9 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) -#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) -#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) @@ -265,14 +249,14 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ ((EVENT) == ENABLE)) -#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT) -#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) -#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING)) +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) /** * @} @@ -293,6 +277,6 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); } #endif -#endif /* __STM32L4xx_HAL_DMA_H */ +#endif /* STM32L4xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c index 570bef2b50..e1fc3d15d7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c @@ -9,32 +9,146 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DSI HAL driver can be used as follows: + + (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi; + + (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API: + (##) Enable the DSI interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the DSI interrupt priority + (+++) Enable the NVIC DSI IRQ Channel + + (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and + TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit(). + + *** Configuration *** + ========================= + [..] + (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted + command mode. + + (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host. + + (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. + + (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer(). + + (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop(). + Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively + to write DSI short packets, long packets and to read DSI packets. + + (#) The DSI Host Offers two Low power modes : + (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData() + and HAL_DSI_ExitULPMData() + + (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM() + and HAL_DSI_ExitULPM() + + (#) To control DSI state you can use the following function: HAL_DSI_GetState() + + *** Error management *** + ======================== + [..] + (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor() + When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve + the error code by calling function HAL_DSI_GetError() + + *** DSI HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DSI HAL driver. + + (+) __HAL_DSI_ENABLE: Enable the DSI Host. + (+) __HAL_DSI_DISABLE: Disable the DSI Host. + (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper. + (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper. + (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL. + (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL. + (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator. + (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator. + (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags. + (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags. + (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts. + (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. + (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. + + [..] + (@) You can refer to the DSI HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_DSI_RegisterCallback() to register a callback. + + [..] + Function HAL_DSI_RegisterCallback() allows to register following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + + [..] + By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_DSI_Init() + and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit() + or HAL_DSI_Init() function. + + [..] + When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -82,21 +196,28 @@ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, + uint32_t Data1); + +static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); /* Private functions ---------------------------------------------------------*/ /** * @brief Generic DSI packet header configuration - * @param DSIx: Pointer to DSI register base - * @param ChannelID: Virtual channel ID of the header packet - * @param DataType: Packet data type of the header packet + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet * This parameter can be any value of : - * @ref DSI_SHORT_WRITE_PKT_Data_Type - * or @ref DSI_LONG_WRITE_PKT_Data_Type - * or @ref DSI_SHORT_READ_PKT_Data_Type - * or DSI_MAX_RETURN_PKT_SIZE - * @param Data0: Word count LSB - * @param Data1: Word count MSB + * @arg DSI_SHORT_WRITE_PKT_Data_Type + * @arg DSI_LONG_WRITE_PKT_Data_Type + * @arg DSI_SHORT_READ_PKT_Data_Type + * @arg DSI_MAX_RETURN_PKT_SIZE + * @param Data0 Word count LSB + * @param Data1 Word count MSB * @retval None */ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, @@ -106,7 +227,48 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t Data1) { /* Update the DSI packet header with new information */ - DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U)); + DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U)); +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. + * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @arg DSI_DCS_Command or a + * generic command code. + * @param Param2 DSC parameter or second generic parameter. + * @retval HAL status + */ +static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + /* Update the DSI packet header with new information */ + hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); + + return HAL_OK; } /* Exported functions --------------------------------------------------------*/ @@ -115,8 +277,8 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, */ /** @defgroup DSI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### @@ -132,10 +294,10 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, /** * @brief Initializes the DSI according to the specified * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains - * the PLL Clock structure definition for the DSI. + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) @@ -145,7 +307,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI uint32_t tempIDF; /* Check the DSI handle allocation */ - if(hdsi == NULL) + if (hdsi == NULL) { return HAL_ERROR; } @@ -157,11 +319,28 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); - if(hdsi->State == HAL_DSI_STATE_RESET) +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if (hdsi->State == HAL_DSI_STATE_RESET) + { + /* Reset the DSI callback to the legacy weak callbacks */ + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hdsi->MspInitCallback == NULL) + { + hdsi->MspInitCallback = HAL_DSI_MspInit; + } + /* Initialize the low level hardware */ + hdsi->MspInitCallback(hdsi); + } +#else + if (hdsi->State == HAL_DSI_STATE_RESET) { /* Initialize the low level hardware */ HAL_DSI_MspInit(hdsi); } +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /* Change DSI peripheral state */ hdsi->State = HAL_DSI_STATE_BUSY; @@ -175,10 +354,10 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI tickstart = HAL_GetTick(); /* Wait until the regulator is ready */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -186,7 +365,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /* Set the PLL division factors */ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U)); /* Enable the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); @@ -195,10 +374,10 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI tickstart = HAL_GetTick(); /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -227,7 +406,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; - unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); + unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV); /* Set the bit period in high-speed mode */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; @@ -252,14 +431,14 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /** * @brief De-initializes the DSI peripheral registers to their default reset * values. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) { /* Check the DSI handle allocation */ - if(hdsi == NULL) + if (hdsi == NULL) { return HAL_ERROR; } @@ -282,8 +461,17 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) /* Disable the regulator */ __HAL_DSI_REG_DISABLE(hdsi); +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if (hdsi->MspDeInitCallback == NULL) + { + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; + } + /* DeInit the low level hardware */ + hdsi->MspDeInitCallback(hdsi); +#else /* DeInit the low level hardware */ HAL_DSI_MspDeInit(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /* Initialise the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; @@ -299,10 +487,10 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) /** * @brief Enable the error monitor flags - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ActiveErrors: indicates which error interrupts will be enabled. - * This parameter can be any combination of @ref DSI_Error_Data_Type. + * @param ActiveErrors indicates which error interrupts will be enabled. + * This parameter can be any combination of @arg DSI_Error_Data_Type. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) @@ -316,61 +504,61 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A /* Store active errors to the handle */ hdsi->ErrorMsk = ActiveErrors; - if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; } - if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) + if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; @@ -384,11 +572,11 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A /** * @brief Initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ -__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdsi); @@ -399,11 +587,11 @@ __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) /** * @brief De-initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ -__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdsi); @@ -412,13 +600,196 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ } +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DSI Callback + * To be used instead of the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, + pDSI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdsi); + + if (hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = pCallback; + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = pCallback; + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = pCallback; + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} + +/** + * @brief Unregister a DSI Callback + * DSI callabck is redirected to the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdsi); + + if (hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup DSI_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -431,7 +802,7 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ /** * @brief Handles DSI interrupt request. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -440,101 +811,119 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) uint32_t ErrorStatus0, ErrorStatus1; /* Tearing Effect Interrupt management ***************************************/ - if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) + if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) { - if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) + if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U) { /* Clear the Tearing Effect Interrupt Flag */ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); /* Tearing Effect Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Tearing Effect callback */ + hdsi->TearingEffectCallback(hdsi); +#else + /*Call legacy Tearing Effect callback*/ HAL_DSI_TearingEffectCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ } } /* End of Refresh Interrupt management ***************************************/ - if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) + if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U) { - if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) + if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U) { /* Clear the End of Refresh Interrupt Flag */ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); /* End of Refresh Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered End of refresh callback */ + hdsi->EndOfRefreshCallback(hdsi); +#else + /*Call Legacy End of refresh callback */ HAL_DSI_EndOfRefreshCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ } } /* Error Interrupts management ***********************************************/ - if(hdsi->ErrorMsk != 0U) + if (hdsi->ErrorMsk != 0U) { ErrorStatus0 = hdsi->Instance->ISR[0U]; ErrorStatus0 &= hdsi->Instance->IER[0U]; ErrorStatus1 = hdsi->Instance->ISR[1U]; ErrorStatus1 &= hdsi->Instance->IER[1U]; - if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) + if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; } - if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) + if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; } - if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_TX; } - if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_RX; } - if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; } - if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; } - if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; } - if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; } - if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; } - if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) + if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U) { hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; } /* Check only selected errors */ - if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE) { - /* DSI error interrupt user callback */ + /* DSI error interrupt callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Error callback */ + hdsi->ErrorCallback(hdsi); +#else + /*Call Legacy Error callback */ HAL_DSI_ErrorCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ } } } /** * @brief Tearing Effect DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -549,7 +938,7 @@ __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) /** * @brief End of Refresh DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -564,7 +953,7 @@ __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) /** * @brief Operation Error DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -582,8 +971,8 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) */ /** @defgroup DSI_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -623,9 +1012,9 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) /** * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VirtualChannelID: Virtual channel ID + * @param VirtualChannelID Virtual channel ID * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) @@ -645,10 +1034,10 @@ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t Virtu /** * @brief Select video mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) @@ -671,7 +1060,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); /* Check the LooselyPacked variant only in 18-bit mode */ - if(VidCfg->ColorCoding == DSI_RGB666) + if (VidCfg->ColorCoding == DSI_RGB666) { assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); } @@ -710,10 +1099,10 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp /* Select the color coding for the wrapper */ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; - hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U); + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U); /* Enable/disable the loosely packed variant to 18-bit configuration */ - if(VidCfg->ColorCoding == DSI_RGB666) + if (VidCfg->ColorCoding == DSI_RGB666) { hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; @@ -753,7 +1142,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp /* Low power largest packet size */ hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; - hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U); + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U); /* Low power VACT largest packet size */ hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; @@ -795,9 +1184,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp /** * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @retval HAL status */ @@ -836,7 +1225,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ /* Select the color coding for the wrapper */ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; - hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U); + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U); /* Configure the maximum allowed size for write memory command */ hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; @@ -844,7 +1233,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ /* Configure the tearing effect source and polarity and select the refresh mode */ hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); - hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | + CmdCfg->VSyncPol); /* Configure the tearing effect acknowledge request */ hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; @@ -865,9 +1255,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ /** * @brief Configure command transmission mode: High-speed or Low-power * and enable/disable acknowledge request after packet transmission - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains * the DSI command transmission mode configuration parameters * @retval HAL status */ @@ -891,29 +1281,29 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); /* Select High-speed or Low-power for command transmission */ - hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ - DSI_CMCR_GSW1TX |\ - DSI_CMCR_GSW2TX |\ - DSI_CMCR_GSR0TX |\ - DSI_CMCR_GSR1TX |\ - DSI_CMCR_GSR2TX |\ - DSI_CMCR_GLWTX |\ - DSI_CMCR_DSW0TX |\ - DSI_CMCR_DSW1TX |\ - DSI_CMCR_DSR0TX |\ - DSI_CMCR_DLWTX |\ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \ + DSI_CMCR_GSW1TX | \ + DSI_CMCR_GSW2TX | \ + DSI_CMCR_GSR0TX | \ + DSI_CMCR_GSR1TX | \ + DSI_CMCR_GSR2TX | \ + DSI_CMCR_GLWTX | \ + DSI_CMCR_DSW0TX | \ + DSI_CMCR_DSW1TX | \ + DSI_CMCR_DSR0TX | \ + DSI_CMCR_DLWTX | \ DSI_CMCR_MRDPS); - hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ - LPCmd->LPGenShortWriteOneP |\ - LPCmd->LPGenShortWriteTwoP |\ - LPCmd->LPGenShortReadNoP |\ - LPCmd->LPGenShortReadOneP |\ - LPCmd->LPGenShortReadTwoP |\ - LPCmd->LPGenLongWrite |\ - LPCmd->LPDcsShortWriteNoP |\ - LPCmd->LPDcsShortWriteOneP |\ - LPCmd->LPDcsShortReadNoP |\ - LPCmd->LPDcsLongWrite |\ + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \ + LPCmd->LPGenShortWriteOneP | \ + LPCmd->LPGenShortWriteTwoP | \ + LPCmd->LPGenShortReadNoP | \ + LPCmd->LPGenShortReadOneP | \ + LPCmd->LPGenShortReadTwoP | \ + LPCmd->LPGenLongWrite | \ + LPCmd->LPDcsShortWriteNoP | \ + LPCmd->LPDcsShortWriteOneP | \ + LPCmd->LPDcsShortReadNoP | \ + LPCmd->LPDcsLongWrite | \ LPCmd->LPMaxReadPacket); /* Configure the acknowledge request after each packet transmission */ @@ -928,10 +1318,10 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe /** * @brief Configure the flow control parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param FlowControl: flow control feature(s) to be enabled. - * This parameter can be any combination of @ref DSI_FlowControl. + * @param FlowControl flow control feature(s) to be enabled. + * This parameter can be any combination of @arg DSI_FlowControl. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) @@ -954,9 +1344,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t Fl /** * @brief Configure the DSI PHY timer parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains * the DSI PHY timing parameters * @retval HAL status */ @@ -966,7 +1356,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT /* Process locked */ __HAL_LOCK(hdsi); - maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime : + PhyTimers->ClockLaneHS2LPTime; /* Clock lane timer configuration */ @@ -978,17 +1369,18 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. - */ + */ hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); - hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U)); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U)); /* Data lane timer configuration */ hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); - hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U)); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | (( + PhyTimers->DataLaneHS2LPTime) << 24U)); /* Configure the wait period to request HS transmission after a stop state */ hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; - hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U); + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U); /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -998,9 +1390,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT /** * @brief Configure the DSI HOST timeout parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains * the DSI host timeout parameters * @retval HAL status */ @@ -1011,11 +1403,11 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T /* Set the timeout clock division factor */ hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; - hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U); + hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U); /* High-speed transmission timeout */ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; - hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U); + hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U); /* Low-power reception timeout */ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; @@ -1053,7 +1445,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T /** * @brief Start the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1076,7 +1468,7 @@ HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) /** * @brief Stop the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1099,7 +1491,7 @@ HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) /** * @brief Refresh the display in command mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1119,10 +1511,10 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) /** * @brief Controls the display color mode in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ColorMode: Color mode (full or 8-colors). - * This parameter can be any value of @ref DSI_Color_Mode + * @param ColorMode Color mode (full or 8-colors). + * This parameter can be any value of @arg DSI_Color_Mode * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) @@ -1145,10 +1537,10 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) /** * @brief Control the display shutdown in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Shutdown: Shut-down (Display-ON or Display-OFF). - * This parameter can be any value of @ref DSI_ShutDown + * @param Shutdown Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @arg DSI_ShutDown * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) @@ -1171,15 +1563,15 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) /** * @brief write short DCS or short Generic command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI short packet data type. - * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1: DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. + * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @arg DSI_DCS_Command or a * generic command code. - * @param Param2: DSC parameter or second generic parameter. + * @param Param2 DSC parameter or second generic parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, @@ -1188,55 +1580,33 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, uint32_t Param1, uint32_t Param2) { - uint32_t tickstart; + HAL_StatusTypeDef status; + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); /* Process locked */ __HAL_LOCK(hdsi); - /* Check the parameters */ - assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Configure the packet to send a short DCS command with 0 or 1 parameter */ - DSI_ConfigPacketHeader(hdsi->Instance, - ChannelID, - Mode, - Param1, - Param2); + status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); /* Process unlocked */ __HAL_UNLOCK(hdsi); - return HAL_OK; + return status; } /** * @brief write long DCS or long Generic command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI long packet data type. - * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams: Number of parameters. - * @param Param1: DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. + * This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @arg DSI_DCS_Command or a * generic command code - * @param ParametersTable: Pointer to parameter values table. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, @@ -1244,12 +1614,12 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t* ParametersTable) + uint8_t *ParametersTable) { uint32_t uicounter, nbBytes, count; uint32_t tickstart; uint32_t fifoword; - uint8_t* pparams = ParametersTable; + uint8_t *pparams = ParametersTable; /* Process locked */ __HAL_LOCK(hdsi); @@ -1261,10 +1631,10 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, tickstart = HAL_GetTick(); /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1277,22 +1647,22 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, fifoword = Param1; nbBytes = (NbParams < 3U) ? NbParams : 3U; - for(count = 0U; count < nbBytes; count++) + for (count = 0U; count < nbBytes; count++) { - fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count))); + fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count))); } hdsi->Instance->GPDR = fifoword; uicounter = NbParams - nbBytes; pparams += nbBytes; /* Set the Next parameters on the write FIFO command*/ - while(uicounter != 0U) + while (uicounter != 0U) { nbBytes = (uicounter < 4U) ? uicounter : 4U; fifoword = 0U; - for(count = 0U; count < nbBytes; count++) + for (count = 0U; count < nbBytes; count++) { - fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count)); + fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count)); } hdsi->Instance->GPDR = fifoword; @@ -1304,8 +1674,8 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, DSI_ConfigPacketHeader(hdsi->Instance, ChannelID, Mode, - ((NbParams+1U)&0x00FFU), - (((NbParams+1U)&0xFF00U)>>8U)); + ((NbParams + 1U) & 0x00FFU), + (((NbParams + 1U) & 0xFF00U) >> 8U)); /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1315,28 +1685,31 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, /** * @brief Read command (DCS or generic) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelNbr: Virtual channel ID - * @param Array: pointer to a buffer to store the payload of a read back operation. - * @param Size: Data size to be read (in byte). - * @param Mode: DSI read packet data type. - * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd: DCS get/read command. - * @param ParametersTable: Pointer to parameter values table. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. + * This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, - uint8_t* Array, + uint8_t *Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, - uint8_t* ParametersTable) + uint8_t *ParametersTable) { uint32_t tickstart; - uint8_t* pdata = Array; + uint8_t *pdata = Array; uint32_t datasize = Size; + uint32_t fifoword; + uint32_t nbbytes; + uint32_t count; /* Process locked */ __HAL_LOCK(hdsi); @@ -1344,10 +1717,11 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, /* Check the parameters */ assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); - if(datasize > 2U) + if (datasize > 2U) { /* set max return packet size */ - if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK) + if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), + (((datasize) >> 8U) & 0xFFU)) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1384,49 +1758,24 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, /* Get tick */ tickstart = HAL_GetTick(); - /* Check that the payload read FIFO is not empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) + /* If DSI fifo is not empty, read requested bytes */ + while (((int32_t)(datasize)) > 0) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); + fifoword = hdsi->Instance->GPDR; + nbbytes = (datasize < 4U) ? datasize : 4U; - return HAL_TIMEOUT; - } - } - - /* Get the first byte */ - *((uint32_t *)pdata) = (hdsi->Instance->GPDR); - if (datasize > 4U) - { - datasize -= 4U; - pdata += 4U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the remaining bytes if any */ - while(((int)(datasize)) > 0U) - { - if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) - { - *((uint32_t *)pdata) = (hdsi->Instance->GPDR); - datasize -= 4U; - pdata += 4U; + for (count = 0U; count < nbbytes; count++) + { + *pdata = (uint8_t)(fifoword >> (8U * count)); + pdata++; + datasize--; + } } /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1444,7 +1793,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1462,12 +1811,12 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) tickstart = HAL_GetTick(); /* Wait until the D-PHY active lanes enter into ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1478,10 +1827,10 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1507,7 +1856,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1525,12 +1874,12 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) tickstart = HAL_GetTick(); /* Wait until all active lanes exit ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1541,10 +1890,10 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1576,7 +1925,7 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1600,12 +1949,12 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) tickstart = HAL_GetTick(); /* Wait until all active lanes exit ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1616,10 +1965,10 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1648,7 +1997,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1666,10 +2015,10 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) tickstart = HAL_GetTick(); /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1685,12 +2034,12 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) tickstart = HAL_GetTick(); /* Wait until all active lanes exit ULPM */ - if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1701,10 +2050,11 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | + DSI_PSR_UANC)) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1741,13 +2091,13 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /** * @brief Start test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Mode: Pattern generator mode + * @param Mode Pattern generator mode * This parameter can be one of the following values: * 0 : Color bars (horizontal or vertical) * 1 : BER pattern (vertical only) - * @param Orientation: Pattern generator orientation + * @param Orientation Pattern generator orientation * This parameter can be one of the following values: * 0 : Vertical color bars * 1 : Horizontal color bars @@ -1760,7 +2110,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_ /* Configure pattern generator mode and orientation */ hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); - hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U)); + hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U)); /* Enable pattern generator by setting PGE bit */ hdsi->Instance->VMCR |= DSI_VMCR_PGE; @@ -1773,7 +2123,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_ /** * @brief Stop test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1793,16 +2143,17 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) /** * @brief Set Slew-Rate And Delay Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CommDelay: Communication delay to be adjusted. - * This parameter can be any value of @ref DSI_Communication_Delay - * @param Lane: select between clock or data lanes. - * This parameter can be any value of @ref DSI_Lane_Group - * @param Value: Custom value of the slew-rate or delay + * @param CommDelay Communication delay to be adjusted. + * This parameter can be any value of @arg DSI_Communication_Delay + * @param Lane select between clock or data lanes. + * This parameter can be any value of @arg DSI_Lane_Group + * @param Value Custom value of the slew-rate or delay * @retval HAL status */ -HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, + uint32_t Value) { /* Process locked */ __HAL_LOCK(hdsi); @@ -1811,73 +2162,73 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); assert_param(IS_DSI_LANE_GROUP(Lane)); - switch(CommDelay) + switch (CommDelay) { - case DSI_SLEW_RATE_HSTX: - if(Lane == DSI_CLOCK_LANE) - { - /* High-Speed Transmission Slew Rate Control on Clock Lane */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; - hdsi->Instance->WPCR[1U] |= Value<<16U; - } - else if(Lane == DSI_DATA_LANES) - { - /* High-Speed Transmission Slew Rate Control on Data Lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; - hdsi->Instance->WPCR[1U] |= Value<<18U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); + case DSI_SLEW_RATE_HSTX: + if (Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Slew Rate Control on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; + hdsi->Instance->WPCR[1U] |= Value << 16U; + } + else if (Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Slew Rate Control on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; + hdsi->Instance->WPCR[1U] |= Value << 18U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - break; - case DSI_SLEW_RATE_LPTX: - if(Lane == DSI_CLOCK_LANE) - { - /* Low-Power transmission Slew Rate Compensation on Clock Lane */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; - hdsi->Instance->WPCR[1U] |= Value<<6U; - } - else if(Lane == DSI_DATA_LANES) - { - /* Low-Power transmission Slew Rate Compensation on Data Lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; - hdsi->Instance->WPCR[1U] |= Value<<8U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + break; + case DSI_SLEW_RATE_LPTX: + if (Lane == DSI_CLOCK_LANE) + { + /* Low-Power transmission Slew Rate Compensation on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; + hdsi->Instance->WPCR[1U] |= Value << 6U; + } + else if (Lane == DSI_DATA_LANES) + { + /* Low-Power transmission Slew Rate Compensation on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; + hdsi->Instance->WPCR[1U] |= Value << 8U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - break; - case DSI_HS_DELAY: - if(Lane == DSI_CLOCK_LANE) - { - /* High-Speed Transmission Delay on Clock Lane */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; - hdsi->Instance->WPCR[1U] |= Value; - } - else if(Lane == DSI_DATA_LANES) - { - /* High-Speed Transmission Delay on Data Lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; - hdsi->Instance->WPCR[1U] |= Value<<2U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + break; + case DSI_HS_DELAY: + if (Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Delay on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; + hdsi->Instance->WPCR[1U] |= Value; + } + else if (Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Delay on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; + hdsi->Instance->WPCR[1U] |= Value << 2U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - break; - default: - break; + return HAL_ERROR; + } + break; + default: + break; } /* Process unlocked */ @@ -1888,9 +2239,9 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin /** * @brief Low-Power Reception Filter Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @param Frequency cutoff frequency of low-pass filter at the input of LPRX * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) @@ -1900,7 +2251,7 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t /* Low-Power RX low-pass Filtering Tuning */ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; - hdsi->Instance->WPCR[1U] |= Frequency<<25U; + hdsi->Instance->WPCR[1U] |= Frequency << 25U; /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1911,9 +2262,9 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t /** * @brief Activate an additional current path on all lanes to meet the SDDTx parameter * defined in the MIPI D-PHY specification - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -1936,16 +2287,17 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) /** * @brief Custom lane pins configuration - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane: Function to be applyed on selected lane. - * This parameter can be any value of @ref DSI_CustomLane - * @param Lane: select between clock or data lane 0 or data lane 1. - * This parameter can be any value of @ref DSI_Lane_Select - * @param State: ENABLE or DISABLE + * @param CustomLane Function to be applyed on selected lane. + * This parameter can be any value of @arg DSI_CustomLane + * @param Lane select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @arg DSI_Lane_Select + * @param State ENABLE or DISABLE * @retval HAL status */ -HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, + FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); @@ -1955,64 +2307,64 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint assert_param(IS_DSI_LANE(Lane)); assert_param(IS_FUNCTIONAL_STATE(State)); - switch(CustomLane) + switch (CustomLane) { - case DSI_SWAP_LANE_PINS: - if(Lane == DSI_CLK_LANE) - { - /* Swap pins on clock lane */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); - } - else if(Lane == DSI_DATA_LANE0) - { - /* Swap pins on data lane 0 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); - } - else if(Lane == DSI_DATA_LANE1) - { - /* Swap pins on data lane 1 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); + case DSI_SWAP_LANE_PINS: + if (Lane == DSI_CLK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); + } + else if (Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); + } + else if (Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - break; - case DSI_INVERT_HS_SIGNAL: - if(Lane == DSI_CLK_LANE) - { - /* Invert HS signal on clock lane */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); - } - else if(Lane == DSI_DATA_LANE0) - { - /* Invert HS signal on data lane 0 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); - } - else if(Lane == DSI_DATA_LANE1) - { - /* Invert HS signal on data lane 1 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + break; + case DSI_INVERT_HS_SIGNAL: + if (Lane == DSI_CLK_LANE) + { + /* Invert HS signal on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); + } + else if (Lane == DSI_DATA_LANE0) + { + /* Invert HS signal on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); + } + else if (Lane == DSI_DATA_LANE1) + { + /* Invert HS signal on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - break; - default: - break; + return HAL_ERROR; + } + break; + default: + break; } /* Process unlocked */ @@ -2023,12 +2375,12 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint /** * @brief Set custom timing for the PHY - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Timing: PHY timing to be adjusted. - * This parameter can be any value of @ref DSI_PHY_Timing - * @param State: ENABLE or DISABLE - * @param Value: Custom value of the timing + * @param Timing PHY timing to be adjusted. + * This parameter can be any value of @arg DSI_PHY_Timing + * @param State ENABLE or DISABLE + * @param Value Custom value of the timing * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) @@ -2040,127 +2392,127 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing assert_param(IS_DSI_PHY_TIMING(Timing)); assert_param(IS_FUNCTIONAL_STATE(State)); - switch(Timing) + switch (Timing) { - case DSI_TCLK_POST: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); + case DSI_TCLK_POST: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; - hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; + hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; + } - break; - case DSI_TLPX_CLK: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); + break; + case DSI_TLPX_CLK: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; - hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; + hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; + } - break; - case DSI_THS_EXIT: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); + break; + case DSI_THS_EXIT: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; - hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; + hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; + } - break; - case DSI_TLPX_DATA: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); + break; + case DSI_TLPX_DATA: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; - hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; + hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; + } - break; - case DSI_THS_ZERO: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); + break; + case DSI_THS_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; - hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; + hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; + } - break; - case DSI_THS_TRAIL: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); + break; + case DSI_THS_TRAIL: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; - hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; + hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; + } - break; - case DSI_THS_PREPARE: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); + break; + case DSI_THS_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; - hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; + hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; + } - break; - case DSI_TCLK_ZERO: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); + break; + case DSI_TCLK_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; - hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; + hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; + } - break; - case DSI_TCLK_PREPARE: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); + break; + case DSI_TCLK_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); - if(State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; - hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; - } + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; + hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; + } - break; - default: - break; + break; + default: + break; } /* Process unlocked */ @@ -2171,11 +2523,11 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing /** * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Lane: select between clock or data lanes. - * This parameter can be any value of @ref DSI_Lane_Group - * @param State: ENABLE or DISABLE + * @param Lane select between clock or data lanes. + * This parameter can be any value of @arg DSI_Lane_Group + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) @@ -2187,13 +2539,13 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane assert_param(IS_DSI_LANE_GROUP(Lane)); assert_param(IS_FUNCTIONAL_STATE(State)); - if(Lane == DSI_CLOCK_LANE) + if (Lane == DSI_CLOCK_LANE) { /* Force/Unforce the Clock Lane in TX Stop Mode */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); } - else if(Lane == DSI_DATA_LANES) + else if (Lane == DSI_DATA_LANES) { /* Force/Unforce the Data Lanes in TX Stop Mode */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; @@ -2215,9 +2567,9 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane /** * @brief Force LP Receiver in Low-Power Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2240,9 +2592,9 @@ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalSta /** * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2265,9 +2617,9 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional /** * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2290,9 +2642,9 @@ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState S /** * @brief Switch off the contention detection on data lanes - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2318,8 +2670,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun */ /** @defgroup DSI_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -2335,7 +2687,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun /** * @brief Return the DSI state - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL state */ @@ -2346,7 +2698,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) /** * @brief Return the DSI error code - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval DSI Error Code */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h index 5baeb926e3..75b733d082 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DSI_H -#define __STM32L4xx_HAL_DSI_H +#ifndef STM32L4xx_HAL_DSI_H +#define STM32L4xx_HAL_DSI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -70,7 +54,7 @@ typedef struct uint32_t NumberOfLanes; /*!< Number of lanes This parameter can be any value of @ref DSI_Number_Of_Lanes */ -}DSI_InitTypeDef; +} DSI_InitTypeDef; /** * @brief DSI PLL Clock structure definition @@ -86,7 +70,7 @@ typedef struct uint32_t PLLODF; /*!< PLL Output Division Factor This parameter can be any value of @ref DSI_PLL_ODF */ -}DSI_PLLInitTypeDef; +} DSI_PLLInitTypeDef; /** * @brief DSI Video mode configuration @@ -164,7 +148,7 @@ typedef struct uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable This parameter can be any value of @ref DSI_FBTA_acknowledge */ -}DSI_VidCfgTypeDef; +} DSI_VidCfgTypeDef; /** * @brief DSI Adapted command mode configuration @@ -203,7 +187,7 @@ typedef struct uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ -}DSI_CmdCfgTypeDef; +} DSI_CmdCfgTypeDef; /** * @brief DSI command transmission mode configuration @@ -249,7 +233,7 @@ typedef struct uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable This parameter can be any value of @ref DSI_AcknowledgeRequest */ -}DSI_LPCmdTypeDef; +} DSI_LPCmdTypeDef; /** * @brief DSI PHY Timings definition @@ -273,7 +257,7 @@ typedef struct uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the Stop state */ -}DSI_PHY_TimerTypeDef; +} DSI_PHY_TimerTypeDef; /** * @brief DSI HOST Timeouts definition @@ -299,7 +283,7 @@ typedef struct uint32_t BTATimeout; /*!< BTA time-out */ -}DSI_HOST_TimeoutTypeDef; +} DSI_HOST_TimeoutTypeDef; /** * @brief DSI States Structure definition @@ -311,12 +295,16 @@ typedef enum HAL_DSI_STATE_ERROR = 0x02U, HAL_DSI_STATE_BUSY = 0x03U, HAL_DSI_STATE_TIMEOUT = 0x04U -}HAL_DSI_StateTypeDef; +} HAL_DSI_StateTypeDef; /** * @brief DSI Handle Structure definition */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +typedef struct __DSI_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ { DSI_TypeDef *Instance; /*!< Register base address */ DSI_InitTypeDef Init; /*!< DSI required parameters */ @@ -324,9 +312,45 @@ typedef struct __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ __IO uint32_t ErrorCode; /*!< DSI Error code */ uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ -}DSI_HandleTypeDef; + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ + void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ + void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ + + void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ + void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +} DSI_HandleTypeDef; + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DSI Callback ID enumeration definition + */ +typedef enum +{ + HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ + HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ + + HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ + HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ + HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ + +} HAL_DSI_CallbackIDTypeDef; + +/** + * @brief HAL DSI Callback pointer definition + */ +typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Constants DSI Exported Constants + * @{ + */ /** @defgroup DSI_DCS_Command DSI DCS Command * @{ */ @@ -816,17 +840,20 @@ typedef struct /** @defgroup DSI_Error_Data_Type DSI Error Data Type * @{ */ -#define HAL_DSI_ERROR_NONE 0U -#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ -#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ -#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ -#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ -#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ -#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ -#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ -#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ -#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ -#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#define HAL_DSI_ERROR_NONE 0U +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @} */ @@ -885,17 +912,33 @@ typedef struct * @} */ +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ +/** @defgroup DSI_Exported_Macros DSI Exported Macros + * @{ + */ + /** * @brief Reset DSI handle state. * @param __HANDLE__: DSI handle * @retval None */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) +#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @brief Enables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_ENABLE(__HANDLE__) do { \ @@ -904,11 +947,11 @@ typedef struct /* Delay after an DSI Host enabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Disables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) do { \ @@ -917,11 +960,11 @@ typedef struct /* Delay after an DSI Host disabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Enables the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ @@ -930,11 +973,11 @@ typedef struct /* Delay after an DSI warpper enabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Disable the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ @@ -943,11 +986,11 @@ typedef struct /* Delay after an DSI warpper disabling*/ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Enables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ @@ -956,11 +999,11 @@ typedef struct /* Delay after an DSI PLL enabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Disables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ @@ -969,11 +1012,11 @@ typedef struct /* Delay after an DSI PLL disabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Enables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ @@ -982,11 +1025,11 @@ typedef struct /* Delay after an DSI regulator enabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Disables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ @@ -995,12 +1038,12 @@ typedef struct /* Delay after an DSI regulator disabling */ \ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ UNUSED(tmpreg); \ - }while(0U) + } while(0U) /** * @brief Get the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -1016,8 +1059,8 @@ typedef struct /** * @brief Clears the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -1030,8 +1073,8 @@ typedef struct /** * @brief Enables the specified DSI interrupts. - * @param __HANDLE__: DSI handle. - * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1044,8 +1087,8 @@ typedef struct /** * @brief Disables the specified DSI interrupts. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1058,8 +1101,8 @@ typedef struct /** * @brief Checks whether the specified DSI interrupt source is enabled or not. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. * This parameter can be one of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1070,6 +1113,10 @@ typedef struct */ #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup DSI_Exported_Functions DSI Exported Functions * @{ @@ -1084,6 +1131,13 @@ void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, + pDSI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); @@ -1106,14 +1160,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t* ParametersTable); + uint8_t *ParametersTable); HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, - uint8_t* Array, + uint8_t *Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, - uint8_t* ParametersTable); + uint8_t *ParametersTable); HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); @@ -1122,11 +1176,14 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, + uint32_t Value); HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, + FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, + uint32_t Value); HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); @@ -1291,6 +1348,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); } #endif -#endif /* __STM32L4xx_HAL_DSI_H */ +#endif /* STM32L4xx_HAL_DSI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_exti.c new file mode 100644 index 0000000000..dafb7a0656 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_exti.c @@ -0,0 +1,643 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between MCU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between MCU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Get pending bit */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending register address */ + regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_exti.h new file mode 100644 index 0000000000..3090b290aa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_exti.h @@ -0,0 +1,860 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_EXTI_H +#define STM32L4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L412xx || STM32L422xx */ + +#if defined(STM32L431xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L431xx */ + +#if defined(STM32L432xx) || defined(STM32L442xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L432xx || STM32L442xx */ + +#if defined(STM32L433xx) || defined(STM32L443xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L433xx || STM32L443xx */ + +#if defined(STM32L451xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L451xx */ + +#if defined(STM32L452xx) || defined(STM32L462xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L452xx || STM32L462xx */ + +#if defined(STM32L471xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L471xx */ + +#if defined(STM32L475xx) || defined(STM32L485xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L475xx || STM32L485xx */ + +#if defined(STM32L476xx) || defined(STM32L486xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u) + +#endif /* STM32L476xx || STM32L486xx */ + +#if defined(STM32L496xx) || defined(STM32L4A6xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L496xx || STM32L4A6xx */ + +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +#define EXTI_GPIOG 0x00000005u +#define EXTI_GPIOH 0x00000007u +#define EXTI_GPIOI 0x00000008u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28u +#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 41u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L412xx || STM32L422xx */ + +#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L431xx || STM32L433xx || STM32L443xx */ + +#if defined(STM32L432xx) || defined(STM32L442xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L432xx || STM32L442xx */ + +#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ + +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) + +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ + +#if defined(STM32L496xx) || defined(STM32L4A6xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) + +#endif /* STM32L496xx || STM32L4A6xx */ + +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c index f3fd43776a..3eee0289d4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c @@ -32,29 +32,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -135,24 +119,24 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) /* Check Firewall configuration addresses and lengths when segment is protected */ /* Code segment */ - if (fw_init->CodeSegmentLength != 0) + if (fw_init->CodeSegmentLength != 0U) { assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress)); assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); /* Make sure that NonVDataSegmentLength is properly set to prevent code segment access */ - if (fw_init->NonVDataSegmentLength < 0x100) + if (fw_init->NonVDataSegmentLength < 0x100U) { return HAL_ERROR; } } /* Non volatile data segment */ - if (fw_init->NonVDataSegmentLength != 0) + if (fw_init->NonVDataSegmentLength != 0U) { assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress)); assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); } /* Volatile data segment */ - if (fw_init->VDataSegmentLength != 0) + if (fw_init->VDataSegmentLength != 0U) { assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress)); assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h index 00954474b9..eb23e0940f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h @@ -6,31 +6,15 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -50,22 +34,22 @@ /** @addtogroup FIREWALL FIREWALL * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types * @{ - */ + */ -/** - * @brief FIREWALL Initialization Structure definition - */ +/** + * @brief FIREWALL Initialization Structure definition + */ typedef struct { uint32_t CodeSegmentStartAddress; /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are reserved and forced to 0 in order to allow a 256-byte granularity. */ - uint32_t CodeSegmentLength; /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are + uint32_t CodeSegmentLength; /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */ uint32_t NonVDataSegmentStartAddress; /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB @@ -73,21 +57,21 @@ typedef struct uint32_t NonVDataSegmentLength; /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */ - + uint32_t VDataSegmentStartAddress; /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits are reserved and forced to 0 in order to allow a 64-byte granularity. */ uint32_t VDataSegmentLength; /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */ - + uint32_t VolatileDataExecution; /*!< Set VDE bit specifying whether or not the volatile data segment can be executed. When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning. - This parameter can be a value of @ref FIREWALL_VolatileData_Executable */ - - uint32_t VolatileDataShared; /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a + This parameter can be a value of @ref FIREWALL_VolatileData_Executable */ + + uint32_t VolatileDataShared; /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a non-protected application code. - This parameter can be a value of @ref FIREWALL_VolatileData_Shared */ - + This parameter can be a value of @ref FIREWALL_VolatileData_Shared */ + }FIREWALL_InitTypeDef; @@ -95,7 +79,7 @@ typedef struct * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants * @{ @@ -108,20 +92,20 @@ typedef struct #define FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE) /** * @} - */ + */ /** @defgroup FIREWALL_VolatileData_Shared FIREWALL volatile data segment share status * @{ - */ + */ #define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000) -#define FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS) +#define FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS) /** * @} - */ + */ /** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status * @{ - */ + */ #define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000) #define FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA) @@ -132,29 +116,29 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @defgroup FIREWALL_Private_Macros FIREWALL Private Macros * @{ */ -#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE))) +#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE))) #define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE)) -#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE))) -#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE)) +#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE))) +#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE)) #define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM1_BASE) && ((ADDRESS) < (SRAM1_BASE + SRAM1_SIZE_MAX))) -#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX)) - - +#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM1_BASE + SRAM1_SIZE_MAX)) + + #define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \ ((SHARE) == FIREWALL_VOLATILEDATA_SHARED)) - + #define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \ - ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE)) + ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE)) /** * @} - */ + */ /* Exported macros -----------------------------------------------------------*/ @@ -164,132 +148,132 @@ typedef struct /** @brief Check whether the FIREWALL is enabled or not. * @retval FIREWALL enabling status (TRUE or FALSE). - */ -#define __HAL_FIREWALL_IS_ENABLED() HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) + */ +#define __HAL_FIREWALL_IS_ENABLED() HAL_IS_BIT_CLR(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) -/** @brief Enable FIREWALL pre arm. - * @note When FPA bit is set, any code executed outside the protected segment +/** @brief Enable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment * closes the Firewall, otherwise it generates a system reset. * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API - * but can be executed inside a code area protected by the Firewall. + * but can be executed inside a code area protected by the Firewall. * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. - */ -#define __HAL_FIREWALL_PREARM_ENABLE() \ - do { \ - __IO uint32_t tmpreg; \ - SET_BIT(FIREWALL->CR, FW_CR_FPA) ; \ - /* Read bit back to ensure it is taken into account by IP */ \ - /* (introduce proper delay inside macro execution) */ \ - tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ; \ - UNUSED(tmpreg); \ + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_PREARM_ENABLE() \ + do { \ + __IO uint32_t tmpreg; \ + SET_BIT(FIREWALL->CR, FW_CR_FPA) ; \ + /* Read bit back to ensure it is taken into account by Peripheral */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ; \ + UNUSED(tmpreg); \ } while(0) - -/** @brief Disable FIREWALL pre arm. - * @note When FPA bit is set, any code executed outside the protected segment + +/** @brief Disable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment * closes the Firewall, otherwise, it generates a system reset. * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API * but can be executed inside a code area protected by the Firewall. * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. - */ -#define __HAL_FIREWALL_PREARM_DISABLE() \ - do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ; \ - /* Read bit back to ensure it is taken into account by IP */ \ - /* (introduce proper delay inside macro execution) */ \ - tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ; \ - UNUSED(tmpreg); \ + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_PREARM_DISABLE() \ + do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ; \ + /* Read bit back to ensure it is taken into account by Peripheral */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ; \ + UNUSED(tmpreg); \ } while(0) -/** @brief Enable volatile data sharing in setting VDS bit. +/** @brief Enable volatile data sharing in setting VDS bit. * @note When VDS bit is set, the volatile data segment is shared with non-protected - * application code. It can be accessed whatever the Firewall state (opened or closed). + * application code. It can be accessed whatever the Firewall state (opened or closed). * @note This macro can be executed inside a code area protected by the Firewall. * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. - */ -#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE() \ - do { \ - __IO uint32_t tmpreg; \ - SET_BIT(FIREWALL->CR, FW_CR_VDS) ; \ - /* Read bit back to ensure it is taken into account by IP */ \ - /* (introduce proper delay inside macro execution) */ \ - tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ; \ - UNUSED(tmpreg); \ + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE() \ + do { \ + __IO uint32_t tmpreg; \ + SET_BIT(FIREWALL->CR, FW_CR_VDS) ; \ + /* Read bit back to ensure it is taken into account by Peripheral */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ; \ + UNUSED(tmpreg); \ } while(0) -/** @brief Disable volatile data sharing in resetting VDS bit. - * @note When VDS bit is reset, the volatile data segment is not shared and cannot be - * hit by a non protected executable code when the Firewall is closed. If it is +/** @brief Disable volatile data sharing in resetting VDS bit. + * @note When VDS bit is reset, the volatile data segment is not shared and cannot be + * hit by a non protected executable code when the Firewall is closed. If it is * accessed in such a condition, a system reset is generated by the Firewall. - * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed inside a code area protected by the Firewall. * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. - */ -#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE() \ - do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ; \ - /* Read bit back to ensure it is taken into account by IP */ \ - /* (introduce proper delay inside macro execution) */ \ - tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ; \ - UNUSED(tmpreg); \ + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE() \ + do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ; \ + /* Read bit back to ensure it is taken into account by Peripheral */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ; \ + UNUSED(tmpreg); \ } while(0) /** @brief Enable volatile data execution in setting VDE bit. - * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be - * executed whatever the VDE bit value. + * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be + * executed whatever the VDE bit value. * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When - * the Firewall call is closed, a "call gate" entry procedure is required to open + * the Firewall call is closed, a "call gate" entry procedure is required to open * first the Firewall. * @note This macro can be executed inside a code area protected by the Firewall. * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. - */ -#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE() \ - do { \ - __IO uint32_t tmpreg; \ - SET_BIT(FIREWALL->CR, FW_CR_VDE) ; \ - /* Read bit back to ensure it is taken into account by IP */ \ - /* (introduce proper delay inside macro execution) */ \ - tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ; \ - UNUSED(tmpreg); \ + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE() \ + do { \ + __IO uint32_t tmpreg; \ + SET_BIT(FIREWALL->CR, FW_CR_VDE) ; \ + /* Read bit back to ensure it is taken into account by Peripheral */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ; \ + UNUSED(tmpreg); \ } while(0) /** @brief Disable volatile data execution in resetting VDE bit. - * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be - * executed whatever the VDE bit value. + * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be + * executed whatever the VDE bit value. * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot be executed. - * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed inside a code area protected by the Firewall. * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. + * executed only when the Firewall is opened. */ -#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE() \ - do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ; \ - /* Read bit back to ensure it is taken into account by IP */ \ - /* (introduce proper delay inside macro execution) */ \ - tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ; \ - UNUSED(tmpreg); \ - } while(0) +#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE() \ + do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ; \ + /* Read bit back to ensure it is taken into account by Peripheral */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ; \ + UNUSED(tmpreg); \ + } while(0) /** @brief Check whether or not the volatile data segment is shared. @@ -297,7 +281,7 @@ typedef struct * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. + * executed only when the Firewall is opened. * @retval VDS bit setting status (TRUE or FALSE). */ #define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS) @@ -307,7 +291,7 @@ typedef struct * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. + * executed only when the Firewall is opened. * @retval VDE bit setting status (TRUE or FALSE). */ #define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE) @@ -317,7 +301,7 @@ typedef struct * @note This macro can be executed whatever the Firewall state (opened or closed) when * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from * 0, that is, when the non volatile data segment is defined), the macro can be - * executed only when the Firewall is opened. + * executed only when the Firewall is opened. * @retval FPA bit setting status (TRUE or FALSE). */ #define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA) @@ -332,12 +316,12 @@ typedef struct /** @addtogroup FIREWALL_Exported_Functions FIREWALL Exported Functions * @{ */ - + /** @addtogroup FIREWALL_Exported_Functions_Group1 Initialization Functions - * @brief Initialization and Configuration Functions + * @brief Initialization and Configuration Functions * @{ - */ - + */ + /* Initialization functions ********************************/ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init); void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config); @@ -348,19 +332,19 @@ void HAL_FIREWALL_DisablePreArmFlag(void); /** * @} */ - -/** - * @} - */ /** * @} - */ + */ /** * @} - */ - + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c index ec118ec837..8054bfec8d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c @@ -3,23 +3,23 @@ * @file stm32l4xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions - * + Memory Control functions + * + Memory Control functions * + Peripheral Errors functions - * - @verbatim + * + @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. - + [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. + prefetch and cache lines. [..] The FLASH main features are: (+) Flash memory read operations @@ -31,36 +31,36 @@ (+) 8 cache lines of 4*64 bits on D-Code (+) Error code correction (ECC) : Data in flash are 72-bits word (8 bits added per double word) - - + + ##### How to use this driver ##### ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32L4xx devices. - - (#) Flash Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32L4xx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Program functions: double word and fast program (full row programming) (++) There Two modes of programming : (+++) Polling mode using HAL_FLASH_Program() function (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : + + (#) Interrupts and flags management functions : (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() (++) Callback functions are called when the flash operations are finished : HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise HAL_FLASH_OperationErrorCallback() - (++) Get error flag status by calling HAL_GetError() - + (++) Get error flag status by calling HAL_GetError() + (#) Option bytes management functions : (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and HAL_FLASH_OB_Lock() functions (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. In this case, a reset is generated - - [..] + + [..] In addition to these functions, this driver includes a set of macros allowing to handle the following operations: (+) Set the latency @@ -70,34 +70,18 @@ (+) Enable/Disable the Flash power-down during low-power run and sleep modes (+) Enable/Disable the Flash interrupts (+) Monitor the Flash flags status - - @endverbatim + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -119,9 +103,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 #else -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 #endif /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -129,9 +113,16 @@ * @{ */ /** - * @brief Variable used for Program/Erase sectors under interruption + * @brief Variable used for Program/Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = FLASH_PROC_NONE, \ + .Address = 0U, \ + .Bank = FLASH_BANK_1, \ + .Page = 0U, \ + .NbPagesToErase = 0U, \ + .CacheToReactivate = FLASH_CACHE_DISABLED}; /** * @} */ @@ -140,10 +131,6 @@ FLASH_ProcessTypeDef pFlash; /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -extern void FLASH_PageErase(uint32_t Page, uint32_t Banks); -extern void FLASH_FlushCaches(void); -static void FLASH_SetErrorCode(void); static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** @@ -155,37 +142,37 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); * @{ */ -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions * -@verbatim +@verbatim =============================================================================== ##### Programming operation functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to manage the FLASH + This subsection provides a set of functions allowing to manage the FLASH program operations. - + @endverbatim * @{ */ - + /** * @brief Program double word or fast program of a row at a specified address. * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where + * This parameter is the data for the double word program and the address where * are stored the data for the row fast program - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t prog_bit = 0; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -194,13 +181,13 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + if(status == HAL_OK) { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -221,19 +208,23 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); - + /* If it is the last row, the bit will be cleared at the end of the operation */ if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) { prog_bit = FLASH_CR_FSTPG; } } + else + { + /* Nothing to do */ + } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the program operation is completed, disable the PG or FSTPG Bit */ - if (prog_bit != 0) + if (prog_bit != 0U) { CLEAR_BIT(FLASH->CR, prog_bit); } @@ -245,7 +236,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* Process Unlocked */ __HAL_UNLOCK(&pFlash); - return status; + return status; } /** @@ -254,9 +245,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * This parameter can be a value of @ref FLASH_Type_Program * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where + * This parameter is the data for the double word program and the address where * are stored the data for the row fast program - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) @@ -272,7 +263,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -293,7 +284,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; } pFlash.Address = Address; - + /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); @@ -307,8 +298,12 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); } + else + { + /* Nothing to do */ + } - return status; + return status; } /** @@ -318,6 +313,8 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u void HAL_FLASH_IRQHandler(void) { uint32_t tmp_page; + uint32_t error; + FLASH_ProcedureTypeDef procedure; /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); @@ -326,7 +323,7 @@ void HAL_FLASH_IRQHandler(void) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); #endif - + /* Disable the FSTPG Bit only if it is the last row programmed */ if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) { @@ -334,46 +331,46 @@ void HAL_FLASH_IRQHandler(void) } /* Check FLASH operation error flags */ - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif + error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); + error |= (FLASH->ECCR & FLASH_FLAG_ECCC); + + if (error !=0U) { /*Save the error code*/ - FLASH_SetErrorCode(); - + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(error); + /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; /* FLASH error interrupt user callback */ - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) + procedure = pFlash.ProcedureOnGoing; + if(procedure == FLASH_PROC_PAGE_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Page); } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) + else if(procedure == FLASH_PROC_MASS_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Bank); } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) + else if((procedure == FLASH_PROC_PROGRAM) || + (procedure == FLASH_PROC_PROGRAM_LAST)) { HAL_FLASH_OperationErrorCallback(pFlash.Address); } + else + { + HAL_FLASH_OperationErrorCallback(0U); + } /*Stop the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); @@ -384,7 +381,7 @@ void HAL_FLASH_IRQHandler(void) pFlash.NbPagesToErase--; /* Check if there are still pages to erase*/ - if(pFlash.NbPagesToErase != 0) + if(pFlash.NbPagesToErase != 0U) { /* Indicate user which page has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Page); @@ -398,12 +395,12 @@ void HAL_FLASH_IRQHandler(void) { /* No more pages to Erase */ /* Reset Address and stop Erase pages procedure */ - pFlash.Page = 0xFFFFFFFF; + pFlash.Page = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; - + /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Page); } @@ -413,19 +410,24 @@ void HAL_FLASH_IRQHandler(void) /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; - if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) + procedure = pFlash.ProcedureOnGoing; + if(procedure == FLASH_PROC_MASS_ERASE) { /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Bank); } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) + else if((procedure == FLASH_PROC_PROGRAM) || + (procedure == FLASH_PROC_PROGRAM_LAST)) { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Address); } + else + { + /* Nothing to do */ + } /*Clear the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -446,7 +448,7 @@ void HAL_FLASH_IRQHandler(void) * @brief FLASH end of operation interrupt callback. * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page which has been erased + * Page Erase: Page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * Program: Address which was selected for data program * @retval None @@ -458,7 +460,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ + */ } /** @@ -476,22 +478,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ + */ } /** * @} - */ + */ -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the FLASH + This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim @@ -506,19 +508,19 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { status = HAL_ERROR; } } - + return status; } @@ -530,8 +532,8 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); - - return HAL_OK; + + return HAL_OK; } /** @@ -540,7 +542,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { - if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET) + if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); @@ -549,21 +551,21 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) else { return HAL_ERROR; - } - - return HAL_OK; + } + + return HAL_OK; } /** * @brief Lock the FLASH Option Bytes Registers access. - * @retval HAL Status + * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); - - return HAL_OK; + + return HAL_OK; } /** @@ -573,23 +575,23 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); } /** * @} */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time Errors of the FLASH peripheral. @@ -601,12 +603,12 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode: The returned value can be: * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag - * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag + * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag - * @arg HAL_FLASH_ERROR_NONE: No error set + * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag + * @arg HAL_FLASH_ERROR_NONE: No error set * @arg HAL_FLASH_ERROR_OP: FLASH Operation error * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error @@ -621,13 +623,13 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) * @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected */ uint32_t HAL_FLASH_GetError(void) -{ +{ return pFlash.ErrorCode; } /** * @} - */ + */ /** * @} @@ -649,36 +651,32 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - + uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { + uint32_t error; + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart) >= Timeout) { return HAL_TIMEOUT; } - } + } } - - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif + + error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); + error |= (FLASH->ECCR & FLASH_FLAG_ECCD); + + if(error != 0u) { /*Save the error code*/ - FLASH_SetErrorCode(); - + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(error); + return HAL_ERROR; } @@ -688,86 +686,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } - + /* If there is an error flag set */ - return HAL_OK; + return HAL_OK; } -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD; - } - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY; - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PEMPTY); - } -#endif - - /* Clear error programming flags */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); -} - /** * @brief Program double-word (64-bit) at a specified address. * @param Address: specifies the address to be programmed. @@ -781,10 +704,16 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) /* Set PG bit */ SET_BIT(FLASH->CR, FLASH_CR_PG); - - /* Program the double word */ + + /* Program first word */ *(__IO uint32_t*)Address = (uint32_t)Data; - *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32); } /** @@ -795,6 +724,7 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) */ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) { + uint32_t primask_bit; uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW); __IO uint32_t *dest_addr = (__IO uint32_t*)Address; __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; @@ -804,18 +734,22 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) /* Set FSTPG bit */ SET_BIT(FLASH->CR, FLASH_CR_FSTPG); - + /* Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); __disable_irq(); - + /* Program the double word of the row */ do { - *dest_addr++ = *src_addr++; - } while (--row_index != 0); + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); /* Re-enable the interrupts */ - __enable_irq(); + __set_PRIMASK(primask_bit); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h index e05c897baa..ef307b3612 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -50,7 +34,7 @@ /** @addtogroup FLASH * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types @@ -61,17 +45,17 @@ * @brief FLASH Erase structure definition */ typedef struct -{ +{ uint32_t TypeErase; /*!< Mass erase or page erase. This parameter can be a value of @ref FLASH_Type_Erase */ uint32_t Banks; /*!< Select bank to erase. - This parameter must be a value of @ref FLASH_Banks - (FLASH_BANK_BOTH should be used only for mass erase) */ + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled - This parameter must be a value between 0 and (max number of pages in the bank - 1) + This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 255 for 1MB dual bank) */ uint32_t NbPages; /*!< Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ + This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ } FLASH_EraseInitTypeDef; /** @@ -96,16 +80,16 @@ typedef struct uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, - @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, - @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, - @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, + @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). - This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) + This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) and @ref FLASH_OB_PCROP_RDP */ uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). - This parameter must be a value between begin and end of bank + This parameter must be a value between begin and end of bank => Be careful of the bank swapping for the address */ uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of bank */ @@ -114,7 +98,7 @@ typedef struct /** * @brief FLASH Procedure structure definition */ -typedef enum +typedef enum { FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, @@ -126,7 +110,7 @@ typedef enum /** * @brief FLASH Cache structure definition */ -typedef enum +typedef enum { FLASH_CACHE_DISABLED = 0, FLASH_CACHE_ICACHE_ENABLED, @@ -134,8 +118,8 @@ typedef enum FLASH_CACHE_ICACHE_DCACHE_ENABLED } FLASH_CacheTypeDef; -/** - * @brief FLASH handle Structure definition +/** + * @brief FLASH handle Structure definition */ typedef struct { @@ -160,31 +144,32 @@ typedef struct /** @defgroup FLASH_Error FLASH Error * @{ - */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) -#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001) -#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002) -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004) -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) -#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010) -#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020) -#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040) -#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080) -#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100) -#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) -#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) -#endif + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR +#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR +#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR +#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ + defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \ + defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY +#endif /** * @} */ /** @defgroup FLASH_Type_Erase FLASH Erase Type * @{ - */ + */ #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!> 24) /*!< ECC Correction Interrupt source */ /** * @} - */ + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @brief macros to control FLASH features + * @brief macros to control FLASH features * @{ */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__: FLASH Latency * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states * @retval None - */ + */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) /** * @brief Get the FLASH Latency. - * @retval FLASH Latency + * @retval FLASH Latency * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states - */ + */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) /** * @brief Enable the FLASH prefetch buffer. * @retval None - */ + */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) /** @@ -605,30 +600,30 @@ typedef struct /** * @brief Enable the FLASH instruction cache. * @retval none - */ + */ #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Disable the FLASH instruction cache. * @retval none - */ + */ #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Enable the FLASH data cache. * @retval none - */ + */ #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Disable the FLASH data cache. * @retval none - */ + */ #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Reset the FLASH instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. + * @note This function must be used only when the Instruction Cache is disabled. * @retval None */ #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ @@ -637,7 +632,7 @@ typedef struct /** * @brief Reset the FLASH data Cache. - * @note This function must be used only when the data Cache is disabled. + * @note This function must be used only when the data Cache is disabled. * @retval None */ #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ @@ -667,50 +662,50 @@ typedef struct /** * @brief Enable the FLASH power down during Low-Power sleep mode * @retval none - */ + */ #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @brief Disable the FLASH power down during Low-Power sleep mode * @retval none - */ + */ #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @} - */ + */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros * @brief macros to handle FLASH interrupts * @{ - */ + */ /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt + * @param __INTERRUPT__: FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while(0) /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt + * @param __INTERRUPT__: FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt + * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while(0) /** @@ -720,7 +715,7 @@ typedef struct * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag @@ -728,14 +723,14 @@ typedef struct * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected * @retval The new state of FLASH_FLAG (SET or RESET). */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) /** @@ -745,7 +740,7 @@ typedef struct * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag @@ -758,18 +753,18 @@ typedef struct * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags * @retval None */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ - if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ } while(0) /** * @} - */ + */ /* Include FLASH HAL Extended module */ #include "stm32l4xx_hal_flash_ex.h" #include "stm32l4xx_hal_flash_ramfunc.h" -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ @@ -782,7 +777,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uin HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** @@ -816,27 +811,51 @@ uint32_t HAL_FLASH_GetError(void); * @} */ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + /* Private constants --------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) - + #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) +#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) +#elif defined (STM32L412xx) || defined (STM32L422xx) +#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) #else -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) #endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) + defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \ + defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) #else #define FLASH_BANK_SIZE (FLASH_SIZE) #endif @@ -852,18 +871,18 @@ uint32_t HAL_FLASH_GetError(void); /** * @} */ - + /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \ + defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2) || \ ((BANK) == FLASH_BANK_BOTH)) @@ -878,44 +897,44 @@ uint32_t HAL_FLASH_GetError(void); #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ - ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) + ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) #else -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ - ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ - ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ - ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ - ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ + ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ + ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ + ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ + ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) #endif -#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) +#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ - ((PAGE) < 256))))) +#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ + ((PAGE) < 256U))))) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((PAGE) < 256)))) +#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ + ((PAGE) < 256U)))) #else -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \ - ((PAGE) < 128)))) +#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ + ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ + ((PAGE) < 128U)))) #endif #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \ + defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) #else @@ -927,11 +946,11 @@ uint32_t HAL_FLASH_GetError(void); ((LEVEL) == OB_RDP_LEVEL_2)*/) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) #else -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) #endif #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ @@ -953,8 +972,8 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \ + defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) @@ -962,18 +981,18 @@ uint32_t HAL_FLASH_GetError(void); #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) -#endif - +#endif + #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ + defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \ + defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) @@ -999,19 +1018,19 @@ uint32_t HAL_FLASH_GetError(void); #endif /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c index 1ba98a0c1b..157fdfff37 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c @@ -3,74 +3,58 @@ * @file stm32l4xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the FLASH extended peripheral: * + Extended programming operations functions - * - @verbatim + * + @verbatim ============================================================================== ##### Flash Extended features ##### ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32L4xx - devices contains the following additional features - + + [..] Comparing to other previous devices, the FLASH interface for STM32L4xx + devices contains the following additional features + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write capability (RWW) - (+) Dual bank memory organization + (+) Dual bank memory organization (+) PCROP protection for all banks - + ##### How to use this driver ##### ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory + [..] This driver provides functions to configure and program the FLASH memory of all STM32L4xx devices. It includes - (#) Flash Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Erase function: Erase page, erase all sectors (++) There are two modes of erase : (+++) Polling Mode using HAL_FLASHEx_Erase() (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : (++) Set/Reset the write protection (++) Set the Read protection Level (++) Program the user Option Bytes (++) Configure the PCROP protection - + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : (++) Get the value of a write protection area (++) Know if the read protection is activated (++) Get the value of the user Option Bytes (++) Get the value of a PCROP area - - @endverbatim + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -90,25 +74,14 @@ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_PageErase(uint32_t Page, uint32_t Banks); static void FLASH_MassErase(uint32_t Banks); -void FLASH_FlushCaches(void); static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); @@ -124,19 +97,19 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC /* Exported functions -------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ - */ + */ /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions + * @brief Extended IO operation functions * -@verbatim +@verbatim =============================================================================== ##### Extended programming operation functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to manage the Extended FLASH + This subsection provides a set of functions allowing to manage the Extended FLASH programming operations Operations. - + @endverbatim * @{ */ @@ -144,17 +117,17 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC * @brief Perform a mass erase or erase the specified FLASH memory pages. * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * - * @param[out] PageError : pointer to variable that contains the configuration - * information on faulty page in case of error (0xFFFFFFFF means that all + * + * @param[out] PageError : pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all * the pages have been correctly erased) - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t page_index = 0; + HAL_StatusTypeDef status; + uint32_t page_index; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -170,12 +143,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -186,7 +159,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -213,13 +186,13 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t #else /* If the erase operation is completed, disable the MER1 Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); -#endif +#endif } else { /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; - + *PageError = 0xFFFFFFFFU; + for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) { FLASH_PageErase(page_index, pEraseInit->Banks); @@ -238,7 +211,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } } } - + /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); } @@ -253,7 +226,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) @@ -269,12 +242,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -285,7 +258,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -317,7 +290,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /*Erase 1st page and wait for IT */ FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); } - + return status; } @@ -325,34 +298,34 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) * @brief Program Option bytes. * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_OK; - + /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) { /* Configure of Write protection on the selected area */ if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) { status = HAL_ERROR; } - + } - + /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) { /* Configure the Read protection level */ if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) @@ -360,9 +333,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) status = HAL_ERROR; } } - + /* User Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) { /* Configure the user option bytes */ if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) @@ -370,9 +343,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) status = HAL_ERROR; } } - + /* PCROP Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET) + if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) { if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) { @@ -392,11 +365,11 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /** * @brief Get the Option bytes configuration. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the * configuration information. - * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate + * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate * which area is requested for the WRP and PCROP, else no information will be returned - * + * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) @@ -416,20 +389,20 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /* Get write protection on the selected area */ FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); } - + /* Get Read protection level */ pOBInit->RDPLevel = FLASH_OB_GetRDP(); - + /* Get the user option bytes */ pOBInit->USERConfig = FLASH_OB_GetUser(); - + #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) #else if(pOBInit->PCROPConfig == FLASH_BANK_1) -#endif +#endif { pOBInit->OptionType |= OPTIONBYTE_PCROP; /* Get the Proprietary code readout protection */ @@ -439,7 +412,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /** * @} - */ + */ #if defined (FLASH_CFGR_LVEN) /** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions @@ -472,7 +445,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) */ HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -490,7 +463,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) { /* Configure the LVEN bit */ MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); - + /* Check that the bit has been correctly configured */ if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) { @@ -536,23 +509,23 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) static void FLASH_MassErase(uint32_t Banks) { #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != RESET) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) #endif { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Set the Mass Erase Bit for the bank 1 if requested */ - if((Banks & FLASH_BANK_1) != RESET) + if((Banks & FLASH_BANK_1) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER1); } - + #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Set the Mass Erase Bit for the bank 2 if requested */ - if((Banks & FLASH_BANK_2) != RESET) + if((Banks & FLASH_BANK_2) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER2); } @@ -572,7 +545,7 @@ static void FLASH_MassErase(uint32_t Banks) /** * @brief Erase the specified FLASH memory page. * @param Page: FLASH page to erase - * This parameter must be a value between 0 and (max number of pages in the bank - 1) + * This parameter must be a value between 0 and (max number of pages in the bank - 1) * @param Banks: Bank(s) where the page will be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Page in bank 1 to be erased @@ -588,7 +561,7 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } @@ -597,7 +570,7 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) { assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); - if((Banks & FLASH_BANK_1) != RESET) + if((Banks & FLASH_BANK_1) != 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } @@ -606,10 +579,13 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) SET_BIT(FLASH->CR, FLASH_CR_BKER); } } +#else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); #endif /* Proceed to erase the page */ - MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB))); + MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos)); SET_BIT(FLASH->CR, FLASH_CR_PER); SET_BIT(FLASH->CR, FLASH_CR_STRT); } @@ -620,26 +596,28 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) */ void FLASH_FlushCaches(void) { + FLASH_CacheTypeDef cache = pFlash.CacheToReactivate; + /* Flush instruction cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) + if((cache == FLASH_CACHE_ICACHE_ENABLED) || + (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Reset instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); /* Enable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); } - + /* Flush data cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) + if((cache == FLASH_CACHE_DCACHE_ENABLED) || + (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Reset data cache */ __HAL_FLASH_DATA_CACHE_RESET(); /* Enable data cache */ __HAL_FLASH_DATA_CACHE_ENABLE(); } - + /* Reset internal variable */ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } @@ -647,33 +625,33 @@ void FLASH_FlushCaches(void) /** * @brief Configure the write protection of the desired pages. * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase Flash memory if the CPU debug - * features are connected (JTAG or single wire) or boot code is being - * executed from RAM or System flash, even if WRP is not activated. - * @note To configure the WRP options, the option lock bit OPTLOCK must be + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @note To configure the WRP options, the option lock bit OPTLOCK must be * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the WRP options, the option bytes must be reloaded + * @note To validate the WRP options, the option bytes must be reloaded * through the call of the HAL_FLASH_OB_Launch() function. * * @param WRPArea: specifies the area to be configured. * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices) - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices) + * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A + * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B + * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices) + * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices) * * @param WRPStartOffset: specifies the start page of the write protected area - * This parameter can be page number between 0 and (max number of pages in the bank - 1) + * This parameter can be page number between 0 and (max number of pages in the bank - 1) * * @param WRDPEndOffset: specifies the end page of the write protected area - * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) + * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) * * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_WRPAREA(WRPArea)); @@ -688,12 +666,12 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO /* Configure the write protected area */ if(WRPArea == OB_WRPAREA_BANK1_AREAA) { - MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), + MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), (WRPStartOffset | (WRDPEndOffset << 16))); } else if(WRPArea == OB_WRPAREA_BANK1_AREAB) { - MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), + MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), (WRPStartOffset | (WRDPEndOffset << 16))); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ @@ -701,65 +679,69 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(WRPArea == OB_WRPAREA_BANK2_AREAA) { - MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), + MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), (WRPStartOffset | (WRDPEndOffset << 16))); } else if(WRPArea == OB_WRPAREA_BANK2_AREAB) { - MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), + MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), (WRPStartOffset | (WRDPEndOffset << 16))); } #endif - + else + { + /* Nothing to do */ + } + /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the option byte program operation is completed, disable the OPTSTRT Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); } - + return status; } /** * @brief Set the read protection level. - * - * @note To configure the RDP level, the option lock bit OPTLOCK must be + * + * @note To configure the RDP level, the option lock bit OPTLOCK must be * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the RDP level, the option bytes must be reloaded + * @note To validate the RDP level, the option bytes must be reloaded * through the call of the HAL_FLASH_OB_Launch() function. - * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible * to go back to level 1 or 0 !!! - * + * * @param RDPLevel: specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory * @arg OB_RDP_LEVEL_2: Full chip protection - * + * * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(RDPLevel)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Configure the RDP level in the option bytes register */ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); - + /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); @@ -767,114 +749,114 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); } - return status; + return status; } /** - * @brief Program the FLASH User Option Byte. - * + * @brief Program the FLASH User Option Byte. + * * @note To configure the user option bytes, the option lock bit OPTLOCK must * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the user option bytes, the option bytes must be reloaded + * @note To validate the user option bytes, the option bytes must be reloaded * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param UserType: The FLASH User Option Bytes to be modified - * @param UserConfig: The FLASH User Option Bytes values: + * + * @param UserType: The FLASH User Option Bytes to be modified + * @param UserConfig: The FLASH User Option Bytes values: * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16), - * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), - * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). - * + * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), + * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). + * * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) { uint32_t optr_reg_val = 0; uint32_t optr_reg_mask = 0; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_USER_TYPE(UserType)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { - if((UserType & OB_USER_BOR_LEV) != RESET) + { + if((UserType & OB_USER_BOR_LEV) != 0U) { /* BOR level option byte should be modified */ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); - + /* Set value and mask for BOR level option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); optr_reg_mask |= FLASH_OPTR_BOR_LEV; } - if((UserType & OB_USER_nRST_STOP) != RESET) + if((UserType & OB_USER_nRST_STOP) != 0U) { /* nRST_STOP option byte should be modified */ assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); - + /* Set value and mask for nRST_STOP option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); optr_reg_mask |= FLASH_OPTR_nRST_STOP; } - if((UserType & OB_USER_nRST_STDBY) != RESET) + if((UserType & OB_USER_nRST_STDBY) != 0U) { /* nRST_STDBY option byte should be modified */ assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); - + /* Set value and mask for nRST_STDBY option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); optr_reg_mask |= FLASH_OPTR_nRST_STDBY; } - if((UserType & OB_USER_nRST_SHDW) != RESET) + if((UserType & OB_USER_nRST_SHDW) != 0U) { /* nRST_SHDW option byte should be modified */ assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); - + /* Set value and mask for nRST_SHDW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); optr_reg_mask |= FLASH_OPTR_nRST_SHDW; } - if((UserType & OB_USER_IWDG_SW) != RESET) + if((UserType & OB_USER_IWDG_SW) != 0U) { /* IWDG_SW option byte should be modified */ assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); - + /* Set value and mask for IWDG_SW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); optr_reg_mask |= FLASH_OPTR_IWDG_SW; } - if((UserType & OB_USER_IWDG_STOP) != RESET) + if((UserType & OB_USER_IWDG_STOP) != 0U) { /* IWDG_STOP option byte should be modified */ assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); - + /* Set value and mask for IWDG_STOP option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); optr_reg_mask |= FLASH_OPTR_IWDG_STOP; } - if((UserType & OB_USER_IWDG_STDBY) != RESET) + if((UserType & OB_USER_IWDG_STDBY) != 0U) { /* IWDG_STDBY option byte should be modified */ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); - + /* Set value and mask for IWDG_STDBY option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; } - if((UserType & OB_USER_WWDG_SW) != RESET) + if((UserType & OB_USER_WWDG_SW) != 0U) { /* WWDG_SW option byte should be modified */ assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); - + /* Set value and mask for WWDG_SW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); optr_reg_mask |= FLASH_OPTR_WWDG_SW; @@ -883,97 +865,97 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_BFB2) != RESET) + if((UserType & OB_USER_BFB2) != 0U) { /* BFB2 option byte should be modified */ assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); - + /* Set value and mask for BFB2 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); optr_reg_mask |= FLASH_OPTR_BFB2; } - if((UserType & OB_USER_DUALBANK) != RESET) + if((UserType & OB_USER_DUALBANK) != 0U) { #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* DUALBANK option byte should be modified */ assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M)); - + /* Set value and mask for DUALBANK option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M); optr_reg_mask |= FLASH_OPTR_DB1M; #else /* DUALBANK option byte should be modified */ assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); - + /* Set value and mask for DUALBANK option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); optr_reg_mask |= FLASH_OPTR_DUALBANK; #endif } #endif - - if((UserType & OB_USER_nBOOT1) != RESET) + + if((UserType & OB_USER_nBOOT1) != 0U) { /* nBOOT1 option byte should be modified */ assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); - + /* Set value and mask for nBOOT1 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); optr_reg_mask |= FLASH_OPTR_nBOOT1; } - if((UserType & OB_USER_SRAM2_PE) != RESET) + if((UserType & OB_USER_SRAM2_PE) != 0U) { /* SRAM2_PE option byte should be modified */ assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); - + /* Set value and mask for SRAM2_PE option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE); optr_reg_mask |= FLASH_OPTR_SRAM2_PE; } - if((UserType & OB_USER_SRAM2_RST) != RESET) + if((UserType & OB_USER_SRAM2_RST) != 0U) { /* SRAM2_RST option byte should be modified */ assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); - + /* Set value and mask for SRAM2_RST option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); optr_reg_mask |= FLASH_OPTR_SRAM2_RST; } -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ + defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_nSWBOOT0) != RESET) + if((UserType & OB_USER_nSWBOOT0) != 0U) { /* nSWBOOT0 option byte should be modified */ assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); - + /* Set value and mask for nSWBOOT0 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); optr_reg_mask |= FLASH_OPTR_nSWBOOT0; } - if((UserType & OB_USER_nBOOT0) != RESET) + if((UserType & OB_USER_nBOOT0) != 0U) { /* nBOOT0 option byte should be modified */ assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); - + /* Set value and mask for nBOOT0 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); optr_reg_mask |= FLASH_OPTR_nBOOT0; } #endif - + /* Configure the option bytes register */ MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); - + /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); @@ -981,33 +963,33 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); } - return status; + return status; } /** * @brief Configure the Proprietary code readout protection of the desired addresses. * - * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * @note To configure the PCROP options, the option lock bit OPTLOCK must be * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the PCROP options, the option bytes must be reloaded + * @note To validate the PCROP options, the option bytes must be reloaded * through the call of the HAL_FLASH_OB_Launch() function. * * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option). - * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 + * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE * * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection - * This parameter can be an address between begin and end of the bank + * This parameter can be an address between begin and end of the bank * * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection - * This parameter can be an address between PCROPStartAddr and end of the bank + * This parameter can be an address between PCROPStartAddr and end of the bank * * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t reg_value = 0; + HAL_StatusTypeDef status; + uint32_t reg_value; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -1030,7 +1012,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) + if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; @@ -1043,16 +1025,16 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR #else bank1_addr = FLASH_BASE; #endif - + #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { /* Configure the Proprietary code readout protection */ if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); - + reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } @@ -1060,10 +1042,14 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR { reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); - + reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } + else + { + /* Nothing to do */ + } } else #endif @@ -1073,7 +1059,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR { reg_value = ((PCROPStartAddr - bank1_addr) >> 3); MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); - + reg_value = ((PCROPEndAddr - bank1_addr) >> 3); MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } @@ -1084,25 +1070,29 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR { reg_value = ((PCROPStartAddr - bank2_addr) >> 3); MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); - + reg_value = ((PCROPEndAddr - bank2_addr) >> 3); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } #endif + else + { + /* Nothing to do */ + } } - + MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); - + /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the option byte program operation is completed, disable the OPTSTRT Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); } - + return status; } @@ -1111,15 +1101,15 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR * * @param[in] WRPArea: specifies the area to be returned. * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices) - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices) + * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A + * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B + * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices) + * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices) * - * @param[out] WRPStartOffset: specifies the address where to copied the start page + * @param[out] WRPStartOffset: specifies the address where to copied the start page * of the write protected area * - * @param[out] WRDPEndOffset: specifies the address where to copied the end page of + * @param[out] WRDPEndOffset: specifies the address where to copied the end page of * the write protected area * * @retval None @@ -1151,6 +1141,10 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_ *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16); } #endif + else + { + /* Nothing to do */ + } } /** @@ -1163,8 +1157,9 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_ */ static uint32_t FLASH_OB_GetRDP(void) { - if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && - (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2)) + uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) { return (OB_RDP_LEVEL_1); } @@ -1176,21 +1171,21 @@ static uint32_t FLASH_OB_GetRDP(void) /** * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: + * @retval The FLASH User Option Bytes values: * For STM32L47x/STM32L48x devices : - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), - * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), - * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). + * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), + * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), + * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). * For STM32L43x/STM32L44x devices : * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), - * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), - * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). + * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), + * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). */ static uint32_t FLASH_OB_GetUser(void) { uint32_t user_config = READ_REG(FLASH->OPTR); CLEAR_BIT(user_config, FLASH_OPTR_RDP); - + return user_config; } @@ -1198,32 +1193,32 @@ static uint32_t FLASH_OB_GetUser(void) * @brief Return the FLASH Write Protection Option Bytes value. * * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option). - * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 + * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE * - * @param PCROPStartAddr [out]: specifies the address where to copied the start address + * @param PCROPStartAddr [out]: specifies the address where to copied the start address * of the Proprietary code readout protection * - * @param PCROPEndAddr [out]: specifies the address where to copied the end address of + * @param PCROPEndAddr [out]: specifies the address where to copied the end address of * the Proprietary code readout protection * * @retval None */ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr) { - uint32_t reg_value = 0; + uint32_t reg_value; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) uint32_t bank2_addr; #endif - + #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) + if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; @@ -1236,25 +1231,29 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, #else bank1_addr = FLASH_BASE; #endif - + #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; - + reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); - *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; + *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU; } else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; - + reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); - *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; + *PCROPEndAddr = (reg_value << 4) + FLASH_BASE + 0xFU;; + } + else + { + /* Nothing to do */ } } else @@ -1264,9 +1263,9 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, { reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); *PCROPStartAddr = (reg_value << 3) + bank1_addr; - + reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); - *PCROPEndAddr = (reg_value << 3) + bank1_addr; + *PCROPEndAddr = (reg_value << 3) + bank1_addr + 0x7U; } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -1275,28 +1274,32 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); *PCROPStartAddr = (reg_value << 3) + bank2_addr; - + reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); - *PCROPEndAddr = (reg_value << 3) + bank2_addr; + *PCROPEndAddr = (reg_value << 3) + bank2_addr + 0x7U; } #endif + else + { + /* Nothing to do */ + } } - + *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); } /** * @} - */ + */ /** * @} - */ + */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h index 63d5c9fcd1..594ff33f01 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -102,6 +86,16 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE); */ #endif /* FLASH_CFGR_LVEN */ +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_PageErase(uint32_t Page, uint32_t Banks); +void FLASH_FlushCaches(void); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c index fbd9462a1a..efb3990592 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c @@ -3,7 +3,7 @@ * @file stm32l4xx_hal_flash_ramfunc.c * @author MCD Application Team * @brief FLASH RAMFUNC driver. - * This file provides a Flash firmware functions which should be + * This file provides a Flash firmware functions which should be * executed from internal SRAM * + FLASH HalfPage Programming * + FLASH Power Down in Run mode @@ -11,15 +11,15 @@ * @verbatim ============================================================================== ##### Flash RAM functions ##### - ============================================================================== + ============================================================================== *** ARM Compiler *** -------------------- - [..] RAM functions are defined using the toolchain options. + [..] RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the + Available memory areas are declared in the 'Target' tab of the Options for Target' dialog. *** ICCARM Compiler *** @@ -30,37 +30,21 @@ -------------------- [..] RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". - + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -89,13 +73,13 @@ extern FLASH_ProcessTypeDef pFlash; * @{ */ -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions - * @brief Data transfers functions +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### ramfunc functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions that should be executed from RAM. @@ -112,9 +96,9 @@ __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) { /* Enable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_ENABLE(); - + return HAL_OK; - + } /** @@ -127,33 +111,33 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) /* Disable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_DISABLE(); - return HAL_OK; + return HAL_OK; } #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** - * @brief Program the FLASH DBANK User Option Byte. - * + * @brief Program the FLASH DBANK User Option Byte. + * * @note To configure the user option bytes, the option lock bit OPTLOCK must * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To modify the DBANK option byte, no PCROP region should be defined. + * @note To modify the DBANK option byte, no PCROP region should be defined. * To deactivate PCROP, user should perform RDP changing - * - * @param DBankConfig: The FLASH DBANK User Option Byte value. + * + * @param DBankConfig: The FLASH DBANK User Option Byte value. * This parameter can be one of the following values: * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data - * + * * @retval HAL status */ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) { register uint32_t count, reg; HAL_StatusTypeDef status = HAL_ERROR; - + /* Process Locked */ __HAL_LOCK(&pFlash); - + /* Check if the PCROP is disabled */ reg = FLASH->PCROP1SR; if (reg > FLASH->PCROP1ER) @@ -163,85 +147,86 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) { /* Disable Flash prefetch */ __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); - - if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - + /* Flush Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); } - - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable Flash data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); - + /* Flush Flash data cache */ __HAL_FLASH_DATA_CACHE_RESET(); } - + /* Disable WRP zone 1 of 1st bank if needed */ reg = FLASH->WRP1AR; - if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_STRT)) <= - ((reg & FLASH_WRP1AR_WRP1A_END) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_END))) + if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <= + ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) { MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); } - + /* Disable WRP zone 2 of 1st bank if needed */ reg = FLASH->WRP1BR; - if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_STRT)) <= - ((reg & FLASH_WRP1BR_WRP1B_END) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_END))) + if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <= + ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) { MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); } - + /* Disable WRP zone 1 of 2nd bank if needed */ reg = FLASH->WRP2AR; - if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_STRT)) <= - ((reg & FLASH_WRP2AR_WRP2A_END) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_END))) + if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <= + ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) { MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); } - + /* Disable WRP zone 2 of 2nd bank if needed */ reg = FLASH->WRP2BR; - if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_STRT)) <= - ((reg & FLASH_WRP2BR_WRP2B_END) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_END))) + if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <= + ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) { MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); } - + /* Modify the DBANK user option byte */ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); - + /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - + /* Wait for last operation to be completed */ /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ - count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8 / 1000); + count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U); do { - if (count-- == 0) + if (count == 0U) { break; } + count--; } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); - + /* If the option byte program operation is completed, disable the OPTSTRT Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); } } - + /* Process Unlocked */ __HAL_UNLOCK(&pFlash); - + return status; } #endif @@ -252,11 +237,11 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) /** * @} - */ + */ #endif /* HAL_FLASH_MODULE_ENABLED */ - + /** * @} */ @@ -265,7 +250,7 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) * @} */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h index b0988b0278..a725330b1d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_FLASH_RAMFUNC_H @@ -50,43 +34,10 @@ /** @addtogroup FLASH_RAMFUNC * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_RAMFUNC_Exported_Functions * @{ @@ -103,15 +54,15 @@ __RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); #endif /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c index 1a8dd03657..11c7697cb2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c @@ -53,33 +53,68 @@ HAL_NVIC_DisableIRQ(). (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function. + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_GFXMMU_RegisterCallback() to register a user callback. + + [..] + Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + + [..] + By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples HAL_GFXMMU_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init + and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit + or HAL_GFXMMU_Init function. + + [..] + When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -150,8 +185,20 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address)); assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation)); +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + + /* Call GFXMMU MSP init function */ + if(hgfxmmu->MspInitCallback == NULL) + { + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + } + hgfxmmu->MspInitCallback(hgfxmmu); +#else /* Call GFXMMU MSP init function */ HAL_GFXMMU_MspInit(hgfxmmu); +#endif /* Configure blocks per line and interrupts parameters on GFXMMU_CR register */ hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | @@ -206,7 +253,15 @@ HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu) GFXMMU_CR_AMEIE); /* Call GFXMMU MSP de-init function */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + if(hgfxmmu->MspDeInitCallback == NULL) + { + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + } + hgfxmmu->MspDeInitCallback(hgfxmmu); +#else HAL_GFXMMU_MspDeInit(hgfxmmu); +#endif /* Set GFXMMU to reset state */ hgfxmmu->State = HAL_GFXMMU_STATE_RESET; @@ -245,6 +300,150 @@ __weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) */ } +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user GFXMMU callback + * to be used instead of the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if(HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = pCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user GFXMMU callback. + * GFXMMU callback is redirected to the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ + /** * @} */ @@ -403,7 +602,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU *((uint32_t *)lutxl_address) = (lutLine->LineStatus | (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) | (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET)); - *((uint32_t *)lutxh_address) = lutLine->LineOffset; + *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset; } else { @@ -473,7 +672,11 @@ void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu) hgfxmmu->ErrorCode |= error; /* Call GFXMMU error callback */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + hgfxmmu->ErrorCallback(hgfxmmu); +#else HAL_GFXMMU_ErrorCallback(hgfxmmu); +#endif } } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h index 7c8e6622b3..289b4500a9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_GFXMMU_H -#define __STM32L4xx_HAL_GFXMMU_H +#ifndef STM32L4xx_HAL_GFXMMU_H +#define STM32L4xx_HAL_GFXMMU_H #ifdef __cplusplus extern "C" { @@ -105,12 +89,21 @@ typedef struct /** * @brief GFXMMU handle structure definition */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +typedef struct __GFXMMU_HandleTypeDef +#else typedef struct +#endif { GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */ GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */ HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */ __IO uint32_t ErrorCode; /*!< GFXMMU error code */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + void (*ErrorCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */ + void (*MspInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */ + void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */ +#endif }GFXMMU_HandleTypeDef; /** @@ -132,6 +125,23 @@ typedef struct LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */ }GFXMMU_LutLineTypeDef; +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief GFXMMU callback ID enumeration definition + */ +typedef enum +{ + HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID */ + HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID */ + HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID */ +}HAL_GFXMMU_CallbackIDTypeDef; + +/** + * @brief GFXMMU callback pointer definition + */ +typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu); +#endif + /** * @} */ @@ -172,6 +182,9 @@ typedef struct #define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */ #define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */ #define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /** * @} */ @@ -199,7 +212,15 @@ typedef struct * @param __HANDLE__ GFXMMU handle. * @retval None */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) +#endif /** * @} @@ -219,6 +240,14 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu); HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/* GFXMMU callbacks register/unregister functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID); +#endif /** * @} */ @@ -301,6 +330,6 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); } #endif -#endif /* __STM32L4xx_HAL_GFXMMU_H */ +#endif /* STM32L4xx_HAL_GFXMMU_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c index 280eb31cfc..1e79d4028d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c @@ -74,7 +74,7 @@ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). @@ -91,29 +91,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -129,6 +113,12 @@ * @brief GPIO HAL module driver * @{ */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ #ifdef HAL_GPIO_MODULE_ENABLED @@ -137,28 +127,21 @@ /** @defgroup GPIO_Private_Defines GPIO Private Defines * @{ */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define ANALOG_MODE ((uint32_t)0x00000008) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +#define GPIO_MODE (0x00000003u) +#define ANALOG_MODE (0x00000008u) +#define EXTI_MODE (0x10000000u) +#define GPIO_MODE_IT (0x00010000u) +#define GPIO_MODE_EVT (0x00020000u) +#define RISING_EDGE (0x00100000u) +#define FALLING_EDGE (0x00200000u) +#define GPIO_OUTPUT_TYPE (0x00000010u) -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_NUMBER (16u) /** * @} */ - + /* Private macros ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -/** - * @} - */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -167,7 +150,7 @@ * @{ */ -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -188,9 +171,9 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -199,12 +182,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != RESET) + while (((GPIO_Init->Pin) >> position) != 0x00u) { /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); + iocurrent = (GPIO_Init->Pin) & (1uL << position); - if(iocurrent) + if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ @@ -213,18 +196,18 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - + /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ @@ -235,14 +218,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + temp |= (GPIO_Init->Speed << (position * 2u)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); GPIOx->OTYPER = temp; } @@ -262,8 +245,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ @@ -273,14 +256,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; + temp = SYSCFG->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + SYSCFG->EXTICR[position >> 2u] = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { temp |= iocurrent; @@ -288,7 +271,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) EXTI->IMR1 = temp; temp = EXTI->EMR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { temp |= iocurrent; @@ -297,7 +280,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { temp |= iocurrent; @@ -305,7 +288,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) EXTI->RTSR1 = temp; temp = EXTI->FTSR1; - temp &= ~((uint32_t)iocurrent); + temp &= ~(iocurrent); if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { temp |= iocurrent; @@ -313,7 +296,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) EXTI->FTSR1 = temp; } } - + position++; } } @@ -322,70 +305,68 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while ((GPIO_Pin >> position) != RESET) + while ((GPIO_Pin >> position) != 0x00u) { /* Get current io position */ - iocurrent = (GPIO_Pin) & (1U << position); + iocurrent = (GPIO_Pin) & (1uL << position); - if (iocurrent) + if (iocurrent != 0x00u) { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + tmp &= (0x0FuL << (4u * (position & 0x03u))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FuL << (4u * (position & 0x03u)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + } + /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2)); + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - /* Deactivate the Control bit of Analog mode for the current IO */ GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position); - #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) - { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; - - /* Clear EXTI line configuration */ - EXTI->IMR1 &= ~((uint32_t)iocurrent); - EXTI->EMR1 &= ~((uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~((uint32_t)iocurrent); - EXTI->FTSR1 &= ~((uint32_t)iocurrent); - } } - + position++; } } @@ -394,7 +375,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. * @verbatim @@ -410,7 +391,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @brief Read the specified input port pin. * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -420,7 +401,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) { bitstatus = GPIO_PIN_SET; } @@ -438,10 +419,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -465,8 +446,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggle the specified GPIO pin. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the pin to be toggled. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family + * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -474,7 +455,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - GPIOx->ODR ^= GPIO_Pin; + if ((GPIOx->ODR & GPIO_Pin) != 0x00u) + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } } /** @@ -483,8 +471,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bits to be locked. + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family + * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ @@ -504,10 +492,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; - /* Read LCKK bit*/ + /* Read LCKK register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + /* Read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) { return HAL_OK; } @@ -519,13 +508,13 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h index 9f4bbac544..a1982974b8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -74,7 +58,7 @@ typedef struct uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed */ - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ }GPIO_InitTypeDef; @@ -83,7 +67,7 @@ typedef struct */ typedef enum { - GPIO_PIN_RESET = 0, + GPIO_PIN_RESET = 0U, GPIO_PIN_SET }GPIO_PinState; /** @@ -115,7 +99,7 @@ typedef enum #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ /** * @} */ @@ -130,19 +114,19 @@ typedef enum * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ -#define GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B) /*!< Analog Mode for ADC conversion */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG_ADC_CONTROL (0x0000000Bu) /*!< Analog Mode for ADC conversion */ +#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -151,10 +135,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 5 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< range up to 5 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ /** * @} */ @@ -163,9 +147,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ +#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ /** * @} */ @@ -178,7 +162,7 @@ typedef enum /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ - + /** * @brief Check whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. @@ -229,8 +213,8 @@ typedef enum */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ @@ -261,16 +245,16 @@ typedef enum /* Include GPIO HAL Extended module */ #include "stm32l4xx_hal_gpio_ex.h" -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ -/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @{ */ - + /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); @@ -279,10 +263,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); * @} */ -/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions * @{ */ - + /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); @@ -301,12 +285,12 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h index 63c69cb9e0..703ef21b74 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -63,6 +47,100 @@ * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) +/*--------------STM32L412xx/STM32L422xx---*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ + + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* STM32L412xx || STM32L422xx */ + #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) /*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/ /** @@ -682,7 +760,7 @@ */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_DSI ((uint8_t)0x0C) /* DSI Alternate Function mapping */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ @@ -716,7 +794,7 @@ /** * @} - */ + */ /** * @} @@ -730,69 +808,78 @@ /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL : 7uL) + +#endif /* STM32L412xx || STM32L422xx */ + #if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 7uL) #endif /* STM32L431xx || STM32L433xx || STM32L443xx */ #if defined(STM32L432xx) || defined(STM32L442xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL : 7uL) #endif /* STM32L432xx || STM32L442xx */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 7uL) #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U : 7U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL : 7uL) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ #if defined(STM32L496xx) || defined(STM32L4A6xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL :\ + ((__GPIOx__) == (GPIOH))? 7uL : 8uL) #endif /* STM32L496xx || STM32L4A6xx */ #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :\ + ((__GPIOx__) == (GPIOG))? 6uL :\ + ((__GPIOx__) == (GPIOH))? 7uL : 8uL) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -804,7 +891,7 @@ * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c index 474e3a5c21..0b16302fe6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c @@ -3,22 +3,22 @@ * @file stm32l4xx_hal_hash.c * @author MCD Application Team * @brief HASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: * + Initialization and de-initialization methods * + HASH or HMAC processing in polling mode * + HASH or HMAC processing in interrupt mode * + HASH or HMAC processing in DMA mode * + Peripheral State methods - * + HASH or HMAC processing suspension/resumption - * + * + HASH or HMAC processing suspension/resumption + * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] The HASH HAL driver can be used as follows: - + (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): (##) Enable the HASH interface clock using __HASH_CLK_ENABLE() (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT()) @@ -26,7 +26,7 @@ (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA()) - (+++) Enable the DMAx interface clock using + (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE() (+++) Configure and enable one DMA stream to manage data transfer from memory to peripheral (input stream). Managing data transfer from @@ -35,13 +35,13 @@ using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Stream: use - HAL_NVIC_SetPriority() and + HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - + (#)Initialize the HASH HAL using HAL_HASH_Init(). This function: (##) resorts to HAL_HASH_MspInit() for low-level initialization, (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit. - + (#)Three processing schemes are available: (##) Polling mode: processing APIs are blocking functions i.e. they process the data and wait till the digest computation is finished, @@ -51,143 +51,212 @@ e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC (##) DMA mode: processing APIs are not blocking functions and the CPU is not used for data transfer i.e. the data transfer is ensured by DMA, - e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA() - for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish() + e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA() + for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish() is then required to retrieve the digest. - - (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is - initialized and processes the buffer fed in input. When the input data have all been - fed to the IP, the digest computation can start. - - (#)Multi-buffer processing is possible in polling and DMA mode. - (##) In polling mode, only multi-buffer HASH processing is possible. - API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as - well the computed digest. - - (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. + (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is + initialized and processes the buffer fed in input. When the input data have all been + fed to the Peripheral, the digest computation can start. + + (#)Multi-buffer processing is possible in polling, interrupt and DMA modes. + (##) In polling mode, only multi-buffer HASH processing is possible. + API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one. + User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as + well the computed digest. + + (##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer, + except for the last one. + User must resort to HAL_HASH_xxx_Start_IT() to enter the last one and retrieve as + well the computed digest. + + (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API. + From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the - same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to + same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASH_xxx_Finish(). - - (+++) HMAC processing (requires to resort to extended functions): + (+++) HMAC processing (requires to resort to extended functions): after initialization, the key and the first input buffer are entered - in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and + in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and starts step 2. The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this point, the HMAC processing is still carrying out step 2. - Then, step 2 for the last input buffer and step 3 are carried out by a single call + Then, step 2 for the last input buffer and step 3 are carried out by a single call to HAL_HMACEx_xxx_Step2_3_DMA(). - + The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish(). - - - (#)Context swapping. - (##) Two APIs are available to suspend HASH or HMAC processing: + + + (#)Context swapping. + (##) Two APIs are available to suspend HASH or HMAC processing: (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode), - (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA. - + (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA. + (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows - to save in memory the IP context. This context can be restored afterwards + to save in memory the Peripheral context. This context can be restored afterwards to resume the HASH processing thanks to HAL_HASH_ContextRestoring(). - - (##) Once the HASH IP has been restored to the same configuration as that at suspension + + (##) Once the HASH Peripheral has been restored to the same configuration as that at suspension time, processing can be restarted with the same API call (same API, same handle, - same parameters) as done before the suspension. Relevant parameters to restart at - the proper location are internally saved in the HASH handle. - + same parameters) as done before the suspension. Relevant parameters to restart at + the proper location are internally saved in the HASH handle. + (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral. + *** Remarks on message length *** + =================================== + [..] + (#) HAL in interruption mode (interruptions driven) + + (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. + This is why, for driver implementation simplicity’s sake, user is requested to enter a message the + length of which is a multiple of 4 bytes. + + (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR + to specify which bits to discard at the end of the complete message to process only the message bits + and not extra bits. + + (##) If user needs to perform a hash computation of a large input buffer that is spread around various places + in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it + becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. + It is advised to the user to + (+++) achieve the first formatting operation by software then enter the data + (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs. + (+++) repeat step 2 until the whole message is processed. + + [..] + (#) HAL in DMA mode + + (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis. + The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer + to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the + end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at + the end of the intermediary transfers. + + (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data + by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment + required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (+) InCpltCallback : callback for input completion. + (+) DgstCpltCallback : callback for digest computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : HASH MspInit. + (+) MspDeInitCallback : HASH MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) InCpltCallback : callback for input completion. + (+) DgstCpltCallback : callback for digest computation completion. + (+) ErrorCallback : callback for error. + (+) MspInitCallback : HASH MspInit. + (+) MspDeInitCallback : HASH MspDeInit. + + (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init + and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit + or @ref HAL_HASH_Init function. + + When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#ifdef HAL_HASH_MODULE_ENABLED - -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined (HASH) /** @defgroup HASH HASH * @brief HASH HAL module driver. * @{ */ +#ifdef HAL_HASH_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup HASH_Private_Constants HASH Private Constants * @{ */ - -/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status - * @{ - */ -#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000) /*!< DCAL not set after input data written in DIN register */ -#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001) /*!< DCAL set after input data written in DIN register */ -/** - * @} - */ -/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers +/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status * @{ - */ -#define HASH_NUMBER_OF_CSR_REGISTERS 54 /*!< Number of Context Swap Registers */ -/** - * @} - */ - -/** @defgroup HASH_TimeOut_Value HASH TimeOut Value - * @{ - */ -#define HASH_TIMEOUTVALUE 1000 /*!< Time-out value */ + */ +#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */ +#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */ /** * @} */ - -/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit + +/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers * @{ - */ -#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20 /*!< Number of words below which DMA suspension is aborted */ + */ +#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */ /** * @} - */ - + */ + +/** @defgroup HASH_TimeOut_Value HASH TimeOut Value + * @{ + */ +#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */ +/** + * @} + */ + +/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit + * @{ + */ +#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */ +/** + * @} + */ + /** * @} */ @@ -197,7 +266,7 @@ /* Private function prototypes -----------------------------------------------*/ /** @defgroup HASH_Private_Functions HASH Private Functions * @{ - */ + */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); @@ -214,28 +283,28 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @{ */ -/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization, configuration and call-back functions. +/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization, configuration and call-back functions. * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the HASH according to the specified parameters + (+) Initialize the HASH according to the specified parameters in the HASH_InitTypeDef and create the associated handle (+) DeInitialize the HASH peripheral (+) Initialize the HASH MCU Specific Package (MSP) (+) DeInitialize the HASH MSP - + [..] This section provides as well call back functions definitions for user code to manage: - (+) Input data transfer to IP completion + (+) Input data transfer to Peripheral completion (+) Calculated digest retrieval completion - (+) Error management - - - + (+) Error management + + + @endverbatim * @{ */ @@ -243,12 +312,12 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /** * @brief Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle. - * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(), - * other configuration bits are set by HASH or HMAC processing APIs. - * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for - * multi-buffer HASH processing, user needs to resort to + * @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(), + * other configuration bits are set by HASH or HMAC processing APIs. + * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for + * multi-buffer HASH processing, user needs to resort to * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the - * relevant APIs manage themselves the MDMAT bit. + * relevant APIs manage themselves the MDMAT bit. * @param hhash: HASH handle * @retval HAL status */ @@ -256,13 +325,32 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) { /* Check the parameters */ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); - + /* Check the hash handle allocation */ if(hhash == NULL) { return HAL_ERROR; } - + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if (hhash->State == HAL_HASH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; + + /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ + if(hhash->MspInitCallback == NULL) + { + hhash->MspInitCallback = HAL_HASH_MspInit; + } + + /* Init the low level hardware */ + hhash->MspInitCallback(hhash); + } +#else if(hhash->State == HAL_HASH_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -270,8 +358,9 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Init the low level hardware */ HAL_HASH_MspInit(hhash); - } - + } +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; @@ -283,56 +372,77 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Reset digest calculation bridle (MDMAT bit control) */ hhash->DigestCalculationDisable = RESET; /* Set phase to READY */ - hhash->Phase = HAL_HASH_PHASE_READY; - - /* Set the data type and reset MDMAT bit */ - MODIFY_REG(HASH->CR, HASH_CR_DATATYPE|HASH_CR_MDMAT, hhash->Init.DataType); - + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Set the data type bit */ + MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType); + /* Reset MDMAT bit */ +__HAL_HASH_RESET_MDMAT(); /* Reset HASH handle status */ hhash->Status = HAL_OK; - + /* Set the HASH state to Ready */ hhash->State = HAL_HASH_STATE_READY; - + + /* Initialise the error code */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the HASH peripheral. + * @brief DeInitialize the HASH peripheral. * @param hhash: HASH handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) -{ +{ /* Check the HASH handle allocation */ if(hhash == NULL) { return HAL_ERROR; } - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Set the default HASH phase */ hhash->Phase = HAL_HASH_PHASE_READY; - + /* Reset HashInCount, HashITCounter and HashBuffSize */ hhash->HashInCount = 0; hhash->HashBuffSize = 0; hhash->HashITCounter = 0; /* Reset digest calculation bridle (MDMAT bit control) */ - hhash->DigestCalculationDisable = RESET; - - /* DeInit the low level hardware: CLOCK, NVIC.*/ + hhash->DigestCalculationDisable = RESET; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if(hhash->MspDeInitCallback == NULL) + { + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; + } + + /* DeInit the low level hardware */ + hhash->MspDeInitCallback(hhash); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_HASH_MspDeInit(hhash); - +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + /* Reset HASH handle status */ - hhash->Status = HAL_OK; - + hhash->Status = HAL_OK; + /* Set the HASH state to Ready */ hhash->State = HAL_HASH_STATE_RESET; - + + /* Initialise the error code */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Return function status */ return HAL_OK; } @@ -369,12 +479,12 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Input data transfer complete call back. - * @note HAL_HASH_InCpltCallback() is called when the complete input message - * has been fed to the IP. This API is invoked only when input data are - * entered under interruption or thru DMA. - * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), - * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding - * to the IP. + * @note HAL_HASH_InCpltCallback() is called when the complete input message + * has been fed to the Peripheral. This API is invoked only when input data are + * entered under interruption or thru DMA. + * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), + * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding + * to the Peripheral. * @param hhash: HASH handle. * @retval None */ @@ -389,8 +499,8 @@ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) } /** - * @brief Digest computation complete call back. - * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not + * @brief Digest computation complete call back. + * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not * relevant with DMA. * @param hhash: HASH handle. * @retval None @@ -404,7 +514,7 @@ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) HAL_HASH_DgstCpltCallback() can be implemented in the user file. */ } - + /** * @brief Error callback. * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) @@ -422,33 +532,211 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) */ } +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User HASH Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhash); + + if(HAL_HASH_STATE_READY == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = pCallback; + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = pCallback; + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = pCallback; + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_HASH_STATE_RESET == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhash); + return status; +} + +/** + * @brief Unregister a HASH Callback + * HASH Callback is redirected to the weak (surcharged) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhash); + + if(HAL_HASH_STATE_READY == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_HASH_STATE_RESET == hhash->State) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhash); + return status; +} +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /** * @} */ -/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode - * @brief HASH processing functions using polling mode. +/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode + * @brief HASH processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HASH processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the hash value using one of the following algorithms: (+) MD5 - (++) HAL_HASH_MD5_Start() - (++) HAL_HASH_MD5_Accumulate() + (++) HAL_HASH_MD5_Start() + (++) HAL_HASH_MD5_Accumulate() (+) SHA1 - (++) HAL_HASH_SHA1_Start() - (++) HAL_HASH_SHA1_Accumulate() - + (++) HAL_HASH_SHA1_Start() + (++) HAL_HASH_SHA1_Accumulate() + [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). - + [..] In case of multi-buffer HASH processing (a single digest is computed while - several buffers are fed to the IP), the user can resort to successive calls + several buffers are fed to the Peripheral), the user can resort to successive calls to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASH_xxx_Start(). + to HAL_HASH_xxx_Start(). @endverbatim * @{ @@ -456,54 +744,54 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) /** * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) { - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); + return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } /** - * @brief If not already done, initialize the HASH peripheral in MD5 mode then + * @brief If not already done, initialize the HASH peripheral in MD5 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_MD5_Start(). + * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_MD5_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the Peripheral has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ +{ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); } /** * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -512,20 +800,20 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf } /** - * @brief If not already done, initialize the HASH peripheral in SHA1 mode then + * @brief If not already done, initialize the HASH peripheral in SHA1 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_SHA1_Start(). + * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_SHA1_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the Peripheral has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. @@ -542,24 +830,24 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p */ /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode - * @brief HASH processing functions using interrupt mode. + * @brief HASH processing functions using interrupt mode. * -@verbatim +@verbatim =============================================================================== ##### Interruption mode HASH processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the hash value using one of the following algorithms: (+) MD5 - (++) HAL_HASH_MD5_Start_IT() + (++) HAL_HASH_MD5_Start_IT() (+) SHA1 (++) HAL_HASH_SHA1_Start_IT() - + [..] API HAL_HASH_IRQHandler() manages each HASH interruption. - - [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in + + [..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in HMAC processing mode. - + @endverbatim * @{ @@ -567,42 +855,88 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p /** * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); } +/** + * @brief If not already done, initialize the HASH peripheral in MD5 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASH_MD5_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_MD5_Start_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash: HASH handle. + * @param pInBuffer: pointer to the input buffer (buffer to be hashed). + * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_MD5_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); +} /** * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); } + +/** + * @brief If not already done, initialize the HASH peripheral in SHA1 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASH_SHA1_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_SHA1_Start_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash: HASH handle. + * @param pInBuffer: pointer to the input buffer (buffer to be hashed). + * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); +} + /** * @brief Handle HASH interrupt request. * @param hhash: HASH handle. - * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. + * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. * @note In case of error reported during the HASH interruption processing, * HAL_HASH_ErrorCallback() API is called so that user code can - * manage the error. The error type is available in hhash->Status field. + * manage the error. The error type is available in hhash->Status field. * @retval None */ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) @@ -610,7 +944,12 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) hhash->Status = HASH_IT(hhash); if (hhash->Status != HAL_OK) { - HAL_HASH_ErrorCallback(hhash); + hhash->ErrorCode |= HAL_HASH_ERROR_IT; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /* After error handling by code user, reset HASH handle HAL status */ hhash->Status = HAL_OK; } @@ -621,30 +960,28 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) */ /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode - * @brief HASH processing functions using DMA mode. + * @brief HASH processing functions using DMA mode. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HASH processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the hash value using one of the following algorithms: (+) MD5 - (++) HAL_HASH_MD5_Start_DMA() - (++) HAL_HASH_MD5_Finish() + (++) HAL_HASH_MD5_Start_DMA() + (++) HAL_HASH_MD5_Finish() (+) SHA1 (++) HAL_HASH_SHA1_Start_DMA() (++) HAL_HASH_SHA1_Finish() - - [..] When resorting to DMA mode to enter the data in the IP, user must resort - to HAL_HASH_xxx_Start_DMA() then read the resulting digest with - HAL_HASH_xxx_Finish(). - + + [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort + to HAL_HASH_xxx_Start_DMA() then read the resulting digest with + HAL_HASH_xxx_Finish(). [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before - the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be + the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally - retrieved thanks to HAL_HASH_xxx_Finish(). - + retrieved thanks to HAL_HASH_xxx_Finish(). @endverbatim * @{ @@ -652,47 +989,47 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); +{ + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** * @brief Return the computed digest in MD5 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in - * HMAC MD5 mode. + * HMAC MD5 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -700,15 +1037,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @brief Return the computed digest in SHA1 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in - * HMAC SHA1 mode. + * HMAC SHA1 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); +{ + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -716,18 +1053,18 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB */ /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode - * @brief HMAC processing functions using polling mode. + * @brief HMAC processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HMAC processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the HMAC value using one of the following algorithms: (+) MD5 - (++) HAL_HMAC_MD5_Start() + (++) HAL_HMAC_MD5_Start() (+) SHA1 - (++) HAL_HMAC_SHA1_Start() + (++) HAL_HMAC_SHA1_Start() @endverbatim @@ -736,15 +1073,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB /** * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -754,103 +1091,103 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } /** * @} */ - - + + /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode - * @brief HMAC processing functions using interrupt mode. + * @brief HMAC processing functions using interrupt mode. * -@verbatim +@verbatim =============================================================================== ##### Interrupt mode HMAC processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the HMAC value using one of the following algorithms: (+) MD5 - (++) HAL_HMAC_MD5_Start_IT() + (++) HAL_HMAC_MD5_Start_IT() (+) SHA1 - (++) HAL_HMAC_SHA1_Start_IT() + (++) HAL_HMAC_SHA1_Start_IT() @endverbatim * @{ - */ - + */ + /** * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); -} +} /** * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); -} - +} + /** * @} */ - - + + /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode - * @brief HMAC processing functions using DMA modes. + * @brief HMAC processing functions using DMA modes. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HMAC processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the HMAC value using one of the following algorithms: (+) MD5 - (++) HAL_HMAC_MD5_Start_DMA() + (++) HAL_HMAC_MD5_Start_DMA() (+) SHA1 - (++) HAL_HMAC_SHA1_Start_DMA() - - [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, - user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest - with HAL_HASH_xxx_Finish(). + (++) HAL_HMAC_SHA1_Start_DMA() + + [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing, + user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest + with HAL_HASH_xxx_Finish(). @endverbatim * @{ @@ -858,24 +1195,24 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** - * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the Peripheral. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -883,24 +1220,24 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** - * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the Peripheral. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -910,33 +1247,33 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @} */ -/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions - * @brief Peripheral State functions. +/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State methods ##### - =============================================================================== + =============================================================================== [..] - This section permits to get in run-time the state and the peripheral handle + This section permits to get in run-time the state and the peripheral handle status of the peripheral: - (+) HAL_HASH_GetState() + (+) HAL_HASH_GetState() (+) HAL_HASH_GetStatus() - + [..] Additionally, this subsection provides functions allowing to save and restore - the HASH or HMAC processing context in case of calculation suspension: - (+) HAL_HASH_ContextSaving() - (+) HAL_HASH_ContextRestoring() - + the HASH or HMAC processing context in case of calculation suspension: + (+) HAL_HASH_ContextSaving() + (+) HAL_HASH_ContextRestoring() + [..] This subsection provides functions allowing to suspend the HASH processing - (+) when input are fed to the IP by software - (++) HAL_HASH_SwFeed_ProcessSuspend() - (+) when input are fed to the IP by DMA - (++) HAL_HASH_DMAFeed_ProcessSuspend() - - + (+) when input are fed to the Peripheral by software + (++) HAL_HASH_SwFeed_ProcessSuspend() + (+) when input are fed to the Peripheral by DMA + (++) HAL_HASH_DMAFeed_ProcessSuspend() + + @endverbatim * @{ @@ -944,7 +1281,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Return the HASH handle state. - * @note The API yields the current state of the handle (BUSY, READY,...). + * @note The API yields the current state of the handle (BUSY, READY,...). * @param hhash: HASH handle. * @retval HAL HASH state */ @@ -957,10 +1294,10 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) /** * @brief Return the HASH HAL status. * @note The API yields the HAL status of the handle: it is the result of the - * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT). + * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT). * @param hhash: HASH handle. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) { return hhash->Status; @@ -968,98 +1305,98 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) /** * @brief Save the HASH context in case of processing suspension. - * @param hhash: HASH handle. - * @param pMemBuffer: pointer to the memory buffer where the HASH context - * is saved. + * @param hhash: HASH handle. + * @param pMemBuffer: pointer to the memory buffer where the HASH context + * is saved. * @note The IMR, STR, CR then all the CSR registers are saved - * in that order. Only the r/w bits are read to be restored later on. - * @note By default, all the context swap registers (there are - * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. + * in that order. Only the r/w bits are read to be restored later on. + * @note By default, all the context swap registers (there are + * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. * @note pMemBuffer points to a buffer allocated by the user. The buffer size - * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. + * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; - uint32_t i = 0; + uint32_t i; /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - + UNUSED(hhash); + /* Save IMR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI); - mem_ptr+=4; + mem_ptr+=4U; /* Save STR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW); - mem_ptr+=4; - /* Save CR register content */ + mem_ptr+=4U; + /* Save CR register content */ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT); - mem_ptr+=4; + mem_ptr+=4U; /* By default, save all CSRs registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) { *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr); - mem_ptr+=4; - csr_ptr+=4; - } + mem_ptr+=4U; + csr_ptr+=4U; + } } /** * @brief Restore the HASH context in case of processing resumption. - * @param hhash: HASH handle. - * @param pMemBuffer: pointer to the memory buffer where the HASH context - * is stored. + * @param hhash: HASH handle. + * @param pMemBuffer: pointer to the memory buffer where the HASH context + * is stored. * @note The IMR, STR, CR then all the CSR registers are restored - * in that order. Only the r/w bits are restored. + * in that order. Only the r/w bits are restored. * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS * of those) are restored (all of them have been saved by default - * beforehand). + * beforehand). * @retval None */ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; - uint32_t i = 0; - + uint32_t i; + /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); + UNUSED(hhash); /* Restore IMR register content */ - WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; + WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); + mem_ptr+=4U; /* Restore STR register content */ - WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; - /* Restore CR register content */ - WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; - + WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); + mem_ptr+=4U; + /* Restore CR register content */ + WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); + mem_ptr+=4U; + /* Reset the HASH processor before restoring the Context - Swap Registers (CSR) */ - __HAL_HASH_INIT(); - + Swap Registers (CSR) */ + __HAL_HASH_INIT(); + /* By default, restore all CSR registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) { - WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); - mem_ptr+=4; - csr_ptr+=4; - } + WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); + mem_ptr+=4U; + csr_ptr+=4U; + } } /** * @brief Initiate HASH processing suspension when in polling or interruption mode. * @param hhash: HASH handle. - * @note Set the handle field SuspendRequest to the appropriate value so that - * the on-going HASH processing is suspended as soon as the required + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going HASH processing is suspended as soon as the required * conditions are met. Note that the actual suspension is carried out * by the functions HASH_WriteData() in polling mode and HASH_IT() in - * interruption mode. + * interruption mode. * @retval None */ void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) @@ -1071,239 +1408,283 @@ void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /** * @brief Suspend the HASH processing when in DMA mode. * @param hhash: HASH handle. - * @note When suspension attempt occurs at the very end of a DMA transfer and - * all the data have already been entered in the IP, hhash->State is - * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is - * recommended to wrap-up the processing in reading the digest as usual. + * @note When suspension attempt occurs at the very end of a DMA transfer and + * all the data have already been entered in the Peripheral, hhash->State is + * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is + * recommended to wrap-up the processing in reading the digest as usual. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { - uint32_t tmp_remaining_DMATransferSize_inWords = 0x0; - uint32_t tmp_initial_DMATransferSize_inWords = 0x0; - uint32_t tmp_words_already_pushed = 0x0; - + uint32_t tmp_remaining_DMATransferSize_inWords; + uint32_t tmp_initial_DMATransferSize_inWords; + uint32_t tmp_words_already_pushed; + if (hhash->State == HAL_HASH_STATE_READY) { return HAL_ERROR; } else - { - + { + /* Make sure there is enough time to suspend the processing */ - tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; + tmp_remaining_DMATransferSize_inWords = ((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CNDTR; + if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) { /* No suspension attempted since almost to the end of the transferred data. */ /* Best option for user code is to wrap up low priority message hashing */ - return HAL_ERROR; + return HAL_ERROR; } - /* Wait for DMAS to be reset */ + /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; } - + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) { return HAL_ERROR; } - - /* Wait for DMAS to be set */ + + /* Wait for BUSY flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; - } - + } + /* Disable DMA channel */ - HAL_DMA_Abort(hhash->hdmain); - + if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK) + { + /* + Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + } + /* Clear DMAE bit */ CLEAR_BIT(HASH->CR,HASH_CR_DMAE); - + + /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; } - + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) { return HAL_ERROR; - } - + } + /* At this point, DMA interface is disabled and no transfer is on-going */ /* Retrieve from the DMA handle how many words remain to be written */ - tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; + tmp_remaining_DMATransferSize_inWords = ((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CNDTR; - if (tmp_remaining_DMATransferSize_inWords == 0) + if (tmp_remaining_DMATransferSize_inWords == 0U) { - /* All the DMA transfer is actually done. Suspension occurred at the very end - of the transfer. Either the digest computation is about to start (HASH case) + /* All the DMA transfer is actually done. Suspension occurred at the very end + of the transfer. Either the digest computation is about to start (HASH case) or processing is about to move from one step to another (HMAC case). In both cases, the processing can't be suspended at this point. It is safer to - - retrieve the low priority block digest before starting the high + - retrieve the low priority block digest before starting the high priority block processing (HASH case) - - re-attempt a new suspension (HMAC case) - */ + - re-attempt a new suspension (HMAC case) + */ return HAL_ERROR; } else { - + /* Compute how many words were supposed to be transferred by DMA */ - tmp_initial_DMATransferSize_inWords = (hhash->HashInCount%4 ? (hhash->HashInCount+3)/4: hhash->HashInCount/4); - - /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported - by HASH IP, correct it */ + tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U)); + + /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported + by HASH Peripheral, correct it */ /* tmp_words_already_pushed reflects the number of words that were already pushed before the start of DMA transfer (multi-buffer processing case) */ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; - if ((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16 != HASH_NBW_PUSHED()) + if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED()) { - tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ + tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } - - /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */ - hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; - + + /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */ + hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; + /* And store in HashInCount the remaining size to transfer (in bytes) */ - hhash->HashInCount = 4 * tmp_remaining_DMATransferSize_inWords; - + hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords; + } - - /* Set State as suspended */ - hhash->State = HAL_HASH_STATE_SUSPENDED; - + + /* Set State as suspended */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + return HAL_OK; - + } } - +/** + * @brief Return the HASH handle error code. + * @param hhash: pointer to a HASH_HandleTypeDef structure. + * @retval HASH Error Code +*/ +uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +{ + /* Return HASH Error Code */ + return hhash->ErrorCode; +} /** * @} */ - - + + /** * @} */ /** @defgroup HASH_Private_Functions HASH Private Functions * @{ - */ + */ /** - * @brief DMA HASH Input Data transfer completion callback. + * @brief DMA HASH Input Data transfer completion callback. * @param hdma: DMA handle. * @note In case of HMAC processing, HASH_DMAXferCplt() initiates - * the next DMA transfer for the following HMAC step. + * the next DMA transfer for the following HMAC step. * @retval None */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) { HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint32_t inputaddr = 0x0; - uint32_t buffersize = 0x0; - + uint32_t inputaddr; + uint32_t buffersize; + HAL_StatusTypeDef status ; + if (hhash->State != HAL_HASH_STATE_SUSPENDED) { - - /* Disable the DMA transfer */ - CLEAR_BIT(HASH->CR, HASH_CR_DMAE); - if (READ_BIT(HASH->CR, HASH_CR_MODE) == RESET) - { - /* If no HMAC processing, input data transfer is now over */ - - /* Change the HASH state to ready */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back */ - HAL_HASH_InCpltCallback(hhash); - } - else - { - /* HMAC processing: depending on the current HMAC step and whether or - not multi-buffer processing is on-going, the next step is initiated - and MDMAT bit is set. */ - + /* Disable the DMA transfer */ + CLEAR_BIT(HASH->CR, HASH_CR_DMAE); - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) + if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U) { - /* This is the end of HMAC processing */ - + /* If no HMAC processing, input data transfer is now over */ + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back - (note that the last DMA transfer was that of the key - for the outer HASH operation). */ - HAL_HASH_InCpltCallback(hhash); - - return; - } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) - { - inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */ - buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ - - /* In case of suspension request, save the new starting parameters */ - hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */ - hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */ - hhash->NbWordsAlreadyPushed = 0; /* Reset number of words already pushed */ - - /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ - if (hhash->DigestCalculationDisable != RESET) - { - /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, - no digest calculation will be triggered at the end of the input buffer feeding to the IP */ - __HAL_HASH_SET_MDMAT(); - } + /* Call Input data transfer complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) + else { - if (hhash->DigestCalculationDisable != RESET) + /* HMAC processing: depending on the current HMAC step and whether or + not multi-buffer processing is on-going, the next step is initiated + and MDMAT bit is set. */ + + + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) { - /* No automatic move to Step 3 as a new message buffer will be fed to the IP - (case of multi-buffer HMAC processing): - DCAL must not be set. - Phase remains in Step 2, MDMAT remains set at this point. - Change the HASH state to ready and call Input data transfer complete call back. */ + /* This is the end of HMAC processing */ + + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - HAL_HASH_InCpltCallback(hhash); - return ; + + /* Call Input data transfer complete call back + (note that the last DMA transfer was that of the key + for the outer HASH operation). */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + return; + } + else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) + { + inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */ + buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ + + /* In case of suspension request, save the new starting parameters */ + hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */ + hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */ + + hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */ + /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ + if (hhash->DigestCalculationDisable != RESET) + { + /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, + no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */ + __HAL_HASH_SET_MDMAT(); + } + } + else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/ + { + if (hhash->DigestCalculationDisable != RESET) + { + /* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral + (case of multi-buffer HMAC processing): + DCAL must not be set. + Phase remains in Step 2, MDMAT remains set at this point. + Change the HASH state to ready and call Input data transfer complete call back. */ + hhash->State = HAL_HASH_STATE_READY; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + return ; + } + else + { + /* Digest calculation is not disabled (case of single buffer input or last buffer + of multi-buffer HMAC processing) */ + inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ + buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ + /* In case of suspension request, save the new starting parameters */ + hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */ + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ + + hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */ + } + } + + /* Configure the Number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(buffersize); + + /* Set the HASH DMA transfert completion call back */ + hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; + + /* Enable the DMA In DMA Stream */ + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U))); + + /* Enable DMA requests */ + SET_BIT(HASH->CR, HASH_CR_DMAE); + + /* Return function status */ + if (status != HAL_OK) + { + /* Update DAC state machine to error */ + hhash->State = HAL_HASH_STATE_ERROR; } else { - /* Digest calculation is not disabled (case of single buffer input or last buffer - of multi-buffer HMAC processing) */ - inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ - buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ - /* In case of suspension request, save the new starting parameters */ - hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ - - hhash->NbWordsAlreadyPushed = 0; /* Reset number of words already pushed */ + /* Change DAC state */ + hhash->State = HAL_HASH_STATE_READY; } - } - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(buffersize); - - - /* Set the HASH DMA transfert completion call back */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - - /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4)); - - /* Enable DMA requests */ - SET_BIT(HASH->CR, HASH_CR_DMAE); } } @@ -1311,46 +1692,51 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA HASH communication error callback. + * @brief DMA HASH communication error callback. * @param hdma: DMA handle. * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that - * can contain user code to manage the error. + * can contain user code to manage the error. * @retval None */ static void HASH_DMAError(DMA_HandleTypeDef *hdma) { HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - if (hhash->State != HAL_HASH_STATE_SUSPENDED) + + if (hhash->State != HAL_HASH_STATE_SUSPENDED) { - /* Set HASH state to ready to prevent any blocking issue in user code - present in HAL_HASH_ErrorCallback() */ - hhash->State= HAL_HASH_STATE_READY; - /* Set HASH handle status to error */ - hhash->Status = HAL_ERROR; - HAL_HASH_ErrorCallback(hhash); - /* After error handling by code user, reset HASH handle HAL status */ - hhash->Status = HAL_OK; - - } + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + /* Set HASH state to ready to prevent any blocking issue in user code + present in HAL_HASH_ErrorCallback() */ + hhash->State= HAL_HASH_STATE_READY; + /* Set HASH handle status to error */ + hhash->Status = HAL_ERROR; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /* After error handling by code user, reset HASH handle HAL status */ + hhash->Status = HAL_OK; + + } } /** - * @brief Feed the input buffer to the HASH IP. + * @brief Feed the input buffer to the HASH Peripheral. * @param hhash: HASH handle. * @param pInBuffer: pointer to input buffer. * @param Size: the size of input buffer in bytes. * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether * or not the HASH processing must be suspended. If this is the case, the - * processing is suspended when possible and the IP feeding point reached at - * suspension time is stored in the handle for resumption later on. + * processing is suspended when possible and the Peripheral feeding point reached at + * suspension time is stored in the handle for resumption later on. * @retval HAL status */ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { uint32_t buffercounter; - - for(buffercounter = 0; buffercounter < Size; buffercounter+=4) + + for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U) { /* Write input data 4 bytes at a time */ uint32_t data = (uint32_t) *pInBuffer++; @@ -1358,33 +1744,33 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB data |= (uint32_t) *pInBuffer++ << 16; data |= (uint32_t) *pInBuffer++ << 24; HASH->DIN = data; - + /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) + to end, suspend processing */ + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size)) { - /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free - in the input buffer */ - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free + in the input buffer */ + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) { /* Reset SuspendRequest */ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - - /* Depending whether the key or the input data were fed to the IP, the feeding point - reached at suspension time is not saved in the same handle fields */ + + /* Depending whether the key or the input data were fed to the Peripheral, the feeding point + reached at suspension time is not saved in the same handle fields */ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashInBuffPtr = pInBuffer; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter + 4); + hhash->HashInCount = Size - (buffercounter + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = pInBuffer; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter + 4); + hhash->HashKeyCount = Size - (buffercounter + 4U); } else { @@ -1393,17 +1779,17 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB __HAL_UNLOCK(hhash); return HAL_ERROR; } - + /* Set the HASH state to Suspended and exit to stop entering data */ hhash->State = HAL_HASH_STATE_SUSPENDED; - + return HAL_OK; } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */ } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ - - /* At this point, all the data have been entered to the IP: exit */ - return HAL_OK; + + /* At this point, all the data have been entered to the Peripheral: exit */ + return HAL_OK; } /** @@ -1415,62 +1801,62 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; - + switch(Size) { /* Read the message digest */ case 16: /* MD5 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); break; case 20: /* SHA1 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); break; case 28: /* SHA224 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); break; case 32: /* SHA256 */ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest+=4; + msgdigest+=4U; *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; + break; default: break; } @@ -1485,7 +1871,7 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) * @param Status: the Flag status (SET or RESET). * @param Timeout: Timeout duration. * @retval HAL status - */ + */ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -1498,7 +1884,7 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -1520,7 +1906,7 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -1544,91 +1930,99 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, * @param hhash: HASH handle. * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether * or not the HASH processing must be suspended. If this is the case, the - * processing is suspended when possible and the IP feeding point reached at - * suspension time is stored in the handle for resumption later on. + * processing is suspended when possible and the Peripheral feeding point reached at + * suspension time is stored in the handle for resumption later on. * @retval HAL status */ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) { if (hhash->State == HAL_HASH_STATE_BUSY) - { + { /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */ - if(hhash->HashITCounter == 0) + if(hhash->HashITCounter == 0U) { /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); /* HASH state set back to Ready to prevent any issue in user code present in HAL_HASH_ErrorCallback() */ - hhash->State = HAL_HASH_STATE_READY; + hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - else if (hhash->HashITCounter == 1) + else if (hhash->HashITCounter == 1U) { - /* This is the first call to HASH_IT, the first input data are about to be - entered in the IP. A specific processing is carried out at this point to - start-up the processing. */ - hhash->HashITCounter = 2; + /* This is the first call to HASH_IT, the first input data are about to be + entered in the Peripheral. A specific processing is carried out at this point to + start-up the processing. */ + hhash->HashITCounter = 2U; } else { /* Cruise speed reached, HashITCounter remains equal to 3 until the end of - the HASH processing or the end of the current step for HMAC processing. */ - hhash->HashITCounter = 3; + the HASH processing or the end of the current step for HMAC processing. */ + hhash->HashITCounter = 3U; } - + /* If digest is ready */ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) { /* Read the digest */ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); - + /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; /* Call digest computation complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else HAL_HASH_DgstCpltCallback(hhash); - - return HAL_OK; - } +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - /* If IP ready to accept new data */ + return HAL_OK; + } + + /* If Peripheral ready to accept new data */ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { + { /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (hhash->HashInCount != 0)) + if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) { /* Disable Interrupts */ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); - + /* Reset SuspendRequest */ - hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_SUSPENDED; - + return HAL_OK; - } - - /* Enter input data in the IP thru HASH_Write_Block_Data() call and - check whether the digest calculation has been triggered */ + } + + /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and + check whether the digest calculation has been triggered */ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) { - /* Call Input data transfer complete call back + /* Call Input data transfer complete call back (called at the end of each step for HMAC) */ - HAL_HASH_InCpltCallback(hhash); - +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) { - /* Wait until IP is not busy anymore */ + /* Wait until Peripheral is not busy anymore */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); return HAL_TIMEOUT; - } + } /* Initialization start for HMAC STEP 2 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */ @@ -1636,29 +2030,33 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ - } + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { - /* Wait until IP is not busy anymore */ + /* Wait until Peripheral is not busy anymore */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); return HAL_TIMEOUT; - } + } /* Initialization start for HMAC STEP 3 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ - hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ - hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ + __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ + hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ + hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ + __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ + } + else + { + /* Nothing to do */ } } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/ /* Return function status */ - return HAL_OK; + return HAL_OK; } else { @@ -1668,25 +2066,25 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) /** - * @brief Write a block of data in HASH IP in interruption mode. + * @brief Write a block of data in HASH Peripheral in interruption mode. * @param hhash: HASH handle. - * @note HASH_Write_Block_Data() is called under interruption by HASH_IT(). + * @note HASH_Write_Block_Data() is called under interruption by HASH_IT(). * @retval HAL status */ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) { uint32_t inputaddr; uint32_t buffercounter; - uint32_t inputcounter; + uint32_t inputcounter; uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED; - + /* If there are more than 64 bytes remaining to be entered */ - if(hhash->HashInCount > 64) + if(hhash->HashInCount > 64U) { inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* Write the Input block in the Data IN register (16 32-bit words, or 64 bytes are entered) */ - for(buffercounter = 0; buffercounter < 64; buffercounter+=4) + for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U) { uint32_t data = (uint32_t) *(uint8_t *)inputaddr++; data |= (uint32_t) *(uint8_t *)inputaddr++ << 8; @@ -1696,25 +2094,25 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) } /* If this is the start of input data entering, an additional word must be entered to start up the HASH processing */ - if(hhash->HashITCounter == 2) + if(hhash->HashITCounter == 2U) { uint32_t data = (uint32_t) *(uint8_t *)inputaddr++; data |= (uint32_t) *(uint8_t *)inputaddr++ << 8; data |= (uint32_t) *(uint8_t *)inputaddr++ << 16; data |= (uint32_t) *(uint8_t *)inputaddr++ << 24; HASH->DIN = data; - if(hhash->HashInCount >= 68) + if(hhash->HashInCount >= 68U) { - /* There are still data waiting to be entered in the IP. + /* There are still data waiting to be entered in the Peripheral. Decrement buffer counter and set pointer to the proper memory location for the next data entering round. */ - hhash->HashInCount -= 68; - hhash->pHashInBuffPtr+= 68; + hhash->HashInCount -= 68U; + hhash->pHashInBuffPtr+= 68U; } else { /* All the input buffer has been fed to the HW. */ - hhash->HashInCount = 0; + hhash->HashInCount = 0U; } } else @@ -1722,15 +2120,15 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) /* 64 bytes have been entered and there are still some remaining: Decrement buffer counter and set pointer to the proper memory location for the next data entering round.*/ - hhash->HashInCount -= 64; - hhash->pHashInBuffPtr+= 64; + hhash->HashInCount -= 64U; + hhash->pHashInBuffPtr+= 64U; } } else { /* 64 or less bytes remain to be entered. This is the last - data entering round. */ - + data entering round. */ + /* Get the buffer address */ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* Get the buffer counter */ @@ -1739,7 +2137,7 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) __HAL_HASH_DISABLE_IT(HASH_IT_DINI); /* Write the Input block in the Data IN register */ - for(buffercounter = 0; buffercounter < (inputcounter+3)/4; buffercounter++) + for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++) { uint32_t data = (uint32_t) *(uint8_t *)inputaddr++; data |= (uint32_t) *(uint8_t *)inputaddr++ << 8; @@ -1747,17 +2145,37 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) data |= (uint32_t) *(uint8_t *)inputaddr++ << 24; HASH->DIN = data; } - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Return indication that digest calculation has started: - this return value triggers the call to Input data transfer - complete call back as well as the proper transition from - one step to another in HMAC mode. */ - ret = HASH_DIGEST_CALCULATION_STARTED; + + if (hhash->Accumulation == 1U) + { + /* Field accumulation is set, API only feeds data to the Peripheral and under interruption. + The digest computation will be started when the last buffer data are entered. */ + + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + /* Call Input data transfer complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + /* Start the Digest calculation */ + __HAL_HASH_START_DIGEST(); + /* Return indication that digest calculation has started: + this return value triggers the call to Input data transfer + complete call back as well as the proper transition from + one step to another in HMAC mode. */ + ret = HASH_DIGEST_CALCULATION_STARTED; + } /* Reset buffer counter */ hhash->HashInCount = 0; } - + /* Return whether or digest calculation has started */ return ret; } @@ -1765,9 +2183,9 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) /** * @brief HMAC processing in polling mode. * @param hhash: HASH handle. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status - */ + */ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout) { /* Ensure first that Phase is correct */ @@ -1775,53 +2193,54 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_ERROR; } - + /* HMAC Step 1 processing */ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) { /************************** STEP 1 ******************************************/ /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount); + if (hhash->Status != HAL_OK) { return hhash->Status; } - + /* Check whether or not key entering process has been suspended */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Stop right there and return function status */ return HAL_OK; - } - + } + /* No processing suspension at this point: set DCAL bit. */ __HAL_HASH_START_DIGEST(); - + /* Wait for BUSY flag to be cleared */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Move from Step 1 to Step 2 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; - + } - + /* HMAC Step 2 processing. - After phase check, HMAC_Processing() may + After phase check, HMAC_Processing() may - directly start up from this point in resumption case if the same Step 2 processing was suspended previously - or fall through from the Step 1 processing carried out hereabove */ @@ -1830,88 +2249,90 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /************************** STEP 2 ******************************************/ /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); - + /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount); + if (hhash->Status != HAL_OK) { return hhash->Status; - } - + } + /* Check whether or not data entering process has been suspended */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Stop right there and return function status */ return HAL_OK; - } - + } + /* No processing suspension at this point: set DCAL bit. */ __HAL_HASH_START_DIGEST(); - + /* Wait for BUSY flag to be cleared */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) { return HAL_TIMEOUT; - } - - /* Move from Step 2 to Step 3 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; + } + + /* Move from Step 2 to Step 3 */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* In case Step 1 phase was suspended then resumed, set again Key input buffers and size before moving to next step */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; hhash->HashKeyCount = hhash->Init.KeySize; } - - + + /* HMAC Step 3 processing. - After phase check, HMAC_Processing() may + After phase check, HMAC_Processing() may - directly start up from this point in resumption case if the same Step 3 processing was suspended previously - or fall through from the Step 2 processing carried out hereabove */ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) - { + { /************************** STEP 3 ******************************************/ /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount); + if (hhash->Status != HAL_OK) { return hhash->Status; - } - + } + /* Check whether or not key entering process has been suspended */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Stop right there and return function status */ return HAL_OK; - } - + } + /* No processing suspension at this point: start the Digest calculation. */ __HAL_HASH_START_DIGEST(); - + /* Wait for DCIS flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; - } - + } + /* Read the message digest */ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); - } - + } + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; } @@ -1919,125 +2340,128 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /** * @brief Initialize the HASH peripheral, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. - * @param Algorithm: HASH algorithm. + * @param Timeout: Timeout value. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ - uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */ + uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + /* Initiate HASH processing in case of start or resumption */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; - } + } - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Check if initialization phase has not been already performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - } - else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) - { - /* if the IP has already been initialized, two cases are possible */ - - /* Process resumption time ... */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Check if initialization phase has not been already performed */ + if(hhash->Phase == HAL_HASH_PHASE_READY) { - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(Size); + + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ + pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) + { + /* if the Peripheral has already been initialized, two cases are possible */ + + /* Process resumption time ... */ + if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; - Size_tmp = hhash->HashInCount; + pInBuffer_tmp = hhash->pHashInBuffPtr; + Size_tmp = hhash->HashInCount; + } + /* ... or multi-buffer HASH processing end */ + else + { + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ + pInBuffer_tmp = pInBuffer; + Size_tmp = Size; + /* Configure the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(Size); + } + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; } - /* ... or multi-buffer HASH processing end */ - else + else { - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; - Size_tmp = Size; - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); + /* Phase error */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_ERROR; } - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - } - else - { - /* Phase error */ - hhash->State = HAL_HASH_STATE_READY; - + + + /* Write input buffer in Data register */ + hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp); + if (hhash->Status != HAL_OK) + { + return hhash->Status; + } + + /* If the process has not been suspended, carry on to digest calculation */ + if (hhash->State != HAL_HASH_STATE_SUSPENDED) + { + /* Start the Digest calculation */ + __HAL_HASH_START_DIGEST(); + + /* Wait for DCIS flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Read the message digest */ + HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + } + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_ERROR; - } - - - /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK) - { - return hhash->Status; - } - - /* If the process has not been suspended, carry on to digest calculation */ - if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - + return HAL_OK; + } else { @@ -2047,168 +2471,373 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /** - * @brief If not already done, initialize the HASH peripheral then + * @brief If not already done, initialize the HASH peripheral then * processes pInBuffer. * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the Peripheral has already been initialized. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ - uint32_t Size_tmp = 0x0; /* input data size (in bytes), input parameter of HASH_WriteData() */ - + uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + /* Make sure the input buffer size (in bytes) is a multiple of 4 */ - assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size)); - - + if ((Size % 4U) != 0U) + { + return HAL_ERROR; + } + /* Initiate HASH processing in case of start or resumption */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0)) + if ((pInBuffer == NULL) || (Size == 0U)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; - } - + } + /* Process Locked */ __HAL_LOCK(hhash); - + /* If resuming the HASH processing */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set + + /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ - + } - else + else { /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - + hhash->State = HAL_HASH_STATE_BUSY; + + /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as + input parameters of HASH_WriteData() */ + pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ + /* Check if initialization phase has already be performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); } - + /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; - - } - + + } + /* Write input buffer in Data register */ - if ((hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp)) != HAL_OK) + hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp); + if (hhash->Status != HAL_OK) { return hhash->Status; - } - + } + /* If the process has not been suspended, move the state to Ready */ if (hhash->State != HAL_HASH_STATE_SUSPENDED) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_OK; - + return HAL_OK; + } else { return HAL_BUSY; } - - + + } +/** + * @brief If not already done, initialize the HASH peripheral then + * processes pInBuffer in interruption mode. + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. + * @param hhash: HASH handle. + * @param pInBuffer: pointer to the input buffer (buffer to be hashed). + * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @param Algorithm: HASH algorithm. + * @retval HAL status + */ +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +{ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint32_t SizeVar = Size; + + /* Make sure the input buffer size (in bytes) is a multiple of 4 */ + if ((Size % 4U) != 0U) + { + return HAL_ERROR; + } + + /* Initiate HASH processing in case of start or resumption */ + if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { + /* Check input parameters */ + if ((pInBuffer == NULL) || (Size == 0U)) + { + hhash->State = HAL_HASH_STATE_READY; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* If resuming the HASH processing */ + if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + } + else + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Check if initialization phase has already be performed */ + if(hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + hhash->HashITCounter = 1; + } + else + { + hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ + } + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + /* If DINIS is equal to 0 (for example if an incomplete block has been previously + fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. + Therefore, first words are manually entered until DINIS raises, or until there + is not more data to enter. */ + while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) + { + + /* Write input data 4 bytes at a time */ + HASH->DIN = *(uint32_t*)inputaddr; + inputaddr+=4U; + SizeVar-=4U; + } + + /* If DINIS is still not set or if all the data have been fed, stop here */ + if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U)) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + } + + /* otherwise, carry on in interrupt-mode */ + hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data + to be fed to the Peripheral */ + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at + the next interruption */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ + + } + + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 1U; + + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Enable Data Input interrupt */ + __HAL_HASH_ENABLE_IT(HASH_IT_DINI); + + /* Return function status */ + return HAL_OK; + + } + else + { + return HAL_BUSY; + } + +} + + + /** * @brief Initialize the HASH peripheral, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status - */ + */ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) { - + HAL_HASH_StateTypeDef State_tmp = hhash->State; + __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint32_t polling_step = 0U; + uint32_t initialization_skipped = 0U; + uint32_t SizeVar = Size; + /* If State is ready or suspended, start or resume IT-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - + /* Process Locked */ - __HAL_LOCK(hhash); - + __HAL_LOCK(hhash); + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Initialize IT counter */ hhash->HashITCounter = 1; - + /* Check if initialization phase has already be performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - hhash->HashInCount = Size; /* Counter used to keep track of number of data - to be fed to the IP */ - hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at + /* Configure the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + + + hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data + to be fed to the Peripheral */ + hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ - - hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ + + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } - + else + { + initialization_skipped = 1; /* info user later on in case of multi-buffer */ + } + /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; - + + /* If DINIS is equal to 0 (for example if an incomplete block has been previously + fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. + Therefore, first words are manually entered until DINIS raises. */ + while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) + { + polling_step = 1U; /* note that some words are entered before enabling the interrupt */ + + /* Write input data 4 bytes at a time */ + HASH->DIN = *(uint32_t*)inputaddr; + inputaddr+=4U; + SizeVar-=4U; + } + + if (polling_step == 1U) + { + if (SizeVar == 0U) + { + /* If all the data have been entered at this point, it only remains to + read the digest */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + + /* Start the Digest calculation */ + __HAL_HASH_START_DIGEST(); + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Enable Interrupts */ + __HAL_HASH_ENABLE_IT(HASH_IT_DCI); + + /* Return function status */ + return HAL_OK; + } + else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE, + carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + if (initialization_skipped == 1U) + { + hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ + } + } + else + { + /* DINIS is not set but it remains a few data to enter (not enough for a full word). + Manually enter the last bytes before enabling DCIE. */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + HASH->DIN = *(uint32_t*)inputaddr; + + /* Start the Digest calculation */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + __HAL_HASH_START_DIGEST(); + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Enable Interrupts */ + __HAL_HASH_ENABLE_IT(HASH_IT_DCI); + + /* Return function status */ + return HAL_OK; + } + } /* if (polling_step == 1) */ + + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Enable Interrupts */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); - + /* Return function status */ return HAL_OK; } @@ -2222,127 +2851,135 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u /** * @brief Initialize the HASH peripheral then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status - */ + */ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) -{ +{ uint32_t inputaddr; - uint32_t inputSize = 0x0; - - /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set + uint32_t inputSize; + HAL_StatusTypeDef status ; + HAL_HASH_StateTypeDef State_tmp = hhash->State; + +#if defined (HASH_CR_MDMAT) + /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - - /* If State is ready or suspended, start or resume DMA-based HASH processing */ - if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) +#endif /* MDMA defined*/ + /* If State is ready or suspended, start or resume polling-based HASH processing */ +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { - /* Check input parameters */ - if ( (pInBuffer == NULL ) || (Size == 0) || - /* Check phase coherency. Phase must be + /* Check input parameters */ + if ( (pInBuffer == NULL ) || (Size == 0U) || + /* Check phase coherency. Phase must be either READY (fresh start) - or PROCESS (multi-buffer HASH management) */ + or PROCESS (multi-buffer HASH management) */ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - - + + /* Process Locked */ __HAL_LOCK(hhash); - + /* If not a resumption case */ if (hhash->State == HAL_HASH_STATE_READY) { /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed. + hhash->State = HAL_HASH_STATE_BUSY; + + /* Check if initialization phase has already been performed. If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the - API is processing a new input data message in case of multi-buffer HASH + API is processing a new input data message in case of multi-buffer HASH computation. */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); - + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; + hhash->Phase = HAL_HASH_PHASE_PROCESS; } - + /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */ - inputSize = Size; /* DMA transfer size (in bytes) */ - + __HAL_HASH_SET_NBVALIDBITS(Size); + + inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */ + inputSize = Size; /* DMA transfer size (in bytes) */ + /* In case of suspension request, save the starting parameters */ hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */ - hhash->HashInCount = Size; /* DMA transfer size (in bytes) */ - + hhash->HashInCount = Size; /* DMA transfer size (in bytes) */ + } /* If resumption case */ else { /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Resumption case, inputaddr and inputSize are not set to the API input parameters - but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the - processing was suspended */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Resumption case, inputaddr and inputSize are not set to the API input parameters + but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the + processing was suspended */ + inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */ - + } - + /* Set the HASH DMA transfert complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; /* Store number of words already pushed to manage proper DMA processing suspension */ - hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - + hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); + /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4)); - + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_OK; + if (status != HAL_OK) + { + /* Update HASH state machine to error */ + hhash->State = HAL_HASH_STATE_ERROR; + } + + return status; } else { return HAL_BUSY; } - } /** * @brief Return the computed digest. - * @note The API waits for DCIS to be set then reads the computed digest. + * @note The API waits for DCIS to be set then reads the computed digest. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ if(hhash->State == HAL_HASH_STATE_READY) { @@ -2351,62 +2988,63 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hhash); - + /* Change the HASH state to busy */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Wait for DCIS flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } - + /* Read the message digest */ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - + /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; - + /* Process UnLock */ __HAL_UNLOCK(hhash); - + /* Return function status */ return HAL_OK; - + } else { return HAL_BUSY; - } - + } + } /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. - * @param Algorithm: HASH algorithm. + * @param Timeout: Timeout value. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) -{ +{ + HAL_HASH_StateTypeDef State_tmp = hhash->State; - /* If State is ready or suspended, start or resume polling-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) + /* If State is ready or suspended, start or resume polling-based HASH processing */ +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2414,122 +3052,124 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Process Locked */ __HAL_LOCK(hhash); - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Check if initialization phase has already be performed */ if(hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64) + if(hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - /* Resort to hhash internal fields to feed the IP. + /* Resort to hhash internal fields to feed the Peripheral. Parameters will be updated in case of suspension to contain the proper information at resumption time. */ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */ - hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */ + hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */ - hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */ + hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */ } - + /* Carry out HMAC processing */ return HMAC_Processing(hhash, Timeout); - + } else { return HAL_BUSY; - } + } } /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) -{ +{ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + /* If State is ready or suspended, start or resume IT-based HASH processing */ - if((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hhash); - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - + /* Initialize IT counter */ hhash->HashITCounter = 1; - + /* Check if initialization phase has already be performed */ if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64) + if(hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } - + /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount - to feed the IP whatever the HMAC step. + to feed the Peripheral whatever the HMAC step. Lines below are set to start HMAC Step 1 processing where key is entered first. */ - hhash->HashInCount = hhash->Init.KeySize; /* Key size */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */ - - /* Store input and output parameters in handle fields to manage steps transition + hhash->HashInCount = hhash->Init.KeySize; /* Key size */ + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */ + + /* Store input and output parameters in handle fields to manage steps transition or possible HMAC suspension/resumption */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */ - hhash->HashBuffSize = Size; /* Input message size (in bytes) */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ - + hhash->HashBuffSize = Size; /* Input message size (in bytes) */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ + /* Configure the number of valid bits in last word of the key */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */ - + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { - /* Restart IT-based HASH processing after Step 2 suspension */ - + /* Restart IT-based HASH processing after Step 2 suspension */ + } else { @@ -2537,15 +3177,15 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u /* Process Unlock */ __HAL_UNLOCK(hhash); hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Unlock */ __HAL_UNLOCK(hhash); - + /* Enable Interrupts */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); - + /* Return function status */ return HAL_OK; } @@ -2554,52 +3194,52 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u return HAL_BUSY; } -} +} /** - * @brief Initialize the HASH peripheral in HMAC mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @brief Initialize the HASH peripheral in HMAC mode then initiate the required + * DMA transfers to feed the key and the input buffer to the Peripheral. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must + * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must * be a multiple of 4 otherwise, the HASH digest computation is corrupted. - * Only the length of the last buffer of the thread doesn't have to be a - * multiple of 4. + * Only the length of the last buffer of the thread doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. - * @param Algorithm: HASH algorithm. + * @param Algorithm: HASH algorithm. * @retval HAL status - */ + */ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; - uint32_t inputSize = 0x0; - + uint32_t inputSize; + HAL_StatusTypeDef status ; + HAL_HASH_StateTypeDef State_tmp = hhash->State; /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); - - /* If State is ready or suspended, start or resume DMA-based HASH processing */ - if ((hhash->State == HAL_HASH_STATE_READY) || (hhash->State == HAL_HASH_STATE_SUSPENDED)) + /* If State is ready or suspended, start or resume DMA-based HASH processing */ +if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL ) || (Size == 0) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0) || - /* Check phase coherency. Phase must be + if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) || + /* Check phase coherency. Phase must be either READY (fresh start) - or one of HMAC PROCESS steps (multi-buffer HASH management) */ + or one of HMAC PROCESS steps (multi-buffer HASH management) */ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } - - + + /* Process Locked */ __HAL_LOCK(hhash); - + /* If not a case of resumption after suspension */ if (hhash->State == HAL_HASH_STATE_READY) { @@ -2608,102 +3248,107 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. + /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. At the same time, ensure MDMAT bit is cleared. */ - if(hhash->Init.KeySize > 64) + if(hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - - /* Store input aparameters in handle fields to manage steps transition + MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + /* Store input aparameters in handle fields to manage steps transition or possible HMAC suspension/resumption */ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ hhash->HashBuffSize = Size; /* input data size (in bytes) */ - + /* Set DMA input parameters */ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ - + /* Configure the number of valid bits in last word of the key */ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - + /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { - /* Process a new input data message in case of multi-buffer HMAC processing + /* Process a new input data message in case of multi-buffer HMAC processing (this is not a resumption case) */ - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; /* Save input parameters to be able to manage possible suspension/resumption */ hhash->HashInCount = Size; /* Input message address */ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */ - + /* Set DMA input parameters */ inputaddr = (uint32_t)pInBuffer; /* Input message address */ inputSize = Size; /* Input message size in bytes */ - + if (hhash->DigestCalculationDisable == RESET) { /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ - __HAL_HASH_RESET_MDMAT(); + __HAL_HASH_RESET_MDMAT(); __HAL_HASH_SET_NBVALIDBITS(inputSize); - } + } } else { /* Phase not aligned with handle READY state */ __HAL_UNLOCK(hhash); /* Return function status */ - return HAL_ERROR; + return HAL_ERROR; } } else { /* Resumption case (phase may be Step 1, 2 or 3) */ - + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; - - /* Set DMA input parameters at resumption location; - inputaddr and inputSize are not set to the API input parameters - but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the - processing was suspended. */ + + /* Set DMA input parameters at resumption location; + inputaddr and inputSize are not set to the API input parameters + but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the + processing was suspended. */ inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */ inputSize = hhash->HashInCount; /* Input message size in bytes */ } - + /* Set the HASH DMA transfert complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; - + /* Store number of words already pushed to manage proper DMA processing suspension */ - hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - + hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); + /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (inputSize%4 ? (inputSize+3)/4:inputSize/4)); + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); - + /* Process Unlocked */ __HAL_UNLOCK(hhash); - + /* Return function status */ - return HAL_OK; + if (status != HAL_OK) + { + /* Update HASH state machine to error */ + hhash->State = HAL_HASH_STATE_ERROR; + } + + /* Return function status */ + return status; } else { @@ -2713,17 +3358,17 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ +/** + * @} + */ +#endif /* HASH*/ +/** + * @} + */ + + + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h index be9bb69822..ea86a81707 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h @@ -6,134 +6,134 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_HASH_H -#define __STM32L4xx_HAL_HASH_H +#ifndef STM32L4xx_HAL_HASH_H +#define STM32L4xx_HAL_HASH_H #ifdef __cplusplus extern "C" { #endif -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ - +#if defined (HASH) /** @addtogroup HASH * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup HASH_Exported_Types HASH Exported Types * @{ */ -/** - * @brief HASH Configuration Structure definition +/** + * @brief HASH Configuration Structure definition */ typedef struct -{ +{ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data. This parameter can be a value of @ref HASH_Data_Type. */ - + uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ - + uint8_t* pKey; /*!< The key is used only in HMAC operation. */ - + } HASH_InitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { - HAL_HASH_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_HASH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_HASH_STATE_BUSY = 0x02, /*!< Processing (hashing) is ongoing */ - HAL_HASH_STATE_TIMEOUT = 0x06, /*!< Timeout state */ - HAL_HASH_STATE_ERROR = 0x07, /*!< Error state */ - HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */ + HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */ + HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ + HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */ + HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */ }HAL_HASH_StateTypeDef; -/** - * @brief HAL phase structures definition - */ +/** + * @brief HAL phase structures definition + */ typedef enum { - HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready to start */ - HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in HASH processing phase */ - HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, /*!< HASH peripheral is in HMAC step 1 processing phase + HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */ + HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */ + HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase (step 1 consists in entering the inner hash function key) */ - HAL_HASH_PHASE_HMAC_STEP_2 = 0x04, /*!< HASH peripheral is in HMAC step 2 processing phase + HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase (step 2 consists in entering the message text) */ - HAL_HASH_PHASE_HMAC_STEP_3 = 0x05 /*!< HASH peripheral is in HMAC step 3 processing phase + HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase (step 3 consists in entering the outer hash function key) */ }HAL_HASH_PhaseTypeDef; -/** +/** * @brief HAL HASH mode suspend definitions */ typedef enum { - HAL_HASH_SUSPEND_NONE = 0x00, /*!< HASH peripheral suspension not requested */ - HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */ + HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ + HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ }HAL_HASH_SuspendTypeDef; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL HASH common Callback ID enumeration definition + */ +typedef enum +{ + HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */ + HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */ + HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ + HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ + HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ +}HAL_HASH_CallbackIDTypeDef; +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ -/** - * @brief HASH Handle Structure definition - */ + +/** + * @brief HASH Handle Structure definition + */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +typedef struct __HASH_HandleTypeDef +#else typedef struct -{ +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ +{ HASH_InitTypeDef Init; /*!< HASH required parameters */ - + uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ - + uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ __IO uint32_t HashInCount; /*!< Counter of inputted data */ - + __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */ - + __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */ - + HAL_StatusTypeDef Status; /*!< HASH peripheral status */ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */ @@ -143,15 +143,38 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */ - - HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ - - FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */ - - __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ + HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ + + FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */ + + __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ + + __IO uint32_t ErrorCode; /*!< HASH Error code */ + + __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */ + + void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */ + + void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */ + + void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */ + + void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */ + +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ } HASH_HandleTypeDef; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL HASH Callback pointer definition + */ +typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /** * @} */ @@ -164,19 +187,19 @@ typedef struct /** @defgroup HASH_Algo_Selection HASH algorithm selection * @{ - */ -#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ + */ +#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */ +#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ #define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ #define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ -#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ /** * @} */ /** @defgroup HASH_Algorithm_Mode HASH algorithm mode * @{ - */ -#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ + */ +#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */ #define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ /** * @} @@ -184,8 +207,8 @@ typedef struct /** @defgroup HASH_Data_Type HASH input data type * @{ - */ -#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ + */ +#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */ #define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ #define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ @@ -195,8 +218,8 @@ typedef struct /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type * @{ - */ -#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */ + */ +#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */ #define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */ /** * @} @@ -204,36 +227,46 @@ typedef struct /** @defgroup HASH_flags_definition HASH flags definitions * @{ - */ -#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */ -#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ -#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */ + */ +#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */ +#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ +#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */ /** * @} - */ + */ /** @defgroup HASH_interrupts_definition HASH interrupts definitions * @{ - */ + */ #define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ #define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ /** * @} */ - /** @defgroup HASH_alias HASH API alias * @{ */ #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */ /** * @} - */ - - + */ + +/** @defgroup HASH_Error_Definition HASH Error Definition + * @{ + */ +#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */ +#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +/** + * @} + */ /** * @} @@ -247,10 +280,10 @@ typedef struct /** @brief Check whether or not the specified HASH flag is set. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. * @arg @ref HASH_FLAG_DCIS Digest calculation complete. * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. - * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. + * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. * @retval The new state of __FLAG__ (TRUE or FALSE). */ @@ -262,7 +295,7 @@ typedef struct /** @brief Clear the specified HASH flag. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: - * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. * @arg @ref HASH_FLAG_DCIS Digest calculation complete * @retval None */ @@ -291,7 +324,17 @@ typedef struct * @param __HANDLE__: HASH handle. * @retval None */ + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_HASH_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /** @brief Reset HASH handle status. * @param __HANDLE__: HASH handle. @@ -300,11 +343,11 @@ typedef struct #define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK) /** - * @brief Enable the multi-buffer DMA transfer mode. - * @note This bit is set when hashing large files when multiple DMA transfers are needed. + * @brief Enable the multi-buffer DMA transfer mode. + * @note This bit is set when hashing large files when multiple DMA transfers are needed. * @retval None */ -#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) +#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) /** * @brief Disable the multi-buffer DMA transfer mode. @@ -313,7 +356,6 @@ typedef struct #define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT) - /** * @brief Start the digest computation. * @retval None @@ -325,13 +367,13 @@ typedef struct * @param __SIZE__: size in bytes of last data written in Data register. * @retval None */ -#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4)) - +#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) + /** * @brief Reset the HASH core. * @retval None */ -#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT) +#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT) /** * @} @@ -342,73 +384,59 @@ typedef struct /** @defgroup HASH_Private_Macros HASH Private Macros * @{ */ - /** * @brief Return digest length in bytes. * @retval Digest length */ -#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20 : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28 : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32 : 16 ) ) ) - +#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \ + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) /** * @brief Return number of words already pushed in the FIFO. * @retval Number of words already pushed in the FIFO */ -#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8) +#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U) /** * @brief Ensure that HASH input data type is valid. - * @param __DATATYPE__: HASH input data type. + * @param __DATATYPE__: HASH input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) - */ + */ #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \ ((__DATATYPE__) == HASH_DATATYPE_8B) || \ - ((__DATATYPE__) == HASH_DATATYPE_1B)) - - - + ((__DATATYPE__) == HASH_DATATYPE_1B)) + /** - * @brief Ensure that input data buffer size is valid for multi-buffer HASH - * processing in polling mode. - * @note This check is valid only for multi-buffer HASH processing in polling mode. - * @param __SIZE__: input data buffer size. + * @brief Ensure that input data buffer size is valid for multi-buffer HASH + * processing in DMA mode. + * @note This check is valid only for multi-buffer HASH processing in DMA mode. + * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ -#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0) +#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U)) /** - * @brief Ensure that input data buffer size is valid for multi-buffer HASH - * processing in DMA mode. - * @note This check is valid only for multi-buffer HASH processing in DMA mode. - * @param __SIZE__: input data buffer size. - * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0)) - -/** - * @brief Ensure that input data buffer size is valid for multi-buffer HMAC + * @brief Ensure that input data buffer size is valid for multi-buffer HMAC * processing in DMA mode. * @note This check is valid only for multi-buffer HMAC processing in DMA mode. - * @param __HANDLE__: HASH handle. - * @param __SIZE__: input data buffer size. + * @param __HANDLE__: HASH handle. + * @param __SIZE__: input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0)) - + */ +#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U)) /** * @brief Ensure that handle phase is set to HASH processing. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__: HASH handle. * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing) - */ + */ #define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS) /** * @brief Ensure that handle phase is set to HMAC processing. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__: HASH handle. * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing) - */ + */ #define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) @@ -417,7 +445,6 @@ typedef struct * @} */ - /* Include HASH HAL Extended module */ #include "stm32l4xx_hal_hash_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -425,8 +452,8 @@ typedef struct /** @addtogroup HASH_Exported_Functions HASH Exported Functions * @{ */ - -/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -438,12 +465,18 @@ void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + /** * @} */ -/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode +/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode * @{ */ @@ -458,19 +491,21 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p * @} */ -/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode +/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode * @{ */ /* HASH processing using IT **************************************************/ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_MD5_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} */ -/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode +/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode * @{ */ @@ -484,7 +519,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu * @} */ -/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode +/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode * @{ */ @@ -496,7 +531,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @} */ -/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode +/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode * @{ */ @@ -507,7 +542,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @} */ -/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode +/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @{ */ @@ -519,7 +554,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @} */ -/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions +/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions * @{ */ @@ -531,16 +566,17 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); /** * @} */ - + /** * @} */ -/* Private functions -----------------------------------------------------------*/ +/* Private functions -----------------------------------------------------------*/ /** @addtogroup HASH_Private_Functions HASH Private Functions * @{ @@ -549,6 +585,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); /* Private functions */ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm); HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm); HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); @@ -558,23 +595,22 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /** * @} - */ + */ /** * @} */ - +#endif /* HASH*/ /** * @} - */ - -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ - + */ + + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_HASH_H */ +#endif /* STM32L4xx_HAL_HASH_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c index 0b5fe23b97..b38bba3fa5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c @@ -3,22 +3,22 @@ * @file stm32l4xx_hal_hash_ex.c * @author MCD Application Team * @brief Extended HASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the HASH peripheral for SHA-224 and SHA-256 * alogrithms: * + HASH or HMAC processing in polling mode * + HASH or HMAC processing in interrupt mode * + HASH or HMAC processing in DMA mode * Additionally, this file provides functions to manage HMAC - * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 - * and SHA-256. - * - * + * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 + * and SHA-256. + * + * @verbatim =============================================================================== ##### HASH peripheral extended features ##### =============================================================================== - [..] + [..] The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly the same way as for SHA-1 or MD-5 algorithms. (#) Three modes are available. @@ -30,115 +30,104 @@ e.g. HAL_HASHEx_xxx_Start_IT() (##) DMA mode: processing APIs are not blocking functions and the CPU is not used for data transfer i.e. the data transfer is ensured by DMA, - e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to + e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to HAL_HASHEx_xxx_Finish() is then required to retrieve the digest. - - (#)Multi-buffer processing is possible in polling and DMA mode. - (##) In polling mode, only multi-buffer HASH processing is possible. + + (#)Multi-buffer processing is possible in polling, interrupt and DMA modes. + (##) In polling mode, only multi-buffer HASH processing is possible. API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as + User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as well the computed digest. - + + (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, + except for the last one. + User must resort to HAL_HASHEx_xxx_Start_IT() to enter the last one and retrieve as + well the computed digest. + (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API. + From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the - same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to + same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASHEx_xxx_Finish(). - + (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to extended functions): after initialization, the key and the first input buffer are entered - in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and + in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and starts step 2. The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this point, the HMAC processing is still carrying out step 2. - Then, step 2 for the last input buffer and step 3 are carried out by a single call + Then, step 2 for the last input buffer and step 3 are carried out by a single call to HAL_HMACEx_xxx_Step2_3_DMA(). - + The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for - MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256. - - + MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#ifdef HAL_HASH_MODULE_ENABLED -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined (HASH) /** @defgroup HASHEx HASHEx * @brief HASH HAL extended module driver. * @{ */ - +#ifdef HAL_HASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +#if defined (HASH_CR_MDMAT) /** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions * @{ */ - -/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode - * @brief HASH extended processing functions using polling mode. +/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode + * @brief HASH extended processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HASH extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the hash value using one of the following algorithms: (+) SHA224 - (++) HAL_HASHEx_SHA224_Start() - (++) HAL_HASHEx_SHA224_Accumulate() + (++) HAL_HASHEx_SHA224_Start() + (++) HAL_HASHEx_SHA224_Accumulate() (+) SHA256 - (++) HAL_HASHEx_SHA256_Start() - (++) HAL_HASHEx_SHA256_Accumulate() - + (++) HAL_HASHEx_SHA256_Start() + (++) HAL_HASHEx_SHA256_Accumulate() + [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). - + [..] In case of multi-buffer HASH processing (a single digest is computed while - several buffers are fed to the IP), the user can resort to successive calls + several buffers are fed to the Peripheral), the user can resort to successive calls to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASHEx_xxx_Start(). + to HAL_HASHEx_xxx_Start(). @endverbatim * @{ @@ -147,13 +136,13 @@ /** * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -162,20 +151,20 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI } /** - * @brief If not already done, initialize the HASH peripheral in SHA224 mode then + * @brief If not already done, initialize the HASH peripheral in SHA224 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA224_Start(). + * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA224_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the Peripheral has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. @@ -188,13 +177,13 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value + * @param Timeout: Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -203,20 +192,20 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI } /** - * @brief If not already done, initialize the HASH peripheral in SHA256 mode then + * @brief If not already done, initialize the HASH peripheral in SHA256 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA256_Start(). + * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA256_Start(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the Peripheral has already been initialized. * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. + * to manage the ending buffer with a length in bytes not a multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes, must be a multiple of 4. @@ -232,17 +221,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ * @} */ -/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode - * @brief HASH extended processing functions using interrupt mode. +/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode + * @brief HASH extended processing functions using interrupt mode. * -@verbatim +@verbatim =============================================================================== ##### Interruption mode HASH extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the hash value using one of the following algorithms: (+) SHA224 - (++) HAL_HASHEx_SHA224_Start_IT() + (++) HAL_HASHEx_SHA224_Start_IT() (+) SHA256 (++) HAL_HASHEx_SHA256_Start_IT() @@ -253,62 +242,108 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); } +/** + * @brief If not already done, initialize the HASH peripheral in SHA224 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA224_Start_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash: HASH handle. + * @param pInBuffer: pointer to the input buffer (buffer to be hashed). + * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); +} + /** * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then - * read the computed digest in interruption mode. + * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); } +/** + * @brief If not already done, initialize the HASH peripheral in SHA256 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA256_Start_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash: HASH handle. + * @param pInBuffer: pointer to the input buffer (buffer to be hashed). + * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); +} + /** * @} */ -/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode - * @brief HASH extended processing functions using DMA mode. +/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode + * @brief HASH extended processing functions using DMA mode. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HASH extended processing functionss ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the hash value using one of the following algorithms: (+) SHA224 - (++) HAL_HASHEx_SHA224_Start_DMA() - (++) HAL_HASHEx_SHA224_Finish() + (++) HAL_HASHEx_SHA224_Start_DMA() + (++) HAL_HASHEx_SHA224_Finish() (+) SHA256 (++) HAL_HASHEx_SHA256_Start_DMA() (++) HAL_HASHEx_SHA256_Finish() - - [..] When resorting to DMA mode to enter the data in the IP, user must resort - to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with - HAL_HASHEx_xxx_Finish(). - + + [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort + to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with + HAL_HASHEx_xxx_Finish(). + [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before - the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be + the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally - retrieved thanks to HAL_HASHEx_xxx_Finish(). + retrieved thanks to HAL_HASHEx_xxx_Finish(). @endverbatim * @{ @@ -319,81 +354,81 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** * @brief Return the computed digest in SHA224 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in - * HMAC SHA224 mode. + * HMAC SHA224 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); +{ + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must - * be called to retrieve the computed digest. + * be called to retrieve the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); + return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** * @brief Return the computed digest in SHA256 mode. * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in - * HMAC SHA256 mode. + * HMAC SHA256 mode. * @param hhash: HASH handle. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); +{ + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** * @} */ -/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode - * @brief HMAC extended processing functions using polling mode. +/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode + * @brief HMAC extended processing functions using polling mode. * -@verbatim +@verbatim =============================================================================== ##### Polling mode HMAC extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in polling mode the HMAC value using one of the following algorithms: (+) SHA224 - (++) HAL_HMACEx_SHA224_Start() + (++) HAL_HMACEx_SHA224_Start() (+) SHA256 - (++) HAL_HMACEx_SHA256_Start() + (++) HAL_HMACEx_SHA256_Start() @endverbatim * @{ @@ -403,124 +438,124 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } /** * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then - * read the computed digest. + * read the computed digest. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value. + * @param Timeout: Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) -{ +{ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } /** * @} */ - - -/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode - * @brief HMAC extended processing functions using interruption mode. + + +/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode + * @brief HMAC extended processing functions using interruption mode. * -@verbatim +@verbatim =============================================================================== ##### Interrupt mode HMAC extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in interrupt mode the HMAC value using one of the following algorithms: (+) SHA224 - (++) HAL_HMACEx_SHA224_Start_IT() + (++) HAL_HMACEx_SHA224_Start_IT() (+) SHA256 - (++) HAL_HMACEx_SHA256_Start_IT() + (++) HAL_HMACEx_SHA256_Start_IT() @endverbatim * @{ */ - + /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); -} - +} + /** * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then - * read the computed digest in interrupt mode. + * read the computed digest in interrupt mode. * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) -{ +{ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); -} - - - - +} + + + + /** * @} */ - -/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions using DMA mode. + +/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode + * @brief HMAC extended processing functions using DMA mode. * -@verbatim +@verbatim =============================================================================== ##### DMA mode HMAC extended processing functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the HMAC value using one of the following algorithms: (+) SHA224 - (++) HAL_HMACEx_SHA224_Start_DMA() + (++) HAL_HMACEx_SHA224_Start_DMA() (+) SHA256 (++) HAL_HMACEx_SHA256_Start_DMA() - - [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, - user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest - with HAL_HASHEx_xxx_Finish(). + + [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing, + user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest + with HAL_HASHEx_xxx_Finish(). @endverbatim @@ -530,48 +565,48 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the Peripheral. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required + * DMA transfers to feed the key and the input buffer to the Peripheral. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be + * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. + * be reset and the buffer length (in bytes) doesn't have to be a + * multiple of 4. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (buffer to be hashed). * @param Size: length of the input buffer in bytes. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -582,50 +617,51 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @} */ -/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions in multi-buffer DMA mode. +/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode + * @brief HMAC extended processing functions in multi-buffer DMA mode. * -@verbatim +@verbatim =============================================================================== ##### Multi-buffer DMA mode HMAC extended processing functions ##### =============================================================================== - [..] This section provides functions to manage HMAC multi-buffer + [..] This section provides functions to manage HMAC multi-buffer DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms. (+) MD5 - (++) HAL_HMACEx_MD5_Step1_2_DMA() - (++) HAL_HMACEx_MD5_Step2_DMA() - (++) HAL_HMACEx_MD5_Step2_3_DMA() + (++) HAL_HMACEx_MD5_Step1_2_DMA() + (++) HAL_HMACEx_MD5_Step2_DMA() + (++) HAL_HMACEx_MD5_Step2_3_DMA() (+) SHA1 - (++) HAL_HMACEx_SHA1_Step1_2_DMA() - (++) HAL_HMACEx_SHA1_Step2_DMA() - (++) HAL_HMACEx_SHA1_Step2_3_DMA() + (++) HAL_HMACEx_SHA1_Step1_2_DMA() + (++) HAL_HMACEx_SHA1_Step2_DMA() + (++) HAL_HMACEx_SHA1_Step2_3_DMA() + (+) SHA256 - (++) HAL_HMACEx_SHA224_Step1_2_DMA() - (++) HAL_HMACEx_SHA224_Step2_DMA() - (++) HAL_HMACEx_SHA224_Step2_3_DMA() + (++) HAL_HMACEx_SHA224_Step1_2_DMA() + (++) HAL_HMACEx_SHA224_Step2_DMA() + (++) HAL_HMACEx_SHA224_Step2_3_DMA() (+) SHA256 - (++) HAL_HMACEx_SHA256_Step1_2_DMA() - (++) HAL_HMACEx_SHA256_Step2_DMA() - (++) HAL_HMACEx_SHA256_Step2_3_DMA() - + (++) HAL_HMACEx_SHA256_Step1_2_DMA() + (++) HAL_HMACEx_SHA256_Step2_DMA() + (++) HAL_HMACEx_SHA256_Step2_3_DMA() + [..] User must first start-up the multi-buffer DMA-based HMAC computation in calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and intiates step 2 with the first input buffer. - - [..] The following buffers are next fed to the IP with a call to the API + + [..] The following buffers are next fed to the Peripheral with a call to the API HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls to this API. - + [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to - HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input - buffer to the IP then carries out step 3. - + HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input + buffer to the Peripheral then carries out step 3. + [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or - SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. - + SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. + [..] If only two buffers need to be consecutively processed, a call to HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA() - is sufficient. + is sufficient. @endverbatim * @{ @@ -633,15 +669,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the Peripheral, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -655,14 +691,14 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief MD5 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -672,23 +708,23 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the Peripheral, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -703,15 +739,15 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the Peripheral, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -725,14 +761,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA1 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -742,23 +778,23 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } /** * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the Peripheral, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -772,15 +808,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the Peripheral, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -794,14 +830,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA224 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -811,23 +847,23 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the Peripheral, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -841,15 +877,15 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, - * step 2 consists in writing the message text. + * @note Step 1 consists in writing the inner hash function key in the Peripheral, + * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -863,14 +899,14 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA256 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, + * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. + * @note Same key is used for the inner and the outer hash functions; pointer to key and + * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. + * HASH digest computation is corrupted. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -880,23 +916,23 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t { if (hhash->DigestCalculationDisable != SET) { - return HAL_ERROR; + return HAL_ERROR; } return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, - * step 3 consists in writing the outer hash function key. + * @note Step 2 consists in writing the message text in the Peripheral, + * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and + * then carries out HMAC step 3. + * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. + * @note Once the DMA transfers are finished (indicated by hhash->State set back + * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve + * the computed digest. * @param hhash: HASH handle. * @param pInBuffer: pointer to the input buffer (message buffer). * @param Size: length of the input buffer in bytes. @@ -912,21 +948,20 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ - +#endif /* MDMA defined*/ /** * @} */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ - #endif /* HAL_HASH_MODULE_ENABLED */ +/** + * @} + */ +#endif /* HASH*/ +/** + * @} + */ + + + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h index 8a0011e62c..8ab8673e7c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h @@ -6,66 +6,48 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_HASH_EX_H -#define __STM32L4xx_HAL_HASH_EX_H +#ifndef STM32L4xx_HAL_HASH_EX_H +#define STM32L4xx_HAL_HASH_EX_H #ifdef __cplusplus extern "C" { #endif -#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ - +#if defined (HASH) /** @addtogroup HASHEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions * @{ */ - -/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode + +/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode * @{ */ @@ -78,18 +60,20 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode +/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode * @{ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); /** * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode +/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); @@ -101,7 +85,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode +/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); @@ -110,7 +94,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode +/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode * @{ */ @@ -121,10 +105,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @} */ -/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode +/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode * @{ */ - + HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); @@ -143,7 +127,6 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); @@ -151,10 +134,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - /** * @} - */ + */ /** * @} @@ -162,19 +144,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @} - */ - + */ +#endif /* HASH*/ /** * @} */ - -#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ - + + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_HASH_EX_H */ +#endif /* STM32L4xx_HAL_HASH_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c index daed433956..caf4e7b23c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c @@ -3,13 +3,13 @@ * @file stm32l4xx_hal_hcd.c * @author MCD Application Team * @brief HCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -17,19 +17,18 @@ [..] (#)Declare a HCD_HandleTypeDef handle structure, for example: HCD_HandleTypeDef hhcd; - + (#)Fill parameters of Init structure in HCD handle - - (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: - (##) Enable the HCD/USB Low Level interface clock using the following macro - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE() - + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt - + (#)Associate the Upper USB Host stack to the HAL HCD Driver: (##) hhcd.pData = phost; @@ -40,51 +39,33 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ -/** @defgroup HCD HCD +#ifdef HAL_HCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) + +/** @defgroup HCD HCD * @brief HCD HAL module driver * @{ */ -#ifdef HAL_HCD_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -94,7 +75,7 @@ * @{ */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); /** @@ -106,88 +87,114 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); * @{ */ -/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ /** - * @brief Initialize the Host driver. - * @param hhcd: HCD handle + * @brief Initialize the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) -{ +{ + USB_OTG_GlobalTypeDef *USBx; + /* Check the HCD handle allocation */ - if(hhcd == NULL) + if (hhcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - if(hhcd->State == HAL_HCD_STATE_RESET) + USBx = hhcd->Instance; + + if (hhcd->State == HAL_HCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hhcd->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ } hhcd->State = HAL_HCD_STATE_BUSY; + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hhcd->Init.dma_enable = 0U; + } + /* Disable the Interrupts */ - __HAL_HCD_DISABLE(hhcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hhcd->Instance, hhcd->Init); - - /* Force Host Mode*/ - USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE); - - /* Init Host */ - USB_HostInit(hhcd->Instance, hhcd->Init); - - hhcd->State= HAL_HCD_STATE_READY; - - return HAL_OK; + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; } /** - * @brief Initialize a Host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number. + * @param epnum Endpoint number. * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed: Current device speed. + * @param speed Current device speed. * This parameter can be one of these values: - * HCD_SPEED_HIGH: High speed mode, * HCD_SPEED_FULL: Full speed mode, * HCD_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type, * EP_TYPE_ISOC: Isochronous type, * EP_TYPE_BULK: Bulk type, * EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size. + * @param mps Max Packet Size. * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -195,81 +202,95 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ep_type, uint16_t mps) { - HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - + HAL_StatusTypeDef status; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; hhcd->hc[ch_num].dev_addr = dev_address; hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7F; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); - hhcd->hc[ch_num].speed = speed; - - // Added for MBED PR #3432 - /* reset to 0 */ - hhcd->hc[ch_num].toggle_out = 0; - hhcd->hc[ch_num].toggle_in = 0; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; - status = USB_HC_Init(hhcd->Instance, + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + hhcd->hc[ch_num].speed = speed; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, dev_address, speed, ep_type, mps); - __HAL_UNLOCK(hhcd); - + __HAL_UNLOCK(hhcd); + return status; } /** - * @brief Halt a Host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) { HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - USB_HC_Halt(hhcd->Instance, ch_num); + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_UNLOCK(hhcd); - + return status; } /** - * @brief DeInitialize the Host driver. - * @param hhcd: HCD handle + * @brief DeInitialize the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) { /* Check the HCD handle allocation */ - if(hhcd == NULL) + if (hhcd == NULL) { return HAL_ERROR; } - + hhcd->State = HAL_HCD_STATE_BUSY; - + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_HCD_MspDeInit(hhcd); - - __HAL_HCD_DISABLE(hhcd); - - hhcd->State = HAL_HCD_STATE_RESET; - +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + return HAL_OK; } /** * @brief Initialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) @@ -278,13 +299,13 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) UNUSED(hhcd); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file + the HAL_HCD_MspInit could be implemented in the user file */ } /** * @brief DeInitialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) @@ -293,7 +314,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) UNUSED(hhcd); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file + the HAL_HCD_MspDeInit could be implemented in the user file */ } @@ -301,76 +322,59 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) * @} */ -/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions * @brief HCD IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USB Host Data + [..] This subsection provides a set of functions allowing to manage the USB Host Data Transfer - + @endverbatim * @{ */ - -/** + +/** * @brief Submit a new URB for processing. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param direction: Channel number. + * @param direction Channel number. * This parameter can be one of these values: * 0 : Output / 1 : Input - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type/ * EP_TYPE_ISOC: Isochronous type/ * EP_TYPE_BULK: Bulk type/ * EP_TYPE_INTR: Interrupt type/ - * @param token: Endpoint Type. + * @param token Endpoint Type. * This parameter can be one of these values: * 0: HC_PID_SETUP / 1: HC_PID_DATA1 - * @param pbuff: pointer to URB data - * @param length: Length of URB data - * @param do_ping: activate do ping protocol (for high speed only). + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). * This parameter can be one of these values: - * 0 : do ping inactive / 1 : do ping active + * 0 : do ping inactive / 1 : do ping active * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, - uint16_t length, - uint8_t do_ping) + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) { - // Added for MBED PR #3432 - if (hhcd->hc[ch_num].ep_is_in != direction) { - if (hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL){ - /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - if (direction) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - USBx_HC(ch_num)->HCCHAR |= 1 << 15; - } - else - { - USBx_HC(ch_num)->HCINTMSK &= ~USB_OTG_HCINTMSK_BBERRM; - USBx_HC(ch_num)->HCCHAR &= ~(1 << 15); - } - hhcd->hc[ch_num].ep_is_in = direction; - /* if reception put toggle_in to 1 */ - if (direction == 1) hhcd->hc[ch_num].toggle_in=1; - } - } + UNUSED(do_ping); + + hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; - - if(token == 0) + + if (token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; } @@ -378,215 +382,216 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, { hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } - + /* Manage Data Toggle */ - switch(ep_type) + switch (ep_type) { - case EP_TYPE_CTRL: - if((token == 1) && (direction == 0)) /*send data */ - { - if ( length == 0 ) - { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1; - } - - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /*send data */ { - hhcd->hc[ch_num].do_ping = do_ping; + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } - } - // Added for MBED PR #3432 - else if ((token == 1) && (direction == 1)) - { - if( hhcd->hc[ch_num].toggle_in == 0) + break; + + case EP_TYPE_BULK: + if (direction == 0U) { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } - } - break; - - case EP_TYPE_BULK: - if(direction == 0) - { - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) + + break; + case EP_TYPE_INTR: + if (direction == 0U) { - hhcd->hc[ch_num].do_ping = do_ping; - } - } - else - { - if( hhcd->hc[ch_num].toggle_in == 0) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } else { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } } - } - - break; - case EP_TYPE_INTR: - if(direction == 0) - { - /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) - { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - } - else - { - if( hhcd->hc[ch_num].toggle_in == 0) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - break; - - case EP_TYPE_ISOC: - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - break; + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; } - + hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0 ; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].state = HC_IDLE; - - return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num]); } /** * @brief Handle HCD interrupt request. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t i = 0 , interrupt = 0; - - /* ensure that we are in device mode */ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, interrupt; + + /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) { - /* avoid spurious interrupt */ - if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) { return; } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); } - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); - } - - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); - } - + } + /* Handle Host Disconnect Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) { - + /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - /* Handle Host Port Interrupts */ + USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else HAL_HCD_Disconnect_Callback(hhcd); - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); } - + /* Handle Host Port Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) { - HCD_Port_IRQHandler (hhcd); + HCD_Port_IRQHandler(hhcd); } - - /* Handle Host SOF Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } - - /* Handle Host channel Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (i = 0; i < hhcd->Init.Host_channels ; i++) + for (i = 0U; i < hhcd->Init.Host_channels; i++) { - if (interrupt & (1 << i)) + if ((interrupt & (1UL << (i & 0xFU))) != 0U) { - if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR) + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) { - HCD_HC_IN_IRQHandler (hhcd, i); + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); } else { - HCD_HC_OUT_IRQHandler (hhcd, i); + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); } } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); - } - + } + /* Handle Rx Queue Level Interrupts */ - if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler (hhcd); - + + HCD_RXQLVL_IRQHandler(hhcd); + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); } } @@ -594,7 +599,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @brief SOF callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) @@ -609,7 +614,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Connection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) @@ -624,7 +629,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Disconnection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) @@ -635,21 +640,51 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ -} +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} /** * @brief Notify URB state change callback. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @param urb_state: * This parameter can be one of these values: * URB_IDLE/ * URB_DONE/ * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ * @retval None */ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) @@ -664,19 +699,295 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t */ } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callabck is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the HCD data + This subsection provides a set of functions allowing to control the HCD data transfers. @endverbatim @@ -684,36 +995,36 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t */ /** - * @brief Start the Host driver. - * @param hhcd: HCD handle + * @brief Start the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); +{ + __HAL_LOCK(hhcd); __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); - __HAL_UNLOCK(hhcd); + (void)USB_DriveVbus(hhcd->Instance, 1U); + __HAL_UNLOCK(hhcd); return HAL_OK; } /** - * @brief Stop the Host driver. - * @param hhcd: HCD handle + * @brief Stop the host driver. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); - USB_StopHost(hhcd->Instance); - __HAL_UNLOCK(hhcd); +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); return HAL_OK; } /** - * @brief Reset the Host port. - * @param hhcd: HCD handle + * @brief Reset the host port. + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) @@ -725,15 +1036,15 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) * @} */ -/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -742,7 +1053,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) /** * @brief Return the HCD handle state. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL state */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) @@ -752,17 +1063,17 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) /** * @brief Return URB state for a channel. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval URB state. * This parameter can be one of these values: * URB_IDLE/ * URB_DONE/ * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL + * URB_NYET/ + * URB_ERROR/ + * URB_STALL */ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) { @@ -771,32 +1082,32 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu /** - * @brief Return the last Host transfer size. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - return hhcd->hc[chnum].xfer_count; + return hhcd->hc[chnum].xfer_count; } - + /** * @brief Return the Host Channel state. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval Host channel state * This parameter can be one of these values: * HC_IDLE/ * HC_XFRC/ * HC_HALTED/ - * HC_NYET/ - * HC_NAK/ - * HC_STALL/ - * HC_XACTERR/ - * HC_BBLERR/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ * HC_DATATGLERR */ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) @@ -806,7 +1117,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the current Host frame number. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Current Host frame number */ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) @@ -816,7 +1127,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) /** * @brief Return the Host enumeration speed. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Enumeration speed */ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) @@ -837,428 +1148,454 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) */ /** * @brief Handle Host Channel IN interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - hhcd->hc[chnum].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - } - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - - if (hhcd->Init.dma_enable) - { - hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \ - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); - } - - hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - - } - else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) - { - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - hhcd->hc[chnum].toggle_in ^= 1; - + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) + else { - // Added for MBED PR #3432 - int reactivate = 0; - __HAL_HCD_MASK_HALT_HC_INT(chnum); - - if(hhcd->hc[chnum].state == HC_XFRC) + /* ... */ + } + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + hhcd->hc[ch_num].state = HC_XFRC; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - hhcd->hc[chnum].urb_state = URB_DONE; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - - else if (hhcd->hc[chnum].state == HC_STALL) + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { - hhcd->hc[chnum].urb_state = URB_STALL; - } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[ch_num].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else { - if(hhcd->hc[chnum].ErrCnt++ > 3) - { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + /* ... */ + } + hhcd->hc[ch_num].toggle_in ^= 1U; + + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + { + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + } + else if (hhcd->hc[ch_num].state == HC_STALL) + { + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - + /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - // Added for MBED PR #3432 #4231 - if ( hhcd->hc[chnum].urb_state != URB_ERROR) { - tmpreg |= USB_OTG_HCCHAR_CHENA; - reactivate = 1; - } - USBx_HC(chnum)->HCCHAR = tmpreg; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - // Added for MBED PR #3432 #4231 - if (hhcd->hc[chnum].state == 0) reactivate = 1; - if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - hhcd->hc[chnum].ErrCnt++; - hhcd->hc[chnum].state = HC_XACTERR; - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - } - - /* Clear the NAK flag before re-enabling the channel for new IN request */ - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + else if (hhcd->hc[ch_num].state == HC_NAK) { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; /* re-activate the channel */ - USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + { + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ } } /** * @brief Handle Host Channel OUT interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ -static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; - - if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - - if( hhcd->hc[chnum].do_ping == 1) + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + + if (hhcd->hc[ch_num].do_ping == 1U) { - hhcd->hc[chnum].state = HC_NYET; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { - hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].ErrCnt= 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - hhcd->hc[chnum].state = HC_XFRC; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_STALL; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; - } + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + { + __HAL_HCD_MASK_HALT_HC_INT(ch_num); - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_STALL; - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_XACTERR; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - hhcd->hc[chnum].state = HC_DATATGLERR; - } - - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) - { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - - if(hhcd->hc[chnum].state == HC_XFRC) + if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; - if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) + hhcd->hc[ch_num].urb_state = URB_DONE; + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) { - hhcd->hc[chnum].toggle_out ^= 1; - } + hhcd->hc[ch_num].toggle_out ^= 1U; + } } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[ch_num].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - else if (hhcd->hc[chnum].state == HC_NYET) + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_NYET) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].do_ping = 0; - } - - else if (hhcd->hc[chnum].state == HC_STALL) + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[chnum].urb_state = URB_STALL; - } - - else if((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) - { - hhcd->hc[chnum].ErrCnt = 0; - hhcd->hc[chnum].urb_state = URB_ERROR; + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; } else { - hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; } - + /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(ch_num)->HCCHAR = tmpreg; } - - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + else + { + /* ... */ + } + + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } -} + else + { + /* ... */ + } +} /** * @brief Handle Rx Queue Level interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval none */ -static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; - uint32_t pktcnt; - uint32_t temp = 0; - uint32_t tmpreg = 0; - - temp = hhcd->Instance->GRXSTSP ; - channelnum = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; + + temp = hhcd->Instance->GRXSTSP; + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + switch (pktsts) { - case GRXSTS_PKTSTS_IN: - /* Read the data into the Host buffer. */ - if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) - { - - USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); - - /*manage multiple Xfer */ - hhcd->hc[channelnum].xfer_buff += pktcnt; - hhcd->hc[channelnum].xfer_count += pktcnt; - - if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) { - /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(channelnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(channelnum)->HCCHAR = tmpreg; - hhcd->hc[channelnum].toggle_in ^= 1; - } - } - break; + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - break; - case GRXSTS_PKTSTS_IN_XFER_COMP: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; + /*manage multiple Xfer */ + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; + + if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; } } /** * @brief Handle Host Port interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ -static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0, hprt0_dup; - + /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; hprt0_dup = USBx_HPRT0; - - hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - /* Check whether Port Connect Detected */ - if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) - { - if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } hprt0_dup |= USB_OTG_HPRT_PCDET; - } - + /* Check whether Port Enable Changed */ - if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) { hprt0_dup |= USB_OTG_HPRT_PENCHNG; - - if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) - { - if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); } else { - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } else { - if(hhcd->Init.speed == HCD_SPEED_FULL) + if (hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = (uint32_t)60000; + USBx_HOST->HFIR = 60000U; } } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); HAL_HCD_Connect_Callback(hhcd); - - if(hhcd->Init.speed == HCD_SPEED_HIGH) - { - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } else { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } + USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); + } } - - /* Check For an overcurrent */ - if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { hprt0_dup |= USB_OTG_HPRT_POCCHNG; } @@ -1275,7 +1612,9 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) * @} */ +#endif /* defined (USB_OTG_FS) */ #endif /* HAL_HCD_MODULE_ENABLED */ + /** * @} */ @@ -1284,8 +1623,4 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) * @} */ -#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h index d79b1e531e..ea03d75a9c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h @@ -6,65 +6,46 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_HCD_H -#define __STM32L4xx_HAL_HCD_H +#ifndef STM32L4xx_HAL_HCD_H +#define STM32L4xx_HAL_HCD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" - + +#if defined (USB_OTG_FS) /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @addtogroup HCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Types HCD Exported Types * @{ */ -/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition * @{ - */ -typedef enum + */ +typedef enum { HAL_HCD_STATE_RESET = 0x00, HAL_HCD_STATE_READY = 0x01, @@ -75,25 +56,41 @@ typedef enum typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; -typedef USB_OTG_HCTypeDef HCD_HCTypeDef ; -typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ; -typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; /** * @} */ -/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition * @{ */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +typedef struct __HCD_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ { - HCD_TypeDef *Instance; /*!< Register base address */ + HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ - HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ - void *pData; /*!< Pointer Stack Handler */ - + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } HCD_HandleTypeDef; /** * @} @@ -102,7 +99,7 @@ typedef struct /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ @@ -111,9 +108,9 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ -#define HCD_SPEED_HIGH 0 -#define HCD_SPEED_LOW 2 -#define HCD_SPEED_FULL 3 +#define HCD_SPEED_FULL USBH_FS_SPEED +#define HCD_SPEED_LOW USBH_LS_SPEED + /** * @} */ @@ -121,32 +118,45 @@ typedef struct /** @defgroup HCD_PHY_Module HCD PHY Module * @{ */ -#define HCD_PHY_EMBEDDED 1 +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + /** * @} */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Macros HCD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ -#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) -#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) -#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) -#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) -#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) /** * @} */ @@ -156,25 +166,63 @@ typedef struct * @{ */ -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, - uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ /** * @} */ @@ -184,22 +232,24 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); * @{ */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t pipe, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, uint16_t length, uint8_t do_ping); - /* Non-Blocking mode: Interrupt */ +/* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, - uint8_t chnum, - HCD_URBStateTypeDef urb_state); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, + uint8_t chnum, + HCD_URBStateTypeDef urb_state); /** * @} */ @@ -242,6 +292,20 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); * @} */ +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ + /** * @} */ @@ -249,15 +313,16 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ - -#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) */ + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_HCD_H */ +#endif /* STM32L4xx_HAL_HCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c index f926f76d79..a070a6545e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c @@ -19,7 +19,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -39,54 +39,54 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. - *** Interrupt mode IO sequential operation *** - ============================================== + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== [..] (@) These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change during transfer @@ -98,97 +98,114 @@ and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) + several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() + or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() + or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -196,13 +213,78 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + [..] + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -211,29 +293,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -274,14 +340,14 @@ #define SlaveAddr_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ @@ -300,10 +366,6 @@ */ /* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) - /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -320,8 +382,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); /* Private functions to handle IT transfer */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); @@ -345,14 +407,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -/* Private functions to flush TXDR register */ +/* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); /** * @} */ @@ -424,8 +489,30 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; @@ -504,8 +591,18 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /* Disable the I2C Peripheral Clock */ __HAL_I2C_DISABLE(hi2c); +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_RESET; @@ -550,6 +647,328 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ } +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + /** * @} */ @@ -591,6 +1010,13 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Slave_Receive_IT() (++) HAL_I2C_Mem_Write_IT() (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() (#) No-Blocking mode functions with DMA are : (++) HAL_I2C_Master_Transmit_DMA() @@ -599,15 +1025,22 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Slave_Receive_DMA() (++) HAL_I2C_Mem_Write_DMA() (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() (++) HAL_I2C_MasterTxCpltCallback() (++) HAL_I2C_MasterRxCpltCallback() (++) HAL_I2C_SlaveTxCpltCallback() (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() @endverbatim * @{ @@ -618,7 +1051,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -626,7 +1059,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -638,7 +1071,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_TX; @@ -655,12 +1088,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -668,37 +1101,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; hi2c->XferSize--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -707,14 +1137,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -742,7 +1165,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -750,7 +1173,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -762,7 +1185,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_RX; @@ -779,12 +1202,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -792,38 +1215,35 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -832,14 +1252,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -873,12 +1286,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -904,7 +1318,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear ADDR flag */ @@ -918,7 +1332,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear ADDR flag */ @@ -930,7 +1344,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } while (hi2c->XferCount > 0U) @@ -940,19 +1354,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; } @@ -970,7 +1380,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } else { - return HAL_TIMEOUT; + return HAL_ERROR; } } @@ -982,7 +1392,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Disable Address Acknowledge */ @@ -1013,12 +1423,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -1044,7 +1455,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear ADDR flag */ @@ -1055,7 +1466,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } while (hi2c->XferCount > 0U) @@ -1070,22 +1481,23 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; } - if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; } @@ -1094,15 +1506,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1113,7 +1517,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Disable Address Acknowledge */ @@ -1138,14 +1542,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1180,7 +1584,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1207,14 +1611,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1249,7 +1653,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1374,14 +1778,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1416,37 +1821,71 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t if (hi2c->XferSize > 0U) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { @@ -1455,7 +1894,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1482,14 +1921,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { - uint32_t xfermode = 0U; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1524,37 +1964,71 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D if (hi2c->XferSize > 0U) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { @@ -1563,7 +2037,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1576,6 +2050,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } + return HAL_OK; } else @@ -1594,10 +2069,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef dmaxferstatus; + if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -1614,33 +2092,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -1660,10 +2172,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { + HAL_StatusTypeDef dmaxferstatus; + if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ @@ -1680,33 +2195,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -1720,7 +2269,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1730,7 +2279,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1739,6 +2288,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -1750,7 +2300,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_TX; @@ -1765,30 +2315,21 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } do @@ -1796,38 +2337,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; hi2c->XferSize--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } @@ -1838,14 +2376,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -1873,7 +2404,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1883,7 +2414,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -1892,6 +2423,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -1903,7 +2435,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_RX; @@ -1918,18 +2450,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Send Slave Address */ @@ -1937,12 +2460,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } do @@ -1950,31 +2473,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Wait until RXNE flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -1984,14 +2511,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Clear STOP Flag */ @@ -2018,7 +2538,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2027,8 +2547,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2037,6 +2557,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2075,22 +2596,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2117,7 +2629,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2126,8 +2638,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2136,6 +2648,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2174,22 +2687,13 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2215,7 +2719,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2224,8 +2728,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2234,6 +2739,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2272,51 +2778,77 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -2331,7 +2863,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2340,8 +2872,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2350,6 +2883,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2388,50 +2922,75 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; } - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } return HAL_OK; } @@ -2447,16 +3006,19 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; - __IO uint32_t I2C_Trials = 0U; + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -2479,19 +3041,31 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - /* Device is ready */ + /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + + return HAL_ERROR; } } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); } /* Check if the NACKF flag has not been set */ @@ -2500,7 +3074,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ @@ -2519,7 +3093,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear NACK Flag */ @@ -2530,7 +3104,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) + if (I2C_Trials == Trials) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -2538,21 +3112,28 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } + + /* Increment Trials */ + I2C_Trials++; } while (I2C_Trials < Trials); + /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } else { @@ -2566,15 +3147,15 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - uint32_t xfermode = 0U; + uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; /* Check the parameters */ @@ -2596,7 +3177,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); hi2c->XferISR = I2C_Master_ISR_IT; - /* If size > MAX_NBYTE_SIZE, use reload mode */ + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; @@ -2608,15 +3189,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } - /* If transfer direction not change, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2635,20 +3227,182 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, } /** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - uint32_t xfermode = 0U; + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; /* Check the parameters */ @@ -2682,15 +3436,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } - /* If transfer direction not change, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2708,6 +3473,168 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, } } +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -2718,15 +3645,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2742,6 +3670,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; @@ -2782,6 +3730,185 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, } } +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -2792,15 +3919,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } @@ -2816,6 +3944,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; @@ -2856,6 +4004,185 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u } } +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + /** * @brief Enable the Address listen mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2916,7 +4243,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) @@ -2992,9 +4319,10 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { uint32_t itflags = READ_REG(hi2c->Instance->ISR); uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -3003,7 +4331,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -3012,7 +4340,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -3020,10 +4348,13 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); } + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + /* Call the Error Callback in case of Error detected */ - if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { - I2C_ITError(hi2c, hi2c->ErrorCode); + I2C_ITError(hi2c, tmperror); } } @@ -3265,12 +4596,13 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0U; + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; /* Process Locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3283,41 +4615,52 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -3327,7 +4670,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); + I2C_ITMasterSeqCplt(hi2c); } else { @@ -3337,7 +4680,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -3352,7 +4695,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); + I2C_ITMasterSeqCplt(hi2c); } } } @@ -3363,11 +4706,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } + else + { + /* Nothing to do */ + } - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); + I2C_ITMasterCplt(hi2c, tmpITFlags); } /* Process Unlocked */ @@ -3386,10 +4733,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + /* Process locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -3397,13 +4747,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); + I2C_ITListenCplt(hi2c, tmpITFlags); } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3413,7 +4762,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); + I2C_ITSlaveSeqCplt(hi2c); } else { @@ -3429,30 +4778,43 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } } } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferSize--; hi2c->XferCount--; } if ((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); + I2C_ITSlaveSeqCplt(hi2c); } } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { - I2C_ITAddrCplt(hi2c, ITFlags); + I2C_ITAddrCplt(hi2c, tmpITFlags); } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ @@ -3461,26 +4823,34 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint if (hi2c->XferCount > 0U) { /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + hi2c->XferCount--; hi2c->XferSize--; } else { - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); + I2C_ITSlaveSeqCplt(hi2c); } } } + else + { + /* Nothing to do */ + } /* Check if STOPF is set */ - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); + I2C_ITSlaveCplt(hi2c, tmpITFlags); } /* Process Unlocked */ @@ -3499,13 +4869,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0U; - uint32_t xfermode = 0U; + uint16_t devaddress; + uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3521,7 +4891,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -3529,7 +4899,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui if (hi2c->XferCount != 0U) { /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) @@ -3540,11 +4910,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } } /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3561,16 +4938,55 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } else { - /* Wrong size Status regarding TCR flag event */ + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3588,40 +5004,105 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + /* Process locked */ __HAL_LOCK(hi2c); - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } } else { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ + /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + I2C_ITAddrCplt(hi2c, ITFlags); } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3634,7 +5115,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3643,19 +5124,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* If Memory address size is 8Bit */ @@ -3673,14 +5147,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Send LSB of Memory Address */ @@ -3690,7 +5157,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } return HAL_OK; @@ -3701,7 +5168,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3710,19 +5177,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* If Memory address size is 8Bit */ @@ -3740,14 +5200,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } + return HAL_ERROR; } /* Send LSB of Memory Address */ @@ -3757,7 +5210,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Wait until TC flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } return HAL_OK; @@ -3771,16 +5224,16 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { - uint8_t transferdirection = 0U; - uint16_t slaveaddrcode = 0U; - uint16_t ownadd1code = 0U; - uint16_t ownadd2code = 0U; + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -3806,7 +5259,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } else @@ -3820,7 +5277,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* else 7 bits addressing mode is selected */ @@ -3833,7 +5294,11 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* Else clear address flag only */ @@ -3852,7 +5317,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) * @param hi2c I2C handle. * @retval None */ -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -3872,7 +5337,11 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ else @@ -3888,7 +5357,11 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -3897,7 +5370,7 @@ static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) * @param hi2c I2C handle. * @retval None */ -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -3914,8 +5387,12 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) @@ -3930,8 +5407,16 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Rx complete callback to inform upper layer of the end of receive process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } @@ -3943,6 +5428,8 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { + uint32_t tmperror; + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -3954,7 +5441,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if ((ITFlags & I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3969,8 +5456,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); @@ -3988,7 +5478,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -3998,7 +5492,11 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ @@ -4013,7 +5511,12 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -4022,9 +5525,18 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } + else + { + /* Nothing to do */ + } } /** @@ -4035,12 +5547,12 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); @@ -4054,10 +5566,42 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } } /* All data are not transferred, so set error code accordingly */ @@ -4067,22 +5611,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -4096,11 +5624,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); + I2C_ITListenCplt(hi2c, tmpITFlags); } } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { + /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + I2C_ITSlaveSeqCplt(hi2c); + hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; @@ -4108,7 +5639,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) @@ -4118,8 +5653,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Slave Rx Complete callback */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -4128,8 +5667,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Call the Slave Tx Complete callback */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -4149,10 +5692,13 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; if ((hi2c->XferSize > 0U)) { @@ -4174,7 +5720,11 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_UNLOCK(hi2c); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /** @@ -4185,6 +5735,8 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -4194,9 +5746,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if ((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -4227,18 +5779,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + if (hi2c->hdmatx != NULL) { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } } } /* Abort DMA RX transfer if any */ @@ -4246,18 +5801,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + if (hi2c->hdmarx != NULL) { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } } } else if (hi2c->State == HAL_I2C_STATE_ABORT) @@ -4268,7 +5826,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { @@ -4276,7 +5838,11 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -4308,7 +5874,7 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4336,10 +5902,16 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } } } @@ -4350,12 +5922,24 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } } /** @@ -4365,7 +5949,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -4393,10 +5977,16 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } } } @@ -4407,12 +5997,24 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } } /** @@ -4422,7 +6024,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4439,10 +6041,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ hi2c->hdmatx->XferAbortCallback = NULL; @@ -4454,12 +6053,20 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->State = HAL_I2C_STATE_READY; /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } @@ -4480,14 +6087,15 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } } @@ -4515,7 +6123,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -4524,7 +6132,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } } @@ -4550,7 +6158,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -4559,7 +6167,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } return HAL_OK; @@ -4614,7 +6222,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -4622,7 +6230,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + return HAL_ERROR; } } return HAL_OK; @@ -4647,14 +6255,16 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + + return HAL_ERROR; } } } @@ -4671,7 +6281,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -4702,7 +6312,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -4719,9 +6329,9 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; @@ -4783,8 +6393,6 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; } /** @@ -4792,9 +6400,9 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; @@ -4803,7 +6411,7 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; @@ -4815,7 +6423,7 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; @@ -4850,8 +6458,34 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} - return HAL_OK; +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h index 7a8f85f292..b86d810160 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_H -#define __STM32L4xx_HAL_I2C_H +#ifndef STM32L4xx_HAL_I2C_H +#define STM32L4xx_HAL_I2C_H #ifdef __cplusplus extern "C" { @@ -102,17 +86,17 @@ typedef struct * 01 : Abort (Abort user request on going)\n * 10 : Timeout\n * 11 : Error\n - * b5 IP initilisation status\n - * 0 : Reset (IP not initialized)\n - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n * b4 (not used)\n * x : Should be set to 0\n * b3\n * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (IP in Address Listen Mode)\n + * 1 : Listen (peripheral in Address Listen Mode)\n * b2 Intrinsic process state\n * 0 : Ready\n - * 1 : Busy (IP busy with some configuration or internal operations)\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n * b1 Rx state\n * 0 : Ready (no Rx operation ongoing)\n * 1 : Busy (Rx operation ongoing)\n @@ -186,6 +170,11 @@ typedef enum #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** * @} */ @@ -226,7 +215,54 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ @@ -248,6 +284,13 @@ typedef struct __I2C_HandleTypeDef #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) /** * @} */ @@ -396,7 +439,15 @@ typedef struct __I2C_HandleTypeDef * @param __HANDLE__ specifies the I2C Handle. * @retval None */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. @@ -469,6 +520,7 @@ typedef struct __I2C_HandleTypeDef * * @retval The new state of __FLAG__ (SET or RESET). */ +#define I2C_FLAG_MASK (0x0001FFFFU) #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. @@ -528,6 +580,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ @@ -553,10 +614,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); @@ -568,6 +629,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); /** * @} */ @@ -659,15 +725,20 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) @@ -677,6 +748,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} */ @@ -703,6 +777,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif -#endif /* __STM32L4xx_HAL_I2C_H */ +#endif /* STM32L4xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c index bd4e329dd2..35296a7574 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c @@ -35,29 +35,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -156,7 +140,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { - uint32_t tmpreg = 0U; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h index 726a83fba8..1bae6bafa2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_EX_H -#define __STM32L4xx_HAL_I2C_EX_H +#ifndef STM32L4xx_HAL_I2C_EX_H +#define STM32L4xx_HAL_I2C_EX_H #ifdef __cplusplus extern "C" { @@ -148,6 +132,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) + + + /** * @} */ @@ -181,6 +168,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); } #endif -#endif /* __STM32L4xx_HAL_I2C_EX_H */ +#endif /* STM32L4xx_HAL_I2C_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c index ecefca38d5..8ed8084863 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c @@ -26,13 +26,13 @@ (+++) Enable the clock for the USARTx/UARTx GPIOs. (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() - and HAL_IRDA_Receive_IT() APIs): + and HAL_IRDA_Receive_IT() APIs): (+++) Configure the USARTx/UARTx interrupt priority. - (+++) Enable the NVIC USARTx/UARTx IRQ handle. + (+++) Enable the NVIC USARTx/UARTx IRQ handle. (+++) The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - + (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() and HAL_IRDA_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. @@ -48,11 +48,11 @@ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_IRDA_MspInit() API. - + -@@- The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** @@ -105,33 +105,81 @@ [..] (@) You can refer to the IRDA HAL driver header file for more useful macros + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. + Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + + [..] + By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() + and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() + or @ref HAL_IRDA_Init() function. + + [..] + When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -155,10 +203,10 @@ /** @defgroup IRDA_Private_Constants IRDA Private Constants * @{ */ -#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ +#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ #define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ @@ -168,6 +216,9 @@ */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ #if defined(USART_PRESC_PRESCALER) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ IRDA clock source. @@ -175,29 +226,32 @@ * @param __PRESCALER__ IRDA clock prescaler value. * @retval Division result */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\ + + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ IRDA clock source. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) -#endif +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) +#endif /* USART_PRESC_PRESCALER */ +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -static const uint16_t IRDAPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -#else -#endif - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup IRDA_Private_Functions * @{ */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -210,9 +264,9 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @} */ @@ -248,10 +302,10 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible IRDA frame formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible IRDA frame formats are listed in the following table. - + Table 1. IRDA frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | IRDA frame | @@ -282,7 +336,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == NULL) + if (hirda == NULL) { return HAL_ERROR; } @@ -290,13 +344,25 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /* Check the USART/UART associated to the IRDA handle */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - if(hirda->gState == HAL_IRDA_STATE_RESET) + if (hirda->gState == HAL_IRDA_STATE_RESET) { /* Allocate lock resource and initialize it */ hirda->Lock = HAL_UNLOCKED; +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + IRDA_InitCallbacksToDefault(hirda); + + if (hirda->MspInitCallback == NULL) + { + hirda->MspInitCallback = HAL_IRDA_MspInit; + } + + /* Init the low level hardware */ + hirda->MspInitCallback(hirda); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_IRDA_MspInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ } hirda->gState = HAL_IRDA_STATE_BUSY; @@ -335,7 +401,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == NULL) + if (hirda == NULL) { return HAL_ERROR; } @@ -346,7 +412,16 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) hirda->gState = HAL_IRDA_STATE_BUSY; /* DeInit the low level hardware */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + if (hirda->MspDeInitCallback == NULL) + { + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + } + /* DeInit the low level hardware */ + hirda->MspDeInitCallback(hirda); +#else HAL_IRDA_MspDeInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /* Disable the Peripheral */ __HAL_IRDA_DISABLE(hirda); @@ -392,6 +467,245 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) */ } +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User IRDA Callback + * To be used instead of the weak predefined callback + * @param hirda irda handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hirda); + + if (hirda->gState == HAL_IRDA_STATE_READY) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = pCallback; + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = pCallback; + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hirda->gState == HAL_IRDA_STATE_RESET) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hirda); + + return status; +} + +/** + * @brief Unregister an IRDA callback + * IRDA callback is redirected to the weak predefined callback + * @param hirda irda handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hirda); + + if (HAL_IRDA_STATE_READY == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_IRDA_STATE_RESET == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hirda); + + return status; +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /** * @} */ @@ -464,14 +778,14 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -483,18 +797,19 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @param pData Pointer to data buffer. * @param Size Amount of data to be sent. - * @param Timeout Specify timeout value. + * @param Timeout Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - uint32_t tickstart = 0; + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) + if (hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -510,27 +825,40 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->TxXferSize = Size; hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (hirda->TxXferCount > 0U) { hirda->TxXferCount--; - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t*) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; } else { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; } } - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -555,19 +883,20 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u * the configuration information for the specified IRDA module. * @param pData Pointer to data buffer. * @param Size Amount of data to be received. - * @param Timeout Specify timeout value. + * @param Timeout Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; uint16_t uhMask; - uint32_t tickstart = 0; + uint32_t tickstart; /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) + if (hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -589,24 +918,36 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui IRDA_MASK_COMPUTATION(hirda); uhMask = hirda->Mask; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + /* Check data remaining to be received */ - while(hirda->RxXferCount > 0) + while (hirda->RxXferCount > 0U) { hirda->RxXferCount--; - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData +=2; + *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask); + pdata16bits++; } else { - *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; } } @@ -635,9 +976,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) + if (hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -660,8 +1001,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); -#endif - +#endif /* USART_CR1_FIFOEN */ + return HAL_OK; } else @@ -681,9 +1022,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) + if (hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -707,10 +1048,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); -#endif + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif /* USART_CR1_FIFOEN */ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -734,9 +1075,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(hirda->gState == HAL_IRDA_STATE_READY) + if (hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -764,19 +1105,33 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->hdmatx->XferAbortCallback = NULL; /* Enable the IRDA transmit DMA channel */ - HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size); + if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); - /* Clear the TC flag in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); + /* Process Unlocked */ + __HAL_UNLOCK(hirda); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->gState to ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } } else { @@ -786,20 +1141,20 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When the IRDA parity is enabled (PCE = 1), the received data contains + * the parity bit (MSB position). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData Pointer to data buffer. * @param Size Amount of data to be received. - * @note When the IRDA parity is enabled (PCE = 1), the received data contains - * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hirda->RxState == HAL_IRDA_STATE_READY) + if (hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -826,22 +1181,36 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size); + if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->RxState to ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } } else { @@ -861,21 +1230,25 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - /* Disable the IRDA DMA Tx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the IRDA DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } } - if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - /* Disable the IRDA DMA Rx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + /* Disable the IRDA DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } } /* Process Unlocked */ @@ -895,12 +1268,12 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { /* Enable the IRDA DMA Tx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); @@ -929,39 +1302,61 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) { /* The Lock is not implemented on this API to allow the user application to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / - HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of the stream and the corresponding call back is executed. */ /* Stop IRDA DMA Tx request if ongoing */ - if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel */ - if(hirda->hdmatx != NULL) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { - HAL_DMA_Abort(hirda->hdmatx); - } + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - IRDA_EndTxTransfer(hirda); + /* Abort the IRDA DMA Tx channel */ + if (hirda->hdmatx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + IRDA_EndTxTransfer(hirda); + } } /* Stop IRDA DMA Rx request if ongoing */ - if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel */ - if(hirda->hdmarx != NULL) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { - HAL_DMA_Abort(hirda->hdmarx); - } + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - IRDA_EndRxTransfer(hirda); + /* Abort the IRDA DMA Rx channel */ + if (hirda->hdmarx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + IRDA_EndRxTransfer(hirda); + } } return HAL_OK; @@ -971,7 +1366,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing transfers (blocking mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -979,7 +1374,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -987,7 +1382,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -996,13 +1391,22 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmatx); + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } @@ -1012,19 +1416,28 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmarx); + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Tx and Rx transfer counters */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1043,7 +1456,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Transmit transfer (blocking mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1051,7 +1464,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1059,7 +1472,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) @@ -1067,18 +1480,27 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmatx); + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Tx transfer counter */ - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; @@ -1090,7 +1512,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Receive transfer (blocking mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1098,7 +1520,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1106,7 +1528,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Rx request if enabled */ @@ -1115,18 +1537,27 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback to Null. + /* Set the IRDA DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hirda->hdmarx); + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Rx transfer counter */ - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1141,7 +1572,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing transfers (Interrupt mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1151,27 +1582,27 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) { - uint32_t abortcplt = 1; - + uint32_t abortcplt = 1U; + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; } @@ -1181,11 +1612,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) } } /* DMA Rx Handle is valid */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; } @@ -1194,27 +1625,27 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) hirda->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the IRDA DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* IRDA Tx DMA Abort callback has already been initialised : + /* IRDA Tx DMA Abort callback has already been initialised : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) { hirda->hdmatx->XferAbortCallback = NULL; } else { - abortcplt = 0; + abortcplt = 0U; } } } @@ -1225,30 +1656,30 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* IRDA Rx DMA Abort callback has already been initialised : + /* IRDA Rx DMA Abort callback has already been initialised : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) { hirda->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Reset errorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -1261,7 +1692,13 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) hirda->RxState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } return HAL_OK; @@ -1271,7 +1708,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1281,7 +1718,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1289,7 +1726,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) @@ -1297,14 +1734,14 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - /* Set the IRDA DMA Abort callback : + /* Set the IRDA DMA Abort callback : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) { /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ hirda->hdmatx->XferAbortCallback(hirda->hdmatx); @@ -1313,25 +1750,37 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) else { /* Reset Tx transfer counter */ - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { /* Reset Tx transfer counter */ - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } return HAL_OK; @@ -1341,7 +1790,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) * @brief Abort ongoing Receive transfer (Interrupt mode). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable IRDA Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1351,7 +1800,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1359,7 +1808,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Rx request if enabled */ @@ -1368,14 +1817,14 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback : + /* Set the IRDA DMA Abort callback : will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) { /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ hirda->hdmarx->XferAbortCallback(hirda->hdmarx); @@ -1384,7 +1833,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) else { /* Reset Rx transfer counter */ - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1393,13 +1842,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) hirda->RxState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { /* Reset Rx transfer counter */ - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -1408,7 +1863,13 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) hirda->RxState = HAL_IRDA_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } return HAL_OK; @@ -1416,7 +1877,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) /** * @brief Handle IRDA interrupt request. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1426,35 +1887,36 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) uint32_t cr1its = READ_REG(hirda->Instance->CR1); uint32_t cr3its; uint32_t errorflags; + uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) + if (errorflags == 0U) { /* IRDA in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) #else - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { IRDA_Receive_IT(hirda); return; } - } + } /* If some errors occur */ cr3its = READ_REG(hirda->Instance->CR3); - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) #if defined(USART_CR1_FIFOEN) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)) ) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) #else - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) -#endif + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) +#endif /* USART_CR1_FIFOEN */ { /* IRDA parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); @@ -1462,7 +1924,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); @@ -1470,7 +1932,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); @@ -1478,12 +1940,12 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && + if (((isrflags & USART_ISR_ORE) != 0U) && #if defined(USART_CR1_FIFOEN) - (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) #else - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) -#endif + (((cr1its & USART_CR1_RXNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) +#endif /* USART_CR1_FIFOEN */ { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); @@ -1491,23 +1953,24 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* Call IRDA Error Call back function if need be --------------------------*/ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE) { /* IRDA in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) #else - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { IRDA_Receive_IT(hirda); } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ - if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) - { + errorcode = hirda->ErrorCode; + if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & HAL_IRDA_ERROR_ORE) != 0U)) + { /* Blocking error : transfer is aborted Set the IRDA state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ @@ -1519,14 +1982,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* Abort the IRDA DMA Rx channel */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - /* Set the IRDA DMA Abort callback : + /* Set the IRDA DMA Abort callback : will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) { /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ hirda->hdmarx->XferAbortCallback(hirda->hdmarx); @@ -1534,21 +1997,37 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } else { - /* Call user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { - /* Call user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } else { - /* Non Blocking error : transfer could go on. + /* Non Blocking error : transfer could go on. Error is notified to user through user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; } } @@ -1558,17 +2037,17 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET)) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)) #else - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_TXE) != 0U) && ((cr1its & USART_CR1_TXEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { IRDA_Transmit_IT(hirda); return; } /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) { IRDA_EndTransmit_IT(hirda); return; @@ -1627,7 +2106,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) @@ -1662,7 +2141,7 @@ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ -__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -1678,7 +2157,7 @@ __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ -__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -1694,7 +2173,7 @@ __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ -__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -1736,9 +2215,10 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1= 0x00, temp2 = 0x00; - temp1 = hirda->gState; - temp2 = hirda->RxState; + uint32_t temp1; + uint32_t temp2; + temp1 = (uint32_t)hirda->gState; + temp2 = (uint32_t)hirda->RxState; return (HAL_IRDA_StateTypeDef)(temp1 | temp2); } @@ -1766,6 +2246,27 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) * @{ */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hirda IRDA handle. + * @retval none + */ +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda) +{ + /* Init the IRDA Callback settings */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /** * @brief Configure the IRDA peripheral. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains @@ -1774,9 +2275,12 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { - uint32_t tmpreg = 0x00000000; - IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; + uint32_t tmpreg; + IRDA_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; +#if defined(USART_PRESC_PRESCALER) + const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +#endif /* USART_PRESC_PRESCALER */ /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -1787,7 +2291,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler)); -#endif +#endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART CR1 Configuration -----------------------*/ /* Configure the IRDA Word Length, Parity and transfer Mode: @@ -1806,14 +2310,14 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /* Configure * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */ MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); -#endif +#endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); - tmpreg = 0; + tmpreg = 0U; switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: @@ -1821,37 +2325,36 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); #else tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate)); -#endif +#endif /* USART_PRESC_PRESCALER */ break; case IRDA_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); #else tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate)); -#endif +#endif /* USART_PRESC_PRESCALER */ break; case IRDA_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); #else tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate)); -#endif +#endif /* USART_PRESC_PRESCALER */ break; case IRDA_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); #else tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate)); -#endif +#endif /* USART_PRESC_PRESCALER */ break; case IRDA_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); #else - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate)); -#endif + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ break; - case IRDA_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -1878,7 +2381,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) */ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -1887,20 +2390,20 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ - if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -1927,22 +2430,23 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) + while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); hirda->gState = HAL_IRDA_STATE_READY; @@ -1971,7 +2475,7 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* At end of Tx process, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; @@ -1991,7 +2495,7 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore hirda->RxState to Ready */ @@ -2007,12 +2511,12 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) */ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the IRDA CR3 register */ @@ -2024,7 +2528,13 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Circular mode */ else { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } } @@ -2037,9 +2547,15 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half complete callback */ + hirda->TxHalfCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ HAL_IRDA_TxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2050,12 +2566,12 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); @@ -2069,7 +2585,13 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; } +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ } /** @@ -2080,9 +2602,15 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + hirda->RxHalfCpltCallback(hirda); +#else + /* Call legacy weak Rx Half complete callback */ HAL_IRDA_RxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2093,26 +2621,36 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); /* Stop IRDA DMA Tx request if ongoing */ - if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) ) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - hirda->TxXferCount = 0; - IRDA_EndTxTransfer(hirda); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->TxXferCount = 0U; + IRDA_EndTxTransfer(hirda); + } } /* Stop IRDA DMA Rx request if ongoing */ - if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ) + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - hirda->RxXferCount = 0; - IRDA_EndRxTransfer(hirda); + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->RxXferCount = 0U; + IRDA_EndRxTransfer(hirda); + } } hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2123,11 +2661,17 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2140,22 +2684,22 @@ static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); - + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->hdmatx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hirda->hdmarx != NULL) + if (hirda->hdmarx != NULL) { - if(hirda->hdmarx->XferAbortCallback != NULL) + if (hirda->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Reset errorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -2168,7 +2712,13 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } @@ -2182,22 +2732,22 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); - + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hirda->hdmatx != NULL) + if (hirda->hdmatx != NULL) { - if(hirda->hdmatx->XferAbortCallback != NULL) + if (hirda->hdmatx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hirda->TxXferCount = 0; - hirda->RxXferCount = 0; + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; /* Reset errorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; @@ -2210,7 +2760,13 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } @@ -2224,15 +2780,21 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2245,9 +2807,9 @@ static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); @@ -2256,7 +2818,13 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) hirda->RxState = HAL_IRDA_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2265,50 +2833,43 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) * interruptions have been enabled by HAL_IRDA_Transmit_IT(). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp; + uint16_t *tmp; /* Check that a Tx process is ongoing */ - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - if(hirda->TxXferCount == 0) + if (hirda->TxXferCount == 0U) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* Enable the IRDA Transmit Complete Interrupt */ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; } else { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t*) hirda->pTxBuffPtr; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - hirda->pTxBuffPtr += 2; + tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + hirda->pTxBuffPtr += 2U; } else { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU); + hirda->pTxBuffPtr++; } hirda->TxXferCount--; - - return HAL_OK; } } - else - { - return HAL_BUSY; - } } /** @@ -2325,7 +2886,13 @@ static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) /* Tx process is ended, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ } /** @@ -2334,11 +2901,11 @@ static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) * interruptions have been enabled by HAL_IRDA_Receive_IT() * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = hirda->Mask; uint16_t uhdata; @@ -2348,23 +2915,25 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t*) hirda->pRxBuffPtr ; + tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */ *tmp = (uint16_t)(uhdata & uhMask); - hirda->pRxBuffPtr +=2; + hirda->pRxBuffPtr += 2U; } else { - *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + hirda->pRxBuffPtr++; } - if(--hirda->RxXferCount == 0) + hirda->RxXferCount--; + if (hirda->RxXferCount == 0U) { /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -2372,19 +2941,19 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) /* Rx process is completed, restore hirda->RxState to Ready */ hirda->RxState = HAL_IRDA_STATE_READY; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ HAL_IRDA_RxCpltCallback(hirda); - - return HAL_OK; +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ } - - return HAL_OK; } else { /* Clear RXNE interrupt flag */ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); - - return HAL_BUSY; } } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h index 148d4e78d6..217cc4058e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_IRDA_H -#define __STM32L4xx_HAL_IRDA_H +#ifndef STM32L4xx_HAL_IRDA_H +#define STM32L4xx_HAL_IRDA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -68,7 +52,7 @@ typedef struct where usart_ker_ckpres is the IRDA input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref IRDA_Word_Length */ + This parameter can be a value of @ref IRDAEx_Word_Length */ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref IRDA_Parity @@ -90,29 +74,29 @@ typedef struct #if defined(USART_PRESC_PRESCALER) uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source. This parameter can be a value of @ref IRDA_ClockPrescaler. */ -#endif -}IRDA_InitTypeDef; +#endif /* USART_PRESC_PRESCALER */ +} IRDA_InitTypeDef; /** - * @brief HAL IRDA State structures definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. - * - gState contains IRDA state information related to global Handle management + * @brief HAL IRDA State definition + * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : - * b7-b6 Error information + * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL IRDA Init function already called) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (Peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -122,9 +106,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -133,58 +117,29 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -}HAL_IRDA_StateTypeDef; - -/** - * @brief HAL IRDA Error Code structure definition - */ -typedef enum -{ - HAL_IRDA_ERROR_NONE = 0x00U, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04U, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10U, /*!< DMA transfer error */ - HAL_IRDA_ERROR_BUSY = 0x20U /*!< Busy Error */ -}HAL_IRDA_ErrorTypeDef; +typedef uint32_t HAL_IRDA_StateTypeDef; /** * @brief IRDA clock sources definition */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}IRDA_ClockSourceTypeDef; + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ +} IRDA_ClockSourceTypeDef; /** * @brief IRDA handle Structure definition */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +typedef struct __IRDA_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ { USART_TypeDef *Instance; /*!< USART registers base address */ @@ -210,29 +165,66 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management + __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ - uint32_t ErrorCode; /*!< IRDA Error code */ + __IO uint32_t ErrorCode; /*!< IRDA Error code */ -}IRDA_HandleTypeDef; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */ + + void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */ + + void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */ + + void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */ + + void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */ + + + void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */ + + void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +} IRDA_HandleTypeDef; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /** - * @brief IRDA Configuration enumeration values definition + * @brief HAL IRDA Callback ID enumeration definition */ typedef enum { - IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */ - IRDA_PARITY = 0x01U, /*!< IRDA frame parity */ - IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */ - IRDA_MODE = 0x03U, /*!< IRDA communication mode */ - IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */ - IRDA_POWERMODE = 0x05U /*!< IRDA power mode */ -}IRDA_ControlTypeDef; + HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */ + HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */ + HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */ + HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */ + HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */ + HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */ + HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */ + HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */ + + HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */ + HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */ + +} HAL_IRDA_CallbackIDTypeDef; + +/** + * @brief HAL IRDA Callback pointer definition + */ +typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */ + +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -243,12 +235,43 @@ typedef enum * @{ */ -/** @defgroup IRDA_Word_Length IRDA Word Length +/** @defgroup IRDA_State_Definition IRDA State Code Definition * @{ */ -#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ -#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ -#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ +#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup IRDA_Error_Definition IRDA Error Code Definition + * @{ + */ +#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} */ @@ -276,16 +299,16 @@ typedef enum /** @defgroup IRDA_Low_Power IRDA Low Power * @{ */ -#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ -#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ +#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ +#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ /** * @} */ #if defined(USART_PRESC_PRESCALER) -/** @defgroup IRDA_ClockPrescaler Clock Prescaler +/** @defgroup IRDA_ClockPrescaler Clock Prescaler * @{ - */ + */ #define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -301,18 +324,18 @@ typedef enum /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /** @defgroup IRDA_State IRDA State * @{ */ -#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ -#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ +#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ +#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ /** * @} */ -/** @defgroup IRDA_Mode IRDA Mode +/** @defgroup IRDA_Mode IRDA Mode * @{ */ #define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */ @@ -321,7 +344,7 @@ typedef enum * @} */ -/** @defgroup IRDA_One_Bit IRDA One Bit Sampling +/** @defgroup IRDA_One_Bit IRDA One Bit Sampling * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */ @@ -333,13 +356,13 @@ typedef enum /** @defgroup IRDA_DMA_Tx IRDA DMA Tx * @{ */ -#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ -#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ +#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ +#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ /** * @} */ -/** @defgroup IRDA_DMA_Rx IRDA DMA Rx +/** @defgroup IRDA_DMA_Rx IRDA DMA Rx * @{ */ #define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */ @@ -372,13 +395,13 @@ typedef enum #define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */ #else #define IRDA_FLAG_TXE USART_ISR_TXE /*!< IRDA transmit data register empty */ -#endif +#endif /* USART_CR1_FIFOEN */ #define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */ #if defined(USART_CR1_FIFOEN) #define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */ #else #define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< IRDA read data register not empty */ -#endif +#endif /* USART_CR1_FIFOEN */ #define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */ #define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */ #define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */ @@ -420,12 +443,12 @@ typedef enum * @} */ -/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags +/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags * @{ */ #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ +#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ @@ -433,18 +456,21 @@ typedef enum * @} */ -/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask * @{ */ -#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ +#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ +#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */ +#define IRDA_CR_POS 5U /*!< IRDA control register position */ +#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */ +#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */ /** * @} */ /** - * @} - */ - + * @} + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros @@ -455,20 +481,29 @@ typedef enum * @param __HANDLE__ IRDA handle. * @retval None */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ - } while(0) + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ /** @brief Flush the IRDA DR register. * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0) + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -548,9 +583,9 @@ typedef enum * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -564,9 +599,9 @@ typedef enum * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. @@ -583,7 +618,8 @@ typedef enum * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -597,9 +633,9 @@ typedef enum * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -623,22 +659,22 @@ typedef enum * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request - * * @retval None */ #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__ specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__ specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__ specifies the IRDA Handle. @@ -657,168 +693,108 @@ typedef enum */ /* Private macros --------------------------------------------------------*/ -/** @defgroup IRDA_Private_Macros IRDA Private Macros +/** @addtogroup IRDA_Private_Macros * @{ */ -/** @brief Compute the mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define IRDA_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ -} while(0) - /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ -#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) -/** - * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__ IRDA frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ - ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ - ((__LENGTH__) == IRDA_WORDLENGTH_9B)) - -/** - * @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__ IRDA frame parity. +/** @brief Ensure that IRDA frame parity is valid. + * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ ((__PARITY__) == IRDA_PARITY_EVEN) || \ ((__PARITY__) == IRDA_PARITY_ODD)) -/** - * @brief Ensure that IRDA communication mode is valid. - * @param __MODE__ IRDA communication mode. +/** @brief Ensure that IRDA communication mode is valid. + * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) + */ +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that IRDA power mode is valid. - * @param __MODE__ IRDA power mode. +/** @brief Ensure that IRDA power mode is valid. + * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ ((__MODE__) == IRDA_POWERMODE_NORMAL)) #if defined(USART_PRESC_PRESCALER) -/** - * @brief Ensure that IRDA clock Prescaler is valid. - * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. +/** @brief Ensure that IRDA clock Prescaler is valid. + * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) -#endif + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) -/** - * @brief Ensure that IRDA state is valid. - * @param __STATE__ IRDA state mode. +#endif /* USART_PRESC_PRESCALER */ +/** @brief Ensure that IRDA state is valid. + * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ + */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ ((__STATE__) == IRDA_STATE_ENABLE)) -/** - * @brief Ensure that IRDA associated UART/USART mode is valid. - * @param __MODE__: IRDA associated UART/USART mode. +/** @brief Ensure that IRDA associated UART/USART mode is valid. + * @param __MODE__ IRDA associated UART/USART mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ ((__MODE__) == IRDA_MODE_ENABLE)) -/** - * @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__ IRDA sampling rate. +/** @brief Ensure that IRDA sampling rate is valid. + * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ + */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) -/** - * @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__ IRDA DMA TX mode. +/** @brief Ensure that IRDA DMA TX mode is valid. + * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ + */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ ((__DMATX__) == IRDA_DMA_TX_ENABLE)) -/** - * @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__ IRDA DMA RX mode. +/** @brief Ensure that IRDA DMA RX mode is valid. + * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ + */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ ((__DMARX__) == IRDA_DMA_RX_ENABLE)) -/** - * @brief Ensure that IRDA request is valid. - * @param __PARAM__ IRDA request. +/** @brief Ensure that IRDA request is valid. + * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ + */ #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) /** - * @} - */ + * @} + */ /* Include IRDA HAL Extended module */ #include "stm32l4xx_hal_irda_ex.h" @@ -838,6 +814,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /** * @} */ @@ -870,9 +853,9 @@ void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); /** * @} @@ -908,6 +891,6 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); } #endif -#endif /* __STM32L4xx_HAL_IRDA_H */ +#endif /* STM32L4xx_HAL_IRDA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h index 487795de3d..4d49596e14 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_IRDA_EX_H -#define __STM32L4xx_HAL_IRDA_EX_H +#ifndef STM32L4xx_HAL_IRDA_EX_H +#define STM32L4xx_HAL_IRDA_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -54,8 +38,25 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants + * @{ + */ + +/** @defgroup IRDAEx_Word_Length IRDAEx Word Length + * @{ + */ +#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ +#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ +/** + * @} + */ + +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -68,15 +69,15 @@ * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \ + || defined (STM32L496xx) || defined (STM32L4A6xx) \ + || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -92,12 +93,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -113,12 +114,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -134,12 +135,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -155,12 +156,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART5) \ { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ case RCC_UART5CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -176,16 +177,20 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) -#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) +#elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -201,12 +206,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -222,12 +227,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -243,7 +248,11 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) #elif defined (STM32L432xx) || defined (STM32L442xx) @@ -251,8 +260,8 @@ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -268,12 +277,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -289,7 +298,11 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) @@ -297,8 +310,8 @@ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -314,12 +327,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -335,12 +348,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -356,12 +369,12 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -377,11 +390,71 @@ default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ - } while(0) -#endif + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || + * STM32L496xx || STM32L4A6xx || + * STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx + */ +/** @brief Compute the mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** @brief Ensure that IRDA frame length is valid. + * @param __LENGTH__ IRDA frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_9B)) /** * @} */ @@ -400,6 +473,6 @@ } #endif -#endif /* __STM32L4xx_HAL_IRDA_EX_H */ +#endif /* STM32L4xx_HAL_IRDA_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c index a415996a53..26ed36f884 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c @@ -3,7 +3,7 @@ * @file stm32l4xx_hal_iwdg.c * @author MCD Application Team * @brief IWDG HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: * + Initialization and Start functions * + IO operation functions @@ -19,12 +19,12 @@ (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and both can not be + (+) Once the IWDG is started, the LSI is forced ON and both can not be disabled. The counter starts counting down from the reset value (0xFFF). - When it reaches the end of count value (0x000) a reset signal is + When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). - (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. @@ -34,7 +34,7 @@ reset occurs. (+) Debug mode : When the microcontroller enters debug mode (core halted), - the IWDG counter either continues to work normally or stops, depending + the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros @@ -48,19 +48,19 @@ ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI clock is forced ON and IWDG counter starts downcounting. - (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & + (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & IWDG_WINR. - (++) Configure the IWDG prescaler and counter reload value. This reload - value will be loaded in the IWDG counter each time the watchdog is + (+) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) Wait for status flags to be reset - (++) Depending on window parameter: - (+++) If Window Init parameter is same as Window register value, - nothing more is done but reload counter value in order to exit + (+) wait for status flags to be reset + (+) Depending on window parameter: + (++) If Window Init parameter is same as Window register value, + nothing more is done but reload counter value in order to exit function withy exact time base. - (+++) Else modify Window register. This will automatically reload + (++) Else modify Window register. This will automatically reload watchdog counter. (#) Then the application program must refresh the IWDG counter at regular @@ -79,29 +79,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -147,10 +131,10 @@ ##### Initialization and Start functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters in the + (+) Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef of associated handle. (+) Manage Window option. - (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog is reloaded in order to exit function with correct time base. @endverbatim @@ -158,8 +142,8 @@ */ /** - * @brief Initialize the IWDG according to the specified parameters in the - * IWDG_InitTypeDef and start watchdog. Before exiting function, + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, * watchdog is refreshed in order to have correct time base. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. @@ -170,7 +154,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) uint32_t tickstart; /* Check the IWDG handle allocation */ - if(hiwdg == NULL) + if (hiwdg == NULL) { return HAL_ERROR; } @@ -195,21 +179,21 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); - /* Wait for register to be updated */ - while(hiwdg->Instance->SR != RESET) + /* Wait for register to be updated */ + while (hiwdg->Instance->SR != 0x00u) { - if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) + if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { return HAL_TIMEOUT; } } - /* If window parameter is different than current value, modify window + /* If window parameter is different than current value, modify window register */ - if(hiwdg->Instance->WINR != hiwdg->Init.Window) + if (hiwdg->Instance->WINR != hiwdg->Init.Window) { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, - even if window feature is disabled, Watchdog will be reloaded by writing + even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h index b11dc2119f..b2106b49e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_IWDG_H -#define __STM32L4xx_HAL_IWDG_H +#ifndef STM32L4xx_HAL_IWDG_H +#define STM32L4xx_HAL_IWDG_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -57,7 +41,7 @@ * @{ */ -/** +/** * @brief IWDG Init structure definition */ typedef struct @@ -73,16 +57,16 @@ typedef struct } IWDG_InitTypeDef; -/** - * @brief IWDG Handle Structure definition +/** + * @brief IWDG Handle Structure definition */ typedef struct { IWDG_TypeDef *Instance; /*!< Register base address */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */ +} IWDG_HandleTypeDef; -}IWDG_HandleTypeDef; /** * @} @@ -96,13 +80,14 @@ typedef struct /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ -#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ + /** * @} */ @@ -115,6 +100,7 @@ typedef struct * @} */ + /** * @} */ @@ -250,6 +236,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); } #endif -#endif /* __STM32L4xx_HAL_IWDG_H */ +#endif /* STM32L4xx_HAL_IWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c index 9c6bdc857f..aeb68e7acb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c @@ -16,13 +16,13 @@ [..] The LCD HAL driver can be used as follows: (#) Declare a LCD_HandleTypeDef handle structure. - + -@- The frequency generator allows you to achieve various LCD frame rates starting from an LCD input clock frequency (LCDCLK) which can vary - from 32 kHz up to 1 MHz. - + from 32 kHz up to 1 MHz. + (#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API: - + (++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows: (+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and selected clock source (HSE, LSI or LSE) @@ -32,7 +32,7 @@ (+++) Configure these LCD pins as alternate function no-pull. (++) Enable the LCD interface clock. - + (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer Segment in the Init structure of the LCD handle. @@ -68,29 +68,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -117,7 +101,7 @@ * @{ */ -#define LCD_TIMEOUT_VALUE 1000 +#define LCD_TIMEOUT_VALUE 1000U /** * @} @@ -149,16 +133,17 @@ * @brief Initialize the LCD peripheral according to the specified parameters * in the LCD_InitStruct and initialize the associated handle. * @note This function can be used only when the LCD is disabled. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval None */ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; - uint32_t counter = 0; + uint32_t tickstart; + uint32_t counter; + HAL_StatusTypeDef status; /* Check the LCD handle allocation */ - if(hlcd == NULL) + if (hlcd == NULL) { return HAL_ERROR; } @@ -178,7 +163,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); assert_param(IS_LCD_MUX_SEGMENT(hlcd->Init.MuxSegment)); - if(hlcd->State == HAL_LCD_STATE_RESET) + if (hlcd->State == HAL_LCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hlcd->Lock = HAL_UNLOCKED; @@ -194,13 +179,12 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit in the LCD_SR register */ - for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) + for (counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) { hlcd->Instance->RAM[counter] = 0; } /* Enable the display request */ hlcd->Instance->SR |= LCD_SR_UDR; - /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: Set PS[3:0] bits according to hlcd->Init.Prescaler value Set DIV[3:0] bits according to hlcd->Init.Divider value @@ -210,16 +194,20 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value Set CC[2:0] bits according to hlcd->Init.Contrast value Set HD bit according to hlcd->Init.HighDrive value */ - MODIFY_REG(hlcd->Instance->FCR, \ - (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ - LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC | LCD_FCR_HD), \ - (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ - hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive)); + MODIFY_REG(hlcd->Instance->FCR, \ + (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK | LCD_FCR_BLINKF | \ + LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC | LCD_FCR_HD), \ + (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ + hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive)); /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.*/ - LCD_WaitForSynchro(hlcd); + status = LCD_WaitForSynchro(hlcd); + if (status != HAL_OK) + { + return status; + } /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast: Set DUTY[2:0] bits according to hlcd->Init.Duty value @@ -227,8 +215,8 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) Set VSEL bit according to hlcd->Init.VoltageSource value Set MUX_SEG bit according to hlcd->Init.MuxSegment value */ MODIFY_REG(hlcd->Instance->CR, \ - (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \ - (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment)); + (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \ + (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment)); /* Enable the peripheral */ __HAL_LCD_ENABLE(hlcd); @@ -237,9 +225,9 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /* Wait Until the LCD is enabled */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) + while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_ENS; return HAL_TIMEOUT; @@ -250,9 +238,9 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /*!< Wait Until the LCD Booster is ready */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) + while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_RDY; return HAL_TIMEOUT; @@ -261,20 +249,20 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) /* Initialize the LCD state */ hlcd->ErrorCode = HAL_LCD_ERROR_NONE; - hlcd->State= HAL_LCD_STATE_READY; + hlcd->State = HAL_LCD_STATE_READY; - return HAL_OK; + return status; } /** * @brief DeInitialize the LCD peripheral. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) { /* Check the LCD handle allocation */ - if(hlcd == NULL) + if (hlcd == NULL) { return HAL_ERROR; } @@ -298,7 +286,7 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) /** * @brief DeInitialize the LCD MSP. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval None */ __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd) @@ -313,7 +301,7 @@ __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd) /** * @brief Initialize the LCD MSP. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval None */ __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) @@ -361,8 +349,8 @@ __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) /** * @brief Write a word in the specific LCD RAM. - * @param hlcd: LCD handle - * @param RAMRegisterIndex: specifies the LCD RAM Register. + * @param hlcd LCD handle + * @param RAMRegisterIndex specifies the LCD RAM Register. * This parameter can be one of the following values: * @arg LCD_RAM_REGISTER0: LCD RAM Register 0 * @arg LCD_RAM_REGISTER1: LCD RAM Register 1 @@ -380,20 +368,21 @@ __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd) * @arg LCD_RAM_REGISTER13: LCD RAM Register 13 * @arg LCD_RAM_REGISTER14: LCD RAM Register 14 * @arg LCD_RAM_REGISTER15: LCD RAM Register 15 - * @param RAMRegisterMask: specifies the LCD RAM Register Data Mask. - * @param Data: specifies LCD Data Value to be written. + * @param RAMRegisterMask specifies the LCD RAM Register Data Mask. + * @param Data specifies LCD Data Value to be written. * @retval None */ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data) { - uint32_t tickstart = 0x00; - - if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) + uint32_t tickstart; + HAL_LCD_StateTypeDef state = hlcd->State; + + if ((state == HAL_LCD_STATE_READY) || (state == HAL_LCD_STATE_BUSY)) { /* Check the parameters */ assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex)); - if(hlcd->State == HAL_LCD_STATE_READY) + if (hlcd->State == HAL_LCD_STATE_READY) { /* Process Locked */ __HAL_LOCK(hlcd); @@ -403,9 +392,9 @@ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterInd tickstart = HAL_GetTick(); /*!< Wait Until the LCD is ready */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) + while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_UDR; @@ -430,15 +419,17 @@ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterInd /** * @brief Clear the LCD RAM registers. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval None */ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; - uint32_t counter = 0; - - if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY)) + uint32_t tickstart; + uint32_t counter; + HAL_StatusTypeDef status = HAL_ERROR; + HAL_LCD_StateTypeDef state = hlcd->State; + + if ((state == HAL_LCD_STATE_READY) || (state == HAL_LCD_STATE_BUSY)) { /* Process Locked */ __HAL_LOCK(hlcd); @@ -449,9 +440,9 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /*!< Wait Until the LCD is ready */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) + while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_UDR; @@ -462,25 +453,20 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) } } /* Clear the LCD_RAM registers */ - for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) + for (counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) { hlcd->Instance->RAM[counter] = 0; } /* Update the LCD display */ - HAL_LCD_UpdateDisplayRequest(hlcd); - - return HAL_OK; - } - else - { - return HAL_ERROR; + status = HAL_LCD_UpdateDisplayRequest(hlcd); } + return status; } /** * @brief Enable the Update Display Request. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @note Each time software modifies the LCD_RAM it must set the UDR bit to * transfer the updated data to the second level buffer. * The UDR bit stays set until the end of the update and during this @@ -494,7 +480,7 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) */ HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; + uint32_t tickstart; /* Clear the Update Display Done flag before starting the update display request */ __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD); @@ -506,9 +492,9 @@ HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /*!< Wait Until the LCD display is done */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET) + while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET) { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_UDD; @@ -548,7 +534,7 @@ HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) /** * @brief Return the LCD handle state. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval HAL state */ HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd) @@ -559,7 +545,7 @@ HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd) /** * @brief Return the LCD error code. - * @param hlcd: LCD handle + * @param hlcd LCD handle * @retval LCD Error Code */ uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd) @@ -586,15 +572,15 @@ uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd) */ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) { - uint32_t tickstart = 0x00; + uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); /* Loop until FCRSF flag is set */ - while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET) + while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET) { - if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF; return HAL_TIMEOUT; @@ -621,4 +607,3 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) #endif /* STM32L433xx || STM32L443xx || STM32L476xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h index 754cf5615a..2e9d3a8f95 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_LCD_H -#define __STM32L4xx_HAL_LCD_H +#ifndef STM32L4xx_HAL_LCD_H +#define STM32L4xx_HAL_LCD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L433xx) || defined(STM32L443xx) || defined(STM32L476xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) @@ -118,7 +102,7 @@ typedef struct __IO uint32_t ErrorCode; /* LCD Error code */ -}LCD_HandleTypeDef; +} LCD_HandleTypeDef; /** * @} */ @@ -130,36 +114,36 @@ typedef struct /** @defgroup LCD_ErrorCode LCD Error Code * @{ - */ -#define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */ -#define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */ -#define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */ -#define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */ -#define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */ + */ +#define HAL_LCD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_LCD_ERROR_FCRSF (0x00000001U) /*!< Synchro flag timeout error */ +#define HAL_LCD_ERROR_UDR (0x00000002U) /*!< Update display request flag timeout error */ +#define HAL_LCD_ERROR_UDD (0x00000004U) /*!< Update display done flag timeout error */ +#define HAL_LCD_ERROR_ENS (0x00000008U) /*!< LCD enabled status flag timeout error */ +#define HAL_LCD_ERROR_RDY (0x00000010U) /*!< LCD Booster ready timeout error */ /** * @} */ - + /** @defgroup LCD_Prescaler LCD Prescaler * @{ */ -#define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ -#define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ -#define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ -#define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ -#define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ -#define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ -#define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ -#define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ -#define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ -#define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ -#define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ -#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ -#define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ -#define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ -#define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ -#define LCD_PRESCALER_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */ +#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */ +#define LCD_PRESCALER_2 (0x00400000U) /*!< CLKPS = LCDCLK/2 */ +#define LCD_PRESCALER_4 (0x00800000U) /*!< CLKPS = LCDCLK/4 */ +#define LCD_PRESCALER_8 (0x00C00000U) /*!< CLKPS = LCDCLK/8 */ +#define LCD_PRESCALER_16 (0x01000000U) /*!< CLKPS = LCDCLK/16 */ +#define LCD_PRESCALER_32 (0x01400000U) /*!< CLKPS = LCDCLK/32 */ +#define LCD_PRESCALER_64 (0x01800000U) /*!< CLKPS = LCDCLK/64 */ +#define LCD_PRESCALER_128 (0x01C00000U) /*!< CLKPS = LCDCLK/128 */ +#define LCD_PRESCALER_256 (0x02000000U) /*!< CLKPS = LCDCLK/256 */ +#define LCD_PRESCALER_512 (0x02400000U) /*!< CLKPS = LCDCLK/512 */ +#define LCD_PRESCALER_1024 (0x02800000U) /*!< CLKPS = LCDCLK/1024 */ +#define LCD_PRESCALER_2048 (0x02C00000U) /*!< CLKPS = LCDCLK/2048 */ +#define LCD_PRESCALER_4096 (0x03000000U) /*!< CLKPS = LCDCLK/4096 */ +#define LCD_PRESCALER_8192 (0x03400000U) /*!< CLKPS = LCDCLK/8192 */ +#define LCD_PRESCALER_16384 (0x03800000U) /*!< CLKPS = LCDCLK/16384 */ +#define LCD_PRESCALER_32768 (0x03C00000U) /*!< CLKPS = LCDCLK/32768 */ /** * @} */ @@ -167,22 +151,22 @@ typedef struct /** @defgroup LCD_Divider LCD Divider * @{ */ -#define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ -#define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ -#define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ -#define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ -#define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ -#define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ -#define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ -#define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ -#define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ -#define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ -#define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ -#define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ -#define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ -#define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ -#define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ -#define LCD_DIVIDER_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */ +#define LCD_DIVIDER_16 (0x00000000U) /*!< LCD frequency = CLKPS/16 */ +#define LCD_DIVIDER_17 (0x00040000U) /*!< LCD frequency = CLKPS/17 */ +#define LCD_DIVIDER_18 (0x00080000U) /*!< LCD frequency = CLKPS/18 */ +#define LCD_DIVIDER_19 (0x000C0000U) /*!< LCD frequency = CLKPS/19 */ +#define LCD_DIVIDER_20 (0x00100000U) /*!< LCD frequency = CLKPS/20 */ +#define LCD_DIVIDER_21 (0x00140000U) /*!< LCD frequency = CLKPS/21 */ +#define LCD_DIVIDER_22 (0x00180000U) /*!< LCD frequency = CLKPS/22 */ +#define LCD_DIVIDER_23 (0x001C0000U) /*!< LCD frequency = CLKPS/23 */ +#define LCD_DIVIDER_24 (0x00200000U) /*!< LCD frequency = CLKPS/24 */ +#define LCD_DIVIDER_25 (0x00240000U) /*!< LCD frequency = CLKPS/25 */ +#define LCD_DIVIDER_26 (0x00280000U) /*!< LCD frequency = CLKPS/26 */ +#define LCD_DIVIDER_27 (0x002C0000U) /*!< LCD frequency = CLKPS/27 */ +#define LCD_DIVIDER_28 (0x00300000U) /*!< LCD frequency = CLKPS/28 */ +#define LCD_DIVIDER_29 (0x00340000U) /*!< LCD frequency = CLKPS/29 */ +#define LCD_DIVIDER_30 (0x00380000U) /*!< LCD frequency = CLKPS/30 */ +#define LCD_DIVIDER_31 (0x003C0000U) /*!< LCD frequency = CLKPS/31 */ /** * @} */ @@ -191,7 +175,7 @@ typedef struct /** @defgroup LCD_Duty LCD Duty * @{ */ -#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ +#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */ #define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */ #define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */ #define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */ @@ -204,9 +188,9 @@ typedef struct /** @defgroup LCD_Bias LCD Bias * @{ */ -#define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ -#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ -#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ +#define LCD_BIAS_1_4 (0x00000000U) /*!< 1/4 Bias */ +#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ +#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ /** * @} */ @@ -214,8 +198,8 @@ typedef struct /** @defgroup LCD_Voltage_Source LCD Voltage Source * @{ */ -#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ -#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */ +#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */ +#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */ /** * @} */ @@ -232,7 +216,7 @@ typedef struct /** @defgroup LCD_PulseOnDuration LCD Pulse On Duration * @{ */ -#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ +#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */ #define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */ #define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */ #define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */ @@ -248,7 +232,7 @@ typedef struct /** @defgroup LCD_DeadTime LCD Dead Time * @{ */ -#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ +#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */ #define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */ #define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */ #define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */ @@ -263,10 +247,10 @@ typedef struct /** @defgroup LCD_BlinkMode LCD Blink Mode * @{ */ -#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ -#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ +#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disabled */ +#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ #define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to - 8 pixels according to the programmed duty) */ + 8 pixels according to the programmed duty) */ #define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */ /** * @} @@ -275,7 +259,7 @@ typedef struct /** @defgroup LCD_BlinkFrequency LCD Blink Frequency * @{ */ -#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ +#define LCD_BLINKFREQUENCY_DIV8 (0x00000000U) /*!< The Blink frequency = fLCD/8 */ #define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */ #define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */ #define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */ @@ -290,7 +274,7 @@ typedef struct /** @defgroup LCD_Contrast LCD Contrast * @{ */ -#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ +#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */ #define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */ #define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */ #define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */ @@ -305,22 +289,22 @@ typedef struct /** @defgroup LCD_RAMRegister LCD RAMRegister * @{ */ -#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ -#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ -#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ -#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ -#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ -#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ -#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ -#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ -#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ -#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ -#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ -#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ -#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ -#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ -#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ -#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ +#define LCD_RAM_REGISTER0 (0x00000000U) /*!< LCD RAM Register 0 */ +#define LCD_RAM_REGISTER1 (0x00000001U) /*!< LCD RAM Register 1 */ +#define LCD_RAM_REGISTER2 (0x00000002U) /*!< LCD RAM Register 2 */ +#define LCD_RAM_REGISTER3 (0x00000003U) /*!< LCD RAM Register 3 */ +#define LCD_RAM_REGISTER4 (0x00000004U) /*!< LCD RAM Register 4 */ +#define LCD_RAM_REGISTER5 (0x00000005U) /*!< LCD RAM Register 5 */ +#define LCD_RAM_REGISTER6 (0x00000006U) /*!< LCD RAM Register 6 */ +#define LCD_RAM_REGISTER7 (0x00000007U) /*!< LCD RAM Register 7 */ +#define LCD_RAM_REGISTER8 (0x00000008U) /*!< LCD RAM Register 8 */ +#define LCD_RAM_REGISTER9 (0x00000009U) /*!< LCD RAM Register 9 */ +#define LCD_RAM_REGISTER10 (0x0000000AU) /*!< LCD RAM Register 10 */ +#define LCD_RAM_REGISTER11 (0x0000000BU) /*!< LCD RAM Register 11 */ +#define LCD_RAM_REGISTER12 (0x0000000CU) /*!< LCD RAM Register 12 */ +#define LCD_RAM_REGISTER13 (0x0000000DU) /*!< LCD RAM Register 13 */ +#define LCD_RAM_REGISTER14 (0x0000000EU) /*!< LCD RAM Register 14 */ +#define LCD_RAM_REGISTER15 (0x0000000FU) /*!< LCD RAM Register 15 */ /** * @} */ @@ -339,7 +323,7 @@ typedef struct * @{ */ -#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */ +#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< SEG pin multiplexing disabled */ #define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */ /** * @} @@ -368,25 +352,25 @@ typedef struct */ /** @brief Reset LCD handle state. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @retval None */ #define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET) /** @brief Enable the LCD peripheral. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @retval None */ #define __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN) /** @brief Disable the LCD peripheral. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @retval None */ #define __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN) /** @brief Enable the low resistance divider. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @note Displays with high internal resistance may need a longer drive time to * achieve satisfactory contrast. This function is useful in this case if * some additional power consumption can be tolerated. @@ -401,7 +385,7 @@ typedef struct } while(0) /** @brief Disable the low resistance divider. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @retval None */ #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \ @@ -411,21 +395,21 @@ typedef struct } while(0) /** @brief Enable the voltage output buffer for higher driving capability. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @retval None */ #define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN) /** @brief Disable the voltage output buffer for higher driving capability. - * @param __HANDLE__: specifies the LCD Handle. + * @param __HANDLE__ specifies the LCD Handle. * @retval None */ #define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN) /** * @brief Configure the LCD pulse on duration. - * @param __HANDLE__: specifies the LCD Handle. - * @param __DURATION__: specifies the LCD pulse on duration in terms of + * @param __HANDLE__ specifies the LCD Handle. + * @param __DURATION__ specifies the LCD pulse on duration in terms of * CK_PS (prescaled LCD clock period) pulses. * This parameter can be one of the following values: * @arg LCD_PULSEONDURATION_0: 0 pulse @@ -446,8 +430,8 @@ typedef struct /** * @brief Configure the LCD dead time. - * @param __HANDLE__: specifies the LCD Handle. - * @param __DEADTIME__: specifies the LCD dead time. + * @param __HANDLE__ specifies the LCD Handle. + * @param __DEADTIME__ specifies the LCD dead time. * This parameter can be one of the following values: * @arg LCD_DEADTIME_0: No dead Time * @arg LCD_DEADTIME_1: One Phase between different couple of Frame @@ -467,8 +451,8 @@ typedef struct /** * @brief Configure the LCD contrast. - * @param __HANDLE__: specifies the LCD Handle. - * @param __CONTRAST__: specifies the LCD Contrast. + * @param __HANDLE__ specifies the LCD Handle. + * @param __CONTRAST__ specifies the LCD Contrast. * This parameter can be one of the following values: * @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V * @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V @@ -488,8 +472,8 @@ typedef struct /** * @brief Configure the LCD Blink mode and Blink frequency. - * @param __HANDLE__: specifies the LCD Handle. - * @param __BLINKMODE__: specifies the LCD blink mode. + * @param __HANDLE__ specifies the LCD Handle. + * @param __BLINKMODE__ specifies the LCD blink mode. * This parameter can be one of the following values: * @arg LCD_BLINKMODE_OFF: Blink disabled * @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) @@ -497,7 +481,7 @@ typedef struct * pixels according to the programmed duty) * @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM * (all pixels) - * @param __BLINKFREQUENCY__: specifies the LCD blink frequency. + * @param __BLINKFREQUENCY__ specifies the LCD blink frequency. * @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8 * @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16 * @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32 @@ -515,8 +499,8 @@ typedef struct } while(0) /** @brief Enable the specified LCD interrupt. - * @param __HANDLE__: specifies the LCD Handle. - * @param __INTERRUPT__: specifies the LCD interrupt source to be enabled. + * @param __HANDLE__ specifies the LCD Handle. + * @param __INTERRUPT__ specifies the LCD interrupt source to be enabled. * This parameter can be one of the following values: * @arg LCD_IT_SOF: Start of Frame Interrupt * @arg LCD_IT_UDD: Update Display Done Interrupt @@ -529,8 +513,8 @@ typedef struct } while(0) /** @brief Disable the specified LCD interrupt. - * @param __HANDLE__: specifies the LCD Handle. - * @param __INTERRUPT__: specifies the LCD interrupt source to be disabled. + * @param __HANDLE__ specifies the LCD Handle. + * @param __INTERRUPT__ specifies the LCD interrupt source to be disabled. * This parameter can be one of the following values: * @arg LCD_IT_SOF: Start of Frame Interrupt * @arg LCD_IT_UDD: Update Display Done Interrupt @@ -543,8 +527,8 @@ typedef struct } while(0) /** @brief Check whether the specified LCD interrupt source is enabled or not. - * @param __HANDLE__: specifies the LCD Handle. - * @param __IT__: specifies the LCD interrupt source to check. + * @param __HANDLE__ specifies the LCD Handle. + * @param __IT__ specifies the LCD interrupt source to check. * This parameter can be one of the following values: * @arg LCD_IT_SOF: Start of Frame Interrupt * @arg LCD_IT_UDD: Update Display Done Interrupt. @@ -556,8 +540,8 @@ typedef struct #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__)) /** @brief Check whether the specified LCD flag is set or not. - * @param __HANDLE__: specifies the LCD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the LCD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR @@ -578,8 +562,8 @@ typedef struct #define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified LCD pending flag. - * @param __HANDLE__: specifies the LCD Handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ specifies the LCD Handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg LCD_FLAG_SOF: Start of Frame Interrupt * @arg LCD_FLAG_UDD: Update Display Done Interrupt @@ -782,6 +766,6 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); } #endif -#endif /* __STM32L4xx_HAL_LCD_H */ +#endif /* STM32L4xx_HAL_LCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c index 01b100fb10..7025e945cb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32l4xx_hal_lptim.c * @author MCD Application Team - * @brief LPTIM HAL module driver. - * This file provides firmware functions to manage the following + * @brief LPTIM HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: * + Initialization and de-initialization functions. * + Start/Stop operation functions in polling mode. * + Start/Stop operation functions in interrupt mode. * + Reading operation functions. * + Peripheral State functions. - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -25,7 +25,7 @@ (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). - + (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function configures mainly: (++) The instance: LPTIM1 or LPTIM2. @@ -38,7 +38,7 @@ (+++) Polarity: polarity of the active edge for the counter unit if the ULPTIM input is selected. (+++) SampleTime: clock sampling time to configure the clock glitch - filter. + filter. (++) Trigger: How the counter start. (+++) Source: trigger can be software or one of the hardware triggers. (+++) ActiveEdge : only for hardware trigger. @@ -47,79 +47,114 @@ (++) OutputPolarity : 2 opposite polarities are possible. (++) UpdateMode: specifies whether the update of the autoreload and the compare values is done immediately or after the end of current - period. + period. (++) Input1Source: Source selected for input1 (GPIO or comparator output). - (++) Input2Source: Source selected for input2 (GPIO or comparator output). + (++) Input2Source: Source selected for input2 (GPIO or comparator output). Input2 is used only for encoder feature so is used only for LPTIM1 instance. - + (#)Six modes are available: - + (++) PWM Mode: To generate a PWM signal with specified period and pulse, call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption mode. - + (++) One Pulse Mode: To generate pulse with specified width in response to a stimulus, call HAL_LPTIM_OnePulse_Start() or HAL_LPTIM_OnePulse_Start_IT() for interruption mode. - + (++) Set once Mode: In this mode, the output changes the level (from low level to high level if the output polarity is configured high, else - the opposite) when a compare match occurs. To start this mode, call + the opposite) when a compare match occurs. To start this mode, call HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for interruption mode. - + (++) Encoder Mode: To use the encoder interface call - HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for + HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for interruption mode. Only available for LPTIM1 instance. - + (++) Time out Mode: an active edge on one selected trigger input rests the counter. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will - restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or + restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or HAL_LPTIM_TimeOut_Start_IT() for interruption mode. - + (++) Counter Mode: counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. - To start this mode, call HAL_LPTIM_Counter_Start() or - HAL_LPTIM_Counter_Start_IT() for interruption mode. + To start this mode, call HAL_LPTIM_Counter_Start() or + HAL_LPTIM_Counter_Start_IT() for interruption mode. + - (#) User can stop any process by calling the corresponding API: HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is already started in interruption mode. - + (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit(). + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + [..] + Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. + @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + [..] + Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + default weak function. + @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + These functions allow to register/unregister following callbacks: + + (+) MspInitCallback : LPTIM Base Msp Init Callback. + (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback. + (+) CompareMatchCallback : Compare match Callback. + (+) AutoReloadMatchCallback : Auto-reload match Callback. + (+) TriggerCallback : External trigger event detection Callback. + (+) CompareWriteCallback : Compare register write complete Callback. + (+) AutoReloadWriteCallback : Auto-reload register write complete Callback. + (+) DirectionUpCallback : Up-counting direction change Callback. + (+) DirectionDownCallback : Down-counting direction change Callback. + + [..] + By default, after the Init and when the state is HAL_LPTIM_STATE_RESET + all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init/DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -134,21 +169,29 @@ */ #ifdef HAL_LPTIM_MODULE_ENABLED + +#if defined (LPTIM1) || defined (LPTIM2) + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ +#define TIMEOUT 1000UL /* Timeout is 1s */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions * @{ */ -/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== @@ -157,8 +200,8 @@ LPTIM_InitTypeDef and initialize the associated handle. (+) DeInitialize the LPTIM peripheral. (+) Initialize the LPTIM MSP. - (+) DeInitialize the LPTIM MSP. - + (+) DeInitialize the LPTIM MSP. + @endverbatim * @{ */ @@ -166,152 +209,179 @@ /** * @brief Initialize the LPTIM according to the specified parameters in the * LPTIM_InitTypeDef and initialize the associated handle. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr; /* Check the LPTIM handle allocation */ - if(hlptim == NULL) + if (hlptim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); + if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); - } + } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); + } + assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); - - if(hlptim->State == HAL_LPTIM_STATE_RESET) + +#if defined(LPTIM_RCR_REP) + assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter)); +#endif + + if (hlptim->State == HAL_LPTIM_STATE_RESET) { /* Allocate lock resource and initialize it */ hlptim->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + LPTIM_ResetCallback(hlptim); + + if (hlptim->MspInitCallback == NULL) + { + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hlptim->MspInitCallback(hlptim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_LPTIM_MspInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } - + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; - + /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + + if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - - /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | - LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE )); - + + /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); + /* Set initialization parameters */ tmpcfgr |= (hlptim->Init.Clock.Source | hlptim->Init.Clock.Prescaler | hlptim->Init.OutputPolarity | hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + + if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | hlptim->Init.UltraLowPowerClock.SampleTime); - } - - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + } + + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ tmpcfgr |= (hlptim->Init.Trigger.Source | hlptim->Init.Trigger.ActiveEdge | hlptim->Init.Trigger.SampleTime); } - + /* Write to LPTIMx CFGR */ hlptim->Instance->CFGR = tmpcfgr; /* Configure LPTIM input sources */ - if(hlptim->Instance == LPTIM1) + if (hlptim->Instance == LPTIM1) { - /* Check LPTIM1 Input1 and Input2 sources */ - assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source)); - assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance,hlptim->Init.Input2Source)); - - /* Configure LPTIM1 Input1 and Input2 sources */ + /* Check LPTIM Input1 and Input2 sources */ + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); + assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source)); + + /* Configure LPTIM Input1 and Input2 sources */ hlptim->Instance->OR = (hlptim->Init.Input1Source | hlptim->Init.Input2Source); } else { /* Check LPTIM2 Input1 source */ - assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance,hlptim->Init.Input1Source)); - + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); + /* Configure LPTIM2 Input1 source */ hlptim->Instance->OR = hlptim->Init.Input1Source; } - + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the LPTIM peripheral. - * @param hlptim: LPTIM handle + * @brief DeInitialize the LPTIM peripheral. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) { /* Check the LPTIM handle allocation */ - if(hlptim == NULL) + if (hlptim == NULL) { return HAL_ERROR; } - + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; - + /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); - + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + if (hlptim->MspDeInitCallback == NULL) + { + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hlptim->MspDeInitCallback(hlptim); +#else /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_LPTIM_MspDeInit(hlptim); - +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hlptim); - + /* Return function status */ return HAL_OK; } /** * @brief Initialize the LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) @@ -326,7 +396,7 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitialize LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) @@ -343,13 +413,13 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions + * @brief Start-Stop operation functions. * -@verbatim +@verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start the PWM mode. (+) Stop the PWM mode. @@ -360,21 +430,21 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) (+) Start the Encoder mode. (+) Stop the Encoder mode. (+) Start the Timeout mode. - (+) Stop the Timeout mode. + (+) Stop the Timeout mode. (+) Start the Counter mode. (+) Stop the Counter mode. - + @endverbatim * @{ */ - + /** * @brief Start the LPTIM PWM generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -384,61 +454,69 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the LPTIM PWM generation. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status */ @@ -448,99 +526,123 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Compare write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } + } + +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - - /* Disable Autoreload write complete interrupt */ + + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Compare write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } + } + +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the LPTIM One pulse generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -550,61 +652,69 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ + + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the LPTIM One pulse generation. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -614,99 +724,123 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Compare write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - + +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Compare write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - + +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the LPTIM in Set once mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -716,61 +850,69 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the LPTIM Set once mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -780,276 +922,282 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Pulse)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Compare write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - + } + +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_SINGLE(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Compare write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - + } + +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the Encoder interface. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) { - HAL_StatusTypeDef status = HAL_OK; uint32_t tmpcfgr; /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - /* Encoder feature is only available for LPTIM1 instance */ - if (hlptim->Instance == LPTIM1) - { - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; - /* Clear CKPOL bits */ - tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); - /* Set Input polarity */ - tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; - /* Set ENC bit to enable the encoder interface */ - hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - } - else - { - status = HAL_ERROR; - } + /* Change the TIM state*/ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** * @brief Stop the Encoder interface. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) { - HAL_StatusTypeDef status = HAL_OK; uint32_t tmpcfgr; /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - /* Encoder feature is only available for LPTIM1 instance */ - if (hlptim->Instance == LPTIM1) - { - /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; - /* Configure edge sensitivity for encoder mode */ - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; + /* Configure edge sensitivity for encoder mode */ + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; - /* Clear CKPOL bits */ - tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); - /* Set Input polarity */ - tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; - /* Set ENC bit to enable the encoder interface */ - hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - /* Enable "switch to down direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); + /* Enable "switch to down direction" interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); - /* Enable "switch to up direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); + /* Enable "switch to up direction" interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - } - else - { - status = HAL_ERROR; - } + /* Change the TIM state*/ + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** * @brief Stop the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - + /* Disable "switch to down direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN); - + /* Disable "switch to up direction" interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -1058,10 +1206,10 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Timeout function. * @note The first trigger event will start the timer, any successive * trigger event will reset the counter and the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1071,54 +1219,54 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Timeout)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the Timeout function. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -1127,10 +1275,10 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the Timeout function in interrupt mode. * @note The first trigger event will start the timer, any successive * trigger event will reset the counter and the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1140,68 +1288,74 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); assert_param(IS_LPTIM_PULSE(Timeout)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - + /* Enable Compare match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the Timeout function in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - + /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the Counter mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1210,12 +1364,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1225,47 +1379,55 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + +#if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the Counter mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Start the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1274,66 +1436,96 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_PERIOD(Period)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); /* Set clock prescaler to 0 */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; } - + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Enable Autoreload match interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - + +#if defined(LPTIM_RCR_REP) + /* Enable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_ENABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - + + #if defined(LPTIM_RCR_REP) + /* Load the repetition value in the repetition counter */ + if (hlptim->Init.RepetitionCounter != 0) + { + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + } +#endif + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** * @brief Stop the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - + /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - + +#if defined(LPTIM_RCR_REP) + /* Disable the update event and the repetition register update OK interrupts */ + if ((hlptim->Init.RepetitionCounter) != 0) + { + __HAL_LPTIM_DISABLE_IT(hlptim, (LPTIM_IT_UPDATE | LPTIM_IT_REPOK)); + } +#endif + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; - + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -1342,13 +1534,13 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions * @brief Read operation functions. * -@verbatim +@verbatim ============================================================================== ##### LPTIM Read operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides LPTIM Reading functions. (+) Read the counter value. (+) Read the period (Auto-reload) value. @@ -1359,40 +1551,40 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Return the current counter value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Counter value. */ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + return (hlptim->Instance->CNT); } /** * @brief Return the current Autoreload (Period) value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Autoreload value. */ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + return (hlptim->Instance->ARR); } /** * @brief Return the current Compare (Pulse) value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Compare value. */ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - + return (hlptim->Instance->CMP); } @@ -1400,17 +1592,23 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) * @} */ - - /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks * @brief LPTIM IRQ handler. * -@verbatim +@verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### - ============================================================================== -[..] This section provides LPTIM IRQ handler and callback functions called within - the IRQ handler. + ============================================================================== +[..] This section provides LPTIM IRQ handler and callback functions called within + the IRQ handler: + (+) LPTIM interrupt request handler + (+) Compare match Callback + (+) Auto-reload match Callback + (+) External trigger event detection Callback + (+) Compare register write complete Callback + (+) Auto-reload register write complete Callback + (+) Up-counting direction change Callback + (+) Down-counting direction change Callback @endverbatim * @{ @@ -1418,106 +1616,171 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) /** * @brief Handle LPTIM interrupt request. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Compare match interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET) { /* Clear Compare match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); - + /* Compare match Callback */ - HAL_LPTIM_CompareMatchCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else + HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Autoreload match interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET) { /* Clear Autoreload match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); - + /* Autoreload match Callback */ - HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadMatchCallback(hlptim); +#else + HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Trigger detected interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET) { /* Clear Trigger detected flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); - + /* Trigger detected callback */ - HAL_LPTIM_TriggerCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->TriggerCallback(hlptim); +#else + HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Compare write interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET) { /* Clear Compare write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - + /* Compare write Callback */ - HAL_LPTIM_CompareWriteCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else + HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Autoreload write interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET) { /* Clear Autoreload write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - + /* Autoreload write Callback */ - HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadWriteCallback(hlptim); +#else + HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Direction counter changed from Down to Up interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET) { /* Clear Direction counter changed from Down to Up flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); - + /* Direction counter changed from Down to Up Callback */ - HAL_LPTIM_DirectionUpCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionUpCallback(hlptim); +#else + HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - + /* Direction counter changed from Up to Down interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET) + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET) { /* Clear Direction counter changed from Up to Down flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); - + /* Direction counter changed from Up to Down Callback */ - HAL_LPTIM_DirectionDownCallback(hlptim); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionDownCallback(hlptim); +#else + HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } + +#if defined(LPTIM_RCR_REP) + /* Repetition counter underflowed (or contains zero) and the LPTIM counter + overflowed */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET) + { + /* Clear update event flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE); + + /* Update event Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventCallback(hlptim); +#else + HAL_LPTIM_UpdateEventCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Successful APB bus write to repetition counter register */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET) + { + /* Clear successful APB bus write to repetition counter flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + /* Successful APB bus write to repetition counter Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->RepCounterWriteCallback(hlptim); +#else + HAL_LPTIM_RepCounterWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } +#endif } /** * @brief Compare match callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1527,12 +1790,12 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_CompareMatchCallback could be implemented in the user file - */ + */ } /** * @brief Autoreload match callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1542,12 +1805,12 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file - */ + */ } /** * @brief Trigger detected callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) @@ -1557,12 +1820,12 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_TriggerCallback could be implemented in the user file - */ + */ } /** * @brief Compare write callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1572,12 +1835,12 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_CompareWriteCallback could be implemented in the user file - */ + */ } /** - * @brief Autoreload write callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @brief Autoreload write callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1587,12 +1850,12 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file - */ + */ } /** * @brief Direction counter changed from Down to Up callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) @@ -1602,12 +1865,12 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_DirectionUpCallback could be implemented in the user file - */ + */ } /** * @brief Direction counter changed from Up to Down callback in non-blocking mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) @@ -1617,20 +1880,282 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_DirectionDownCallback could be implemented in the user file - */ + */ } +#if defined(LPTIM_RCR_REP) +/** + * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode. + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_UpdateEventCallback could be implemented in the user file + */ +} + +/** + * @brief Successful APB bus write to repetition counter register callback in non-blocking mode. + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file + */ +} +#endif /* LPTIM_RCR_REP */ + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LPTIM callback to be used instead of the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hlptim); + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = pCallback; + break; + +#if defined(LPTIM_RCR_REP) + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + hlptim->UpdateEventCallback = pCallback; + break; + + case HAL_LPTIM_REPETITION_WRITE_CB_ID : + hlptim->RepCounterWriteCallback = pCallback; + break; +#endif /* LPTIM_RCR_REP */ + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + return status; +} + +/** + * @brief Unregister a LPTIM callback + * LLPTIM callback is redirected to the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hlptim); + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + break; + +#if defined(LPTIM_RCR_REP) + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Legacy weak Update Event Callback */ + break; + + case HAL_LPTIM_REPETITION_WRITE_CB_ID : + hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Legacy weak Repetition counter successful write Callback */ + break; +#endif /* LPTIM_RCR_REP */ + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + return status; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup LPTIM_Group5 Peripheral State functions + * @brief Peripheral State functions. * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### - ============================================================================== + ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -1640,7 +2165,7 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Return the LPTIM handle state. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL state */ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) @@ -1658,6 +2183,175 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) * @} */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @retval None + */ +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) +{ + /* Reset the LPTIM callback to the legacy weak callbacks */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ +#if defined(LPTIM_RCR_REP) + lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; /* Update Event Callback */ + lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; /* Repetition counter successful write Callback */ +#endif /* LPTIM_RCR_REP */ +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief Disable LPTIM HW instance. + * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None + */ +void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) +{ + uint32_t tmpclksource = 0; + uint32_t tmpIER; + uint32_t tmpCFGR; + uint32_t tmpCMP; + uint32_t tmpARR; + uint32_t tmpOR; + + __disable_irq(); + + /*********** Save LPTIM Config ***********/ + /* Save LPTIM source clock */ + switch ((uint32_t)lptim->Instance) + { + case LPTIM1_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + break; +#if defined(LPTIM2) + case LPTIM2_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); + break; +#endif /* LPTIM2 */ + default: + break; + } + + /* Save LPTIM configuration registers */ + tmpIER = lptim->Instance->IER; + tmpCFGR = lptim->Instance->CFGR; + tmpCMP = lptim->Instance->CMP; + tmpARR = lptim->Instance->ARR; + tmpOR = lptim->Instance->OR; + + /*********** Reset LPTIM ***********/ + switch ((uint32_t)lptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; +#if defined(LPTIM2) + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_FORCE_RESET(); + __HAL_RCC_LPTIM2_RELEASE_RESET(); + break; +#endif /* LPTIM2 */ + default: + break; + } + + /*********** Restore LPTIM Config ***********/ + uint32_t Ref_Time; + uint32_t Time_Elapsed; + + if ((tmpCMP != 0UL) || (tmpARR != 0UL)) + { + /* Force LPTIM source kernel clock from APB */ + switch ((uint32_t)lptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); + break; +#if defined(LPTIM2) + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1); + break; +#endif /* LPTIM2 */ + default: + break; + } + + if (tmpCMP != 0UL) + { + /* Restore CMP register (LPTIM should be enabled first) */ + lptim->Instance->CR |= LPTIM_CR_ENABLE; + lptim->Instance->CMP = tmpCMP; + /* Polling on CMP write ok status after above restore operation */ + Ref_Time = HAL_GetTick(); + do + { + Time_Elapsed = HAL_GetTick() - Ref_Time; + } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT)); + + __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK); + } + + if (tmpARR != 0UL) + { + /* Restore ARR register (LPTIM should be enabled first) */ + lptim->Instance->CR |= LPTIM_CR_ENABLE; + lptim->Instance->ARR = tmpARR; + /* Polling on ARR write ok status after above restore operation */ + Ref_Time = HAL_GetTick(); + do + { + Time_Elapsed = HAL_GetTick() - Ref_Time; + } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT)); + + __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK); + } + + /* Restore LPTIM source kernel clock */ + switch ((uint32_t)lptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(tmpclksource); + break; +#if defined(LPTIM2) + case LPTIM2_BASE: + __HAL_RCC_LPTIM2_CONFIG(tmpclksource); + break; +#endif /* LPTIM2 */ + default: + break; + } + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + lptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + lptim->Instance->IER = tmpIER; + lptim->Instance->CFGR = tmpCFGR; + lptim->Instance->OR = tmpOR; + + __enable_irq(); +} +/** + * @} + */ +#endif /* LPTIM1 || LPTIM2 */ + #endif /* HAL_LPTIM_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h index ee1a6b3d65..7b7d0ce676 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_LPTIM_H -#define __STM32L4xx_HAL_LPTIM_H +#ifndef STM32L4xx_HAL_LPTIM_H +#define STM32L4xx_HAL_LPTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,17 +32,20 @@ * @{ */ +#if defined (LPTIM1) || defined (LPTIM2) + /** @addtogroup LPTIM * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Types LPTIM Exported Types * @{ */ +#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR2_IM32 /*!< External interrupt line 32 Connected to the LPTIM EXTI Line */ -/** - * @brief LPTIM Clock configuration definition +/** + * @brief LPTIM Clock configuration definition */ typedef struct { @@ -67,11 +54,11 @@ typedef struct uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. This parameter can be a value of @ref LPTIM_Clock_Prescaler */ - -}LPTIM_ClockConfigTypeDef; -/** - * @brief LPTIM Clock configuration definition +} LPTIM_ClockConfigTypeDef; + +/** + * @brief LPTIM Clock configuration definition */ typedef struct { @@ -80,92 +67,147 @@ typedef struct Note: This parameter is used only when Ultra low power clock source is used. Note: If the polarity is configured on 'both edges', an auxiliary clock (one of the Low power oscillator) must be active. - This parameter can be a value of @ref LPTIM_Clock_Polarity */ - + This parameter can be a value of @ref LPTIM_Clock_Polarity */ + uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. Note: This parameter is used only when Ultra low power clock source is used. - This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ - -}LPTIM_ULPClockConfigTypeDef; + This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ -/** - * @brief LPTIM Trigger configuration definition +} LPTIM_ULPClockConfigTypeDef; + +/** + * @brief LPTIM Trigger configuration definition */ typedef struct { uint32_t Source; /*!< Selects the Trigger source. This parameter can be a value of @ref LPTIM_Trigger_Source */ - + uint32_t ActiveEdge; /*!< Selects the Trigger active edge. Note: This parameter is used only when an external trigger is used. This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ - + uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. - This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ -}LPTIM_TriggerConfigTypeDef; + This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ +} LPTIM_TriggerConfigTypeDef; -/** - * @brief LPTIM Initialization Structure definition +/** + * @brief LPTIM Initialization Structure definition */ typedef struct -{ +{ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ - + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - + uint32_t OutputPolarity; /*!< Specifies the Output polarity. This parameter can be a value of @ref LPTIM_Output_Polarity */ - + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of @ref LPTIM_Updating_Mode */ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + This parameter can be a value of @ref LPTIM_Counter_Source */ uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). - This parameter can be a value of @ref LPTIM_Input1_Source */ + This parameter can be a value of @ref LPTIM_Input1_Source */ uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). - Note: This parameter is used only for encoder feature so is used only + Note: This parameter is used only for encoder feature so is used only for LPTIM1 instance. - This parameter can be a value of @ref LPTIM_Input2_Source */ - -}LPTIM_InitTypeDef; + This parameter can be a value of @ref LPTIM_Input2_Source */ -/** - * @brief HAL LPTIM State structure definition - */ -typedef enum __HAL_LPTIM_StateTypeDef +#if defined(LPTIM_RCR_REP) + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + Note: When using repetition counter the UpdateMode field must be set to + LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable bahavior may occur. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ +#endif + +} LPTIM_InitTypeDef; + +/** + * @brief HAL LPTIM State structure definition + */ +typedef enum { - HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ -}HAL_LPTIM_StateTypeDef; + HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ +} HAL_LPTIM_StateTypeDef; -/** - * @brief LPTIM handle Structure definition - */ +/** + * @brief LPTIM handle Structure definition + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +typedef struct __LPTIM_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ { - LPTIM_TypeDef *Instance; /*!< Register base address */ - - LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ - - HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ - - HAL_LockTypeDef Lock; /*!< LPTIM locking object */ - - __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ - -}LPTIM_HandleTypeDef; + LPTIM_TypeDef *Instance; /*!< Register base address */ + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ + + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ + void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ + void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ + void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ + void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ + void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ + void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ + void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ + void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ +#if defined(LPTIM_RCR_REP) + void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter underflow Callback */ + void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter successful write Callback */ +#endif /* LPTIM_RCR_REP */ +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} LPTIM_HandleTypeDef; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LPTIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ + HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ + HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ + HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ + HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ + HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ + HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ + HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ + HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ +#if defined(LPTIM_RCR_REP) + HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Repetition counter underflow Callback ID */ + HAL_LPTIM_REPETITION_WRITE_CB_ID = 0x0AU, /*!< Repetition counter successful write Callback ID */ +#endif /* LPTIM_RCR_REP */ +} HAL_LPTIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} */ @@ -178,33 +220,33 @@ typedef struct /** @defgroup LPTIM_Clock_Source LPTIM Clock Source * @{ */ -#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00) +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U #define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL -/** +/** * @} */ /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler * @{ */ -#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000) +#define LPTIM_PRESCALER_DIV1 0x00000000U #define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 #define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 -#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)) +#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) #define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 -#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)) -#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)) -#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) +#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /** * @} - */ + */ /** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity * @{ */ -#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) -#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) +#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U +#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL /** * @} */ @@ -212,7 +254,7 @@ typedef struct /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time * @{ */ -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U #define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 #define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 #define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT @@ -223,7 +265,7 @@ typedef struct /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity * @{ */ -#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000) +#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U #define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 #define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /** @@ -233,14 +275,14 @@ typedef struct /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source * @{ */ -#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF) -#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000) -#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) +#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU +#define LPTIM_TRIGSOURCE_0 0x00000000U +#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 #define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 -#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) #define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 -#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) -#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) #define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL /** * @} @@ -259,7 +301,7 @@ typedef struct /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time * @{ */ -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT @@ -271,7 +313,7 @@ typedef struct * @{ */ -#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000) +#define LPTIM_UPDATE_IMMEDIATE 0x00000000U #define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /** * @} @@ -281,20 +323,20 @@ typedef struct * @{ */ -#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000) +#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U #define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE /** * @} */ - + /** @defgroup LPTIM_Input1_Source LPTIM Input1 Source * @{ */ -#define LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000) /*!< For LPTIM1 and LPTIM2 */ -#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */ -#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */ -#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */ +#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */ +#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */ +#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */ +#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */ /** * @} */ @@ -303,8 +345,8 @@ typedef struct * @{ */ -#define LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000) /*!< For LPTIM1 */ -#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */ +#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 */ +#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */ /** * @} */ @@ -312,7 +354,10 @@ typedef struct /** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition * @{ */ - +#if defined(LPTIM_RCR_REP) +#define LPTIM_FLAG_REPOK LPTIM_ISR_REPOK +#define LPTIM_FLAG_UPDATE LPTIM_ISR_UE +#endif #define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN #define LPTIM_FLAG_UP LPTIM_ISR_UP #define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK @@ -327,7 +372,10 @@ typedef struct /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition * @{ */ - +#if defined(LPTIM_RCR_REP) +#define LPTIM_IT_REPOK LPTIM_IER_REPOKIE +#define LPTIM_IT_UPDATE LPTIM_IER_UEIE +#endif #define LPTIM_IT_DOWN LPTIM_IER_DOWNIE #define LPTIM_IT_UP LPTIM_IER_UPIE #define LPTIM_IT_ARROK LPTIM_IER_ARROKIE @@ -349,55 +397,93 @@ typedef struct */ /** @brief Reset LPTIM handle state. - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle * @retval None */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @brief Enable the LPTIM peripheral. - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle * @retval None */ -#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) +#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) /** * @brief Disable the LPTIM peripheral. - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. * @retval None */ -#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE)) +#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) /** - * @brief Start the LPTIM peripheral in Continuous or in single mode. - * @param __HANDLE__: DMA handle + * @brief Start the LPTIM peripheral in Continuous mode. + * @param __HANDLE__ LPTIM handle * @retval None */ #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) +/** + * @brief Start the LPTIM peripheral in single mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ #define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) - - + /** * @brief Write the passed parameter in the Autoreload register. - * @param __HANDLE__: LPTIM handle - * @param __VALUE__: Autoreload value + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Autoreload value * @retval None */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) /** * @brief Write the passed parameter in the Compare register. - * @param __HANDLE__: LPTIM handle - * @param __VALUE__: Compare value + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Compare value * @retval None */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) +#if defined(LPTIM_RCR_REP) +/** + * @brief Write the passed parameter in the Repetition register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Repetition value + * @retval None + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__) \ + do { \ + (__HANDLE__)->Instance->RCR = (__VALUE__); \ + (__HANDLE__)->Init.RepetitionCounter = (__VALUE__); \ + } while(0) + +/** + * @brief Return the current Repetition value. + * @param __HANDLE__ LPTIM handle + * @retval Repetition register value + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__) ((__HANDLE__)->Instance->RCR) +#endif + /** * @brief Check whether the specified LPTIM flag is set or not. - * @param __HANDLE__: LPTIM handle - * @param __FLAG__: LPTIM flag to check + * @param __HANDLE__ LPTIM handle + * @param __FLAG__ LPTIM flag to check * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag (when available). + * @arg LPTIM_FLAG_UPDATE : Update event Flag (when available). * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. @@ -411,9 +497,11 @@ typedef struct /** * @brief Clear the specified LPTIM flag. - * @param __HANDLE__: LPTIM handle. - * @param __FLAG__: LPTIM flag to clear. + * @param __HANDLE__ LPTIM handle. + * @param __FLAG__ LPTIM flag to clear. * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag (when available). + * @arg LPTIM_FLAG_UPDATE : Update event Flag (when available). * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. @@ -421,15 +509,17 @@ typedef struct * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. * @arg LPTIM_FLAG_CMPM : Compare match Flag. - * @retval None + * @retval None. */ #define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable the specified LPTIM interrupt. - * @param __HANDLE__: LPTIM handle. - * @param __INTERRUPT__: LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update Interrupt (when available). + * @arg LPTIM_IT_UPDATE : Update event Interrupt (when available). * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. @@ -437,14 +527,14 @@ typedef struct * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. - * @retval None + * @retval None. */ #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - /** +/** * @brief Disable the specified LPTIM interrupt. - * @param __HANDLE__: LPTIM handle. - * @param __INTERRUPT__: LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -453,14 +543,14 @@ typedef struct * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. - * @retval None + * @retval None. */ #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) - /** +/** * @brief Check whether the specified LPTIM interrupt source is enabled or not. - * @param __HANDLE__: LPTIM handle. - * @param __INTERRUPT__: LPTIM interrupt to check. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -471,13 +561,37 @@ typedef struct * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval Interrupt status. */ - + #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +/** + * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2 |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions * @{ @@ -556,6 +670,16 @@ void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); +#if defined(LPTIM_RCR_REP) +void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); +#endif /* LPTIM_RCR_REP */ + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); @@ -563,7 +687,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** * @} */ - + /* Private types -------------------------------------------------------------*/ /** @defgroup LPTIM_Private_Types LPTIM Private Types * @{ @@ -577,7 +701,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Variables LPTIM Private Variables * @{ */ - + /** * @} */ @@ -595,11 +719,11 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Macros LPTIM Private Macros * @{ */ - + #define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) - + #define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ @@ -648,13 +772,17 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) -#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF) +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF) +#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) -#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF) +#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) + +#if defined(LPTIM_RCR_REP) +#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL) +#endif #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ ((((__INSTANCE__) == LPTIM1) && \ @@ -674,13 +802,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup LPTIM_Private_Functions LPTIM Private Functions * @{ */ - +void LPTIM_Disable(LPTIM_HandleTypeDef *lptim); /** * @} */ @@ -689,6 +817,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); * @} */ +#endif /* LPTIM1 || LPTIM2 */ /** * @} */ @@ -697,6 +826,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); } #endif -#endif /* __STM32L4xx_HAL_LPTIM_H */ +#endif /* STM32L4xx_HAL_LPTIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c index 885043f72a..8e27fadad7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c @@ -3,32 +3,44 @@ * @file stm32l4xx_hal_ltdc.c * @author MCD Application Team * @brief LTDC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions - * - @verbatim + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Program the required configuration through the following parameters: - the LTDC timing, the horizontal and vertical polarity, - the pixel clock polarity, Data Enable polarity and the LTDC background color value - using HAL_LTDC_Init() function + [..] + The LTDC HAL driver can be used as follows: - (#) Program the required configuration through the following parameters: - the pixel format, the blending factors, input alpha value, the window size + (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc; + + (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API: + (##) Enable the LTDC interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the LTDC interrupt priority + (+++) Enable the NVIC LTDC IRQ Channel + + (#) Initialize the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity, + Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function + + *** Configuration *** + ========================= + [..] + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size and the image size using HAL_LTDC_ConfigLayer() function for foreground - or/and background layer. - - (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and HAL_LTDC_EnableCLUT functions. - - (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() and HAL_LTDC_EnableColorKeying functions. @@ -37,71 +49,115 @@ function (#) If needed, reconfigure and change the pixel format value, the alpha value - value, the window size, the window position and the layer start address - for foreground or/and background layer using respectively the following + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. - This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). - After calling the _NoReload functions to set different color/format/layer settings, - the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. - Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required. Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if - the reload should be done in the next vertical blanking period, + the reload should be done in the next vertical blanking period, this option allows to avoid display flicker by applying the new settings during the vertical blanking period. - - (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() *** LTDC HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in LTDC HAL driver. - + (+) __HAL_LTDC_ENABLE: Enable the LTDC. (+) __HAL_LTDC_DISABLE: Disable the LTDC. - (+) __HAL_LTDC_LAYER_ENABLE: Enable a LTDC Layer. - (+) __HAL_LTDC_LAYER_DISABLE: Disable a LTDC Layer. + (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. + (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. + (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. - (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. - - [..] + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. + + [..] (@) You can refer to the LTDC HAL driver header file for more useful macros - + + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function HAL_LTDC_RegisterCallback() to register a callback. + + [..] + Function HAL_LTDC_RegisterCallback() allows to register following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) LineEventCallback : LTDC Line Event Callback + (+) ReloadEventCallback : LTDC Reload Event Callback + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit + (+) MspDeInitCallback : LTDC MspDeInit. + + [..] + By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit() + only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit() + or HAL_LTDC_Init() function. + + [..] + When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -110,19 +166,20 @@ * @{ */ -#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#ifdef HAL_LTDC_MODULE_ENABLED + +#if defined (LTDC) /** @defgroup LTDC LTDC * @brief LTDC HAL module driver * @{ */ -#ifdef HAL_LTDC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); /* Private functions ---------------------------------------------------------*/ @@ -132,20 +189,20 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ /** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim + * @brief Initialization and Configuration functions + * +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the LTDC - (+) De-initialize the LTDC + (+) De-initialize the LTDC @endverbatim * @{ */ - + /** * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains @@ -154,10 +211,10 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { - uint32_t tmp = 0, tmp1 = 0; + uint32_t tmp, tmp1; /* Check the LTDC peripheral state */ - if(hltdc == NULL) + if (hltdc == NULL) { return HAL_ERROR; } @@ -177,45 +234,65 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); - if(hltdc->State == HAL_LTDC_STATE_RESET) +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + + /* Reset the LTDC callback to the legacy weak callbacks */ + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hltdc->MspInitCallback == NULL) + { + hltdc->MspInitCallback = HAL_LTDC_MspInit; + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) { /* Allocate lock resource and initialize it */ hltdc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_LTDC_MspInit(hltdc); } - +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; /* Configure the HS, VS, DE and PC polarity */ hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); - hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ - hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); /* Set Synchronization size */ hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); - tmp = (hltdc->Init.HorizontalSync << 16); + tmp = (hltdc->Init.HorizontalSync << 16U); hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); /* Set Accumulated Back porch */ hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); - tmp = (hltdc->Init.AccumulatedHBP << 16); + tmp = (hltdc->Init.AccumulatedHBP << 16U); hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); /* Set Accumulated Active Width */ hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); - tmp = (hltdc->Init.AccumulatedActiveW << 16); + tmp = (hltdc->Init.AccumulatedActiveW << 16U); hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); /* Set Total Width */ hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); - tmp = (hltdc->Init.TotalWidth << 16); + tmp = (hltdc->Init.TotalWidth << 16U); hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); /* Set the background color value */ - tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8); - tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16); + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); @@ -226,7 +303,7 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) __HAL_LTDC_ENABLE(hltdc); /* Initialize the error code */ - hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -243,8 +320,17 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) { +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->MspDeInitCallback == NULL) + { + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; + } /* DeInit the low level hardware */ - HAL_LTDC_MspDeInit(hltdc); + hltdc->MspDeInitCallback(hltdc); +#else + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ /* Initialize the error code */ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; @@ -264,14 +350,14 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval None */ -__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_MspInit could be implemented in the user file - */ + */ } /** @@ -280,27 +366,209 @@ __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) * the configuration information for the LTDC. * @retval None */ -__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_MspDeInit could be implemented in the user file */ } +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LTDC Callback + * To be used instead of the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = pCallback; + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = pCallback; + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = pCallback; + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} + +/** + * @brief Unregister an LTDC Callback + * LTDC callabck is redirected to the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /** * @} */ - -/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides function allowing to: (+) Handle LTDC interrupt request @@ -310,16 +578,16 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /** * @brief Handle LTDC interrupt request. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. + * the configuration information for the LTDC. * @retval HAL status */ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) { uint32_t isrflags = READ_REG(hltdc->Instance->ISR); uint32_t itsources = READ_REG(hltdc->Instance->IER); - + /* Transfer Error Interrupt management ***************************************/ - if(((isrflags & LTDC_ISR_TERRIF) != RESET) && ((itsources & LTDC_IER_TERRIE) != RESET)) + if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) { /* Disable the transfer Error interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); @@ -337,11 +605,17 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) __HAL_UNLOCK(hltdc); /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* FIFO underrun Interrupt management ***************************************/ - if(((isrflags & LTDC_ISR_FUIF) != RESET) && ((itsources & LTDC_IER_FUIE) != RESET)) + if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) { /* Disable the FIFO underrun interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); @@ -357,18 +631,24 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) /* Process unlocked */ __HAL_UNLOCK(hltdc); - + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Line Interrupt management ************************************************/ - if(((isrflags & LTDC_ISR_LIF) != RESET) && ((itsources & LTDC_IER_LIE) != RESET)) + if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) { /* Disable the Line interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); - /* Clear the Line interrupt flag */ + /* Clear the Line interrupt flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); /* Change LTDC state */ @@ -378,26 +658,38 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) __HAL_UNLOCK(hltdc); /* Line interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ HAL_LTDC_LineEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Register reload Interrupt management ***************************************/ - if(((isrflags & LTDC_ISR_RRIF) != RESET) && ((itsources & LTDC_IER_RRIE) != RESET)) + if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) { /* Disable the register reload interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); - + /* Clear the register reload flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); - + /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - - /* Register reload interrupt Callback */ + + /* Reload interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ HAL_LTDC_ReloadEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } } @@ -411,7 +703,7 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ErrorCallback could be implemented in the user file */ @@ -427,7 +719,7 @@ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_LineEventCallback could be implemented in the user file */ @@ -443,7 +735,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hltdc); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ReloadEvenCallback could be implemented in the user file */ @@ -454,12 +746,12 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) */ /** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim + * @brief Peripheral Control functions + * +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the LTDC foreground or/and background parameters. (+) Set the active layer. @@ -469,7 +761,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) (+) Enable / Disable the C-LUT. (+) Update the layer position. (+) Update the layer size. - (+) Update pixel format on the fly. + (+) Update pixel format on the fly. (+) Update transparency on the fly. (+) Update address on the fly. @@ -490,7 +782,7 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); @@ -502,19 +794,19 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgT assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - /* Configure the LTDC Layer */ + /* Configure the LTDC Layer */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Set the Immediate Reload type */ @@ -571,7 +863,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param pCLUT pointer to the color lookup table address. - * @param CLUTSize the color lookup table size. + * @param CLUTSize the color lookup table size. * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) @@ -579,41 +871,40 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t */ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t counter = 0; - uint32_t pcounter = 0; - + uint32_t tmp; + uint32_t counter; + uint32_t *pcolorlut = pCLUT; /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_LAYER(LayerIdx)); /* Process locked */ __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; + hltdc->State = HAL_LTDC_STATE_BUSY; - for(counter = 0; (counter < CLUTSize); counter++) + for (counter = 0U; (counter < CLUTSize); counter++) { - if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) { - tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } else - { - tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + { + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } - pcounter = (uint32_t)pCLUT + sizeof(*pCLUT); - pCLUT = (uint32_t *)pcounter; + + pcolorlut++; /* Specifies the C-LUT address and RGB value */ LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; } - + /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ - __HAL_UNLOCK(hltdc); + __HAL_UNLOCK(hltdc); return HAL_OK; } @@ -628,7 +919,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -645,14 +936,14 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); - return HAL_OK; + return HAL_OK; } - + /** * @brief Disable the color keying. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains @@ -680,7 +971,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_ hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -715,7 +1006,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -729,14 +1020,14 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI * the configuration information for the LTDC. * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); @@ -750,7 +1041,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer hltdc->Instance->SRCR = LTDC_SRCR_IMR; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -777,7 +1068,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -823,7 +1114,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -836,7 +1127,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; + hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; @@ -844,7 +1135,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi /* update horizontal stop */ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - /* update vertical stop */ + /* update vertical stop */ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; /* Reconfigures the color frame buffer pitch in byte */ @@ -882,7 +1173,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; - + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_CFBLL(X0)); @@ -945,13 +1236,13 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pi hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; /* Reconfigure the pixel format */ pLayerCfg->PixelFormat = Pixelformat; /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Set the Immediate Reload type */ hltdc->Instance->SRCR = LTDC_SRCR_IMR; @@ -1055,8 +1346,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres /** * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). @@ -1068,63 +1359,63 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres */ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t pitchUpdate = 0; - uint32_t pixelFormat = 0; - + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; - + /* get LayerIdx used pixel format */ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - - if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { - tmp = 4; + tmp = 4U; } else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) { - tmp = 3; + tmp = 3U; } - else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) { - tmp = 2; + tmp = 2U; } else { - tmp = 1; + tmp = 1U; } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16); - + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + /* Clear previously set standard pitch */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - + /* Set the Reload type as immediate update of LTDC pitch configured above */ LTDC->SRCR |= LTDC_SRCR_IMR; - + /* Set new line pitch value */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - + /* Set the Reload type as immediate update of LTDC pitch configured above */ LTDC->SRCR |= LTDC_SRCR_IMR; - + /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - - return HAL_OK; + + return HAL_OK; } /** @@ -1132,7 +1423,7 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Line Line Interrupt Position. - * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) @@ -1171,7 +1462,7 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t * @param ReloadType This parameter can be one of the following values : * LTDC_RELOAD_IMMEDIATE : Immediate Reload * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking - * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) @@ -1183,20 +1474,20 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable the Reload interrupt */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); - + /* Apply Reload type */ - hltdc->Instance->SRCR = ReloadType; + hltdc->Instance->SRCR = ReloadType; /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - + return HAL_OK; } @@ -1214,7 +1505,7 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); @@ -1226,23 +1517,21 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - /* Configure the LTDC Layer */ + /* Configure the LTDC Layer */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1264,7 +1553,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1277,7 +1566,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin __HAL_LOCK(hltdc); /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; + hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ pLayerCfg = &hltdc->LayerCfg[LayerIdx]; @@ -1285,7 +1574,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin /* update horizontal stop */ pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - /* update vertical stop */ + /* update vertical stop */ pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; /* Reconfigures the color frame buffer pitch in byte */ @@ -1297,8 +1586,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1323,7 +1610,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; - + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); assert_param(IS_LTDC_CFBLL(X0)); @@ -1349,8 +1636,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1386,15 +1671,13 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, ui hltdc->State = HAL_LTDC_STATE_BUSY; /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; /* Reconfigure the pixel format */ pLayerCfg->PixelFormat = Pixelformat; /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Do not set the Immediate Reload */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1439,8 +1722,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1452,7 +1733,7 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Reconfigure the frame buffer Address without reloading. - * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param Address new address value. @@ -1483,8 +1764,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /* Set LTDC parameters */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1496,12 +1775,12 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /** * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * Variant of the function HAL_LTDC_SetPitch without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. @@ -1510,59 +1789,57 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 */ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t pitchUpdate = 0; - uint32_t pixelFormat = 0; - + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); - + /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; - + /* get LayerIdx used pixel format */ pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - - if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { - tmp = 4; + tmp = 4U; } else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) { - tmp = 3; + tmp = 3U; } - else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) { - tmp = 2; + tmp = 2U; } else { - tmp = 1; + tmp = 1U; } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16); - + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + /* Clear previously set standard pitch */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - + /* Set new line pitch value */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - - /* Do not set the Immediate Reload */ - + /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hltdc); - - return HAL_OK; + + return HAL_OK; } @@ -1592,8 +1869,6 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1614,7 +1889,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ +{ /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -1627,15 +1902,13 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, /* Enable LTDC color keying by setting COLKEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); - return HAL_OK; + return HAL_OK; } /** @@ -1662,10 +1935,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc /* Disable LTDC color keying by setting COLKEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -1697,10 +1968,8 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /* Disable LTDC color lookup table by setting CLUTEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -1715,14 +1984,14 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32 * the configuration information for the LTDC. * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); - + /* Process locked */ __HAL_LOCK(hltdc); @@ -1732,10 +2001,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 /* Disable LTDC color lookup table by setting CLUTEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - /* Do not set the Immediate Reload */ - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; + hltdc->State = HAL_LTDC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hltdc); @@ -1748,20 +2015,20 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 */ /** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim + * @brief Peripheral State and Errors functions + * +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the LTDC handle state. - (+) Get the LTDC handle error code. + (+) Get the LTDC handle error code. @endverbatim * @{ - */ + */ /** * @brief Return the LTDC handle state. @@ -1778,8 +2045,8 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) * @brief Return the LTDC handle error code. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. -* @retval LTDC Error Code -*/ + * @retval LTDC Error Code + */ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) { return hltdc->ErrorCode; @@ -1798,7 +2065,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) */ /** - * @brief Configure the LTDC peripheral + * @brief Configure the LTDC peripheral * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param pLayerCfg Pointer LTDC Layer Configuration structure @@ -1808,30 +2075,30 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) */ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { - uint32_t tmp = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; /* Configure the horizontal start and stop position */ - tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16); + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); /* Configure the vertical start and stop position */ - tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16); + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); /* Specifies the pixel format */ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); /* Configure the default color values */ - tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8); - tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16); - tmp2 = (pLayerCfg->Alpha0 << 24); + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + tmp2 = (pLayerCfg->Alpha0 << 24U); LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -1845,35 +2112,34 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); - if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { - tmp = 4; + tmp = 4U; } else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) { - tmp = 3; + tmp = 3U; } - else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) { - tmp = 2; + tmp = 2U; } else { - tmp = 1; + tmp = 1U; } /* Configure the color frame buffer pitch in byte */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3)); - + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); /* Configure the frame buffer line number */ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); - /* Enable LTDC_Layer by setting LEN bit */ + /* Enable LTDC_Layer by setting LEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; } @@ -1881,14 +2147,15 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay * @} */ + +/** + * @} + */ + +#endif /* LTDC */ + #endif /* HAL_LTDC_MODULE_ENABLED */ -/** - * @} - */ - -#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4S7xx || STM32L4S9xx */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h index b5f308980a..a48b37ecc7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h @@ -6,46 +6,29 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_LTDC_H -#define __STM32L4xx_HAL_LTDC_H +#ifndef STM32L4xx_HAL_LTDC_H +#define STM32L4xx_HAL_LTDC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#if defined (LTDC) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -60,9 +43,13 @@ /** @defgroup LTDC_Exported_Types LTDC Exported Types * @{ */ +#if defined(LTDC_Layer2_BASE) #define MAX_LAYER 2U +#elif defined(LTDC_Layer1_BASE) +#define MAX_LAYER 1U +#endif -/** +/** * @brief LTDC color structure definition */ typedef struct @@ -73,13 +60,13 @@ typedef struct uint8_t Green; /*!< Configures the green value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - uint8_t Red; /*!< Configures the red value. + uint8_t Red; /*!< Configures the red value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ uint8_t Reserved; /*!< Reserved 0xFF */ } LTDC_ColorTypeDef; -/** +/** * @brief LTDC Init structure definition */ typedef struct @@ -90,16 +77,16 @@ typedef struct uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. This parameter can be one value of @ref LTDC_VS_POLARITY */ - uint32_t DEPolarity; /*!< configures the data enable polarity. + uint32_t DEPolarity; /*!< configures the data enable polarity. This parameter can be one of value of @ref LTDC_DE_POLARITY */ - uint32_t PCPolarity; /*!< configures the pixel clock polarity. + uint32_t PCPolarity; /*!< configures the pixel clock polarity. This parameter can be one of value of @ref LTDC_PC_POLARITY */ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. @@ -108,7 +95,7 @@ typedef struct uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ - uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. @@ -123,7 +110,7 @@ typedef struct LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ } LTDC_InitTypeDef; -/** +/** * @brief LTDC Layer structure definition */ typedef struct @@ -140,7 +127,7 @@ typedef struct uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ - uint32_t PixelFormat; /*!< Specifies the pixel format. + uint32_t PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ uint32_t Alpha; /*!< Specifies the constant alpha used for blending. @@ -149,24 +136,24 @@ typedef struct uint32_t Alpha0; /*!< Configures the default alpha value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - uint32_t BlendingFactor1; /*!< Select the blending factor 1. + uint32_t BlendingFactor1; /*!< Select the blending factor 1. This parameter can be one of value of @ref LTDC_BlendingFactor1 */ - uint32_t BlendingFactor2; /*!< Select the blending factor 2. + uint32_t BlendingFactor2; /*!< Select the blending factor 2. This parameter can be one of value of @ref LTDC_BlendingFactor2 */ uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ - uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ - uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ } LTDC_LayerCfgTypeDef; -/** +/** * @brief HAL LTDC State structures definition */ typedef enum @@ -176,12 +163,16 @@ typedef enum HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ -}HAL_LTDC_StateTypeDef; +} HAL_LTDC_StateTypeDef; -/** +/** * @brief LTDC handle Structure definition */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +typedef struct __LTDC_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ { LTDC_TypeDef *Instance; /*!< LTDC Register base address */ @@ -195,7 +186,41 @@ typedef struct __IO uint32_t ErrorCode; /*!< LTDC Error code */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ + void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ + void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ + + void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ + void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + } LTDC_HandleTypeDef; + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LTDC Callback ID enumeration definition + */ +typedef enum +{ + HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ + HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ + + HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ + HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ + HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ + +} HAL_LTDC_CallbackIDTypeDef; + +/** + * @brief HAL LTDC Callback pointer definition + */ +typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /** * @} */ @@ -208,10 +233,13 @@ typedef struct /** @defgroup LTDC_Error_Code LTDC Error Code * @{ */ -#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */ -#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */ -#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */ -#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */ +#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ /** * @} */ @@ -219,8 +247,12 @@ typedef struct /** @defgroup LTDC_Layer LTDC Layer * @{ */ -#define LTDC_LAYER_1 ((uint32_t)0x00000000U) /*!< LTDC Layer 1 */ -#define LTDC_LAYER_2 ((uint32_t)0x00000001U) /*!< LTDC Layer 2 */ +#if defined(LTDC_Layer1_BASE) +#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ +#endif +#if defined(LTDC_Layer2_BASE) +#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ +#endif /** * @} */ @@ -228,7 +260,7 @@ typedef struct /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY * @{ */ -#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ #define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ /** * @} @@ -237,16 +269,16 @@ typedef struct /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY * @{ */ -#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ #define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ /** * @} */ - + /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY * @{ */ -#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ #define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ /** * @} @@ -255,7 +287,7 @@ typedef struct /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY * @{ */ -#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ #define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ /** * @} @@ -264,7 +296,7 @@ typedef struct /** @defgroup LTDC_SYNC LTDC SYNC * @{ */ -#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ #define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ /** * @} @@ -273,16 +305,16 @@ typedef struct /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR * @{ */ -#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */ +#define LTDC_COLOR 0x000000FFU /*!< Color mask */ /** * @} */ - + /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 * @{ */ -#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ /** * @} */ @@ -290,23 +322,23 @@ typedef struct /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 * @{ */ -#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ /** * @} */ - + /** @defgroup LTDC_Pixelformat LTDC Pixel format * @{ */ -#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ /** * @} */ @@ -325,7 +357,7 @@ typedef struct #define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ #define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ -#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ #define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ /** * @} @@ -341,7 +373,7 @@ typedef struct /** * @} */ - + /** @defgroup LTDC_Flags LTDC Flags * @{ */ @@ -364,7 +396,7 @@ typedef struct /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup LTDC_Exported_Macros LTDC Exported Macros @@ -375,7 +407,15 @@ typedef struct * @param __HANDLE__ LTDC handle * @retval None */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) +#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ /** * @brief Enable the LTDC. @@ -429,10 +469,10 @@ typedef struct * @param __HANDLE__ LTDC handle * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag * @arg LTDC_FLAG_TE: Transfer Error interrupt flag - * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag * @retval The state of FLAG (SET or RESET). */ #define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) @@ -442,10 +482,10 @@ typedef struct * @param __HANDLE__ LTDC handle * @param __FLAG__ Specify the flag to clear. * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag * @arg LTDC_FLAG_TE: Transfer Error interrupt flag - * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag * @retval None */ #define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -453,9 +493,9 @@ typedef struct /** * @brief Enables the specified LTDC interrupts. * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag * @arg LTDC_IT_TE: Transfer Error interrupt flag * @arg LTDC_IT_RR: Register Reload Interrupt Flag @@ -466,9 +506,9 @@ typedef struct /** * @brief Disables the specified LTDC interrupts. * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag * @arg LTDC_IT_TE: Transfer Error interrupt flag * @arg LTDC_IT_RR: Register Reload Interrupt Flag @@ -481,7 +521,7 @@ typedef struct * @param __HANDLE__ LTDC handle * @param __INTERRUPT__ Specify the LTDC interrupt source to check. * This parameter can be one of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag * @arg LTDC_IT_TE: Transfer Error interrupt flag * @arg LTDC_IT_RR: Register Reload Interrupt Flag @@ -505,11 +545,18 @@ typedef struct /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); -void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + /** * @} */ @@ -582,7 +629,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** @defgroup LTDC_Private_Macros LTDC Private Macros * @{ */ -#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__))))) #define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) #define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) #define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) @@ -619,7 +666,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup LTDC_Private_Functions LTDC Private Functions @@ -632,18 +679,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** * @} - */ + */ /** * @} */ -#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4R7xx || STM32L4S9xx */ +#endif /* LTDC */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_LTDC_H */ +#endif /* STM32L4xx_HAL_LTDC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c index bc0eab10fe..99181bdfa0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -40,15 +24,15 @@ * @{ */ -#if defined (STM32L4R9xx) || defined (STM32L4S9xx) +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +#if defined (LTDC) && defined (DSI) /** @defgroup LTDCEx LTDCEx * @brief LTDC HAL module driver * @{ */ -#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -61,12 +45,12 @@ */ /** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim + * @brief Initialization and Configuration functions + * +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the LTDC @@ -84,31 +68,29 @@ * polarities inversion as described in the current LTDC specification * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg) { /* Retrieve signal polarities from DSI */ - - /* The following polarities are inverted: - LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH - LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH - LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - + + /* The following polarity is inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ + /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; - hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; - hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ - + /* Retrieve vertical timing parameters from DSI */ - hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; - hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; - + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + return HAL_OK; } @@ -122,25 +104,25 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc * polarities inversion as described in the current LTDC specification * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg) { /* Retrieve signal polarities from DSI */ - + /* The following polarities are inverted: LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - + /* Note 1 : Code in line w/ Current LTDC specification */ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; - + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ - + return HAL_OK; } @@ -152,14 +134,14 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD * @} */ +/** + * @} + */ + +#endif /* LTDC && DSI */ + #endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ -/** - * @} - */ - -#endif /* STM32L4R9xx || STM32L4S9xx */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h index ff827cb2f9..82147aaeab 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h @@ -6,45 +6,30 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_LTDC_EX_H -#define __STM32L4xx_HAL_LTDC_EX_H +#ifndef STM32L4xx_HAL_LTDC_EX_H +#define STM32L4xx_HAL_LTDC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined (STM32L4R9xx) || defined (STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" + +#if defined (LTDC) && defined (DSI) + #include "stm32l4xx_hal_dsi.h" /** @addtogroup STM32L4xx_HAL_Driver @@ -55,7 +40,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -66,15 +51,15 @@ /** @addtogroup LTDCEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg); -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); /** * @} - */ - + */ + /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -84,18 +69,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD /** * @} - */ + */ /** * @} */ -#endif /* STM32L4R9xx || STM32L4S9xx */ - +#endif /* LTDC && DSI */ + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_LTDC_EX_H */ +#endif /* STM32L4xx_HAL_LTDC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc.c new file mode 100644 index 0000000000..0184656072 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc.c @@ -0,0 +1,3327 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_mmc.c + * @author MCD Application Team + * @brief MMC card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + MMC card Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_MMC_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with MMC and eMMC cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for MMC card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) On STM32L4Rx/STM32L4Sxx devices, no DMA configuration is need, an internal DMA for SDMMC Peripheral is used. + (##) On other devices, perform DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA() + and HAL_MMC_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority(); + DMA priority is superior to SDMMC's priority + (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization + + + *** MMC Card Initialization and configuration *** + ================================================ + [..] + To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes + SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Initialize the SDMMC peripheral interface with defaullt configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. + The MMC Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) on STM32L4Rx/STM32L4Sxx devices + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) on other devices + + In initialization mode and according to the MMC Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). + This phase allows the card initialization and identification + and check the MMC Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with MMC standard. + + This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer + frequency by adjusting the "ClockDiv" field. + In transfer mode and according to the MMC Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch. + + (#) Select the corresponding MMC Card according to the address read with the step 2. + + (#) Configure the MMC Card in wide bus mode: 4-bits data. + + *** MMC Card Read operation *** + ============================== + [..] + (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. + + *** MMC Card Write operation *** + =============================== + [..] + (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** MMC card CID register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. + Some of the CID parameters are useful for card initialization and identification. + + *** MMC HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in MMC HAL driver. + + (+) __HAL_MMC_ENABLE : Enable the MMC device + (+) __HAL_MMC_DISABLE : Disable the MMC device + (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt + (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt + (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not + (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags + + [..] + (@) You can refer to the MMC HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init + and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit + or @ref HAL_MMC_Init function. + + When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#ifdef HAL_MMC_MODULE_ENABLED + +#if defined(SDMMC1) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup MMC MMC + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup MMC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAError(DMA_HandleTypeDef *hdma); +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +#else +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout); +#endif + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Functions MMC Exported Functions + * @{ + */ + +/** @defgroup MMC_Exported_Functions_Group1 MMC_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the MMC + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MMC according to the specified parameters in the + MMC_HandleTypeDef and create the associated handle. + * @param hmmc: Pointer to the MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge)); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + assert_param(IS_SDMMC_CLOCK_BYPASS(hmmc->Init.ClockBypass)); +#endif + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); + + if(hmmc->State == HAL_MMC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hmmc->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_MMC_STATE_RESET only */ + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback; + hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback; + hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback; + hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback; +#endif + + if(hmmc->MspInitCallback == NULL) + { + hmmc->MspInitCallback = HAL_MMC_MspInit; + } + + /* Init the low level hardware */ + hmmc->MspInitCallback(hmmc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_MMC_MspInit(hmmc); +#endif + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize the Card parameters */ + if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Initialize the error code */ + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + /* Initialize the MMC state */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the MMC Card. + * @param hmmc: Pointer to MMC handle + * @note This function initializes the MMC card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + MMC_InitTypeDef Init; + HAL_StatusTypeDef status; + + /* Default SDMMC peripheral configuration for MMC card initialization */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; +#endif + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + + /* Initialize SDMMC peripheral interface with default configuration */ + status = SDMMC_Init(hmmc->Instance, Init); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Disable SDMMC Clock */ + __HAL_MMC_DISABLE(hmmc); +#endif + + /* Set Power State to ON */ + status = SDMMC_PowerState_ON(hmmc->Instance); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Enable MMC Clock */ + __HAL_MMC_ENABLE(hmmc); +#endif + + /* Identify card operating voltage */ + errorstate = MMC_PowerON(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = MMC_InitCard(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the MMC card. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set MMC power state to off */ + MMC_PowerOFF(hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + if(hmmc->MspDeInitCallback == NULL) + { + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + } + + /* DeInit the low level hardware */ + hmmc->MspDeInitCallback(hmmc); +#else + /* De-Initialize the MSP layer */ + HAL_MMC_MspDeInit(hmmc); +#endif + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to MMC card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of MMC blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_ENABLE; +#else + config.DPSM = SDMMC_DPSM_DISABLE; +#endif + (void)SDMMC_ConfigData(hmmc->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); +#endif + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); +#endif + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Empty FIFO if there is still any data */ + while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } +#endif + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of MMC blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); +#endif + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); +#endif + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); +#endif + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_ENABLE; +#else + config.DPSM = SDMMC_DPSM_DISABLE; +#endif + (void)SDMMC_ConfigData(hmmc->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); +#endif + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); +#endif + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); +#endif + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + /* Set the DMA transfer complete callback */ + hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt; + + /* Set the DMA error callback */ + hmmc->hdmarx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmarx->XferAbortCallback = NULL; + +#else + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; +#endif + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode = errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + hmmc->Instance->IDMABASE0 = (uint32_t) pData ; + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; +#else + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode = HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Enable MMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); +#endif + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + hmmc->ErrorCode = errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + } +#endif + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Enable MMC Error interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + + /* Set the DMA transfer complete callback */ + hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; + + /* Set the DMA error callback */ + hmmc->hdmatx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmatx->XferAbortCallback = NULL; +#else + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; +#endif + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + + hmmc->Instance->IDMABASE0 = (uint32_t) pData ; + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; +#endif + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Enable SDMMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } +#else + return HAL_OK; +#endif + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given MMC card. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if(end_add < start_add) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(end_add > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + start_add *= 512U; + end_add *= 512U; + } + + /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles MMC card interrupt request. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t context = hmmc->Context; + + /* Check for SDMMC interrupt flags */ + if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Read_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); + + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + hmmc->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); +#else + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); +#endif + + if((context & MMC_CONTEXT_DMA) != 0U) + { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hmmc->Instance->DLEN = 0; + hmmc->Instance->DCTRL = 0; + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ; + + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif + } +#else + if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + hmmc->State = HAL_MMC_STATE_READY; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } +#endif + } + else if((context & MMC_CONTEXT_IT) != 0U) + { + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } + } + else + { + /* Nothing to do */ + } + } + + else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Write_IT(hmmc); + } + + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + { + /* Set Error code */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP; +#endif + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT); +#endif + + if((context & MMC_CONTEXT_IT) != 0U) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else if((context & MMC_CONTEXT_DMA) != 0U) + { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + /* Disable Internal DMA */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } +#else + /* Abort the MMC DMA Streams */ + if(hmmc->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + MMC_DMATxAbort(hmmc->hdmatx); + } + } + else if(hmmc->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + MMC_DMARxAbort(hmmc->hdmarx); + } + } + else + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } +#endif + } + else + { + /* Nothing to do */ + } + } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC); + if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) + { + /* Current buffer is buffer0, Transfer complete for buffer1 */ + if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->Write_DMADblBuf1CpltCallback(hmmc); +#else + HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(hmmc); +#endif + } + else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */ + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->Read_DMADblBuf1CpltCallback(hmmc); +#else + HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(hmmc); +#endif + } + } + else /* MMC_DMA_BUFFER1 */ + { + /* Current buffer is buffer1, Transfer complete for buffer0 */ + if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->Write_DMADblBuf0CpltCallback(hmmc); +#else + HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(hmmc); +#endif + } + else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */ + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->Read_DMADblBuf0CpltCallback(hmmc); +#else + HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(hmmc); +#endif + } + } + } +#endif + + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the MMC state + * @param hmmc: Pointer to mmc handle + * @retval HAL state + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +{ + return hmmc->State; +} + +/** +* @brief Return the MMC error code +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. +* @retval MMC Error Code +*/ +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +{ + return hmmc->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief MMC error callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC Abort callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_AbortCallback can be implemented in the user file + */ +} + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User MMC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Rx Double buffer 0 Callback ID + * @arg @ref HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Rx Double buffer 1 Callback ID + * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID + * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmmc); + + if(hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = pCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = pCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = pCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = pCallback; + break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Write_DMADblBuf1CpltCallback = pCallback; + break; +#endif + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmmc); + return status; +} + +/** + * @brief Unregister a User MMC Callback + * MMC Callback is redirected to the weak (surcharged) predefined callback + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Rx Double buffer 0 Callback ID + * @arg @ref HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Rx Double buffer 1 Callback ID + * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID MMC DMA Tx Double buffer 0 Callback ID + * @arg @ref HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID MMC DMA Tx Double buffer 1 Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hmmc); + + if(hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback; + break; +#endif + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmmc); + return status; +} +#endif + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the MMC card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hmmc: Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hmmc: Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) +{ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t block_nbr = 0; +#endif + + pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(MMC_ReadExtCSD(hmmc, &block_nbr, 0x0FFFFFFFU) != HAL_OK) + { + return HAL_ERROR; + } + + if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + { +#endif + pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); + + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockSize = 512U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + } + else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = block_nbr; + hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; + hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } +#endif + + pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the MMC card info. + * @param hmmc: Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * will contain the MMC card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); + pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hmmc: Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) +{ + __IO uint32_t count = 0U; + SDMMC_InitTypeDef Init; + uint32_t errorstate; + uint32_t response = 0U, busy = 0U; + + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); + + /* Chnage Satte */ + hmmc->State = HAL_MMC_STATE_BUSY; + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Update Clock for Bus mode update */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = WideMode; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + /* Initialize SDMMC*/ + (void)SDMMC_Init(hmmc->Instance, Init); +#endif + + if(WideMode == SDMMC_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else if(WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else if(WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* WideMode is not a valid argument*/ + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + while(busy == 0U) + { + if(count == SDMMC_MAX_TRIAL) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + count++; + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + busy = (((response >> 7U) == 1U) ? 0U : 1U); + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_DATATIMEOUT; + while((response & 0x00000100U) == 0U) + { + if(count == 0U) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + count--; + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + } + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hmmc->Init.ClockEdge; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + Init.ClockBypass = hmmc->Init.ClockBypass; +#endif + Init.ClockPowerSave = hmmc->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; + Init.ClockDiv = hmmc->Init.ClockDiv; + (void)SDMMC_Init(hmmc->Instance, Init); + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Gets the current mmc card data state. + * @param hmmc: pointer to MMC handle + * @retval Card state + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0U; + + errorstate = MMC_SendStatus(hmmc, &resp1); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_MMC_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the MMC. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } + } + } +#else + /* If IDMA Context, disable Internal DMA */ + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; +#endif + + hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the MMC (IT mode). + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* If IDMA Context, disable Internal DMA */ + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; +#endif + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + hmmc->hdmatx = NULL; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + hmmc->hdmarx = NULL; + } + } + } + + /* No transfer ongoing on both DMA channels*/ + if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL)) + { +#endif + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->State = HAL_MMC_STATE_READY; + + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + } +#endif + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup MMC_Private_Functions + * @{ + */ + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) +/** + * @brief DMA MMC transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DATAEND)); +} + +/** + * @brief DMA MMC receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate; + + /* Send stop command in multiblock write */ + if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif +} + +/** + * @brief DMA MMC communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAError(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; + + RxErrorCode = hmmc->hdmarx->ErrorCode; + TxErrorCode = hmmc->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + } + + hmmc->State= HAL_MMC_STATE_READY; + } + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + +/** + * @brief DMA MMC Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmarx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + } +} + +/** + * @brief DMA MMC Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmatx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + } +} +#endif + +/** + * @brief Initializes the mmc card. + * @param hmmc: Pointer to MMC handle + * @retval MMC Card error state + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t mmc_rca = 1U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MMC_InitTypeDef Init; +#endif + + /* Check the power State */ + if(SDMMC_GetPowerState(hmmc->Instance) == 0U) + { + /* Power off */ + return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + } + + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* MMC Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get the MMC card RCA */ + hmmc->MmcCard.RelCardAdd = mmc_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Get the Card Class */ + hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + /* Get CSD parameters */ + if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Configure SDMMC peripheral interface */ + (void)SDMMC_Init(hmmc->Instance, hmmc->Init); +#else + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get CSD parameters */ + if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hmmc->Init.ClockEdge; + Init.ClockPowerSave = hmmc->Init.ClockPowerSave; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; + Init.ClockDiv = hmmc->Init.ClockDiv; + (void)SDMMC_Init(hmmc->Instance, Init); +#endif + + /* All cards are initialized */ + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores MMC information that will be needed in future + * in the MMC handle. + * @param hmmc: Pointer to MMC handle + * @retval error state + */ +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + while(validvoltage == 0U) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_MMC_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + + /* When power routine is finished and command returns valid voltage */ + if (((response & (0xFF000000U)) >> 24) == 0xC0U) + { + hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD; + } + else + { + hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD; + } + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Turns the SDMMC output signals off. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +{ + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hmmc->Instance); +} + +/** + * @brief Returns the current card's status. + * @param hmmc: Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card + * status (Card Status register) + * @retval error state + */ +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if(pCardStatus == NULL) + { + return HAL_MMC_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get MMC card status */ + *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + return HAL_MMC_ERROR_NONE; +} + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Reads extended CSD register to get the sectors number of the device + * @param hmmc: Pointer to MMC handle + * @param pBlockNbr: Pointer to the read buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t i = 0; + uint32_t tmp_data; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 0; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + tmp_data = SDMMC_ReadFIFO(hmmc->Instance); + if ((i == 48U) && (count == 5U)) + { + *pBlockNbr = tmp_data; + } + } + i += 8U; + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} +#endif + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hmmc->pRxBuffPtr; + dataremaining = hmmc->RxXferSize; + + if (dataremaining > 0U) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } + + hmmc->pRxBuffPtr = tmp; + hmmc->RxXferSize = dataremaining; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hmmc->pTxBuffPtr; + dataremaining = hmmc->TxXferSize; + + if (dataremaining > 0U) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + + hmmc->pTxBuffPtr = tmp; + hmmc->TxXferSize = dataremaining; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MMC_MODULE_ENABLED */ + +#endif /* SDMMC1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc.h new file mode 100644 index 0000000000..4b09f357a0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc.h @@ -0,0 +1,824 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_mmc.h + * @author MCD Application Team + * @brief Header file of MMC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_MMC_H +#define STM32L4xx_HAL_MMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_ll_sdmmc.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#if defined(SDMMC1) + +/** @addtogroup MMC + * @brief MMC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_Types MMC Exported Types + * @{ + */ + +/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */ + HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ +}HAL_MMC_StateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_MMC_CardStateTypeDef; + +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition + * @{ + */ +#define MMC_InitTypeDef SDMMC_InitTypeDef +#define MMC_TypeDef SDMMC_TypeDef + +/** + * @brief MMC Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_MMC_CardInfoTypeDef; + +/** + * @brief MMC handle Structure definition + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +typedef struct __MMC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +{ + MMC_TypeDef *Instance; /*!< MMC registers base address */ + + MMC_InitTypeDef Init; /*!< MMC required parameters */ + + HAL_LockTypeDef Lock; /*!< MMC locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + + __IO uint32_t Context; /*!< MMC transfer context */ + + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + + uint32_t CSD[4U]; /*!< MMC card specific data table */ + + uint32_t CID[4U]; /*!< MMC card identification number table */ + + uint32_t Ext_CSD[128]; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); +#endif + + void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); +#endif +}MMC_HandleTypeDef; + + +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +}HAL_MMC_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_MMC_CardCIDTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ + HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ + HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ + HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */ + HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */ + HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */ + HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */ +#endif + + HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ + HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ +}HAL_MMC_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition + * @{ + */ +typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); +/** + * @} + */ +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Constants Exported Constants + * @{ + */ + +#define MMC_BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ + +/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition + * @{ + */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration + * @{ + */ +#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode + * @{ + */ +/** + * @brief + */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */ +#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */ +#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */ +#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards + * @{ + */ +#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */ +#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_macros MMC Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset MMC handle state. + * @param __HANDLE__ : MMC handle. + * @retval None + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) +#endif + +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) +/** + * @brief Enable the MMC device. + * @retval None + */ +#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the MMC device. + * @retval None + */ +#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) +#endif + +/** + * @brief Enable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified MMC flag is set or not. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval The new state of MMC FLAG (SET or RESET). + */ +#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the MMC's pending flags. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval None + */ +#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified MMC interrupt has occurred or not. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of MMC IT (SET or RESET). + */ +#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the MMC's interrupt pending bits. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include MMC HAL Extension module */ +#include "stm32l4xx_hal_mmc_ex.h" +#endif + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMC_Exported_Functions + * @{ + */ + +/** @addtogroup MMC_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); + +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); + +/* Callback in non blocking modes (DMA) */ +void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/* MMC callback registering/unregistering */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); +#endif +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions + * @{ + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MMC_Private_Types MMC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MMC_Private_Defines MMC Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Variables MMC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Constants MMC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MMC_Private_Macros MMC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDMMC1 */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32L4xx_HAL_MMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc_ex.c new file mode 100644 index 0000000000..a9a4de4450 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc_ex.c @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_mmc_ex.c + * @author MCD Application Team + * @brief MMC card Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The MMC Extension HAL driver can be used as follows: + (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function. + + (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup MMCEx MMCEx + * @brief MMC Extended HAL module driver + * @{ + */ + +#ifdef HAL_MMC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMCEx_Exported_Types MMCEx Exported Types + * @{ + */ + +/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure + * @brief Multibuffer functions + * +@verbatim + ============================================================================== + ##### Multibuffer functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure the multibuffer mode and start read and write + multibuffer mode for MMC HAL driver. + +@endverbatim + * @{ + */ + +/** + * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. + * @param hmmc: MMC handle + * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data + * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data + * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize) +{ + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ; + hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ; + hmmc->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function. + * @param hmmc: MMC handle + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + DmaBase0_reg = hmmc->Instance->IDMABASE0; + DmaBase1_reg = hmmc->Instance->IDMABASE1; + if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) + { + hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + + /* Read Blocks in DMA mode */ + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + +} + +/** + * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function. + * @param hmmc: MMC handle + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t add = BlockAdd; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + DmaBase0_reg = hmmc->Instance->IDMABASE0; + DmaBase1_reg = hmmc->Instance->IDMABASE1; + if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) + { + hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + + /* Write Blocks in DMA mode */ + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Change the DMA Buffer0 or Buffer1 address on the fly. + * @param hmmc: pointer to a MMC_HandleTypeDef structure. + * @param Buffer: the buffer to be changed, This parameter can be one of + * the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1 + * @param pDataBuffer: The new address + * @note The BUFFER0 address can be changed only when the current transfer use + * BUFFER1 and the BUFFER1 address can be changed only when the current + * transfer use BUFFER0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +{ + if(Buffer == MMC_DMA_BUFFER0) + { + /* change the buffer0 address */ + hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer; + } + else + { + /* change the memory1 address */ + hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer; + } + + return HAL_OK; +} + +/** + * @brief Read DMA Buffer 0 Transfer completed callbacks + * @param hmmc: MMC handle + * @retval None + */ +__weak void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Read DMA Buffer 1 Transfer completed callbacks + * @param hmmc: MMC handle + * @retval None + */ +__weak void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Write DMA Buffer 0 Transfer completed callbacks + * @param hmmc: MMC handle + * @retval None + */ +__weak void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Write DMA Buffer 1 Transfer completed callbacks + * @param hmmc: MMC handle + * @retval None + */ +__weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MMC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc_ex.h new file mode 100644 index 0000000000..f2edfca80e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_mmc_ex.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_mmc_ex.h + * @author MCD Application Team + * @brief Header file of SD HAL extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_MMC_EX_H +#define STM32L4xx_HAL_MMC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup MMCEx + * @brief SD HAL extended module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @addtogroup MMCEx_Exported_Types + * @{ + */ + +/** @addtogroup MMCEx_Exported_Types_Group1 + * @{ + */ +typedef enum +{ + MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */ + MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */ + +}HAL_MMCEx_DMABuffer_MemoryTypeDef; + + +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions + * @{ + */ + +/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions + * @{ + */ +HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); + +void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32L4xx_HAL_MMCEx_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c index d66dda6cef..9e41510413 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c @@ -3,89 +3,74 @@ * @file stm32l4xx_hal_nand.c * @author MCD Application Team * @brief NAND HAL module driver. - * This file provides a generic firmware to drive NAND memories mounted + * This file provides a generic firmware to drive NAND memories mounted * as external device. - * + * @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control NAND flash memories. It uses the FMC layer functions to interface + This driver is a generic layered driver which contains a set of APIs used to + control NAND flash memories. It uses the FMC layer functions to interface with NAND devices. This driver is used as follows: - - (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() + + (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() with control and timing parameters for both common and attribute spaces. - + (+) Read NAND flash memory maker and device IDs using the function - HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef - structure declared by the function caller. - + HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef + structure declared by the function caller. + (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() - to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef + HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), + HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), + HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), + HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() + to read/write page(s)/spare area(s). These functions use specific device + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef structure. The read/write address information is contained by the Nand_Address_Typedef structure passed as parameter. - + (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). - + (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). - The erase block address information is contained in the Nand_Address_Typedef + The erase block address information is contained in the Nand_Address_Typedef structure passed as parameter. - + (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). - + (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction - feature or the function HAL_NAND_GetECC() to get the ECC correction code. - + feature or the function HAL_NAND_GetECC() to get the ECC correction code. + (+) You can monitor the NAND device HAL state by calling the function - HAL_NAND_GetState() + HAL_NAND_GetState() [..] (@) This driver is a set of generic APIs which handle standard NAND flash operations. - If a NAND flash device contains different operations and/or implementations, + If a NAND flash device contains different operations and/or implementations, it should be implemented separately. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK3) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -99,61 +84,37 @@ */ /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup NAND_Private_Constants NAND Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup NAND_Private_Macros NAND Private Macros - * @{ - */ - -/** - * @} - */ - +/* Private Constants ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup NAND_Private_Functions NAND Private Functions - * @{ - */ -static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address); -/** - * @} - */ - /* Exported functions ---------------------------------------------------------*/ /** @defgroup NAND_Exported_Functions NAND Exported Functions * @{ */ - -/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### NAND Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the NAND memory - + @endverbatim * @{ */ - + /** - * @brief Perform NAND memory Initialization sequence. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Perform NAND memory Initialization sequence + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ComSpace_Timing: pointer to Common space timing structure - * @param AttSpace_Timing: pointer to Attribute space timing structure + * @param ComSpace_Timing pointer to Common space timing structure + * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) @@ -168,23 +129,22 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT { /* Allocate lock resource and initialize it */ hnand->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); - } + } /* Initialize NAND control Interface */ FMC_NAND_Init(hnand->Instance, &(hnand->Init)); - - /* Initialize NAND common space timing Interface */ + + /* Initialize NAND common space timing Interface */ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); - - /* Initialize NAND attribute space timing Interface */ + + /* Initialize NAND attribute space timing Interface */ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); - + /* Enable the NAND device */ - __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); - + __FMC_NAND_ENABLE(hnand->Instance); + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -192,12 +152,12 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT } /** - * @brief Perform NAND memory De-Initialization sequence. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Perform NAND memory De-Initialization sequence + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); @@ -215,8 +175,8 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) } /** - * @brief Initialize the NAND MSP. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Initialize the NAND MSP + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -227,12 +187,12 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NAND_MspInit could be implemented in the user file - */ + */ } /** - * @brief DeInitialize the NAND MSP. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief DeInitialize the NAND MSP + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -243,13 +203,13 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NAND_MspDeInit could be implemented in the user file - */ + */ } /** * @brief This function handles NAND device interrupt request. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -260,11 +220,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* NAND interrupt callback*/ HAL_NAND_ITCallback(hnand); - + /* Clear NAND interrupt Rising edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE); + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); } - + /* Check NAND interrupt Level flag */ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) { @@ -272,7 +232,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) HAL_NAND_ITCallback(hnand); /* Clear NAND interrupt Level pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL); + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); } /* Check NAND interrupt Falling edge flag */ @@ -280,25 +240,26 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* NAND interrupt callback*/ HAL_NAND_ITCallback(hnand); - + /* Clear NAND interrupt Falling edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE); + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); } - + /* Check NAND interrupt FIFO empty flag */ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) { /* NAND interrupt callback*/ HAL_NAND_ITCallback(hnand); - + /* Clear NAND interrupt FIFO empty pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT); - } + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); + } + } /** - * @brief NAND interrupt feature callback. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief NAND interrupt feature callback + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -311,476 +272,81 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) the HAL_NAND_ITCallback could be implemented in the user file */ } - + /** * @} */ - -/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions + +/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### NAND Input and Output functions ##### ============================================================================== - [..] - This section provides functions allowing to use and control the NAND + [..] + This section provides functions allowing to use and control the NAND memory - + @endverbatim * @{ */ /** - * @brief Read the NAND memory electronic signature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Read the NAND memory electronic signature + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pNAND_ID: NAND ID structure + * @param pNAND_ID NAND ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { __IO uint32_t data = 0; - uint32_t deviceaddress = 0; + __IO uint32_t data1 = 0; + uint32_t deviceAddress = 0; - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - - /* Read the electronic signature from NAND flash */ - data = *(__IO uint32_t *)deviceaddress; - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief NAND memory reset. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) -{ - uint32_t deviceaddress = 0; - /* Process Locked */ __HAL_LOCK(hnand); - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; - - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; - -} - -/** - * @brief Read Page(s) from NAND memory block. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to destination read buffer - * @param NumPageToRead: number of pages to read from block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - /* Identify the device address */ - deviceaddress = NAND_DEVICE; + deviceAddress = NAND_DEVICE; - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Page(s) read loop */ - while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* update the buffer size */ - size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; - } - - /* Increment read pages number */ - numpagesread++; - - /* Decrement pages to read */ - NumPageToRead--; - - /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; - -} - -/** - * @brief Write Page(s) to NAND memory block. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumPageToWrite: number of pages to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) -{ - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Page(s) write loop */ - while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* update the buffer size */ - size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numpageswritten++; - - /* Decrement pages to write */ - NumPageToWrite--; - - /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Read Spare area(s) from NAND memory. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaToRead: Number of spare area to read - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) -{ - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read); + hnand->State = HAL_NAND_STATE_BUSY; - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - - /* Get Data into Buffer */ - for ( ;index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; - } - - /* Increment read spare areas number */ - num_spare_area_read++; - - /* Decrement spare areas to read */ - NumSpareAreaToRead--; - - /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief Write Spare area(s) to NAND memory. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaTowrite: number of spare areas to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) -{ - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; - - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + /* Read the electronic signature from NAND flash */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) { - return HAL_BUSY; + data = *(__IO uint32_t *)deviceAddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); } - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; - - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { - /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); + else + { + data = *(__IO uint32_t *)deviceAddress; + data1 = *((__IO uint32_t *)deviceAddress + 4); - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Increment written spare areas number */ - num_spare_area_written++; - - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; - - /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); } /* Update the NAND controller state */ @@ -788,117 +354,1275 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* Process unlocked */ __HAL_UNLOCK(hnand); - - return HAL_OK; + + return HAL_OK; } /** - * @brief NAND memory Block erase. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief NAND memory reset + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceaddress = 0; - uint32_t tickstart = 0; - + uint32_t deviceAddress = 0; + /* Process Locked */ __HAL_LOCK(hnand); - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; - + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - + /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; + __HAL_UNLOCK(hnand); + + return HAL_OK; + } /** - * @brief NAND memory read status. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Configure the device: Enter the physical parameters of the device + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @retval NAND status + * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure + * @retval HAL status */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) { - uint32_t data = 0; - uint32_t deviceaddress = 0; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); + hnand->Config.PageSize = pDeviceConfig->PageSize; + hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; + hnand->Config.BlockSize = pDeviceConfig->BlockSize; + hnand->Config.BlockNbr = pDeviceConfig->BlockNbr; + hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; + hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr; + hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; - /* Identify the device address */ - deviceaddress = NAND_DEVICE; + return HAL_OK; +} - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)deviceaddress; - /* Return the status */ - if((data & NAND_ERROR) == NAND_ERROR) +/** + * @brief Read Page(s) from NAND memory block (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer + * @param NumPageToRead number of pages to read from block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) { - return NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) - { - return NAND_READY; + return HAL_BUSY; } - return NAND_BUSY; + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + + /* Get Data into Buffer */ + for(; index < size; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; + } + + /* Increment read pages number */ + numPagesRead++; + + /* Decrement pages to read */ + NumPageToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; } /** - * @brief Increment the NAND memory address. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Read Page(s) from NAND memory block (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned + * @param NumPageToRead number of pages to read from block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + { + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; + } + + /* Increment read pages number */ + numPagesRead++; + + /* Decrement pages to read */ + NumPageToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Page(s) to NAND memory block (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumPageToWrite number of pages to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for (; index < size; index++) + { + *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numPagesWritten++; + + /* Decrement pages to write */ + NumPageToWrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Page(s) to NAND memory block (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned + * @param NumPageToWrite number of pages to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numPagesWritten++; + + /* Decrement pages to write */ + NumPageToWrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Read Spare area(s) from NAND memory (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaToRead Number of spare area to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) read loop */ + while ((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; + } + + /* Increment read spare areas number */ + numSpareAreaRead++; + + /* Decrement spare areas to read */ + NumSpareAreaToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Read Spare area(s) from NAND memory (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaToRead Number of spare area to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0U; + uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); + + /* Spare area(s) read loop */ + while ((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + __DSB(); + } + + /* Get Data into Buffer */ + for ( ;index < size; index++) + { + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress; + } + + /* Increment read spare areas number */ + numSpareAreaRead++; + + /* Decrement spare areas to read */ + NumSpareAreaToRead--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaTowrite number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the FMC_NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Page address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) write loop */ + while ((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numSpareAreaWritten++; + + /* Decrement spare areas to write */ + NumSpareAreaTowrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaTowrite number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + deviceAddress = NAND_DEVICE; + + /* Update the FMC_NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandAddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); + + /* Spare area(s) write loop */ + while ((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535) + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + __DSB(); + } + } + + /* Write data to memory */ + for (; index < size; index++) + { + *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numSpareAreaWritten++; + + /* Decrement spare areas to write */ + NumSpareAreaTowrite--; + + /* Increment the NAND address */ + nandAddress = (uint32_t)(nandAddress + 1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief NAND memory Block erase + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +{ + uint32_t DeviceAddress = 0; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + DeviceAddress = NAND_DEVICE; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; + __DSB(); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; + __DSB(); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Increment the NAND memory address + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure * @retval The new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address @@ -906,56 +1630,56 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; - + /* Increment page address */ pAddress->Page++; /* Check NAND address is valid */ - if(pAddress->Page == hnand->Info.BlockSize) + if (pAddress->Page == hnand->Config.BlockSize) { pAddress->Page = 0; pAddress->Block++; - - if(pAddress->Block == hnand->Info.ZoneSize) + + if (pAddress->Block == hnand->Config.PlaneSize) { pAddress->Block = 0; - pAddress->Zone++; + pAddress->Plane++; - if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) + if (pAddress->Plane == (hnand->Config.PlaneNbr)) { status = NAND_INVALID_ADDRESS; } } - } - + } + return (status); } /** * @} */ -/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions +/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### NAND Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the NAND interface. @endverbatim * @{ - */ + */ + - /** * @brief Enable dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ @@ -966,23 +1690,23 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) /* Update the NAND state */ hnand->State = HAL_NAND_STATE_BUSY; - + /* Enable ECC feature */ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); - + /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; + + return HAL_OK; } /** - * @brief Disable dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Disable dynamically NAND ECC feature + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) + */ +HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) @@ -992,69 +1716,69 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) /* Update the NAND state */ hnand->State = HAL_NAND_STATE_BUSY; - + /* Disable ECC feature */ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); - + /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; + + return HAL_OK; } /** - * @brief Disable dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Get NAND ECC value + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ECCval: pointer to ECC value - * @param Timeout: maximum timeout to wait + * @param ECCval pointer to ECC value + * @param Timeout maximum timeout to wait * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - + /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - + hnand->State = HAL_NAND_STATE_BUSY; + /* Get NAND ECC value */ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); - + /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - return status; + return status; } - + /** * @} */ - - -/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + + +/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### NAND State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the NAND controller + This subsection permits to get in run-time the status of the NAND controller and the data flow. @endverbatim * @{ */ - + /** - * @brief Return the NAND handle state. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief Return the NAND state + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL state */ @@ -1065,50 +1789,36 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) } /** - * @} - */ - -/** - * @} - */ - -/** @addtogroup NAND_Private_Functions - * @{ - */ - -/** - * @brief Increment the NAND memory address. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @brief NAND memory read status + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param Address: address to be incremented. - * @retval The new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address + * @retval NAND status */ -static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address) +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { - uint32_t status = NAND_VALID_ADDRESS; - - Address->Page++; + uint32_t data = 0; + uint32_t DeviceAddress = 0; - if(Address->Page == hnand->Info.BlockSize) + /* Identify the device address */ + DeviceAddress = NAND_DEVICE; + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + + /* Read status register data */ + data = *(__IO uint8_t *)DeviceAddress; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) { - Address->Page = 0; - Address->Block++; - - if(Address->Block == hnand->Info.ZoneSize) - { - Address->Block = 0; - Address->Zone++; + return NAND_ERROR; + } + else if ((data & NAND_READY) == NAND_READY) + { + return NAND_READY; + } - if(Address->Zone == hnand->Info.BlockNbr) - { - status = NAND_INVALID_ADDRESS; - } - } - } - - return (status); + return NAND_BUSY; } /** @@ -1119,14 +1829,16 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp * @} */ +/** + * @} + */ + #endif /* HAL_NAND_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK3 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h index 1292ae8727..6ddce86b23 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -41,9 +25,7 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK3) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -54,69 +36,6 @@ /** @addtogroup NAND * @{ - */ - -/** @addtogroup NAND_Private_Constants - * @{ - */ - -#define NAND_DEVICE FMC_BANK3 -#define NAND_WRITE_TIMEOUT ((uint32_t)1000) - -#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ - -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) - -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) - -/* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) -#define NAND_BUSY ((uint32_t)0x00000000) -#define NAND_ERROR ((uint32_t)0x00000001) -#define NAND_READY ((uint32_t)0x00000040) - -/** - * @} - */ - -/** @addtogroup NAND_Private_Macros - * @{ - */ - -/** - * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__: NAND handle. - * @retval NAND Raw address value - */ -#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize)))) - -/** - * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. - * @retval NAND address cycling value. - */ -#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ -#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ -#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ -#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ - -/** - * @} */ /* Exported typedef ----------------------------------------------------------*/ @@ -125,25 +44,24 @@ * @{ */ -/** +/** * @brief HAL NAND State structures definition */ typedef enum { - HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ - HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ - HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ - HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ + HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ + HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ + HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ + HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ }HAL_NAND_StateTypeDef; - -/** + +/** * @brief NAND Memory electronic signature Structure definition */ typedef struct { /*State = HAL_NAND_STATE_RESET) @@ -221,43 +149,55 @@ typedef struct /** @addtogroup NAND_Exported_Functions NAND Exported Functions * @{ */ - -/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); -void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); + +HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); + +void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); +void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /** * @} */ - -/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions + +/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions * @{ */ /* IO operation functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); + +HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); + +uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); /** * @} */ -/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions * @{ */ @@ -269,34 +209,108 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** * @} */ - -/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions + +/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions * @{ */ - /* NAND State functions *******************************************************/ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +/** + * @} + */ /** * @} - */ + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup NAND_Private_Constants NAND Private Constants + * @{ + */ +#define NAND_DEVICE FMC_BANK3 +#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) + +#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ +#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ + +#define NAND_CMD_AREA_A ((uint8_t)0x00U) +#define NAND_CMD_AREA_B ((uint8_t)0x01U) +#define NAND_CMD_AREA_C ((uint8_t)0x50U) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) + +#define NAND_CMD_WRITE0 ((uint8_t)0x80U) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) +#define NAND_CMD_ERASE0 ((uint8_t)0x60U) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) +#define NAND_CMD_READID ((uint8_t)0x90U) +#define NAND_CMD_STATUS ((uint8_t)0x70U) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) +#define NAND_CMD_RESET ((uint8_t)0xFFU) + +/* NAND memory status */ +#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) +#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) +#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) +#define NAND_BUSY ((uint32_t)0x00000000U) +#define NAND_ERROR ((uint32_t)0x00000001U) +#define NAND_READY ((uint32_t)0x00000040U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup NAND_Private_Macros NAND Private Macros + * @{ + */ + +/** + * @brief NAND memory address computation. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. + * @retval NAND Raw address value + */ +#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + +#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) + +/** + * @brief NAND memory address cycling. + * @param __ADDRESS__ NAND memory address. + * @retval NAND address cycling value. + */ +#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ +#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ + +/** + * @brief NAND memory Columns cycling. + * @param __ADDRESS__ NAND memory address. + * @retval NAND Column address cycling value. + */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/** + * @} + */ + +#endif /* FMC_BANK3 */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c index 585ffaa0ef..9f5ce648b0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c @@ -3,89 +3,71 @@ * @file stm32l4xx_hal_nor.c * @author MCD Application Team * @brief NOR HAL module driver. - * This file provides a generic firmware to drive NOR memories mounted + * This file provides a generic firmware to drive NOR memories mounted * as external device. - * + * @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control NOR flash memories. It uses the FMC layer functions to interface + This driver is a generic layered driver which contains a set of APIs used to + control NOR flash memories. It uses the FMC layer functions to interface with NOR devices. This driver is used as follows: - - (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() + + (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() with control and timing parameters for both normal and extended mode. - + (+) Read NOR flash memory manufacturer code and device IDs using the function - HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef - structure declared by the function caller. - + HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef + structure declared by the function caller. + (+) Access NOR flash memory by read/write data unit operations using the functions HAL_NOR_Read(), HAL_NOR_Program(). - - (+) Perform NOR flash erase block/chip operations using the functions + + (+) Perform NOR flash erase block/chip operations using the functions HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). - + (+) Read the NOR flash CFI (common flash interface) IDs using the function HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef structure declared by the function caller. - + (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ - HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation - + HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation + (+) You can monitor the NOR device HAL state by calling the function - HAL_NOR_GetState() + HAL_NOR_GetState() [..] (@) This driver is a set of generic APIs which handle standard NOR flash operations. - If a NOR flash device contains different operations and/or implementations, + If a NOR flash device contains different operations and/or implementations, it should be implemented separately. *** NOR HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in NOR HAL driver. - + (+) NOR_WRITE : NOR memory write data to specified address @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -94,12 +76,14 @@ #ifdef HAL_NOR_MODULE_ENABLED /** @defgroup NOR NOR - * @brief NOR HAL module driver + * @brief NOR driver modules * @{ */ + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup NOR_Private_Constants NOR Private Constants + +/** @defgroup NOR_Private_Defines NOR Private Defines * @{ */ @@ -137,16 +121,7 @@ */ /* Private macro -------------------------------------------------------------*/ -/** @defgroup NOR_Private_Macros NOR Private Macros - * @{ - */ - -/** - * @} - */ - /* Private variables ---------------------------------------------------------*/ - /** @defgroup NOR_Private_Variables NOR Private Variables * @{ */ @@ -157,33 +132,33 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @} */ -/* Exported functions ---------------------------------------------------------*/ - +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup NOR_Exported_Functions NOR Exported Functions * @{ */ -/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### NOR Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the NOR memory - + @endverbatim * @{ */ - + /** - * @brief Perform the NOR memory Initialization sequence. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Perform the NOR memory Initialization sequence + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timing: pointer to NOR control timing structure - * @param ExtTiming: pointer to NOR extended mode timing structure + * @param Timing pointer to NOR control timing structure + * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -193,12 +168,11 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe { return HAL_ERROR; } - + if(hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ hnor->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_NOR_MspInit(hnor); } @@ -207,13 +181,13 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); /* Initialize NOR timing Interface */ - FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); + FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); + __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); /* Initialize NOR Memory Data Width*/ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) @@ -226,25 +200,25 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe } /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - + hnor->State = HAL_NOR_STATE_READY; + return HAL_OK; } /** - * @brief Perform NOR memory De-Initialization sequence. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Perform NOR memory De-Initialization sequence + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { /* De-Initialize the low level hardware (MSP) */ HAL_NOR_MspDeInit(hnor); - + /* Configure the NOR registers with their reset values */ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_RESET; @@ -256,7 +230,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) /** * @brief Initialize the NOR MSP. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -267,12 +241,12 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NOR_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitialize the NOR MSP. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -283,14 +257,14 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NOR_MspDeInit could be implemented in the user file - */ + */ } /** - * @brief NOR MSP Wait for Ready/Busy signal. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief NOR MSP Wait for Ready/Busy signal + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timeout: Maximum timeout value + * @param Timeout Maximum timeout value * @retval None */ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) @@ -301,47 +275,47 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) /* NOTE : This function should not be modified, when the callback is needed, the HAL_NOR_MspWait could be implemented in the user file - */ + */ } - + /** * @} */ -/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions +/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### NOR Input and Output functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to use and control the NOR memory - + @endverbatim * @{ */ - + /** - * @brief Read NOR flash IDs. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Read NOR flash IDs + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_ID : pointer to NOR ID structure + * @param pNOR_ID pointer to NOR ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -358,11 +332,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read ID command */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); @@ -373,35 +347,35 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - + __HAL_UNLOCK(hnor); + return HAL_OK; } /** * @brief Return the NOR memory to Read mode. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { - uint32_t deviceaddress = 0; - + uint32_t deviceaddress = 0; + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -418,40 +392,40 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - + __HAL_UNLOCK(hnor); + return HAL_OK; } /** - * @brief Read data from NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Read data from NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: pointer to Device address - * @param pData : pointer to read data + * @param pAddress pointer to Device address + * @param pData pointer to read data * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -468,49 +442,49 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); /* Read the data */ *pData = *(__IO uint32_t *)(uint32_t)pAddress; - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Program data to NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Program data to NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: Device address - * @param pData : pointer to the data to write + * @param pAddress Device address + * @param pData pointer to the data to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -527,11 +501,11 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send program data command */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); @@ -539,39 +513,38 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /* Write the data */ NOR_WRITE(pAddress, *pData); - + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Read a block of data from the FMC NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param uwAddress: NOR memory internal address to read from. - * @param pData: pointer to the buffer that receives the data read from the + * @brief Read a half-word buffer from the NOR memory. + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal address to read from. + * @param pData pointer to the buffer that receives the data read from the * NOR memory. - * @param uwBufferSize : number of Half word to read. + * @param uwBufferSize number of Half word to read. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -588,62 +561,57 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); - + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + /* Read buffer */ - while( uwBufferSize > 0) + while( uwBufferSize > 0) { *pData++ = *(__IO uint16_t *)uwAddress; uwAddress += 2; uwBufferSize--; - } - + } + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Write a half-word buffer to the FMC NOR memory. This function - * must be used only with S29GL128P NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param uwAddress: NOR memory internal address from which the data - * @note Some NOR memory need Address aligned to xx bytes (can be aligned to - * 64 bytes boundary for example). - * @param pData: pointer to source data buffer. - * @param uwBufferSize: number of Half words to write. - * @note The maximum buffer size allowed is NOR memory dependent - * (can be 64 Bytes max for example). + * @brief Writes a half-word buffer to the NOR memory. This function must be used + only with S29GL128P NOR memory. + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal start write address + * @param pData pointer to source data buffer. + * @param uwBufferSize Size of the buffer to write * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { uint16_t * p_currentaddress = (uint16_t *)NULL; uint16_t * p_endaddress = (uint16_t *)NULL; uint32_t lastloadedaddress = 0, deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -660,11 +628,11 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Initialize variables */ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); p_endaddress = p_currentaddress + (uwBufferSize-1); @@ -672,41 +640,41 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Issue unlock command sequence */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); /* Write Buffer Load Command */ - NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); + NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); /* Load Data into NOR Buffer */ while(p_currentaddress <= p_endaddress) { /* Store last loaded address & data value (for polling) */ lastloadedaddress = (uint32_t)p_currentaddress; - + NOR_WRITE(p_currentaddress, *pData++); - + p_currentaddress++; } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); - + NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; - + + return HAL_OK; + } /** - * @brief Erase the specified block of the NOR memory. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Erase the specified block of the NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param BlockAddress : Block to erase address - * @param Address: Device address + * @param BlockAddress Block to erase address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) @@ -715,13 +683,13 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -739,10 +707,10 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd { deviceaddress = NOR_MEMORY_ADRESS4; } - + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send block erase command sequence */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); @@ -753,37 +721,37 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - + return HAL_OK; - + } /** * @brief Erase the entire NOR chip. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address : Device address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { uint32_t deviceaddress = 0; - + /* Prevent unused argument(s) compilation warning */ UNUSED(Address); /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -801,47 +769,47 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { deviceaddress = NOR_MEMORY_ADRESS4; } - + /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - + hnor->State = HAL_NOR_STATE_BUSY; + /* Send NOR chip erase command sequence */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); - + /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Read NOR flash CFI IDs. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Read NOR flash CFI IDs + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_CFI : pointer to NOR CFI IDs structure + * @param pNOR_CFI pointer to NOR CFI IDs structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { uint32_t deviceaddress = 0; - + /* Process Locked */ __HAL_LOCK(hnor); - + /* Check the NOR controller state */ if(hnor->State == HAL_NOR_STATE_BUSY) { return HAL_BUSY; } - + /* Select the NOR device address */ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) { @@ -858,11 +826,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR else /* FMC_NORSRAM_BANK4 */ { deviceaddress = NOR_MEMORY_ADRESS4; - } - + } + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Send read CFI query command */ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); @@ -874,21 +842,21 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hnor); - + return HAL_OK; } /** * @} */ - -/** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions + +/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### NOR Control functions ##### ============================================================================== @@ -899,10 +867,10 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR @endverbatim * @{ */ - + /** * @brief Enable dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -912,20 +880,20 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) __HAL_LOCK(hnor); /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - + FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + __HAL_UNLOCK(hnor); + + return HAL_OK; } /** * @brief Disable dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -936,41 +904,41 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) /* Update the SRAM controller state */ hnor->State = HAL_NOR_STATE_BUSY; - + /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - + FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + /* Update the NOR controller state */ hnor->State = HAL_NOR_STATE_PROTECTED; - + /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + __HAL_UNLOCK(hnor); + + return HAL_OK; } /** * @} - */ - -/** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + */ + +/** @defgroup NOR_Exported_Functions_Group4 NOR State functions + * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### NOR State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the NOR controller + This subsection permits to get in run-time the status of the NOR controller and the data flow. @endverbatim * @{ */ - + /** - * @brief Return the NOR controller handle state. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @brief Return the NOR controller state + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval NOR controller state */ @@ -982,22 +950,24 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) /** * @brief Return the NOR operation status. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address: Device address - * @param Timeout: NOR programming Timeout - * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Address Device address + * @param Timeout NOR programming Timeout + * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) -{ +{ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmp_sr1 = 0, tmp_sr2 = 0; + uint16_t tmpSR1 = 0, tmpSR2 = 0; uint32_t tickstart = 0; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); - + + /* Get the NOR memory operation status -------------------------------------*/ + /* Get tick */ tickstart = HAL_GetTick(); while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) @@ -1007,37 +977,37 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { - status = HAL_NOR_STATUS_TIMEOUT; - } - } + status = HAL_NOR_STATUS_TIMEOUT; + } + } /* Read NOR status register (DQ6 and DQ5) */ - tmp_sr1 = *(__IO uint16_t *)Address; - tmp_sr2 = *(__IO uint16_t *)Address; + tmpSR1 = *(__IO uint16_t *)Address; + tmpSR2 = *(__IO uint16_t *)Address; - /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) { return HAL_NOR_STATUS_SUCCESS; } - - if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) + + if((tmpSR1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) { status = HAL_NOR_STATUS_ONGOING; } - - tmp_sr1 = *(__IO uint16_t *)Address; - tmp_sr2 = *(__IO uint16_t *)Address; - /* If DQ6 did not toggle between the two reads then return NOR_Success */ - if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + tmpSR1 = *(__IO uint16_t *)Address; + tmpSR2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) { return HAL_NOR_STATUS_SUCCESS; } - else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) { return HAL_NOR_STATUS_ERROR; - } + } } /* Return the operation status */ @@ -1051,17 +1021,17 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ + /** * @} */ + #endif /* HAL_NOR_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h index d302ee479d..4ff0a1e17c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_NOR_H @@ -41,9 +25,7 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -55,64 +37,6 @@ /** @addtogroup NOR * @{ - */ - -/** @addtogroup NOR_Private_Constants - * @{ - */ - -/* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) - -/* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x10) -#define CFI2_ADDRESS ((uint16_t)0x11) -#define CFI3_ADDRESS ((uint16_t)0x12) -#define CFI4_ADDRESS ((uint16_t)0x13) - -/* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) - -/* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 FMC_BANK1_1 -#define NOR_MEMORY_ADRESS2 FMC_BANK1_2 -#define NOR_MEMORY_ADRESS3 FMC_BANK1_3 -#define NOR_MEMORY_ADRESS4 FMC_BANK1_4 - -/** - * @} - */ - -/** @addtogroup NOR_Private_Macros - * @{ - */ - -/** - * @brief NOR memory address shifting. - * @param __NOR_ADDRESS: NOR base address - * @param __NOR_MEMORY_WIDTH_: NOR memory width - * @param __ADDRESS__: NOR memory address - * @retval NOR shifted address value - */ -#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ - ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) - -/** - * @brief NOR memory write data to specified address. - * @param __ADDRESS__: NOR memory address - * @param __DATA__: Data to write - * @retval None - */ -#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) - -/** - * @} */ /* Exported typedef ----------------------------------------------------------*/ @@ -120,16 +44,16 @@ * @{ */ -/** - * @brief HAL SRAM State structures definition - */ +/** + * @brief HAL SRAM State structures definition + */ typedef enum -{ - HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ +{ + HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ }HAL_NOR_StateTypeDef; /** @@ -137,11 +61,11 @@ typedef enum */ typedef enum { - HAL_NOR_STATUS_SUCCESS = 0, + HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT -}HAL_NOR_StatusTypeDef; +}HAL_NOR_StatusTypeDef; /** * @brief FMC NOR ID typedef @@ -154,10 +78,10 @@ typedef struct uint16_t Device_Code2; - uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. - These codes can be accessed by performing read operations with specific - control signals and addresses set.They can also be accessed by issuing - an Auto Select command. */ + uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. + These codes can be accessed by performing read operations with specific + control signals and addresses set.They can also be accessed by issuing + an Auto Select command. */ }NOR_IDTypeDef; /** @@ -165,20 +89,22 @@ typedef struct */ typedef struct { + /*!< Defines the information stored in the memory's Common flash interface + which contains a description of various electrical and timing parameters, + density information and functions supported by the memory */ + uint16_t CFI_1; uint16_t CFI_2; uint16_t CFI_3; - uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface - which contains a description of various electrical and timing parameters, - density information and functions supported by the memory. */ + uint16_t CFI_4; }NOR_CFITypeDef; -/** +/** * @brief NOR handle Structure definition - */ + */ typedef struct { FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ @@ -190,9 +116,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< NOR locking object */ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ - -}NOR_HandleTypeDef; - +}NOR_HandleTypeDef; /** * @} */ @@ -202,13 +126,11 @@ typedef struct /** @defgroup NOR_Exported_Macros NOR Exported Macros * @{ */ - -/** @brief Reset NOR handle state. - * @param __HANDLE__: NOR handle +/** @brief Reset NOR handle state + * @param __HANDLE__ specifies the NOR handle. * @retval None */ #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) - /** * @} */ @@ -218,7 +140,7 @@ typedef struct * @{ */ -/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -228,12 +150,11 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); - /** * @} */ -/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions +/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions * @{ */ @@ -249,34 +170,96 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); - /** * @} */ - -/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions + +/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions * @{ */ /* NOR Control functions *****************************************************/ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); - /** * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions + */ + +/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions * @{ */ /* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); +/** + * @} + */ /** * @} - */ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup NOR_Private_Constants NOR Private Constants + * @{ + */ +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000U) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x61U) +#define CFI2_ADDRESS ((uint16_t)0x62U) +#define CFI3_ADDRESS ((uint16_t)0x63U) +#define CFI4_ADDRESS ((uint16_t)0x64U) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFFU) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0U) +#define NOR_MEMORY_16B ((uint8_t)0x1U) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) +#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) +#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) +#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup NOR_Private_Macros NOR Private Macros + * @{ + */ +/** + * @brief NOR memory address shifting. + * @param __NOR_ADDRESS NOR base address + * @param __NOR_MEMORY_WIDTH_ NOR memory width + * @param __ADDRESS__ NOR memory address + * @retval NOR shifted address value + */ +#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) + +/** + * @brief NOR memory write data to specified address. + * @param __ADDRESS__ NOR memory address + * @param __DATA__ Data to write + * @retval None + */ +#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ + (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ + __DSB(); \ + } while(0) /** * @} @@ -284,15 +267,13 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} - */ + */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c index 3aa42edc21..14e9f796e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c @@ -3,8 +3,8 @@ * @file stm32l4xx_hal_opamp.c * @author MCD Application Team * @brief OPAMP HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the operational amplifier(s) peripheral: + * This file provides firmware functions to manage the following + * functionalities of the operational amplifier(s) peripheral: * + OPAMP configuration * + OPAMP calibration * Thanks to @@ -12,16 +12,16 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ================================================================================ ##### OPAMP Peripheral Features ##### ================================================================================ - + [..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2 - - (#) The OPAMP(s) provide(s) several exclusive running modes. - (++) 1 OPAMP: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx + + (#) The OPAMP(s) provide(s) several exclusive running modes. + (++) 1 OPAMP: STM32L412xx STM32L422xx STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx (++) 2 OPAMP: STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx (#) The OPAMP(s) provide(s) several exclusive running modes. @@ -35,47 +35,47 @@ (#) Each OPAMP(s) can be configured in normal and low power mode. - (#) The OPAMP(s) provide(s) calibration capabilities. + (#) The OPAMP(s) provide(s) calibration capabilities. (++) Calibration aims at correcting some offset for running mode. - (++) The OPAMP uses either factory calibration settings OR user defined + (++) The OPAMP uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). - (++) The user defined settings can be figured out using self calibration + (++) The user defined settings can be figured out using self calibration handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll (++) HAL_OPAMP_SelfCalibrate: (+++) Runs automatically the calibration. (+++) Enables the user trimming mode - (+++) Updates the init structure with trimming values with fresh calibration - results. - The user may store the calibration results for larger - (ex monitoring the trimming as a function of temperature + (+++) Updates the init structure with trimming values with fresh calibration + results. + The user may store the calibration results for larger + (ex monitoring the trimming as a function of temperature for instance) (+++) HAL_OPAMPEx_SelfCalibrateAll runs calibration of all OPAMPs in parallel to save search time. - - (#) Running mode: Standalone mode + + (#) Running mode: Standalone mode (++) Gain is set externally (gain depends on external loads). (++) Follower mode also possible externally by connecting the inverting input to the output. - + (#) Running mode: Follower mode (++) No Inverting Input is connected. - - (#) Running mode: Programmable Gain Amplifier (PGA) mode + + (#) Running mode: Programmable Gain Amplifier (PGA) mode (Resistor feedback output) (++) The OPAMP(s) output(s) can be internally connected to resistor feedback output. (++) OPAMP gain is either 2, 4, 8 or 16. - - (#) The OPAMPs inverting input can be selected according to the Reference Manual + + (#) The OPAMPs inverting input can be selected according to the Reference Manual "OPAMP function description" chapter. - - (#) The OPAMPs non inverting input can be selected according to the Reference Manual + + (#) The OPAMPs non inverting input can be selected according to the Reference Manual "OPAMP function description" chapter. - - + + ##### How to use this driver ##### ================================================================================ - [..] + [..] *** Power supply range *** ============================================ @@ -97,34 +97,51 @@ ============================================ [..] To run the OPAMP calibration self calibration: - (#) Start calibration using HAL_OPAMP_SelfCalibrate. + (#) Start calibration using HAL_OPAMP_SelfCalibrate. Store the calibration results. *** Running mode *** ============================================ - + [..] To use the OPAMP, perform the following steps: - + (#) Fill in the HAL_OPAMP_MspInit() to (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE() - (++) Configure the OPAMP input AND output in analog mode using + (++) Configure the OPAMP input AND output in analog mode using HAL_GPIO_Init() to map the OPAMP output to the GPIO pin. - + + (#) Registrate Callbacks + (++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+++) MspInitCallback : OPAMP MspInit. + (+++) MspDeInitCallback : OPAMP MspFeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+++) MspInitCallback : OPAMP MspInit. + (+++) MspDeInitCallback : OPAMP MspdeInit. + (+++) All Callbacks + (#) Configure the OPAMP using HAL_OPAMP_Init() function: (++) Select the mode (++) Select the inverting input - (++) Select the non-inverting input + (++) Select the non-inverting input (++) If PGA mode is enabled, Select if inverting input is connected. (++) Select either factory or user defined trimming mode. (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values (typically values set by HAL_OPAMP_SelfCalibrate function). - + (#) Enable the OPAMP using HAL_OPAMP_Start() function. - + (#) Disable the OPAMP using HAL_OPAMP_Stop() function. - + (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function. - Caution: On STM32L4, HAL OPAMP lock is software lock only (not + Caution: On STM32L4, HAL OPAMP lock is software lock only (not hardware lock as on some other STM32 devices) (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function. @@ -137,9 +154,9 @@ (#) Configure the OPAMP using HAL_OPAMP_Init() function: (++) As in configure case, select first the parameters you wish to modify. - - (#) Change from low power mode to normal power mode (& vice versa) requires - first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). + + (#) Change from low power mode to normal power mode (& vice versa) requires + first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode alone. @@ -147,7 +164,7 @@ ****************************************************************************** Table 1. OPAMPs inverting/non-inverting inputs for the STM32L4 devices: - +------------------------------------------------------------------------| + +------------------------------------------------------------------------| | | | OPAMP1 | OPAMP2 | |-----------------|---------|----------------------|---------------------| | Inverting Input | VM_SEL | | | @@ -162,11 +179,11 @@ +------------------------------------------------------------------------| (1): NA in follower mode. (2): Available on some package only (ex. BGA132). - - + + Table 2. OPAMPs outputs for the STM32L4 devices: - +------------------------------------------------------------------------- + +------------------------------------------------------------------------- | | | OPAMP1 | OPAMP2 | |-----------------|--------|-----------------------|---------------------| | Output | VOUT | PA3 | PB0 | @@ -178,36 +195,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -226,7 +227,7 @@ * @{ */ -/* CSR register reset value */ +/* CSR register reset value */ #define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000) #define OPAMP_CSR_RESET_BITS (OPAMP_CSR_OPAMPxEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE \ @@ -246,7 +247,7 @@ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -256,14 +257,14 @@ * @{ */ -/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== - + @endverbatim * @{ */ @@ -277,14 +278,21 @@ * @retval HAL status */ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - uint32_t updateotrlpotr = 0; + uint32_t updateotrlpotr; /* Check the OPAMP handle allocation and lock status */ /* Init not allowed if calibration is ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if(hopamp == NULL) + { + return HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) + { + return HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) { return HAL_ERROR; } @@ -292,29 +300,39 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + /* Set OPAMP parameters */ assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange)); assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); - + + if(hopamp->State == HAL_OPAMP_STATE_RESET) + { +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) + if(hopamp->MspInitCallback == NULL) + { + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + } +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + } + if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE) { assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput)); } - if ((hopamp->Init.Mode) == OPAMP_PGA_MODE) + if ((hopamp->Init.Mode) == OPAMP_PGA_MODE) { assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput)); } - + if ((hopamp->Init.Mode) == OPAMP_PGA_MODE) { assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain)); } - - assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); + + assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER) { if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) @@ -328,19 +346,23 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower)); } } - + if(hopamp->State == HAL_OPAMP_STATE_RESET) { /* Allocate lock resource and initialize it */ hopamp->Lock = HAL_UNLOCKED; } +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) + hopamp->MspInitCallback(hopamp); +#else /* Call MSP init function */ HAL_OPAMP_MspInit(hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ /* Set operating mode */ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON); - + if (hopamp->Init.Mode == OPAMP_PGA_MODE) { MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \ @@ -351,7 +373,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Init.NonInvertingInput | \ hopamp->Init.UserTrimming); } - + if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE) { /* In Follower mode InvertingInput is Not Applicable */ @@ -359,9 +381,9 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Init.PowerMode | \ hopamp->Init.Mode | \ hopamp->Init.NonInvertingInput | \ - hopamp->Init.UserTrimming); - } - + hopamp->Init.UserTrimming); + } + if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE) { MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \ @@ -370,8 +392,8 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) hopamp->Init.InvertingInput | \ hopamp->Init.NonInvertingInput | \ hopamp->Init.UserTrimming); - } - + } + if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { /* Set power mode and associated calibration parameters */ @@ -382,7 +404,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) /* transistors differential pair high (PMOS) and low (NMOS) for */ /* normal mode. */ updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \ - | (hopamp->Init.TrimmingValueN)); + | (hopamp->Init.TrimmingValueN)); MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); } else @@ -391,16 +413,16 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) /* transistors differential pair high (PMOS) and low (NMOS) for */ /* low power mode. */ updateotrlpotr = (((hopamp->Init.TrimmingValuePLowPower) << (OPAMP_INPUT_NONINVERTING)) \ - | (hopamp->Init.TrimmingValueNLowPower)); - MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); + | (hopamp->Init.TrimmingValueNLowPower)); + MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); } - } + } /* Configure the power supply range */ /* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */ /* bit OPAMP1_CSR_OPARANGE is used for both OPAMPs */ MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, hopamp->Init.PowerSupplyRange); - + /* Update the OPAMP state*/ if (hopamp->State == HAL_OPAMP_STATE_RESET) { @@ -422,10 +444,14 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp) HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the OPAMP handle allocation */ /* DeInit not allowed if calibration is ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) { status = HAL_ERROR; } @@ -435,25 +461,31 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp) assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); /* Set OPAMP_CSR register to reset value */ - /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */ - /* OPAMP shall be disabled first separately */ + /* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */ + /* OPAMP shall be disabled first separately */ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE); - + +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) + if(hopamp->MspDeInitCallback == NULL) + { + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + } + /* DeInit the low level hardware */ + hopamp->MspDeInitCallback(hopamp); +#else /* DeInit the low level hardware: GPIO, CLOCK and NVIC */ HAL_OPAMP_MspDeInit(hopamp); - +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ /* Update the OPAMP state*/ - hopamp->State = HAL_OPAMP_STATE_RESET; - + hopamp->State = HAL_OPAMP_STATE_RESET; + /* Process unlocked */ __HAL_UNLOCK(hopamp); } - return status; } - /** * @brief Initialize the OPAMP MSP. * @param hopamp: OPAMP handle @@ -489,13 +521,13 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp) */ -/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to manage the OPAMP start, stop and calibration actions. @@ -511,12 +543,16 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp) */ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) { status = HAL_ERROR; } @@ -524,21 +560,21 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + if(hopamp->State == HAL_OPAMP_STATE_READY) { /* Enable the selected opamp */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); - /* Update the OPAMP state*/ + /* Update the OPAMP state*/ /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */ - hopamp->State = HAL_OPAMP_STATE_BUSY; + hopamp->State = HAL_OPAMP_STATE_BUSY; } else { status = HAL_ERROR; } - + } return status; } @@ -549,14 +585,21 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp) * @retval HAL status */ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ /* Check if OPAMP calibration ongoing */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) { status = HAL_ERROR; } @@ -568,9 +611,9 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp) if(hopamp->State == HAL_OPAMP_STATE_BUSY) { /* Disable the selected opamp */ - CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Update the OPAMP state*/ + CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); + + /* Update the OPAMP state*/ /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/ hopamp->State = HAL_OPAMP_STATE_READY; } @@ -596,20 +639,24 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp) */ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) -{ +{ HAL_StatusTypeDef status = HAL_OK; - - uint32_t trimmingvaluen = 0; - uint32_t trimmingvaluep = 0; + + uint32_t trimmingvaluen; + uint32_t trimmingvaluep; uint32_t delta; uint32_t opampmode; - + __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - + /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if(hopamp == NULL) + { + status = HAL_ERROR; + } + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) { status = HAL_ERROR; } @@ -626,13 +673,13 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ /* the calibration is not working in PGA mode */ opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_OPAMODE); - - /* Use of standalone mode */ - MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); + + /* Use of standalone mode */ + MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); /* user trimming values are used for offset calibration */ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM); - + /* Select trimming settings depending on power mode */ if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) { @@ -642,34 +689,34 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) { tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR; } - + /* Enable calibration */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON); - + /* 1st calibration - N */ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL); - + /* Enable the selected opamp */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Init trimming counter */ + + /* Init trimming counter */ /* Medium value */ - trimmingvaluen = 16; - delta = 8; - - while (delta != 0) + trimmingvaluen = 16U; + delta = 8U; + + while (delta != 0U) { /* Set candidate trimming */ /* OPAMP_POWERMODE_NORMAL */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ HAL_Delay(OPAMP_TRIMMING_DELAY); - if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { + if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ trimmingvaluen -= delta; } @@ -678,22 +725,22 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* OPAMP_CSR_CALOUT is LOW try lower trimming */ trimmingvaluen += delta; } - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; } /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */ /* Set candidate trimming */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ HAL_Delay(OPAMP_TRIMMING_DELAY); - - if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0) - { + + if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U) + { /* Trimming value is actually one value more */ trimmingvaluen++; /* Set right trimming */ @@ -702,25 +749,25 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* 2nd calibration - P */ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL); - - /* Init trimming counter */ + + /* Init trimming counter */ /* Medium value */ - trimmingvaluep = 16; - delta = 8; - - while (delta != 0) + trimmingvaluep = 16U; + delta = 8U; + + while (delta != 0U) { /* Set candidate trimming */ /* OPAMP_POWERMODE_NORMAL */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { + if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ trimmingvaluep += delta; } @@ -729,38 +776,38 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* OPAMP_CSR_CALOUT is LOW try lower trimming */ trimmingvaluep -= delta; } - + /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; + delta >>= 1U; } - + /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ /* Set candidate trimming */ MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) + + if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) { /* Trimming value is actually one value more */ trimmingvaluep++; MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<Instance->CSR, OPAMP_CSR_OPAMPxEN); - + /* Disable calibration & set normal mode (operating mode) */ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON); - + /* Self calibration is successful */ /* Store calibration(user trimming) results in init structure. */ - /* Set user trimming mode */ + /* Set user trimming mode */ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER; /* Affect calibration parameters depending on mode normal/low power */ @@ -778,15 +825,15 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* Write calibration result P */ hopamp->Init.TrimmingValuePLowPower = trimmingvaluep; } - + /* Restore OPAMP mode after calibration */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode); } else { - /* OPAMP can not be calibrated from this mode */ + /* OPAMP can not be calibrated from this mode */ status = HAL_ERROR; - } + } } return status; } @@ -795,15 +842,15 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) * @} */ -/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the OPAMP data + This subsection provides a set of functions allowing to control the OPAMP data transfers. @@ -814,8 +861,8 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /** * @brief Lock the selected OPAMP configuration. - * @note On STM32L4, HAL OPAMP lock is software lock only (in - * contrast of hardware lock available on some other STM32 + * @note On STM32L4, HAL OPAMP lock is software lock only (in + * contrast of hardware lock available on some other STM32 * devices). * @param hopamp: OPAMP handle * @retval HAL status @@ -826,44 +873,43 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - /* OPAMP can be locked when enabled and running in normal mode */ + /* OPAMP can be locked when enabled and running in normal mode */ /* It is meaningless otherwise */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ - || (hopamp->State == HAL_OPAMP_STATE_READY) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) - + if(hopamp == NULL) { status = HAL_ERROR; } - - else + else if(hopamp->State == HAL_OPAMP_STATE_BUSY) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + /* OPAMP state changed to locked */ hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED; } - return status; + else + { + status = HAL_ERROR; + } + return status; } /** * @brief Return the OPAMP factory trimming value. - * @note On STM32L4 OPAMP, user can retrieve factory trimming if + * @note On STM32L4 OPAMP, user can retrieve factory trimming if * OPAMP has never been set to user trimming before. - * Therefore, this function must be called when OPAMP init - * parameter "UserTrimming" is set to trimming factory, - * and before OPAMP calibration (function + * Therefore, this function must be called when OPAMP init + * parameter "UserTrimming" is set to trimming factory, + * and before OPAMP calibration (function * "HAL_OPAMP_SelfCalibrate()"). - * Otherwise, factory trimming value cannot be retrieved and + * Otherwise, factory trimming value cannot be retrieved and * error status is returned. * @param hopamp : OPAMP handle * @param trimmingoffset : Trimming offset (P or N) * This parameter must be a value of @ref OPAMP_FactoryTrimming - * @note Calibration parameter retrieved is corresponding to the mode - * specified in OPAMP init structure (mode normal or low-power). - * To retrieve calibration parameters for both modes, repeat this + * @note Calibration parameter retrieved is corresponding to the mode + * specified in OPAMP init structure (mode normal or low-power). + * To retrieve calibration parameters for both modes, repeat this * function after OPAMP init structure accordingly updated. * @retval Trimming value (P or N): range: 0->31 * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available @@ -874,25 +920,25 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop { HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - + /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \ - || (hopamp->State == HAL_OPAMP_STATE_BUSY) \ - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\ - || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) + if(hopamp == NULL) { return OPAMP_FACTORYTRIMMING_DUMMY; } - else + + /* Check the OPAMP handle allocation */ + /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ + if(hopamp->State == HAL_OPAMP_STATE_READY) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset)); assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); - + /* Check the trimming mode */ - if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM) != RESET) + if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM) != 0U) { /* This function must called when OPAMP init parameter "UserTrimming" */ /* is set to trimming factory, and before OPAMP calibration (function */ @@ -911,8 +957,8 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop else { tmp_opamp_reg_trimming = &OPAMP->LPOTR; - } - + } + /* Get factory trimming */ if (trimmingoffset == OPAMP_FACTORYTRIMMING_P) { @@ -925,7 +971,11 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN; } } - } + } + else + { + return OPAMP_FACTORYTRIMMING_DUMMY; + } return trimmingvalue; } @@ -934,13 +984,13 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop */ -/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -972,14 +1022,150 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) * @} */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User OPAMP Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hopamp : OPAMP handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID + * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hopamp); + + if(hopamp->State == HAL_OPAMP_STATE_READY) + { + switch (CallbackID) + { + case HAL_OPAMP_MSPINIT_CB_ID : + hopamp->MspInitCallback = pCallback; + break; + case HAL_OPAMP_MSPDEINIT_CB_ID : + hopamp->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hopamp->State == HAL_OPAMP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OPAMP_MSPINIT_CB_ID : + hopamp->MspInitCallback = pCallback; + break; + case HAL_OPAMP_MSPDEINIT_CB_ID : + hopamp->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hopamp); + return status; +} + +/** + * @brief Unregister a User OPAMP Callback + * OPAMP Callback is redirected to the weak (surcharged) predefined callback + * @param hopamp : OPAMP handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID + * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID + * @arg @ref HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks + * @retval status + */ + +HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hopamp); + + if(hopamp->State == HAL_OPAMP_STATE_READY) + { + switch (CallbackID) + { + case HAL_OPAMP_MSPINIT_CB_ID : + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + break; + case HAL_OPAMP_MSPDEINIT_CB_ID : + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + break; + case HAL_OPAMP_ALL_CB_ID : + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hopamp->State == HAL_OPAMP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OPAMP_MSPINIT_CB_ID : + hopamp->MspInitCallback = HAL_OPAMP_MspInit; + break; + case HAL_OPAMP_MSPDEINIT_CB_ID : + hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hopamp); + return status; +} + +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + + /** * @} */ - + /** * @} - */ - + */ + #endif /* HAL_OPAMP_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h index a9dca5c23e..56725fb349 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h @@ -6,41 +6,25 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_OPAMP_H -#define __STM32L4xx_HAL_OPAMP_H +#ifndef STM32L4xx_HAL_OPAMP_H +#define STM32L4xx_HAL_OPAMP_H #ifdef __cplusplus extern "C" { #endif - + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -50,18 +34,18 @@ /** @addtogroup OPAMP * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Types OPAMP Exported Types * @{ */ -/** - * @brief OPAMP Init structure definition +/** + * @brief OPAMP Init structure definition */ - + typedef struct { uint32_t PowerSupplyRange; /*!< Specifies the power supply range: above or under 2.4V. @@ -70,84 +54,94 @@ typedef struct uint32_t PowerMode; /*!< Specifies the power mode Normal or Low-Power. This parameter must be a value of @ref OPAMP_PowerMode */ - + uint32_t Mode; /*!< Specifies the OPAMP mode - This parameter must be a value of @ref OPAMP_Mode + This parameter must be a value of @ref OPAMP_Mode mode is either Standalone, - Follower or PGA */ - + uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & PGA modes - In Standalone mode: i.e. when mode is OPAMP_STANDALONE_MODE & PGA mode: i.e. when mode is OPAMP_PGA_MODE - This parameter must be a value of @ref OPAMP_InvertingInput + This parameter must be a value of @ref OPAMP_InvertingInput - In Follower mode i.e. when mode is OPAMP_FOLLOWER_MODE - This parameter is Not Applicable */ + This parameter is Not Applicable */ - uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: - This parameter must be a value of @ref OPAMP_NonInvertingInput */ - - uint32_t PgaGain; /*!< Specifies the gain in PGA mode - i.e. when mode is OPAMP_PGA_MODE. + uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp: + This parameter must be a value of @ref OPAMP_NonInvertingInput */ + + uint32_t PgaGain; /*!< Specifies the gain in PGA mode + i.e. when mode is OPAMP_PGA_MODE. This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */ - - uint32_t UserTrimming; /*!< Specifies the trimming mode - This parameter must be a value of @ref OPAMP_UserTrimming + + uint32_t UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref OPAMP_UserTrimming UserTrimming is either factory or user trimming.*/ - + uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ - + uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ - + uint32_t TrimmingValuePLowPower; /*!< Specifies the offset trimming value (PMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ uint32_t TrimmingValueNLowPower; /*!< Specifies the offset trimming value (NMOS) - i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 0 and Max_Data = 31 + i.e. when UserTrimming is OPAMP_TRIMMING_USER. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 16 is typical default value */ }OPAMP_InitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPAMP is not yet Initialized */ - + HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */ HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */ - - HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ + + HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005 /*!< OPAMP is locked only system reset allows reconfiguring the opamp. */ - + }HAL_OPAMP_StateTypeDef; -/** +/** * @brief OPAMP Handle Structure definition - */ + */ + +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +typedef struct __OPAMP_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ { OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */ - HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */ + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */ - -} OPAMP_HandleTypeDef; -/** - * @brief HAl_OPAMP_TrimmingValueTypeDef definition - */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +void (* MspInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); +void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + +}OPAMP_HandleTypeDef; + +/** + * @brief HAl_OPAMP_TrimmingValueTypeDef definition + */ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; @@ -155,28 +149,46 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @} */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL OPAMP Callback ID enumeration definition + */ +typedef enum +{ + HAL_OPAMP_MSPINIT_CB_ID = 0x01U, /*!< OPAMP MspInit Callback ID */ + HAL_OPAMP_MSPDEINIT_CB_ID = 0x02U, /*!< OPAMP MspDeInit Callback ID */ + HAL_OPAMP_ALL_CB_ID = 0x03U /*!< OPAMP All ID */ +}HAL_OPAMP_CallbackIDTypeDef; + +/** + * @brief HAL OPAMP Callback pointer definition + */ +typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + + /* Exported constants --------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants * @{ - */ + */ /** @defgroup OPAMP_Mode OPAMP Mode * @{ */ -#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */ +#define OPAMP_STANDALONE_MODE 0x00000000U /*!< standalone mode */ #define OPAMP_PGA_MODE OPAMP_CSR_OPAMODE_1 /*!< PGA mode */ #define OPAMP_FOLLOWER_MODE OPAMP_CSR_OPAMODE /*!< follower mode */ - + /** * @} - */ - + */ + /** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input * @{ */ -#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP non-inverting input connected to dedicated IO pin */ +#define OPAMP_NONINVERTINGINPUT_IO0 0x00000000U /*!< OPAMP non-inverting input connected to dedicated IO pin */ #define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL /*!< OPAMP non-inverting input connected internally to DAC channel */ /** @@ -187,7 +199,7 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */ +#define OPAMP_INVERTINGINPUT_IO0 0x00000000U /*!< OPAMP inverting input connected to dedicated IO pin low-leakage */ #define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to alternative IO pin available on some device packages */ #define OPAMP_INVERTINGINPUT_CONNECT_NO OPAMP_CSR_VMSEL_1 /*!< OPAMP inverting input not connected externally (PGA mode only) */ @@ -199,7 +211,7 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000) /*!< PGA gain = 2 */ +#define OPAMP_PGA_GAIN_2 0x00000000U /*!< PGA gain = 2 */ #define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */ #define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */ #define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */ @@ -211,7 +223,7 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_PowerMode OPAMP PowerMode * @{ */ -#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000) +#define OPAMP_POWERMODE_NORMAL 0x00000000U #define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM /** @@ -221,17 +233,17 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange * @{ */ -#define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000) /*!< Power supply range low (VDDA lower than 2.4V) */ +#define OPAMP_POWERSUPPLY_LOW 0x00000000U /*!< Power supply range low (VDDA lower than 2.4V) */ #define OPAMP_POWERSUPPLY_HIGH OPAMP1_CSR_OPARANGE /*!< Power supply range high (VDDA higher than 2.4V) */ /** * @} - */ + */ /** @defgroup OPAMP_UserTrimming OPAMP User Trimming * @{ */ -#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ +#define OPAMP_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ #define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */ /** @@ -241,18 +253,17 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming * @{ */ -#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */ - -#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */ -#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */ +#define OPAMP_FACTORYTRIMMING_DUMMY 0xFFFFFFFFU /*!< Dummy value if trimming value could not be retrieved */ +#define OPAMP_FACTORYTRIMMING_N 0U /*!< Offset trimming N */ +#define OPAMP_FACTORYTRIMMING_P 1U /*!< Offset trimming P */ /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup OPAMP_Private_Constants OPAMP Private Constants @@ -260,8 +271,8 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @{ */ -/* NONINVERTING bit position in OTR & LPOTR */ -#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */ +/* NONINVERTING bit position in OTR & LPOTR */ +#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */ /* Offset trimming time: during calibration, minimum time needed between two */ /* steps to have 1 mV accuracy. */ @@ -282,11 +293,21 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; * @param __HANDLE__: OPAMP handle. * @retval None */ +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_OPAMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET) +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + + /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ @@ -307,14 +328,30 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; /* STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L412xx STM32L422xx */ + /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L451xx STM32L452xx STM32L462xx */ +#if defined (STM32L412xx) || defined (STM32L422xx) +#define IS_OPAMP_NONINVERTING_INPUT(INPUT) ((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) +#endif /* STM32L412xx STM32L422xx */ + +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH)) +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L451xx STM32L452xx STM32L462xx */ + /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ @@ -326,11 +363,13 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; /* STM32L496xx STM32L4A6xx */ /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO)) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L412xx STM32L422xx */ + /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \ @@ -348,14 +387,14 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; ((TRIMMING) == OPAMP_TRIMMING_USER)) -#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) +#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 31U) #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ ((TRIMMING) == OPAMP_FACTORYTRIMMING_P)) /** * @} - */ + */ /* Include OPAMP HAL Extended module */ #include "stm32l4xx_hal_opamp_ex.h" @@ -384,7 +423,7 @@ void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp); /* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp); HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp); -HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); /** * @} @@ -395,7 +434,13 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); */ /* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); +#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) +/* OPAMP callback registering/unregistering */ +HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ + +HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** @@ -419,16 +464,16 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_OPAMP_H */ +#endif /* STM32L4xx_HAL_OPAMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c index 8a0f250e93..c86ad8718f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c @@ -8,34 +8,18 @@ * peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions - * + * @verbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -77,7 +61,7 @@ ##### Extended IO operation functions ##### =============================================================================== [..] - (+) OPAMP Self calibration. + (+) OPAMP Self calibration. @endverbatim * @{ @@ -85,17 +69,17 @@ /* 2 OPAMPS available */ /* 2 OPAMPS can be calibrated in parallel */ -/* Not available on STM32L43x/STM32L44x where only one OPAMP available */ +/* Not available on STM32L41x/STM32L42x/STM32L43x/STM32L44x where only one OPAMP available */ /** * @brief Run the self calibration of the 2 OPAMPs in parallel. - * @note Trimming values (PMOS & NMOS) are updated and user trimming is + * @note Trimming values (PMOS & NMOS) are updated and user trimming is * enabled is calibration is successful. * @note Calibration is performed in the mode specified in OPAMP init * structure (mode normal or low-power). To perform calibration for * both modes, repeat this function twice after OPAMP init structure * accordingly updated. - * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P + * @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P * and N transistors: 10 steps with 1 ms for each step). * @param hopamp1 handle * @param hopamp2 handle @@ -106,280 +90,279 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { HAL_StatusTypeDef status = HAL_OK; - uint32_t trimmingvaluen1 = 0; - uint32_t trimmingvaluep1 = 0; - uint32_t trimmingvaluen2 = 0; - uint32_t trimmingvaluep2 = 0; + uint32_t trimmingvaluen1; + uint32_t trimmingvaluep1; + uint32_t trimmingvaluen2; + uint32_t trimmingvaluep2; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ - __IO uint32_t* tmp_opamp1_reg_trimming; + __IO uint32_t* tmp_opamp1_reg_trimming; __IO uint32_t* tmp_opamp2_reg_trimming; uint32_t delta; uint32_t opampmode1; uint32_t opampmode2; - - if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \ - (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED)) + + if((hopamp1 == NULL) || (hopamp2 == NULL)) + { + status = HAL_ERROR; + } + /* Check if OPAMP in calibration mode and calibration not yet enable */ + else if(hopamp1->State != HAL_OPAMP_STATE_READY) + { + status = HAL_ERROR; + } + else if(hopamp2->State != HAL_OPAMP_STATE_READY) { status = HAL_ERROR; } else { - /* Check if OPAMP in calibration mode and calibration not yet enable */ - if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY)) + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); + + assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); + assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); + + /* Save OPAMP mode as in */ + /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* the calibration is not working in PGA mode */ + opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_OPAMODE); + opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_OPAMODE); + + /* Use of standalone mode */ + MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); + MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); + + /* user trimming values are used for offset calibration */ + SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); + SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); + + /* Select trimming settings depending on power mode */ + if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) { - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); - - assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode)); - assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode)); - - /* Save OPAMP mode as in */ - /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ - /* the calibration is not working in PGA mode */ - opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_OPAMODE); - opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_OPAMODE); - - /* Use of standalone mode */ - MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); - MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); - - /* user trimming values are used for offset calibration */ - SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); - SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); - - /* Select trimming settings depending on power mode */ - if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp1_reg_trimming = &OPAMP1->OTR; - } - else - { - tmp_opamp1_reg_trimming = &OPAMP1->LPOTR; - } - - if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) - { - tmp_opamp2_reg_trimming = &OPAMP2->OTR; - } - else - { - tmp_opamp2_reg_trimming = &OPAMP2->LPOTR; - } - - /* Enable calibration */ - SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); - SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); - - /* 1st calibration - N */ - CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); - CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); - - /* Enable the selected opamp */ - SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN); - SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Init trimming counter */ - /* Medium value */ - trimmingvaluen1 = 16; - trimmingvaluen2 = 16; - delta = 8; - - while (delta != 0) - { - /* Set candidate trimming */ - /* OPAMP_POWERMODE_NORMAL */ - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ - /* Offset trim time: during calibration, minimum time needed between */ - /* two steps to have 1 mV accuracy */ - HAL_Delay(OPAMP_TRIMMING_DELAY); - - if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ - trimmingvaluen1 -= delta; - } - else - { - /* OPAMP_CSR_CALOUT is LOW try higher trimming */ - trimmingvaluen1 += delta; - } - - if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ - trimmingvaluen2 -= delta; - } - else - { - /* OPAMP_CSR_CALOUT is LOW try higher trimming */ - trimmingvaluen2 += delta; - } - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; - } - - /* Still need to check if right calibration is current value or one step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */ - /* Set candidate trimming */ - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); - - /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ - /* Offset trim time: during calibration, minimum time needed between */ - /* two steps to have 1 mV accuracy */ - HAL_Delay(OPAMP_TRIMMING_DELAY); - - if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0) - { - /* Trimming value is actually one value more */ - trimmingvaluen1++; - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); - } - - if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0) - { - /* Trimming value is actually one value more */ - trimmingvaluen2++; - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); - } - - /* 2nd calibration - P */ - SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); - SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); - - /* Init trimming counter */ - /* Medium value */ - trimmingvaluep1 = 16; - trimmingvaluep2 = 16; - delta = 8; - - while (delta != 0) - { - /* Set candidate trimming */ - /* OPAMP_POWERMODE_NORMAL */ - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ - trimmingvaluep1 += delta; - } - else - { - /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ - trimmingvaluep1 -= delta; - } - - if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ - trimmingvaluep2 += delta; - } - else - { - /* OPAMP_CSR_CALOUT is LOW try lower trimming */ - trimmingvaluep2 -= delta; - } - /* Divide range by 2 to continue dichotomy sweep */ - delta >>= 1; - } - - /* Still need to check if right calibration is current value or one step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ - /* Set candidate trimming */ - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* Trimming value is actually one value more */ - trimmingvaluep1++; - MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != RESET) - { - /* Trimming value is actually one value more */ - trimmingvaluep2++; - MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<Instance->CSR, OPAMP_CSR_OPAMPxEN); - CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); - - /* Disable calibration & set normal mode (operating mode) */ - CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); - CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); - - /* Self calibration is successful */ - /* Store calibration (user trimming) results in init structure. */ - - /* Set user trimming mode */ - hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; - hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; - - /* Affect calibration parameters depending on mode normal/low power */ - if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueN = trimmingvaluen1; - /* Write calibration result P */ - hopamp1->Init.TrimmingValueP = trimmingvaluep1; - } - else - { - /* Write calibration result N */ - hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1; - /* Write calibration result P */ - hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1; - } - - if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) - { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueN = trimmingvaluen2; - /* Write calibration result P */ - hopamp2->Init.TrimmingValueP = trimmingvaluep2; - } - else - { - /* Write calibration result N */ - hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2; - /* Write calibration result P */ - hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2; - } - - /* Update OPAMP state */ - hopamp1->State = HAL_OPAMP_STATE_READY; - hopamp2->State = HAL_OPAMP_STATE_READY; - - /* Restore OPAMP mode after calibration */ - MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1); - MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2); + tmp_opamp1_reg_trimming = &OPAMP1->OTR; } else { - /* At least one OPAMP can not be calibrated */ - status = HAL_ERROR; - } + tmp_opamp1_reg_trimming = &OPAMP1->LPOTR; + } + + if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL) + { + tmp_opamp2_reg_trimming = &OPAMP2->OTR; + } + else + { + tmp_opamp2_reg_trimming = &OPAMP2->LPOTR; + } + + /* Enable calibration */ + SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); + SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); + + /* 1st calibration - N */ + CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); + CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); + + /* Enable the selected opamp */ + SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN); + SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); + + /* Init trimming counter */ + /* Medium value */ + trimmingvaluen1 = 16U; + trimmingvaluen2 = 16U; + delta = 8U; + + while (delta != 0U) + { + /* Set candidate trimming */ + /* OPAMP_POWERMODE_NORMAL */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + HAL_Delay(OPAMP_TRIMMING_DELAY); + + if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trimmingvaluen1 -= delta; + } + else + { + /* OPAMP_CSR_CALOUT is LOW try higher trimming */ + trimmingvaluen1 += delta; + } + + if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trimmingvaluen2 -= delta; + } + else + { + /* OPAMP_CSR_CALOUT is LOW try higher trimming */ + trimmingvaluen2 += delta; + } + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; + } + + /* Still need to check if right calibration is current value or one step below */ + /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */ + /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); + + /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */ + /* Offset trim time: during calibration, minimum time needed between */ + /* two steps to have 1 mV accuracy */ + HAL_Delay(OPAMP_TRIMMING_DELAY); + + if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluen1++; + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); + } + + if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluen2++; + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); + } + + /* 2nd calibration - P */ + SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALSEL); + SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALSEL); + + /* Init trimming counter */ + /* Medium value */ + trimmingvaluep1 = 16U; + trimmingvaluep2 = 16U; + delta = 8U; + + while (delta != 0U) + { + /* Set candidate trimming */ + /* OPAMP_POWERMODE_NORMAL */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ + trimmingvaluep1 += delta; + } + else + { + /* OPAMP_CSR_CALOUT is HIGH try lower trimming */ + trimmingvaluep1 -= delta; + } + + if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* OPAMP_CSR_CALOUT is HIGH try higher trimming */ + trimmingvaluep2 += delta; + } + else + { + /* OPAMP_CSR_CALOUT is LOW try lower trimming */ + trimmingvaluep2 -= delta; + } + /* Divide range by 2 to continue dichotomy sweep */ + delta >>= 1U; + } + + /* Still need to check if right calibration is current value or one step below */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ + /* Set candidate trimming */ + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluep1++; + MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<Instance->CSR, OPAMP_CSR_CALOUT) != 0U) + { + /* Trimming value is actually one value more */ + trimmingvaluep2++; + MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<Instance->CSR, OPAMP_CSR_OPAMPxEN); + CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); + + /* Disable calibration & set normal mode (operating mode) */ + CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON); + CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); + + /* Self calibration is successful */ + /* Store calibration (user trimming) results in init structure. */ + + /* Set user trimming mode */ + hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; + hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; + + /* Affect calibration parameters depending on mode normal/low power */ + if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueN = trimmingvaluen1; + /* Write calibration result P */ + hopamp1->Init.TrimmingValueP = trimmingvaluep1; + } + else + { + /* Write calibration result N */ + hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1; + /* Write calibration result P */ + hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1; + } + + if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueN = trimmingvaluen2; + /* Write calibration result P */ + hopamp2->Init.TrimmingValueP = trimmingvaluep2; + } + else + { + /* Write calibration result N */ + hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2; + /* Write calibration result P */ + hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2; + } + + /* Update OPAMP state */ + hopamp1->State = HAL_OPAMP_STATE_READY; + hopamp2->State = HAL_OPAMP_STATE_READY; + + /* Restore OPAMP mode after calibration */ + MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1); + MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2); } return status; } @@ -390,15 +373,15 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA #endif -/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] - (+) OPAMP unlock. + (+) OPAMP unlock. @endverbatim * @{ @@ -416,23 +399,26 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ - if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) - || (hopamp->State == HAL_OPAMP_STATE_READY) - || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) - || (hopamp->State == HAL_OPAMP_STATE_BUSY)) - + if(hopamp == NULL) { status = HAL_ERROR; } - else + /* Check the OPAMP handle allocation */ + /* Check if OPAMP locked */ + else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - + /* OPAMP state changed to locked */ hopamp->State = HAL_OPAMP_STATE_BUSY; } - return status; + else + { + status = HAL_ERROR; + } + + return status; } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h index ac507d8879..ba4dbf282e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_OPAMP_EX_H -#define __STM32L4xx_HAL_OPAMP_EX_H +#ifndef STM32L4xx_HAL_OPAMP_EX_H +#define STM32L4xx_HAL_OPAMP_EX_H #ifdef __cplusplus extern "C" { @@ -62,14 +46,14 @@ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - + /* I/O operation functions *****************************************************/ /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions * @{ */ -HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); /** * @} @@ -80,7 +64,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /** @addtogroup OPAMPEx_Exported_Functions_Group2 * @{ */ -HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); +HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); /** * @} */ @@ -101,7 +85,6 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); } #endif - -#endif /* __STM32L4xx_HAL_OPAMP_EX_H */ +#endif /* STM32L4xx_HAL_OPAMP_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c index 5c87b74618..17650a55d0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c @@ -3,7 +3,7 @@ * @file stm32l4xx_hal_ospi.c * @author MCD Application Team * @brief OSPI HAL module driver. - This file provides firmware functions to manage the following + This file provides firmware functions to manage the following functionalities of the OctoSPI interface (OSPI). + Initialization and de-initialization functions + Hyperbus configuration @@ -14,7 +14,7 @@ + DMA channel configuration for indirect functional mode + Errors management and abort functionality + IO manager configuration - + @verbatim =============================================================================== ##### How to use this driver ##### @@ -25,33 +25,33 @@ [..] (#) As prerequisite, fill in the HAL_OSPI_MspInit() : (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE(). - (++) Reset OctoSPI IP with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). + (++) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt or DMA mode is used, enable and configure OctoSPI global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure + (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the fifo threshold, the dual-quad mode, the memory type, the - device size, the CS high time, the free running clock, the clock mode, - the wrap size, the clock prescaler, the sample shifting, the hold delay + (#) Configure the fifo threshold, the dual-quad mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay and the CS boundary using the HAL_OSPI_Init() function. - (#) When using Hyperbus, configure the RW recovery time, the access time, - the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + (#) When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() function. *** Indirect functional mode *** ================================ [..] - (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() + (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() or HAL_OSPI_Command_IT() functions : - (++) Instruction phase : the mode used and if present the size, the instruction + (++) Instruction phase : the mode used and if present the size, the instruction opcode and the DTR mode. - (++) Address phase : the mode used and if present the size, the address + (++) Address phase : the mode used and if present the size, the address value and the DTR mode. - (++) Alternate-bytes phase : the mode used and if present the size, the + (++) Alternate-bytes phase : the mode used and if present the size, the alternate bytes values and the DTR mode. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used and if present the number of bytes and the DTR mode. @@ -59,36 +59,36 @@ (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (++) Flash identifier : in dual-quad mode, indicates which flash is concerned (++) Operation type : always common configuration - (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() + (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() function : - (++) Address space : indicate if the access will be done in register or memory + (++) Address space : indicate if the access will be done in register or memory (++) Address size (++) Number of data (++) Data strobe (DQS) mode : the activation (or not) of this mode - (#) If no data is required for the command (only for regular mode, not for + (#) If no data is required for the command (only for regular mode, not for Hyperbus mode), it is sent directly to the memory : (++) In polling mode, the output of the function is done when the transfer is complete. (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or + (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or HAL_OSPI_Transmit_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or + (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or HAL_OSPI_Receive_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== [..] (#) Configure the command sequence by the same way than the indirect mode - (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() + (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() or HAL_OSPI_AutoPolling_IT() functions : (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), the polling interval and the automatic stop activation. @@ -100,29 +100,29 @@ *** Memory-mapped functional mode *** ===================================== [..] - (#) Configure the command sequence by the same way than the indirect mode except + (#) Configure the command sequence by the same way than the indirect mode except for the operation type in regular mode : - (++) Operation type equals to read configuration : the command configuration + (++) Operation type equals to read configuration : the command configuration applies to read access in memory-mapped mode - (++) Operation type equals to write configuration : the command configuration + (++) Operation type equals to write configuration : the command configuration applies to write access in memory-mapped mode - (++) Both read and write configuration should be performed before activating + (++) Both read and write configuration should be performed before activating memory-mapped mode - (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() + (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() functions : (++) The timeout activation and the timeout period. - (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on + (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** ================================================= [..] (#) HAL_OSPI_GetError() function gives the error raised during the last operation. - (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer + (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when + (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when the transfer complete bit is set. *** Control functions *** @@ -130,43 +130,86 @@ [..] (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. - (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI IP. - (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral. + (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold *** IO manager configuration functions *** ========================================== [..] (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : OSPI MspInit. + (+) MspDeInitCallback : OSPI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : OSPI MspInit. + (+) MspDeInitCallback : OSPI MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init + and @ref HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit + or @ref HAL_OSPI_Init function. + + When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -184,7 +227,7 @@ */ #ifdef HAL_OSPI_MODULE_ENABLED - + /** @cond 0 */ @@ -199,8 +242,9 @@ #define OSPI_CFG_STATE_MASK 0x00000004U #define OSPI_BUSY_STATE_MASK 0x00000008U -#define OSPI_NB_INSTANCE 2 -#define OSPI_IOM_NB_PORTS 2 +#define OSPI_NB_INSTANCE 2U +#define OSPI_IOM_NB_PORTS 2U +#define OSPI_IOM_PORT_MASK 0x1U /* Private macro -------------------------------------------------------------*/ #define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ @@ -213,7 +257,7 @@ /* Private function prototypes -----------------------------------------------*/ static void OSPI_DMACplt (DMA_HandleTypeDef *hdma); static void OSPI_DMAHalfCplt (DMA_HandleTypeDef *hdma); -static void OSPI_DMAError (DMA_HandleTypeDef *hdma); +static void OSPI_DMAError (DMA_HandleTypeDef *hdma); static void OSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); @@ -228,8 +272,8 @@ static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSP * @{ */ -/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -276,55 +320,82 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting)); assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle)); assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary)); - + /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - + /* Check if the state is the reset state */ if (hospi->State == HAL_OSPI_STATE_RESET) { +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */ + hospi->ErrorCallback = HAL_OSPI_ErrorCallback; + hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; + hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback; + hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback; + hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback; + hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback; + hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback; + hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback; + hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback; + hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback; + + if(hospi->MspInitCallback == NULL) + { + hospi->MspInitCallback = HAL_OSPI_MspInit; + } + + /* Init the low level hardware */ + hospi->MspInitCallback(hospi); +#else /* Initialization of the low level hardware */ HAL_OSPI_MspInit(hospi); - +#endif + /* Configure the default timeout for the OSPI memory access */ status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); } - + if (status == HAL_OK) { /* Configure memory type, device size, chip select high time, free running clock, clock mode */ MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), - (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1) << OCTOSPI_DCR1_DEVSIZE_Pos) | - ((hospi->Init.ChipSelectHighTime - 1) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.FreeRunningClock | - hospi->Init.ClockMode)); - + (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) | + ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.ClockMode)); + /* Configure wrap size */ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); - + /* Configure chip select boundary */ hospi->Instance->DCR3 = (hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos); /* Configure FIFO threshold */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1) << OCTOSPI_CR_FTHRES_Pos)); - + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos)); + /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Configure clock prescaler */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1) << OCTOSPI_DCR2_PRESCALER_Pos)); - + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); + /* Configure Dual Quad mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); - + /* Configure sample shifting and delay hold quarter cycle */ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); - + /* Enable OctoSPI */ __HAL_OSPI_ENABLE(hospi); - + + /* Enable free running clock if needed : must be done after OSPI enable */ + if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE) + { + SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + } + /* Initialize the OSPI state */ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { @@ -337,7 +408,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) } } } - + /* Return function status */ return status; } @@ -354,11 +425,11 @@ __weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) /* NOTE : This function should not be modified, when the callback is needed, the HAL_OSPI_MspInit can be implemented in the user file - */ + */ } /** - * @brief De-Initialize the OSPI peripheral. + * @brief De-Initialize the OSPI peripheral. * @param hospi : OSPI handle * @retval HAL status */ @@ -376,10 +447,23 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) { /* Disable OctoSPI */ __HAL_OSPI_DISABLE(hospi); - + + /* Disable free running clock if needed : must be done after OSPI disable */ + CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); + +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + if(hospi->MspDeInitCallback == NULL) + { + hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; + } + + /* DeInit the low level hardware */ + hospi->MspDeInitCallback(hospi); +#else /* De-initialize the low-level hardware */ HAL_OSPI_MspDeInit(hospi); - +#endif + /* Reset the driver state */ hospi->State = HAL_OSPI_STATE_RESET; } @@ -399,15 +483,15 @@ __weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) /* NOTE : This function should not be modified, when the callback is needed, the HAL_OSPI_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions - * @brief OSPI Transmit/Receive functions +/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief OSPI Transmit/Receive functions * @verbatim =============================================================================== @@ -438,24 +522,30 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) uint32_t flag = hospi->Instance->SR; uint32_t itsource = hospi->Instance->CR; uint32_t currentstate = hospi->State; - + /* OctoSPI fifo threshold interrupt occurred -------------------------------*/ - if (((flag & HAL_OSPI_FLAG_FT) != 0) && ((itsource & HAL_OSPI_IT_FT) != 0)) + if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U)) { if (currentstate == HAL_OSPI_STATE_BUSY_TX) { /* Write a data in the fifo */ - *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; + hospi->pBuffPtr++; hospi->XferCount--; } else if (currentstate == HAL_OSPI_STATE_BUSY_RX) { /* Read a data from the fifo */ - *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); + hospi->pBuffPtr++; hospi->XferCount--; } + else + { + /* Nothing to do */ + } - if (hospi->XferCount == 0) + if (hospi->XferCount == 0U) { /* All data have been received or transmitted for the transfer */ /* Disable fifo threshold interrupt */ @@ -463,20 +553,25 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) } /* Fifo threshold callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->FifoThresholdCallback(hospi); +#else HAL_OSPI_FifoThresholdCallback(hospi); +#endif } /* OctoSPI transfer complete interrupt occurred ----------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TC) != 0) && ((itsource & HAL_OSPI_IT_TC) != 0)) + else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U)) { if (currentstate == HAL_OSPI_STATE_BUSY_RX) { - if (((flag & OCTOSPI_SR_FLEVEL) != 0) && (hospi->XferCount > 0)) + if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U)) { /* Read the last data received in the fifo */ - *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void*)data_reg); + *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); + hospi->pBuffPtr++; hospi->XferCount--; } - else if(hospi->XferCount == 0) + else if(hospi->XferCount == 0U) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TC; @@ -488,7 +583,15 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->State = HAL_OSPI_STATE_READY; /* RX complete callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->RxCpltCallback(hospi); +#else HAL_OSPI_RxCpltCallback(hospi); +#endif + } + else + { + /* Nothing to do */ } } else @@ -505,12 +608,20 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) if (currentstate == HAL_OSPI_STATE_BUSY_TX) { /* TX complete callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->TxCpltCallback(hospi); +#else HAL_OSPI_TxCpltCallback(hospi); +#endif } else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) { /* Command complete callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->CmdCpltCallback(hospi); +#else HAL_OSPI_CmdCpltCallback(hospi); +#endif } else if (currentstate == HAL_OSPI_STATE_ABORT) { @@ -518,80 +629,119 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) { /* Abort called by the user */ /* Abort complete callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->AbortCpltCallback(hospi); +#else HAL_OSPI_AbortCpltCallback(hospi); +#endif } else { /* Abort due to an error (eg : DMA error) */ /* Error callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->ErrorCallback(hospi); +#else HAL_OSPI_ErrorCallback(hospi); +#endif } } + else + { + /* Nothing to do */ + } } } /* OctoSPI status match interrupt occurred ---------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_SM) != 0) && ((itsource & HAL_OSPI_IT_SM) != 0)) + else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U)) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_SM; - + /* Check if automatic poll mode stop is activated */ - if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U) { /* Disable the interrupts */ __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } - + /* Status match callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->StatusMatchCallback(hospi); +#else HAL_OSPI_StatusMatchCallback(hospi); +#endif } /* OctoSPI transfer error interrupt occurred -------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TE) != 0) && ((itsource & HAL_OSPI_IT_TE) != 0)) + else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U)) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TE; /* Disable all interrupts */ __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); - + /* Set error code */ hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER; - + /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA transfer on the DMA side */ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hospi->hdma); + if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->ErrorCallback(hospi); +#else + HAL_OSPI_ErrorCallback(hospi); +#endif + } } else { /* Update state */ hospi->State = HAL_OSPI_STATE_READY; - + /* Error callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->ErrorCallback(hospi); +#else HAL_OSPI_ErrorCallback(hospi); +#endif } } /* OctoSPI timeout interrupt occurred --------------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TO) != 0) && ((itsource & HAL_OSPI_IT_TO) != 0)) + else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U)) { /* Clear flag */ hospi->Instance->FCR = HAL_OSPI_FLAG_TO; - + /* Timeout callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->TimeOutCallback(hospi); +#else HAL_OSPI_TimeOutCallback(hospi); +#endif + } + else + { + /* Nothing to do */ } } /** - * @brief Set the command configuration. + * @brief Set the command configuration. * @param hospi : OSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration @@ -599,12 +749,13 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) */ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + uint32_t state; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the command structure */ assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); - + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); @@ -616,7 +767,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); } - + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) { @@ -644,20 +795,21 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Check the state of the driver */ - if (((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || - ((hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || - ((hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) + state = hospi->State; + if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || + ((state == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || + ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - + /* Configure the registers */ status = OSPI_ConfigCmd(hospi, cmd); @@ -665,7 +817,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp { if (cmd->DataMode == HAL_OSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done + /* When there is no data phase, the transfer start as soon as the configuration is done so wait until TC flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); @@ -674,7 +826,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp else { /* Update the state */ - if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) { hospi->State = HAL_OSPI_STATE_CMD_CFG; } @@ -715,7 +867,7 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp } /** - * @brief Set the command configuration in interrupt mode. + * @brief Set the command configuration in interrupt mode. * @param hospi : OSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes @@ -723,12 +875,12 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp */ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters of the command structure */ assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); - + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); @@ -740,7 +892,7 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); } - + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) { @@ -765,19 +917,19 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Check the state of the driver */ if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) && (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Initialize error code */ hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - + /* Clear flags related to interrupt */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); @@ -805,7 +957,7 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd } /** - * @brief Configure the Hyperbus parameters. + * @brief Configure the Hyperbus parameters. * @param hospi : OSPI handle * @param cfg : Structure containing the Hyperbus configuration * @param Timeout : Timeout duration @@ -813,7 +965,8 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd */ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + uint32_t state; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the hyperbus configuration structure */ @@ -823,18 +976,19 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode)); /* Check the state of the driver */ - if ((hospi->State == HAL_OSPI_STATE_HYPERBUS_INIT) || (hospi->State == HAL_OSPI_STATE_READY)) + state = hospi->State; + if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY)) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Configure Hyperbus configuration Latency register */ - WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | + WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) | cfg->WriteZeroLatency | cfg->LatencyMode)); - + /* Update the state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -844,13 +998,13 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; } - + /* Return function status */ return status; } /** - * @brief Set the Hyperbus command configuration. + * @brief Set the Hyperbus command configuration. * @param hospi : OSPI handle * @param cmd : Structure containing the Hyperbus command * @param Timeout : Timeout duration @@ -858,7 +1012,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC */ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the hyperbus command structure */ @@ -872,30 +1026,30 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Re-initialize the value of the functional mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); /* Configure the address space in the DCR1 register */ MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace); - + /* Configure the CCR and WCCR registers with the address size and the following configuration : - DQS signal enabled (used as RWDS) - DTR mode enabled on address and data - address and data on 8 lines */ - WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | + WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2)); - WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | + WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2)); /* Configure the DLR register with the number of data */ - WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1)); + WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U)); /* Configure the AR register with the address value */ WRITE_REG(hospi->Instance->AR, cmd->Address); - + /* Update the state */ hospi->State = HAL_OSPI_STATE_CMD_CFG; } @@ -905,13 +1059,13 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; } - + /* Return function status */ return status; } /** - * @brief Transmit an amount of data in blocking mode. + * @brief Transmit an amount of data in blocking mode. * @param hospi : OSPI handle * @param pData : pointer to data buffer * @param Timeout : Timeout duration @@ -920,7 +1074,7 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC */ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hospi->Instance->DR; @@ -936,37 +1090,38 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + do { /* Wait till fifo threshold flag is set to send data */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout); - + if (status != HAL_OK) { break; } - *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; + hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0); - + } while (hospi->XferCount > 0U); + if (status == HAL_OK) { /* Wait till transfer complete flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - + if (status == HAL_OK) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -993,12 +1148,12 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u */ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hospi->Instance->DR; uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; - + /* Check the data pointer allocation */ if (pData == NULL) { @@ -1011,13 +1166,13 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Trig the transfer by re-writing address or instruction register */ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { @@ -1034,31 +1189,32 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui WRITE_REG(hospi->Instance->IR, ir_reg); } } - + do { /* Wait till fifo threshold or transfer complete flags are set to read received data */ status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout); - + if (status != HAL_OK) { break; } - *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); + hospi->pBuffPtr++; hospi->XferCount--; - } while(hospi->XferCount > 0); + } while(hospi->XferCount > 0U); if (status == HAL_OK) { /* Wait till transfer complete flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - + if (status == HAL_OK) { /* Clear transfer complete flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -1083,7 +1239,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui * @retval HAL status */ HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) -{ +{ HAL_StatusTypeDef status = HAL_OK; /* Check the data pointer allocation */ @@ -1098,10 +1254,10 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1150,13 +1306,13 @@ HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Clear flags related to interrupt */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); @@ -1195,21 +1351,20 @@ HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) } /** - * @brief Send an amount of data in non-blocking mode with DMA. + * @brief Send an amount of data in non-blocking mode with DMA. * @param hospi : OSPI handle * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = hospi->Instance->DLR + 1; + uint32_t data_size = hospi->Instance->DLR + 1U; /* Check the data pointer allocation */ if (pData == NULL) @@ -1229,9 +1384,9 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1243,9 +1398,9 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1255,12 +1410,16 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat hospi->XferCount = (data_size >> 2); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1272,29 +1431,35 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat /* Set the DMA transfer complete callback */ hospi->hdma->XferCpltCallback = OSPI_DMACplt; - + /* Set the DMA Half transfer complete callback */ hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; - + /* Set the DMA error callback */ hospi->hdma->XferErrorCallback = OSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hospi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hospi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); /* Enable the transmit DMA Channel */ - tmp = (uint32_t*)((void*)&pData); - HAL_DMA_Start_IT(hospi->hdma, *(uint32_t*)tmp, (uint32_t)&hospi->Instance->DR, hospi->XferSize); + if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize) == HAL_OK) + { + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + hospi->State = HAL_OSPI_STATE_READY; + } } } else @@ -1309,21 +1474,20 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } /** - * @brief Receive an amount of data in non-blocking mode with DMA. + * @brief Receive an amount of data in non-blocking mode with DMA. * @param hospi : OSPI handle * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = hospi->Instance->DLR + 1; + uint32_t data_size = hospi->Instance->DLR + 1U; uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; @@ -1345,9 +1509,9 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1359,9 +1523,9 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1371,15 +1535,19 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData hospi->XferCount = (data_size >> 2); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { hospi->XferSize = hospi->XferCount; hospi->pBuffPtr = pData; - + /* Configure CR register with functional mode as indirect read */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Clear flags related to interrupt */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); @@ -1388,46 +1556,52 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData /* Set the DMA transfer complete callback */ hospi->hdma->XferCpltCallback = OSPI_DMACplt; - + /* Set the DMA Half transfer complete callback */ hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; - + /* Set the DMA error callback */ hospi->hdma->XferErrorCallback = OSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hospi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hospi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); /* Enable the transmit DMA Channel */ - tmp = (uint32_t*)((void *)&pData); - HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, *(uint32_t*)tmp, hospi->XferSize); - - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + if (HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize) == HAL_OK) { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { WRITE_REG(hospi->Instance->AR, addr_reg); } else { - WRITE_REG(hospi->Instance->IR, ir_reg); + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } } - } - /* Enable the DMA transfer by setting the DMAEN bit */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + hospi->State = HAL_OSPI_STATE_READY; + } } } else @@ -1442,7 +1616,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData } /** - * @brief Configure the OSPI Automatic Polling Mode in blocking mode. + * @brief Configure the OSPI Automatic Polling Mode in blocking mode. * @param hospi : OSPI handle * @param cfg : structure that contains the polling configuration information. * @param Timeout : Timeout duration @@ -1452,30 +1626,33 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData */ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hospi->Instance->DLR; +#endif /* Check the parameters of the autopolling configuration structure */ assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); assert_param(IS_OSPI_INTERVAL (cfg->Interval)); - assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U)); /* Check the state */ if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE)) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Configure registers */ WRITE_REG (hospi->Instance->PSMAR, cfg->Match); WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); WRITE_REG (hospi->Instance->PIR, cfg->Interval); - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); /* Trig the transfer by re-writing address or instruction register */ @@ -1493,16 +1670,16 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli { WRITE_REG(hospi->Instance->IR, ir_reg); } - } - + } + /* Wait till status match flag is set to go back in idle state */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout); - + if (status == HAL_OK) { /* Clear status match flag */ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM); - + /* Update state */ hospi->State = HAL_OSPI_STATE_READY; } @@ -1515,11 +1692,11 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli } /* Return function status */ - return status; + return status; } /** - * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. + * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. * @param hospi : OSPI handle * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode @@ -1528,30 +1705,33 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli */ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hospi->Instance->DLR; +#endif /* Check the parameters of the autopolling configuration structure */ assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); assert_param(IS_OSPI_INTERVAL (cfg->Interval)); - assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U)); /* Check the state */ if (hospi->State == HAL_OSPI_STATE_CMD_CFG) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Configure registers */ WRITE_REG (hospi->Instance->PSMAR, cfg->Match); WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); WRITE_REG (hospi->Instance->PIR, cfg->Interval); - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); /* Clear flags related to interrupt */ @@ -1559,7 +1739,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo /* Update state */ hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING; - + /* Enable the status match and transfer error interrupts */ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); @@ -1588,11 +1768,11 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo } /* Return function status */ - return status; + return status; } /** - * @brief Configure the Memory Mapped mode. + * @brief Configure the Memory Mapped mode. * @param hospi : OSPI handle * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode @@ -1600,7 +1780,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo */ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters of the memory-mapped configuration structure */ @@ -1611,16 +1791,16 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - + if (status == HAL_OK) { /* Update state */ hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED; - + if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - + /* Configure register */ WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod); @@ -1632,7 +1812,7 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa } /* Configure CR register with functional mode as memory-mapped */ - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); } } @@ -1643,7 +1823,7 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa } /* Return function status */ - return status; + return status; } /** @@ -1733,7 +1913,7 @@ __weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi) /* NOTE: This function should not be modified, when the callback is needed, the HAL_OSPI_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1763,7 +1943,7 @@ __weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi) /* NOTE: This function should not be modified, when the callback is needed, the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file - */ + */ } /** @@ -1796,20 +1976,232 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) */ } +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User OSPI Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hospi : OSPI handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID + * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID + * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID + * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID + * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID + * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID + * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID + * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID + * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID + * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID + * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID + * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if(hospi->State == HAL_OSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_OSPI_ERROR_CB_ID : + hospi->ErrorCallback = pCallback; + break; + case HAL_OSPI_ABORT_CB_ID : + hospi->AbortCpltCallback = pCallback; + break; + case HAL_OSPI_FIFO_THRESHOLD_CB_ID : + hospi->FifoThresholdCallback = pCallback; + break; + case HAL_OSPI_CMD_CPLT_CB_ID : + hospi->CmdCpltCallback = pCallback; + break; + case HAL_OSPI_RX_CPLT_CB_ID : + hospi->RxCpltCallback = pCallback; + break; + case HAL_OSPI_TX_CPLT_CB_ID : + hospi->TxCpltCallback = pCallback; + break; + case HAL_OSPI_RX_HALF_CPLT_CB_ID : + hospi->RxHalfCpltCallback = pCallback; + break; + case HAL_OSPI_TX_HALF_CPLT_CB_ID : + hospi->TxHalfCpltCallback = pCallback; + break; + case HAL_OSPI_STATUS_MATCH_CB_ID : + hospi->StatusMatchCallback = pCallback; + break; + case HAL_OSPI_TIMEOUT_CB_ID : + hospi->TimeOutCallback = pCallback; + break; + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = pCallback; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hospi->State == HAL_OSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = pCallback; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User OSPI Callback + * OSPI Callback is redirected to the weak (surcharged) predefined callback + * @param hospi : OSPI handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID + * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID + * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID + * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID + * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID + * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID + * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID + * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID + * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID + * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID + * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID + * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hospi->State == HAL_OSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_OSPI_ERROR_CB_ID : + hospi->ErrorCallback = HAL_OSPI_ErrorCallback; + break; + case HAL_OSPI_ABORT_CB_ID : + hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; + break; + case HAL_OSPI_FIFO_THRESHOLD_CB_ID : + hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback; + break; + case HAL_OSPI_CMD_CPLT_CB_ID : + hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback; + break; + case HAL_OSPI_RX_CPLT_CB_ID : + hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback; + break; + case HAL_OSPI_TX_CPLT_CB_ID : + hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback; + break; + case HAL_OSPI_RX_HALF_CPLT_CB_ID : + hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback; + break; + case HAL_OSPI_TX_HALF_CPLT_CB_ID : + hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback; + break; + case HAL_OSPI_STATUS_MATCH_CB_ID : + hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback; + break; + case HAL_OSPI_TIMEOUT_CB_ID : + hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback; + break; + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = HAL_OSPI_MspInit; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hospi->State == HAL_OSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_OSPI_MSP_INIT_CB_ID : + hospi->MspInitCallback = HAL_OSPI_MspInit; + break; + case HAL_OSPI_MSP_DEINIT_CB_ID : + hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; + break; + default : + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif + /** * @} */ -/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief OSPI control and State functions +/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief OSPI control and State functions * @verbatim =============================================================================== ##### Peripheral Control and State functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. + (+) Check in run-time the state of the driver. (+) Check the error code set during last operation. (+) Abort any operation. (+) Manage the Fifo threshold. @@ -1827,17 +2219,19 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) { HAL_StatusTypeDef status = HAL_OK; + uint32_t state; uint32_t tickstart = HAL_GetTick(); /* Check if the state is in one of the busy or configured states */ - if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + state = hospi->State; + if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U)) { /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA transfer on the DMA side */ status = HAL_DMA_Abort(hospi->hdma); if (status != HAL_OK) @@ -1845,27 +2239,35 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) hospi->ErrorCode = HAL_OSPI_ERROR_DMA; } } - - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); - - /* Wait until the transfer complete flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); - - if (status == HAL_OK) + + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Wait until the busy flag is reset to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); if (status == HAL_OK) { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } } } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } } else { @@ -1885,36 +2287,64 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) { HAL_StatusTypeDef status = HAL_OK; + uint32_t state; /* Check if the state is in one of the busy or configured states */ - if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + state = hospi->State; + if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U)) { /* Disable all interrupts */ __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); /* Update state */ hospi->State = HAL_OSPI_STATE_ABORT; - + /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA transfer on the DMA side */ hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hospi->hdma); + if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->AbortCpltCallback(hospi); +#else + HAL_OSPI_AbortCpltCallback(hospi); +#endif + } } else { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Enable the transfer complete interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->AbortCpltCallback(hospi); +#else + HAL_OSPI_AbortCpltCallback(hospi); +#endif + } } } else @@ -1937,21 +2367,21 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t HAL_StatusTypeDef status = HAL_OK; /* Check the state */ - if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0) + if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U) { /* Synchronize initialization structure with the new fifo threshold value */ hospi->Init.FifoThreshold = Threshold; - + /* Configure new fifo threshold */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1) << OCTOSPI_CR_FTHRES_Pos)); - + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos)); + } else { status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; } - + /* Return function status */ return status; } @@ -1962,7 +2392,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t */ uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi) { - return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1); + return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U); } /** @brief Set OSPI timeout. @@ -2001,13 +2431,13 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) * @} */ -/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function - * @brief OSPI IO Manager configuration function +/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief OSPI IO Manager configuration function * @verbatim =============================================================================== ##### IO Manager configuration function ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to : (+) Configure the IO manager. @@ -2017,7 +2447,7 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) */ /** - * @brief Configure the OctoSPI IO manager. + * @brief Configure the OctoSPI IO manager. * @param hospi : OSPI handle * @param cfg : Configuration of the IO Manager for the instance * @param Timeout : Timeout duration @@ -2026,106 +2456,110 @@ uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; - uint32_t instance = 0; - uint8_t index = 0, ospi_enabled = 0, other_instance = 0; + uint32_t instance; + uint8_t index, ospi_enabled = 0U, other_instance; OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + /* Check the parameters of the OctoSPI IO Manager configuration structure */ assert_param(IS_OSPIM_PORT(cfg->ClkPort)); assert_param(IS_OSPIM_PORT(cfg->DQSPort)); assert_param(IS_OSPIM_PORT(cfg->NCSPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); - + if (hospi->Instance == OCTOSPI1) { - instance = 0; - other_instance = 1; + instance = 0U; + other_instance = 1U; } else { - instance = 1; - other_instance = 0; + instance = 1U; + other_instance = 0U; } /**************** Get current configuration of the instances ****************/ - for (index = 0; index < OSPI_NB_INSTANCE; index++) + for (index = 0U; index < OSPI_NB_INSTANCE; index++) { - if (OSPIM_GetConfig(index+1, &(IOM_cfg[index])) != HAL_OK) + if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK) { status = HAL_ERROR; hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; } } - + if (status == HAL_OK) { /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/ - if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0) + if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U) { CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); - ospi_enabled |= 0x1; + ospi_enabled |= 0x1U; } - if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0) + if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U) { CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); - ospi_enabled |= 0x2; + ospi_enabled |= 0x2U; } - + /***************** Deactivation of previous configuration *****************/ - if (IOM_cfg[instance].ClkPort != 0) + if (IOM_cfg[instance].ClkPort != 0U) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); } - + /********************* Deactivation of other instance *********************/ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); } - + /******************** Activation of new configuration *********************/ - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); - MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); - - if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0) + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); + + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } - if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0) + + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } - + /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ - if ((ospi_enabled & 0x1) != 0) + if ((ospi_enabled & 0x1U) != 0U) { SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); } - if ((ospi_enabled & 0x2) != 0) + if ((ospi_enabled & 0x2U) != 0U) { SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); } @@ -2143,18 +2577,18 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * @cond 0 */ /** - * @brief DMA OSPI process complete callback. + * @brief DMA OSPI process complete callback. * @param hdma : DMA handle * @retval None */ -static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) +static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; - + /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -2163,22 +2597,30 @@ static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA OSPI process half complete callback. + * @brief DMA OSPI process half complete callback. * @param hdma : DMA handle * @retval None */ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = (hospi->XferCount >> 1); - + if (hospi->State == HAL_OSPI_STATE_BUSY_RX) { +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->RxHalfCpltCallback(hospi); +#else HAL_OSPI_RxHalfCpltCallback(hospi); +#endif } else { +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->TxHalfCpltCallback(hospi); +#else HAL_OSPI_TxHalfCpltCallback(hospi); +#endif } } @@ -2187,17 +2629,31 @@ static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void OSPI_DMAError(DMA_HandleTypeDef *hdma) +static void OSPI_DMAError(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; hospi->ErrorCode = HAL_OSPI_ERROR_DMA; /* Disable the DMA transfer on the OctoSPI side */ CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - + /* Abort the OctoSPI */ - HAL_OSPI_Abort_IT(hospi); + if (HAL_OSPI_Abort_IT(hospi) != HAL_OK) + { + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->ErrorCallback(hospi); +#else + HAL_OSPI_ErrorCallback(hospi); +#endif + } } /** @@ -2205,32 +2661,51 @@ static void OSPI_DMAError(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { - OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hdma->Parent); hospi->XferCount = 0; /* Check the state */ if (hospi->State == HAL_OSPI_STATE_ABORT) { /* DMA abort called by OctoSPI abort */ - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Enable the transfer complete interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->AbortCpltCallback(hospi); +#else + HAL_OSPI_AbortCpltCallback(hospi); +#endif + } } else { /* DMA abort called due to a transfer error interrupt */ /* Update state */ hospi->State = HAL_OSPI_STATE_READY; - + /* Error callback */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + hospi->ErrorCallback(hospi); +#else HAL_OSPI_ErrorCallback(hospi); +#endif } } @@ -2243,20 +2718,20 @@ static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) * @param Tickstart : Tick start value * @retval HAL status */ -static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { - /* Wait until flag is in expected state */ + /* Wait until flag is in expected state */ while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout)) + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hospi->State = HAL_OSPI_STATE_ERROR; hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - + return HAL_ERROR; } } @@ -2276,28 +2751,28 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg; /* Re-initialize the value of the functional mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); - + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); + /* Configure the flash ID */ if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) { MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId); } - - if (cmd->OperationType != HAL_OSPI_OPTYPE_WRITE_CFG) - { - ccr_reg = &(hospi->Instance->CCR); - tcr_reg = &(hospi->Instance->TCR); - ir_reg = &(hospi->Instance->IR); - abr_reg = &(hospi->Instance->ABR); - } - else + + if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) { ccr_reg = &(hospi->Instance->WCCR); tcr_reg = &(hospi->Instance->WTCR); ir_reg = &(hospi->Instance->WIR); abr_reg = &(hospi->Instance->WABR); } + else + { + ccr_reg = &(hospi->Instance->CCR); + tcr_reg = &(hospi->Instance->TCR); + ir_reg = &(hospi->Instance->IR); + abr_reg = &(hospi->Instance->ABR); + } /* Configure the CCR register with DQS and SIOO modes */ *ccr_reg = (cmd->DQSMode | cmd->SIOOMode); @@ -2306,13 +2781,13 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC { /* Configure the ABR register with alternate bytes value */ *abr_reg = cmd->AlternateBytes; - + /* Configure the CCR register with alternate bytes communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE), (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize)); } - /* Configure the TCR register with the number of dummy cycles */ + /* Configure the TCR register with the number of dummy cycles */ MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles); if (cmd->DataMode != HAL_OSPI_DATA_NONE) @@ -2320,10 +2795,10 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) { /* Configure the DLR register with the number of data */ - hospi->Instance->DLR = (cmd->NbData - 1); + hospi->Instance->DLR = (cmd->NbData - 1U); } } - + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) { if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) @@ -2331,7 +2806,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC if (cmd->DataMode != HAL_OSPI_DATA_NONE) { /* ---- Command with instruction, address and data ---- */ - + /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | @@ -2343,7 +2818,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC else { /* ---- Command with instruction and address ---- */ - + /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), @@ -2351,7 +2826,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) { MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); @@ -2360,7 +2835,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the IR register with the instruction value */ *ir_reg = cmd->Instruction; - + /* Configure the AR register with the address value */ hospi->Instance->AR = cmd->Address; } @@ -2369,7 +2844,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC if (cmd->DataMode != HAL_OSPI_DATA_NONE) { /* ---- Command with instruction and data ---- */ - + /* Configure the CCR register with all communication parameters */ MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), @@ -2385,7 +2860,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize)); /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) { MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); @@ -2394,7 +2869,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC /* Configure the IR register with the instruction value */ *ir_reg = cmd->Instruction; - + } } else @@ -2444,10 +2919,10 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) { HAL_StatusTypeDef status = HAL_OK; - uint32_t reg = 0, value = 0; - uint32_t index = 0; - - if ((instance_nb == 0) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) + uint32_t reg, value = 0U; + uint32_t index; + + if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) { /* Invalid parameter -> error returned */ status = HAL_ERROR; @@ -2455,82 +2930,82 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * else { /* Initialize the structure */ - cfg->ClkPort = cfg->DQSPort = cfg->NCSPort = cfg->IOLowPort = cfg->IOHighPort = 0; - - if (instance_nb == 1) - { - value = 0; - } - else if (instance_nb == 2) + cfg->ClkPort = 0U; + cfg->DQSPort = 0U; + cfg->NCSPort = 0U; + cfg->IOLowPort = 0U; + cfg->IOHighPort = 0U; + + if (instance_nb == 2U) { value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); } /* Get the information about the instance */ - for (index = 0; index < OSPI_IOM_NB_PORTS; index ++) + for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) { reg = OCTOSPIM->PCR[index]; - if ((reg & OCTOSPIM_PCR_CLKEN) != 0) + if ((reg & OCTOSPIM_PCR_CLKEN) != 0U) { /* The clock is enabled on this port */ if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) { /* The clock correspond to the instance passed as parameter */ - cfg->ClkPort = index+1; + cfg->ClkPort = index+1U; } } - if ((reg & OCTOSPIM_PCR_DQSEN) != 0) + if ((reg & OCTOSPIM_PCR_DQSEN) != 0U) { /* The DQS is enabled on this port */ if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) { /* The DQS correspond to the instance passed as parameter */ - cfg->DQSPort = index+1; + cfg->DQSPort = index+1U; } } - if ((reg & OCTOSPIM_PCR_NCSEN) != 0) + if ((reg & OCTOSPIM_PCR_NCSEN) != 0U) { /* The nCS is enabled on this port */ if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) { /* The nCS correspond to the instance passed as parameter */ - cfg->NCSPort = index+1; + cfg->NCSPort = index+1U; } } - if ((reg & OCTOSPIM_PCR_IOLEN) != 0) + if ((reg & OCTOSPIM_PCR_IOLEN) != 0U) { /* The IO Low is enabled on this port */ if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) { /* The IO Low correspond to the instance passed as parameter */ - if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0) + if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U) { - cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); } else { - cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U)); } } } - if ((reg & OCTOSPIM_PCR_IOHEN) != 0) + if ((reg & OCTOSPIM_PCR_IOHEN) != 0U) { /* The IO High is enabled on this port */ if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) { /* The IO High correspond to the instance passed as parameter */ - if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0) + if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U) { - cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); } else { - cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U)); } } } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h index 82eb12e4b2..6f1236df5a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_OSPI_H -#define __STM32L4xx_HAL_OSPI_H +#ifndef STM32L4xx_HAL_OSPI_H +#define STM32L4xx_HAL_OSPI_H #ifdef __cplusplus extern "C" { @@ -52,32 +36,32 @@ /** @addtogroup OSPI * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup OSPI_Exported_Types OSPI Exported Types * @{ */ -/** - * @brief OSPI Init structure definition +/** + * @brief OSPI Init structure definition */ typedef struct { - uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt - indicating that data are available in reception or free place + uint32_t FifoThreshold; /* This is the threshold used by the Peripheral to generate the interrupt + indicating that data are available in reception or free place is available in transmission. This parameter can be a value between 1 and 32 */ - uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to + uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to quad mode on two different devices to increase the throughput. This parameter can be a value of @ref OSPI_DualQuad */ uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. This parameter can be a value of @ref OSPI_MemoryType */ - uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, - it corresponds to the number of address bits required to access + uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, + it corresponds to the number of address bits required to access the external device. This parameter can be a value between 1 and 32 */ - uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select + uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select must remain high between commands. This parameter can be a value between 1 and 8 */ uint32_t FreeRunningClock; /* It enables or not the free running clock. @@ -86,45 +70,60 @@ typedef struct This parameter can be a value of @ref OSPI_ClockMode */ uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. This parameter can be a value of @ref OSPI_WrapSize */ - uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating - the external clock based on the AHB clock. + uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating + the external clock based on the AHB clock. This parameter can be a value between 1 and 256 */ - uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order + uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order to take in account external signal delays. This parameter can be a value of @ref OSPI_SampleShifting */ - uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. + uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ - uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and + uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and defines the boundary of bytes to release the chip select. This parameter can be a value between 0 and 31 */ }OSPI_InitTypeDef; -/** - * @brief HAL OSPI Handle Structure definition - */ -typedef struct +/** + * @brief HAL OSPI Handle Structure definition + */ +typedef struct __OSPI_HandleTypeDef { OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ OSPI_InitTypeDef Init; /* OSPI initialization parameters */ uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ __IO uint32_t XferSize; /* Number of data to transfer */ __IO uint32_t XferCount; /* Counter of data transferred */ - DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */ + DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */ __IO uint32_t State; /* Internal state of the OSPI HAL driver */ __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ uint32_t Timeout; /* Timeout used for the OSPI external device access */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) + void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); + void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); + + void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); + void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); +#endif }OSPI_HandleTypeDef; -/** - * @brief HAL OSPI Regular Command Structure definition - */ +/** + * @brief HAL OSPI Regular Command Structure definition + */ typedef struct { - uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or - to the registers for the write operation (these registers are only + uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or + to the registers for the write operation (these registers are only used for memory-mapped mode). This parameter can be a value of @ref OSPI_OperationType */ - uint32_t FlashId; /* It indicates which external device is selected for this command (it + uint32_t FlashId; /* It indicates which external device is selected for this command (it applies only if Dualquad is disabled in the initialization structure). This parameter can be a value of @ref OSPI_FlashId */ uint32_t Instruction; /* It contains the instruction to be sent to the device. @@ -153,7 +152,7 @@ typedef struct This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ uint32_t DataMode; /* It indicates the mode of the data. This parameter can be a value of @ref OSPI_DataMode */ - uint32_t NbData; /* It indicates the number of data transferred with this command. + uint32_t NbData; /* It indicates the number of data transferred with this command. This field is only used for indirect mode. This parameter can be a value between 1 and 0xFFFFFFFF */ uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. @@ -166,9 +165,9 @@ typedef struct This parameter can be a value of @ref OSPI_SIOOMode */ }OSPI_RegularCmdTypeDef; -/** - * @brief HAL OSPI Hyperbus Configuration Structure definition - */ +/** + * @brief HAL OSPI Hyperbus Configuration Structure definition + */ typedef struct { uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. @@ -181,9 +180,9 @@ typedef struct This parameter can be a value of @ref OSPI_LatencyMode */ }OSPI_HyperbusCfgTypeDef; -/** - * @brief HAL OSPI Hyperbus Command Structure definition - */ +/** + * @brief HAL OSPI Hyperbus Command Structure definition + */ typedef struct { uint32_t AddressSpace; /* It indicates the address space accessed by the command. @@ -200,14 +199,14 @@ typedef struct This parameter can be a value of @ref OSPI_DQSMode */ }OSPI_HyperbusCmdTypeDef; -/** - * @brief HAL OSPI Auto Polling mode configuration structure definition +/** + * @brief HAL OSPI Auto Polling mode configuration structure definition */ typedef struct { uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. This parameter can be any value between 0 and 0xFFFFFFFF */ uint32_t MatchMode; /* Specifies the method used for determining a match. This parameter can be a value of @ref OSPI_MatchMode */ @@ -217,19 +216,19 @@ typedef struct This parameter can be any value between 0 and 0xFFFF */ }OSPI_AutoPollingTypeDef; -/** - * @brief HAL OSPI Memory Mapped mode configuration structure definition +/** + * @brief HAL OSPI Memory Mapped mode configuration structure definition */ typedef struct { - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref OSPI_TimeOutActivation */ uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ }OSPI_MemoryMappedTypeDef; -/** - * @brief HAL OSPI IO Manager Configuration structure definition +/** + * @brief HAL OSPI IO Manager Configuration structure definition */ typedef struct { @@ -245,6 +244,32 @@ typedef struct This parameter can be a value of @ref OSPIM_IOPort */ }OSPIM_CfgTypeDef; +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL OSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ + HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ + HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ + HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ + HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ + HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ + HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ + HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ + HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ + HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ + + HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ + HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ +}HAL_OSPI_CallbackIDTypeDef; + +/** + * @brief HAL OSPI Callback pointer definition + */ +typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); +#endif /** * @} */ @@ -256,7 +281,7 @@ typedef struct /** @defgroup OSPI_State OSPI State * @{ - */ + */ #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ @@ -272,62 +297,68 @@ typedef struct #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ /** * @} - */ + */ /** @defgroup OSPI_ErrorCode OSPI Error Code * @{ - */ + */ #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) +#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ +#endif /** * @} - */ + */ /** @defgroup OSPI_DualQuad OSPI Dual-Quad * @{ - */ + */ #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ /** * @} - */ + */ /** @defgroup OSPI_MemoryType OSPI Memory Type * @{ - */ + */ #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx) +#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ +#endif #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ /** * @} - */ + */ /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock * @{ - */ + */ #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ /** * @} - */ + */ /** @defgroup OSPI_ClockMode OSPI Clock Mode * @{ - */ + */ #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ /** * @} - */ + */ /** @defgroup OSPI_WrapSize OSPI Wrap-Size * @{ - */ + */ #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ @@ -335,48 +366,48 @@ typedef struct #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ /** * @} - */ + */ /** @defgroup OSPI_SampleShifting OSPI Sample Shifting * @{ - */ + */ #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ /** * @} - */ + */ /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle * @{ - */ + */ #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ /** * @} - */ + */ /** @defgroup OSPI_OperationType OSPI Operation Type * @{ - */ + */ #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ /** * @} - */ + */ /** @defgroup OSPI_FlashID OSPI Flash Id * @{ - */ + */ #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ /** * @} - */ + */ /** @defgroup OSPI_InstructionMode OSPI Instruction Mode * @{ - */ + */ #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ @@ -384,31 +415,31 @@ typedef struct #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_InstructionSize OSPI Instruction Size * @{ - */ + */ #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ /** * @} - */ + */ /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode * @{ - */ + */ #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ /** * @} - */ + */ /** @defgroup OSPI_AddressMode OSPI Address Mode * @{ - */ + */ #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ @@ -416,31 +447,31 @@ typedef struct #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_AddressSize OSPI Address Size * @{ - */ + */ #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ /** * @} - */ + */ /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode * @{ - */ + */ #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ /** * @} - */ + */ /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode * @{ - */ + */ #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ @@ -448,31 +479,31 @@ typedef struct #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size * @{ - */ + */ #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ /** * @} - */ + */ /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode * @{ - */ + */ #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ /** * @} - */ + */ /** @defgroup OSPI_DataMode OSPI Data Mode * @{ - */ + */ #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ @@ -480,61 +511,61 @@ typedef struct #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ /** * @} - */ + */ /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode * @{ - */ + */ #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ /** * @} - */ + */ /** @defgroup OSPI_DQSMode OSPI DQS Mode * @{ - */ + */ #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ /** * @} - */ + */ /** @defgroup OSPI_SIOOMode OSPI SIOO Mode * @{ - */ + */ #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ /** * @} - */ + */ /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation * @{ - */ + */ #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ /** * @} - */ + */ /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode * @{ - */ + */ #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ /** * @} - */ + */ /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space * @{ - */ + */ #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ /** * @} - */ + */ /** @defgroup OSPI_MatchMode OSPI Match Mode * @{ @@ -543,7 +574,7 @@ typedef struct #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ /** * @} - */ + */ /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop * @{ @@ -552,7 +583,7 @@ typedef struct #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ /** * @} - */ + */ /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation * @{ @@ -561,7 +592,7 @@ typedef struct #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ /** * @} - */ + */ /** @defgroup OSPI_Flags OSPI Flags * @{ @@ -578,7 +609,7 @@ typedef struct /** @defgroup OSPI_Interrupts OSPI Interrupts * @{ - */ + */ #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ @@ -590,22 +621,22 @@ typedef struct /** @defgroup OSPI_Timeout_definition OSPI Timeout definition * @{ - */ + */ #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ /** * @} - */ + */ /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port * @{ - */ -#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1)) /*!< Port 1 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ + */ +#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ +#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ /** * @} - */ + */ /** * @} */ @@ -618,12 +649,20 @@ typedef struct * @param __HANDLE__: OSPI handle. * @retval None */ +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) +#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) +#endif /** @brief Enable the OSPI peripheral. * @param __HANDLE__: specifies the OSPI Handle. * @retval None - */ + */ #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) /** @brief Disable the OSPI peripheral. @@ -670,7 +709,7 @@ typedef struct * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Check whether the selected OSPI flag is set or not. @@ -685,7 +724,7 @@ typedef struct * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag * @retval None */ -#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) +#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified OSPI's flag status. * @param __HANDLE__: specifies the OSPI Handle. @@ -703,7 +742,7 @@ typedef struct * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup OSPI_Exported_Functions * @{ */ @@ -767,6 +806,11 @@ void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); /* OSPI memory-mapped mode functions */ void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); +#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) +/* OSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); +#endif /** * @} */ @@ -800,24 +844,33 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, /** * @} */ -/* End of exported functions -------------------------------------------------*/ +/* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @cond 0 */ -#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1) && ((THRESHOLD) <= 32)) +#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) +#else +#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) +#endif -#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 32)) +#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) -#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1) && ((TIME) <= 8)) +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) @@ -831,7 +884,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) -#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 256)) +#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) @@ -843,8 +896,8 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) -#define IS_OSPI_FLASH_ID(FLASH) (((FLASH) == HAL_OSPI_FLASH_ID_1) || \ - ((FLASH) == HAL_OSPI_FLASH_ID_2)) +#define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ + ((FLASHID) == HAL_OSPI_FLASH_ID_2)) #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ @@ -894,12 +947,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, ((MODE) == HAL_OSPI_DATA_4_LINES) || \ ((MODE) == HAL_OSPI_DATA_8_LINES)) -#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1) +#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) -#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31) +#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ ((MODE) == HAL_OSPI_DQS_ENABLE)) @@ -907,9 +960,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) -#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255) +#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) -#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255) +#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) @@ -926,18 +979,18 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) -#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFF) +#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) -#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) +#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) + ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) -#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) +#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) -#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31) +#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) -#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 2)) +#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U)) #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ @@ -951,11 +1004,11 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, /** * @} - */ + */ /** * @} - */ + */ #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ @@ -963,6 +1016,6 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, } #endif -#endif /* __STM32L4xx_HAL_OSPI_H */ +#endif /* STM32L4xx_HAL_OSPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c index 1215aae48c..5e95669726 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c @@ -3,13 +3,13 @@ * @file stm32l4xx_hal_pcd.c * @author MCD Application Team * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,18 +19,19 @@ (#) Declare a PCD_HandleTypeDef handle structure, for example: PCD_HandleTypeDef hpcd; - + (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral + (##) Initialize the related GPIO clocks (##) Configure PCD pin-out (##) Configure PCD NVIC interrupt - + (#)Associate the Upper USB device stack to the HAL PCD Driver: (##) hpcd.pData = pdev; @@ -41,32 +42,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -81,22 +66,12 @@ */ #ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +#if defined (USB) || defined (USB_OTG_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** - * USB_OTG_CORE VERSION ID - */ -#define USB_OTG_CORE_ID_310A 0x4F54310A -#define USB_OTG_CORE_ID_320A 0x4F54320A - /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ @@ -113,11 +88,13 @@ */ #if defined (USB_OTG_FS) static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -static HAL_StatusTypeDef PCD_ReadRxFifo(PCD_HandleTypeDef *hpcd); // MBED PATCH -#endif /* USB_OTG_FS */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) */ + #if defined (USB) static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); -#endif /* USB */ +#endif /* defined (USB) */ /** * @} */ @@ -127,15 +104,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); * @{ */ -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ @@ -143,120 +120,170 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t index = 0U; - +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + uint8_t i; + /* Check the PCD handle allocation */ - if(hpcd == NULL) + if (hpcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - if(hpcd->State == HAL_PCD_STATE_RESET) + +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) { // MBED PATCH - hpcd->EPLock[index].Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); /* Init endpoints structures */ - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { /* Init ep structure */ - hpcd->IN_ep[index].is_in = 1; - hpcd->IN_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; /* Control until ep is activated */ - hpcd->IN_ep[index].type = EP_TYPE_CTRL; - hpcd->IN_ep[index].maxpacket = 0; - hpcd->IN_ep[index].xfer_buff = 0; - hpcd->IN_ep[index].xfer_len = 0; + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; } - - for (index = 0; index < 15 ; index++) + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { - hpcd->OUT_ep[index].is_in = 0; - hpcd->OUT_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; /* Control until ep is activated */ - hpcd->OUT_ep[index].type = EP_TYPE_CTRL; - hpcd->OUT_ep[index].maxpacket = 0; - hpcd->OUT_ep[index].xfer_buff = 0; - hpcd->OUT_ep[index].xfer_len = 0; + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; } /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); - - hpcd->USB_Address = 0; - - hpcd->State= HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable ==1) + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) { - HAL_PCDEx_ActivateLPM(hpcd); - } - /* Activate Battery charging */ - if (hpcd->Init.battery_charging_enable ==1) - { - HAL_PCDEx_ActivateBCD(hpcd); + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; } - USB_DevDisconnect (hpcd->Instance); + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + + (void)USB_DevDisconnect(hpcd->Instance); + return HAL_OK; } /** * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { /* Check the PCD handle allocation */ - if(hpcd == NULL) + if (hpcd == NULL) { return HAL_ERROR; } hpcd->State = HAL_PCD_STATE_BUSY; - + /* Stop Device */ - HAL_PCD_Stop(hpcd); - + (void)HAL_PCD_Stop(hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + return HAL_OK; } /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -271,7 +298,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -284,669 +311,1228 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) */ } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callabck is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD BCD Callback + * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD BCD Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD BCD Callback + * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the PCD data + This subsection provides a set of functions allowing to manage the PCD data transfers. @endverbatim * @{ */ - + /** - * @brief Start The USB OTG Device. - * @param hpcd: PCD handle + * @brief Start the USB device + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - // MBED PATCH __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); +{ +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + __HAL_LOCK(hpcd); +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } +#endif /* defined (USB_OTG_FS) */ + (void)USB_DevConnect(hpcd->Instance); __HAL_PCD_ENABLE(hpcd); - // MBED PATCH __HAL_UNLOCK(hpcd); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle + * @brief Stop the USB device. + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - // MBED PATCH __HAL_LOCK(hpcd); +{ + __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); - // MBED PATCH __HAL_UNLOCK(hpcd); + + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + __HAL_UNLOCK(hpcd); + return HAL_ERROR; + } + + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + return HAL_OK; } - #if defined (USB_OTG_FS) /** * @brief Handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U; - uint32_t fifoemptymsk = 0U, temp = 0U; - // USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 80000000; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, ep_intr, epint, epnum = 0U; + uint32_t fifoemptymsk, temp; + USB_OTG_EPTypeDef *ep; + /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) { /* avoid spurious interrupt */ - if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) { return; } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { - epnum = 0; - + epnum = 0U; + /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while (ep_intr) + + while (ep_intr != 0U) { - if (ep_intr & 0x1) + if ((ep_intr & 0x1U) != 0U) { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - - if (( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - - /* setup/out transaction management for Core ID 310A */ - if (USBx->GSNPSID == USB_OTG_CORE_ID_310A) - { - if (!(USBx_OUTEP(0)->DOEPINT & (0x1 << 15))) - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - - hpcd->OUT_ep[epnum].xfer_buff += - hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - - /* Clear the SetPktRcvd flag*/ - USBx_OUTEP(0)->DOEPINT |= (0x1 << 15) | (0x1 << 5); - } - else - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); } - // MBED PATCH - if (( epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); - } - // MBED PATCH - - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) - { - /* Inform the upper layer that a setup packet is available */ - HAL_PCD_SetupStageCallback(hpcd); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } - - if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } - -#ifdef USB_OTG_DOEPINT_OTEPSPR + /* Clear Status Phase Received interrupt */ - if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } -#endif /* USB_OTG_DOEPINT_OTEPSPR */ + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) { /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0; - - while ( ep_intr ) - { - if (ep_intr & 0x1) /* In ITR */ - { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) - { - fifoemptymsk = 0x1 << epnum; - atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); // MBED PATCH - + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } - - HAL_PCD_DataInStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) - { - /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { - PCD_WriteEmptyTxFifo(hpcd , epnum); + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } - + /* Handle Resume Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { /* Clear the Remote Wake-up Signaling */ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if(hpcd->LPM_State == LPM_L1) + + if (hpcd->LPM_State == LPM_L1) { hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); } - + /* Handle Suspend Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { - +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - if( hpcd->LPM_State == LPM_L0) - { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } /* Handle Reset Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0x10); - - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; - - if(hpcd->Init.use_dedicated_ep1) + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) { - USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); - USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; } else { -#ifdef USB_OTG_DOEPINT_OTEPSPR - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); -#else - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); -#endif /* USB_OTG_DOEPINT_OTEPSPR */ - USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; } - + /* Set Default Address to 0 */ USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - + /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); } - - /* Handle Enumeration done Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) - { - USB_ActivateSetup(hpcd->Instance); - hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - if((hclk >= 14200000)&&(hclk < 15000000)) - { - /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 15000000)&&(hclk < 16000000)) - { - /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 16000000)&&(hclk < 17200000)) - { - /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 17200000)&&(hclk < 18500000)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 18500000)&&(hclk < 20000000)) - { - /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 20000000)&&(hclk < 21800000)) - { - /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 21800000)&&(hclk < 24000000)) - { - /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 24000000)&&(hclk < 27700000)) - { - /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 27700000)&&(hclk < 32000000)) - { - /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-80 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); - } - + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else HAL_PCD_ResetCallback(hpcd); - +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - + /* Handle RxQLevel Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { - PCD_ReadRxFifo(hpcd); // MBED PATCH + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + temp = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } - + /* Handle SOF Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } - + /* Handle Incomplete ISO IN Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - + } + /* Handle Incomplete ISO OUT Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - + } + /* Handle Connection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - + } + /* Handle Disconnection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { temp = hpcd->Instance->GOTGINT; - - if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + + if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } hpcd->Instance->GOTGINT |= temp; } } } - -// MBED PATCH -/** - * @brief Abort a transaction. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - HAL_StatusTypeDef ret = HAL_OK; - USB_OTG_EPTypeDef *ep; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); - - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - USB_EPSetNak(hpcd->Instance, ep); - - if ((0x80 & ep_addr) == 0x80) - { - ret = USB_EPStopXfer(hpcd->Instance , ep); - if (ret == HAL_OK) - { - ret = USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); - } - } - else - { - /* Set global NAK */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; - - /* Read all entries from the fifo so global NAK takes effect */ - while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - PCD_ReadRxFifo(hpcd); - } - - /* Stop the transfer */ - ret = USB_EPStopXfer(hpcd->Instance , ep); - if (ret == HAL_BUSY) - { - /* If USB_EPStopXfer returns HAL_BUSY then a setup packet - * arrived after the rx fifo was processed but before USB_EPStopXfer - * was called. Process the rx fifo one more time to read the - * setup packet. - * - * Note - after the setup packet has been received no further - * packets will be received over USB. This is because the next - * phase (data or status) of the control transfer started by - * the setup packet will be naked until global nak is cleared. - */ - while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - PCD_ReadRxFifo(hpcd); - } - - ret = USB_EPStopXfer(hpcd->Instance , ep); - } - - /* Clear global nak */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; - } - - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); - - return ret; -} -// MBED PATCH - -#endif /* USB_OTG_FS */ +#endif /* defined (USB_OTG_FS) */ #if defined (USB) /** * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - uint32_t wInterrupt_Mask = 0; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR)) { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); + (void)PCD_EP_ISR_Handler(hpcd); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET)) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetAddress(hpcd, 0U); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) { - - hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE); + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - /* enable L1REQ interrupt */ - if (hpcd->Init.lpm_enable ==1) - { - wInterrupt_Mask |= USB_CNTR_L1REQM; - - /* Enable LPM support and enable ACK answer to LPM request*/ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - } - - if(hpcd->LPM_State == LPM_L1) + if (hpcd->LPM_State == LPM_L1) { hpcd->LPM_State = LPM_L0; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) + { /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); - if( hpcd->LPM_State == LPM_L0) - { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); + if (hpcd->LPM_State == LPM_L0) + { /* Force suspend and low-power mode before going to L1 state*/ hpcd->Instance->CNTR |= USB_CNTR_LPMODE; hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - + hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ; + hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF)) { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF)) { /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); } } -#endif /* USB */ +#endif /* defined (USB) */ /** * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -957,13 +1543,13 @@ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ + */ } /** - * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -974,11 +1560,11 @@ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DataInStageCallback could be implemented in the user file - */ + */ } /** - * @brief Setup stage callback. - * @param hpcd: PCD handle + * @brief Setup stage callback + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -988,12 +1574,12 @@ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SetupStageCallback could be implemented in the user file - */ + */ } /** * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -1003,12 +1589,12 @@ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SOFCallback could be implemented in the user file - */ + */ } /** * @brief USB Reset callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -1018,12 +1604,12 @@ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResetCallback could be implemented in the user file - */ + */ } /** * @brief Suspend event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -1033,12 +1619,12 @@ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_SuspendCallback could be implemented in the user file - */ + */ } /** * @brief Resume event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -1048,13 +1634,13 @@ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ResumeCallback could be implemented in the user file - */ + */ } /** * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -1065,13 +1651,13 @@ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t ep /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ + */ } /** * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -1082,12 +1668,12 @@ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epn /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ + */ } /** * @brief Connection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -1097,12 +1683,12 @@ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_ConnectCallback could be implemented in the user file - */ + */ } /** * @brief Disconnection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -1112,22 +1698,22 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCD_DisconnectCallback could be implemented in the user file - */ + */ } /** * @} */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the PCD data + This subsection provides a set of functions allowing to control the PCD data transfers. @endverbatim @@ -1135,321 +1721,352 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** - * @brief Connect the USB device. - * @param hpcd: PCD handle + * @brief Connect the USB device + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { - __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + __HAL_LOCK(hpcd); +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } +#endif /* defined (USB_OTG_FS) */ + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Disconnect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { - __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (USB_OTG_FS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { - __HAL_LOCK(hpcd); + __HAL_LOCK(hpcd); hpcd->USB_Address = address; - USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; + + ep->num = ep_addr & EP_ADDR_MSK; ep->maxpacket = ep_mps; ep->type = ep_type; - - // MBED PATCH __HAL_LOCK(hpcd); - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); // MBED PATCH - USB_ActivateEndpoint(hpcd->Instance , ep); - // MBED PATCH __HAL_UNLOCK(hpcd); - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); // MBED PATCH + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return ret; - } - /** * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - - // MBED PATCH __HAL_LOCK(hpcd); - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); // MBED PATCH - USB_DeactivateEndpoint(hpcd->Instance , ep); - // MBED PATCH __HAL_UNLOCK(hpcd); - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); // MBED PATCH + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); return HAL_OK; } /** * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH - - if ((ep_addr & 0x7F) == 0 ) + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if ((ep_addr & EP_ADDR_MSK) == 0U) { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep); } - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH - return HAL_OK; } /** - * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } /** - * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + /*setup and start the Xfer */ - ep->xfer_buff = pBuf; + ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH - - if ((ep_addr & 0x7F) == 0 ) + if ((ep_addr & EP_ADDR_MSK) == 0U) { - USB_EP0StartXfer(hpcd->Instance,ep, hpcd->Init.dma_enable); + (void)USB_EP0StartXfer(hpcd->Instance, ep); } else { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); + (void)USB_EPStartXfer(hpcd->Instance, ep); } - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH - return HAL_OK; } /** - * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; } else { ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & EP_ADDR_MSK) == 0U) { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); } + __HAL_UNLOCK(hpcd); - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH - return HAL_OK; } /** - * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; } else { - ep = &hpcd->OUT_ep[ep_addr]; + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; - USB_EPClearStall(hpcd->Instance , ep); + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH - return HAL_OK; } /** - * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH + __HAL_LOCK(hpcd); - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); } else { - USB_FlushRxFifo(hpcd->Instance); + (void)USB_FlushRxFifo(hpcd->Instance); } - __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED PATCH + __HAL_UNLOCK(hpcd); return HAL_OK; } /** - * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - return(USB_ActivateRemoteWakeup(hpcd->Instance)); + return (USB_ActivateRemoteWakeup(hpcd->Instance)); } /** * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - return(USB_DeActivateRemoteWakeup(hpcd->Instance)); + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); } + /** * @} */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1458,13 +2075,14 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD handle state. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) { return hpcd->State; } + /** * @} */ @@ -1480,181 +2098,242 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) #if defined (USB_OTG_FS) /** * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - USB_OTG_EPTypeDef *ep = NULL; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; uint32_t len; - uint32_t len32b = 0; - uint32_t fifoemptymsk = 0; + uint32_t len32b; + uint32_t fifoemptymsk; ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - - - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; - + if (len > ep->maxpacket) { len = ep->maxpacket; } - len32b = (len + 3) / 4; - - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); - + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len); + ep->xfer_buff += len; ep->xfer_count += len; } - - if (ep->xfer_count >= ep->xfer_len) + + if (ep->xfer_len <= ep->xfer_count) { - fifoemptymsk = 0x1 << epnum; - atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); // MBED PATCH + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; } - - return HAL_OK; + + return HAL_OK; } -// MBED PATCH + /** - * @brief Process the next RX fifo entry - * @param hpcd: PCD handle + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number * @retval HAL status */ -static HAL_StatusTypeDef PCD_ReadRxFifo(PCD_HandleTypeDef *hpcd) +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - USB_OTG_EPTypeDef *ep; - uint32_t temp = 0; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - temp = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT) + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT) - { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - return HAL_OK; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return HAL_OK; } -// MBED PATCH -#endif /* USB_OTG_FS */ + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + + if ((gSNPSiD == USB_OTG_CORE_ID_310A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) */ #if defined (USB) /** * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { - PCD_EPTypeDef *ep = NULL; - uint16_t count = 0; - uint8_t epindex = 0; - __IO uint16_t wIstr = 0; - __IO uint16_t wEPVal = 0; - + PCD_EPTypeDef *ep; + uint16_t count; + uint16_t wIstr; + uint16_t wEPVal; + uint8_t epindex; + /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { + wIstr = hpcd->Instance->ISTR; /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (epindex == 0) + + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) { /* DIR = 0 */ - + /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; - + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff += ep->xfer_count; - + /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; + hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; } - } else { /* DIR = 1 */ - + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) + + if ((wEPVal & USB_EP_SETUP) != 0U) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + ep->pmaadress, (uint16_t)ep->xfer_count); + + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Process SETUP Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) + + else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) + + if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); + + ep->xfer_buff += ep->xfer_count; + + /* Process Control Data OUT Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } @@ -1663,31 +2342,31 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) else { /* Decode and service non control endpoints interrupt */ - + /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { + if ((wEPVal & USB_EP_CTR_RX) != 0U) + { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - + /* OUT double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) + count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); } } else { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) { /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); } @@ -1695,99 +2374,71 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) else { /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + /* free EP OUT Buffer */ + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); } /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + ep->xfer_count += count; + ep->xfer_buff += count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { /* RX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, ep->num); +#else HAL_PCD_DataOutStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - + } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) + + if ((wEPVal & USB_EP_CTR_TX) != 0U) { ep = &hpcd->IN_ep[epindex]; - + /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } + /*multi-packet on the NON control IN endpoint*/ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - + ep->xfer_buff += ep->xfer_count; + /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); } - } + } } } return HAL_OK; } -#endif /* USB */ +#endif /* defined (USB) */ /** * @} */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* defined (USB) || defined (USB_OTG_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h index eb45993fb3..8bae5a2cfb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h @@ -6,67 +6,47 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PCD_H -#define __STM32L4xx_HAL_PCD_H +#ifndef STM32L4xx_HAL_PCD_H +#define STM32L4xx_HAL_PCD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" - + +#if defined (USB) || defined (USB_OTG_FS) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ /** @addtogroup PCD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PCD_Exported_Types PCD Exported Types * @{ */ - /** - * @brief PCD State structure definition - */ -typedef enum +/** + * @brief PCD State structure definition + */ +typedef enum { HAL_PCD_STATE_RESET = 0x00, HAL_PCD_STATE_READY = 0x01, @@ -76,86 +56,105 @@ typedef enum } PCD_StateTypeDef; /* Device LPM suspend state */ -typedef enum +typedef enum { LPM_L0 = 0x00, /* on */ LPM_L1 = 0x01, /* LPM L1 sleep */ LPM_L2 = 0x02, /* suspend */ LPM_L3 = 0x03, /* off */ -}PCD_LPM_StateTypeDef; +} PCD_LPM_StateTypeDef; -#if defined (USB) -/** - * @brief PCD double buffered endpoint direction - */ typedef enum { - PCD_EP_DBUF_OUT, - PCD_EP_DBUF_IN, - PCD_EP_DBUF_ERR, -}PCD_EP_DBUF_DIR; + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; -/** - * @brief PCD endpoint buffer number - */ -typedef enum +typedef enum { - PCD_EP_NOBUF, - PCD_EP_BUF0, - PCD_EP_BUF1 -}PCD_EP_BUF_NUM; -#endif /* USB */ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, +} PCD_BCD_MsgTypeDef; + +#if defined (USB) + +#endif /* defined (USB) */ #if defined (USB_OTG_FS) typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; typedef USB_OTG_EPTypeDef PCD_EPTypeDef; -#endif /* USB_OTG_FS */ - +#endif /* defined (USB_OTG_FS) */ #if defined (USB) typedef USB_TypeDef PCD_TypeDef; typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; -#endif /* USB */ +#endif /* defined (USB) */ -// Added for MBED PR #3062 +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - HAL_LockTypeDef Lock; -} PCD_EPLockDef; - -/** - * @brief PCD Handle Structure definition - */ -typedef struct -{ - PCD_TypeDef *Instance; /*!< Register base address */ + PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ - PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_FS) + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_FS) */ +#if defined (USB) + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB) */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ -// Added for MBED PR #3062 - PCD_EPLockDef EPLock[15]; __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - - - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ - + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } PCD_HandleTypeDef; /** * @} */ - + /* Include PCD HAL Extended module */ #include "stm32l4xx_hal_pcd_ex.h" @@ -167,116 +166,77 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_FULL 1 +#define PCD_SPEED_FULL USBD_FS_SPEED /** * @} */ - + /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ -#define PCD_PHY_EMBEDDED 1 +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U /** * @} */ -/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition * @{ */ -#ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 -#endif /* USBD_FS_TRDT_VALUE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /** * @} */ /** * @} - */ - + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ #if defined (USB_OTG_FS) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) - +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ ~(USB_OTG_PCGCCTL_STOPCLK) #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) - + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE) - -#endif /* USB_OTG_FS */ +#endif /* defined (USB_OTG_FS) */ #if defined (USB) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_WAKEUP_EXTI_LINE +#endif /* defined (USB) */ -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE) - -#endif /* USB */ - /** * @} */ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup PCD_Exported_Functions PCD Exported Functions * @{ */ @@ -286,9 +246,71 @@ typedef struct * @{ */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ +typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** * @} */ @@ -298,22 +320,22 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ - /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); /** * @} */ @@ -329,8 +351,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); // MBED PATCH -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); @@ -361,21 +382,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @{ */ #if defined (USB_OTG_FS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the USB EXTI Line */ -#endif /* USB_OTG_FS */ +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) */ #if defined (USB) -#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17Connected to the USB EXTI Line */ -#endif /* USB */ +#define USB_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB) */ /** * @} */ - #if defined (USB) /** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ @@ -383,22 +403,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_EP0MPS_64 DEP0CTL_MPS_64 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 #define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 /** * @} */ - + /** @defgroup PCD_ENDP PCD ENDP * @{ */ -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) +#define PCD_ENDP0 0U +#define PCD_ENDP1 1U +#define PCD_ENDP2 2U +#define PCD_ENDP3 3U +#define PCD_ENDP4 4U +#define PCD_ENDP5 5U +#define PCD_ENDP6 6U +#define PCD_ENDP7 7U /** * @} */ @@ -406,172 +426,187 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind * @{ */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U /** * @} */ -#endif /* USB */ +#endif /* defined (USB) */ /** * @} */ +#if defined (USB_OTG_FS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif +#endif /* defined (USB_OTG_FS) */ + /* Private macros ------------------------------------------------------------*/ -/** @addtogroup PCD_Private_Macros PCD Private Macros +/** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ #if defined (USB) +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 10) +#define USB_CNTRX_BLSIZE (0x1U << 15) + /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) /* ENDPOINT transfer */ #define USB_EP0StartXfer USB_EPStartXfer /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. * @retval None */ -#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Endpoint Type */ #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) /** * @brief free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir * @retval None */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ -{\ - if ((bDir) == PCD_EP_DBUF_OUT)\ - { /* OUT double buffered endpoint */\ - PCD_TX_DTOG((USBx), (bEpNum));\ - }\ - else if ((bDir) == PCD_EP_DBUF_IN)\ - { /* IN double buffered endpoint */\ - PCD_RX_DTOG((USBx), (bEpNum));\ - }\ -} - -/** - * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval EP_DBUF_OUT, EP_DBUF_IN, - * EP_DBUF_ERR if the endpoint counter not yet programmed. - */ -#define PCD_GET_DB_DIR(USBx, bEpNum)\ -{\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ - return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ - return(PCD_EP_DBUF_IN);\ - else\ - return(PCD_EP_DBUF_ERR);\ -} +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ +} while(0) /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ + register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0)\ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\ - } /* PCD_SET_EP_TX_STATUS */ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TX_STATUS */ /** * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state * @retval None */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ + register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_RX_STATUS */ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_RX_STATUS */ /** * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. * @retval None */ -#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ + register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ - } /* PCD_SET_EP_TXRX_STATUS */ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TXRX_STATUS */ /** * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval status */ #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) @@ -579,8 +614,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) @@ -588,8 +623,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval TRUE = endpoint in stall condition. */ #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ @@ -599,19 +634,30 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) +#define PCD_SET_EP_KIND(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ + } while(0) /* PCD_SET_EP_KIND */ + +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_EP_KIND */ /** * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -619,8 +665,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) @@ -628,77 +674,130 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_RX_EP_CTR */ + +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ + } while(0) /* PCD_CLEAR_TX_EP_CTR */ /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) -#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) +#define PCD_RX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ + } while(0) /* PCD_RX_DTOG */ +#define PCD_TX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ + } while(0) /* PCD_TX_DTOG */ /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - { \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - { \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } - +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_RX_DTOG */ + +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_TX_DTOG */ + /** * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. * @retval None */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_ADDRESS */ +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))) - -#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) /** * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ + register uint16_t *_wRegVal; \ + register uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ +} while(0) /* PCD_SET_EP_TX_ADDRESS */ + +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ + register uint16_t *_wRegVal; \ + register uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ +} while(0) /* PCD_SET_EP_RX_ADDRESS */ /** * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval address of the buffer. */ #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -706,92 +805,116 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. * @retval None */ -#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ - { \ - (wNBlocks)--;\ - } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ - }/* PCD_CALC_BLK32 */ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ + (wNBlocks) = (wCount) >> 5; \ + *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ + } while(0) /* PCD_CALC_BLK32 */ -#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ - { \ - (wNBlocks)++;\ - } \ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ - }/* PCD_CALC_BLK2 */ +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \ + (wNBlocks) = (wCount) >> 1; \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + } while(0) /* PCD_CALC_BLK2 */ -#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if((wCount) > 62) \ - { \ - PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ - } \ - else \ - { \ - PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ - } \ - }/* PCD_SET_EP_CNT_RX_REG */ +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \ + uint32_t wNBlocks; \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if((wCount) < 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \ + } \ + } while(0) /* PCD_SET_EP_CNT_RX_REG */ -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + uint16_t *pdwReg; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ + } while(0) /** * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. * @retval None */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + *_wRegVal = (uint16_t)(wCount); \ +} while(0) +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ +} while(0) /** * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval Counter value */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) /** * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \ + PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ + } while(0) /* PCD_SET_EP_DBUF0_ADDR */ +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \ + PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF1_ADDR */ /** * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @param wBuf0Addr: buffer 0 address. * @param wBuf1Addr = buffer 1 address. * @retval None */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ - PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ - PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ - } /* PCD_SET_EP_DBUF_ADDR */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF_ADDR */ /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) @@ -799,62 +922,66 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value * @retval None */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \ + if ((bDir) == 0U) \ /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ - else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } /* SetEPDblBuf0Count*/ + { \ + PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + } \ + } while(0) /* SetEPDblBuf0Count*/ -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - {/* OUT endpoint */ \ - PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ - } \ - else if((bDir) == PCD_EP_DBUF_IN)\ - {/* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf1Count */ +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ + register uint32_t _wBase = (uint32_t)(USBx); \ + uint16_t *_wEPRegVal; \ + \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + _wBase += (uint32_t)(USBx)->BTABLE; \ + _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + *_wEPRegVal = (uint16_t)(wCount); \ + } \ + } \ + } while(0) /* SetEPDblBuf1Count */ -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } /* PCD_SET_EP_DBUF_CNT */ + } while(0) /* PCD_SET_EP_DBUF_CNT */ /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. * @retval None */ #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) -#endif /* USB */ +#endif /* defined (USB) */ -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) - -/** @defgroup PCD_Instance_definition PCD Instance definition - * @{ - */ -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE -/** - * @} - */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx */ - /** * @} */ @@ -866,18 +993,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** * @} */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ #ifdef __cplusplus } #endif - -#endif /* __STM32L4xx_HAL_PCD_H */ +#endif /* STM32L4xx_HAL_PCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c index 8a3cc9a345..4900f5a992 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c @@ -2,40 +2,24 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.c * @author MCD Application Team - * @brief PCD Extended HAL module driver. - * This file provides firmware functions to manage the following + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Extended features functions * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -51,12 +35,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - +#if defined (USB) || defined (USB_OTG_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -67,14 +46,14 @@ /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions * @{ */ - + /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions + * @brief PCDEx control functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Update FIFO configuration @@ -84,199 +63,241 @@ #if defined (USB_OTG_FS) /** * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { - uint8_t index = 0; - uint32_t Tx_Offset = 0; + uint8_t i; + uint32_t Tx_Offset; /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: + When a TxFIFO is not used, the Configuration should be as follows: case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) --> Txm can use the space allocated for Txn. case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top + The FIFO is used optimally when used TxFIFOs are allocated in the top of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - + Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) + + if (fifo == 0U) { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; } else { Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (index = 0; index < (fifo - 1); index++) + for (i = 0U; i < (fifo - 1U); i++) { - Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); } - + /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; } - + return HAL_OK; } /** * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo + * @param hpcd PCD handle + * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) { hpcd->Instance->GRXFSIZ = size; - + return HAL_OK; } /** * @brief Activate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; hpcd->LPM_State = LPM_L0; USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - return HAL_OK; + return HAL_OK; } /** * @brief Deactivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; + + return HAL_OK; } + /** * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t tickstart = HAL_GetTick(); - - /* Start BCD When device is connected */ - if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) - { - /* Enable DCD : Data Contact Detect */ - USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) + + /* Enable DCD : Data Contact Detect */ + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + + /* Wait Detect flag or a timeout is happen*/ + while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > 1000U) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; } - - /* Right response got */ - HAL_Delay(100); - - /* Check Detect flag*/ - if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - - /*Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(100); - - if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) - { - /* Case of Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } - else - { - /* start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(100); - - if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) - { - /* case Dedicated Charging Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* case Charging Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - } - } - /* Battery Charging capability discovery finished */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); } + + /* Right response got */ + HAL_Delay(200U); + + /* Check Detect flag*/ + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + /*Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + HAL_Delay(50U); + + if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) + { + /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(50U); + + if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) + { + /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } /** * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = ENABLE; - USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); - - return HAL_OK; + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Power Down USB tranceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Enable Battery charging */ + USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + + hpcd->battery_charging_active = 1U; + + return HAL_OK; } /** * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); - return HAL_OK; -} -#endif /* USB_OTG_FS */ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + + /* Disable Battery charging */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + + hpcd->battery_charging_active = 0U; + + return HAL_OK; +} + +#endif /* defined (USB_OTG_FS) */ #if defined (USB) /** * @brief Configure PMA for EP - * @param hpcd : Device instance - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind + * @param hpcd Device instance + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind * USB_SNG_BUF: Single Buffer used * USB_DBL_BUF: Double Buffer used * @param pmaadress: EP address in The PMA: In case of single buffer endpoint @@ -289,200 +310,228 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress) - { - PCD_EPTypeDef *ep = NULL; - + PCD_EPTypeDef *ep; + /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; } else { ep = &hpcd->OUT_ep[ep_addr]; } - + /* Here we check if the endpoint is single or double Buffer*/ if (ep_kind == PCD_SNG_BUF) { - /*Single Buffer*/ - ep->doublebuffer = 0; - /*Configure te PMA*/ + /* Single Buffer */ + ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } - else /*USB_DBL_BUF*/ + else /* USB_DBL_BUF */ { - /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; - /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); } - - return HAL_OK; + + return HAL_OK; } /** * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = ENABLE; - - USBx->BCDR |= (USB_BCDR_BCDEN); + hpcd->battery_charging_active = 1U; + /* Enable DCD : Data Contact Detect */ - USBx->BCDR |= (USB_BCDR_DCDEN); - - return HAL_OK; + USBx->BCDR &= ~(USB_BCDR_PDEN); + USBx->BCDR &= ~(USB_BCDR_SDEN); + USBx->BCDR |= USB_BCDR_DCDEN; + + return HAL_OK; } /** * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - + hpcd->battery_charging_active = 0U; + USBx->BCDR &= ~(USB_BCDR_BCDEN); - return HAL_OK; + + return HAL_OK; } /** * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; uint32_t tickstart = HAL_GetTick(); - + /* Wait Detect flag or a timeout is happen*/ - while ((USBx->BCDR & USB_BCDR_DCDET) == 0) + while ((USBx->BCDR & USB_BCDR_DCDET) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) + if ((HAL_GetTick() - tickstart) > 1000U) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + return; } } - HAL_Delay(300); - + HAL_Delay(200U); + /* Data Pin Contact ? Check Detect flag */ - if (USBx->BCDR & USB_BCDR_DCDET) + if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - /* Primary detection: checks if connected to Standard Downstream Port +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->BCDR &= ~(USB_BCDR_DCDEN); + HAL_Delay(50U); USBx->BCDR |= (USB_BCDR_PDEN); - HAL_Delay(300); - + HAL_Delay(50U); + /* If Charger detect ? */ - if (USBx->BCDR & USB_BCDR_PDET) + if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) { - /* Start secondary detection to check connection to Charging Downstream + /* Start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ USBx->BCDR &= ~(USB_BCDR_PDEN); + HAL_Delay(50U); USBx->BCDR |= (USB_BCDR_SDEN); - HAL_Delay(300); - + HAL_Delay(50U); + /* If CDP ? */ - if (USBx->BCDR & USB_BCDR_SDET) + if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) { /* Dedicated Downstream Port DCP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Charging Downstream Port CDP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - - /* Battery Charging capability discovery finished - Start Enumeration*/ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else /* NO */ { /* Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } + + /* Battery Charging capability discovery finished Start Enumeration */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } + /** * @brief Activate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) { USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; + hpcd->lpm_active = 1U; hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - - - return HAL_OK; + + USBx->LPMCSR |= USB_LPMCSR_LMPEN; + USBx->LPMCSR |= USB_LPMCSR_LPMACK; + + return HAL_OK; } /** * @brief Deactivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) { - USB_TypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - - USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN); - USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK); - - return HAL_OK; + USB_TypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + + USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN); + USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK); + + return HAL_OK; } -#endif /* USB */ +#endif /* defined (USB) */ /** * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ +{ /* Prevent unused argument(s) compilation warning */ UNUSED(hpcd); UNUSED(msg); /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ + */ } /** * @brief Send BatteryCharging message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) @@ -493,7 +542,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /* NOTE : This function should not be modified, when the callback is needed, the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ + */ } /** @@ -503,13 +552,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* defined (USB) || defined (USB_OTG_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h index f27c8b6a4a..c3c7703610 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h @@ -2,54 +2,33 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.h * @author MCD Application Team - * @brief Header file of PCD HAL module. + * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PCD_EX_H -#define __STM32L4xx_HAL_PCD_EX_H +#ifndef STM32L4xx_HAL_PCD_EX_H +#define STM32L4xx_HAL_PCD_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + +#if defined (USB) || defined (USB_OTG_FS) /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -58,23 +37,6 @@ * @{ */ /* Exported types ------------------------------------------------------------*/ -typedef enum -{ - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ -}PCD_LPM_MsgTypeDef; - -typedef enum -{ - PCD_BCD_ERROR = 0xFF, - PCD_BCD_CONTACT_DETECTION = 0xFE, - PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, - PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, - PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, - PCD_BCD_DISCOVERY_COMPLETED = 0x00, - -}PCD_BCD_MsgTypeDef; - /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -85,52 +47,51 @@ typedef enum * @{ */ -#if defined(USB_OTG_FS) +#if defined (USB_OTG_FS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#endif /* USB_OTG_FS */ +#endif /* defined (USB_OTG_FS) */ #if defined (USB) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); -#endif /* USB */ +#endif /* defined (USB) */ + HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); + + HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); + void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} - */ - -/** - * @} - */ - -/** - * @} - */ + */ /** * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_PCD_EX_H */ +#endif /* STM32L4xx_HAL_PCD_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c index 3f5877b4d9..bee73b022b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c @@ -11,29 +11,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -53,19 +37,19 @@ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Defines PWR Private Defines * @{ */ - + /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ - */ -#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ -#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ -#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ +#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ +#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ +#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ /** * @} */ @@ -73,7 +57,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -83,7 +67,7 @@ * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -107,30 +91,30 @@ void HAL_PWR_DeInit(void) } /** - * @brief Enable access to the backup domain + * @brief Enable access to the backup domain * (RTC registers, RTC backup data registers). - * @note After reset, the backup domain is protected against + * @note After reset, the backup domain is protected against * possible unwanted write accesses. * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. * In order to set or modify the RTC clock, the backup domain access must be - * disabled. + * disabled. * @note LSEON bit that switches on and off the LSE crystal belongs as well to the - * back-up domain. + * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { - SET_BIT(PWR->CR1, PWR_CR1_DBP); + SET_BIT(PWR->CR1, PWR_CR1_DBP); } /** * @brief Disable access to the backup domain - * (RTC registers, RTC backup data registers). + * (RTC registers, RTC backup data registers). * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); } @@ -150,7 +134,7 @@ void HAL_PWR_DisableBkUpAccess(void) =============================================================================== ##### Peripheral Control functions ##### =============================================================================== - + [..] *** PVD configuration *** ========================= @@ -163,17 +147,17 @@ void HAL_PWR_DisableBkUpAccess(void) line16 and can generate an interrupt if enabled. This is done through __HAL_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. - - + + *** WakeUp pin configuration *** ================================ [..] - (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. - The polarity of these pins can be set to configure event detection on high + (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. + The polarity of these pins can be set to configure event detection on high level (rising edge) or low level (falling edge). - + *** Low Power modes configuration *** ===================================== [..] @@ -183,8 +167,8 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. - (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. - (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. + (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. + (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. @@ -193,8 +177,8 @@ void HAL_PWR_DisableBkUpAccess(void) ========================== [..] (+) Entry: (from main run mode) - (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. - + (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. + (+) Exit: (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency be increased above 2 MHz. @@ -203,90 +187,90 @@ void HAL_PWR_DisableBkUpAccess(void) *** Sleep mode / Low-power sleep mode *** ========================================= [..] - (+) Entry: + (+) Entry: The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API - in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. - (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. + (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). - In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. + In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - + (+) WFI Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) or any wake-up event. - + (+) WFE Exit: - (++) Any wake-up event such as an EXTI line configured in event mode. - - [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, - the MCU is in Low-power Run mode. + (++) Any wake-up event such as an EXTI line configured in event mode. + + [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, + the MCU is in Low-power Run mode. *** Stop 0, Stop 1 and Stop 2 modes *** =============================== [..] - (+) Entry: + (+) Entry: The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). - (++) HAL_PWREx_EnterSTOP2Mode() for mode 2. + (++) HAL_PWREx_EnterSTOP2Mode() for mode 2. (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON (++) PWR_LOWPOWERREGULATOR_ON (+) Exit (interrupt or event-triggered, specified when entering STOP mode): (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction - + (+) WFI Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt mode. - (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts - when programmed in wakeup mode. - (+) WFE Exit: + (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts + when programmed in wakeup mode. + (+) WFE Exit: (++) Any EXTI Line (Internal or External) configured in Event mode. - - [..] + + [..] When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode - depending on the LPR bit setting. - When exiting Stop 2 mode, the MCU is in Run mode. + depending on the LPR bit setting. + When exiting Stop 2 mode, the MCU is in Run mode. *** Standby mode *** ==================== [..] - The Standby mode offers two options: + The Standby mode offers two options: (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). - SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers - and Standby circuitry. + SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers + and Standby circuitry. (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). - SRAM and register contents are lost except for the RTC registers, RTC backup registers + SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry. - (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. - SRAM1 and register contents are lost except for registers in the Backup domain and - Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - to set RRS bit. - + (++) Entry: + (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. + SRAM1 and register contents are lost except for registers in the Backup domain and + Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API + to set RRS bit. + (++) Exit: - (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - + [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. - + *** Shutdown mode *** ====================== [..] - In Shutdown mode, + In Shutdown mode, voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. SRAM and registers contents are lost except for backup domain registers. - (+) Entry: + (+) Entry: The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. - + (+) Exit: - (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin. - + [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. @@ -298,7 +282,7 @@ void HAL_PWR_DisableBkUpAccess(void) an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes - + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. @@ -318,7 +302,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). - * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD + * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD * configuration information. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each @@ -333,11 +317,11 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) /* Set PLS bits according to PVDLevel value */ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); - + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -345,24 +329,24 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } - + return HAL_OK; } @@ -373,7 +357,7 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) */ void HAL_PWR_EnablePVD(void) { - SET_BIT(PWR->CR2, PWR_CR2_PVDE); + SET_BIT(PWR->CR2, PWR_CR2_PVDE); } /** @@ -382,7 +366,7 @@ void HAL_PWR_EnablePVD(void) */ void HAL_PWR_DisablePVD(void) { - CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); } @@ -391,46 +375,46 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enable the WakeUp PINx functionality. * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values which set the default polarity + * This parameter can be one of the following legacy values which set the default polarity * i.e. detection on high level (rising edge): * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * + * * or one of the following value where the user can explicitly specify the enabled pin and - * the chosen polarity: - * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + * the chosen polarity: + * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) { - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); - + MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + /* Enable wake-up pin */ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); - + } /** * @brief Disable the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); + CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); } @@ -440,22 +424,22 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) - * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet - * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set - * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the + * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) + * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet + * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set + * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWR_EnterSLEEPMode() API. - * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in - * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. + * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWR_EnterSLEEPMode() API. + * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in + * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction - * @note When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) @@ -470,8 +454,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) /* If in low-power run mode at this point, exit it */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { - HAL_PWREx_DisableLowPowerRunMode(); - } + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + { + return ; + } + } /* Regulator now in main mode. */ } else @@ -480,13 +467,13 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) The system clock frequency must be below 2 MHz at this point. */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) { - HAL_PWREx_EnableLowPowerRunMode(); - } - } - + HAL_PWREx_EnableLowPowerRunMode(); + } + } + /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - + /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { @@ -508,18 +495,18 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @brief Enter Stop mode * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running * on devices where only "Stop mode" is mentioned with main or low power regulator ON. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. - * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). + * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note When the voltage regulator operates in low power mode (Stop 1), an additional * startup delay is incurred when waking up. * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption @@ -527,7 +514,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. @@ -538,7 +525,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); - + if(Regulator == PWR_LOWPOWERREGULATOR_ON) { HAL_PWREx_EnterSTOP1Mode(STOPEntry); @@ -551,20 +538,20 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /** * @brief Enter Standby mode. - * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched + * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched * off. The voltage regulator is disabled, except when SRAM2 content is preserved - * in which case the regulator is in low-power mode. - * SRAM1 and register contents are lost except for registers in the Backup domain and - * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - * to set RRS bit. - * The BOR is available. + * in which case the regulator is in low-power mode. + * SRAM1 and register contents are lost except for registers in the Backup domain and + * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API + * to set RRS bit. + * The BOR is available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the * same. * These states are effective in Standby mode only if APC bit is set through - * HAL_PWREx_EnablePullUpPullDownConfig() API. + * HAL_PWREx_EnablePullUpPullDownConfig() API. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) @@ -586,11 +573,11 @@ void HAL_PWR_EnterSTANDBYMode(void) /** - * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. + * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) @@ -601,9 +588,9 @@ void HAL_PWR_EnableSleepOnExit(void) /** - * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) @@ -615,8 +602,8 @@ void HAL_PWR_DisableSleepOnExit(void) /** - * @brief Enable CORTEX M4 SEVONPEND bit. - * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes + * @brief Enable CORTEX M4 SEVONPEND bit. + * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ @@ -628,9 +615,9 @@ void HAL_PWR_EnableSEVOnPend(void) /** - * @brief Disable CORTEX M4 SEVONPEND bit. - * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. + * @brief Disable CORTEX M4 SEVONPEND bit. + * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h index f33df34e85..3721d62922 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -52,7 +36,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ @@ -106,12 +90,12 @@ typedef struct #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ - - + + /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode @@ -140,7 +124,7 @@ typedef struct /** * @} */ - + /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line * @{ @@ -152,7 +136,7 @@ typedef struct /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line * @{ - */ + */ #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ /** * @} @@ -179,16 +163,19 @@ typedef struct * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event * was received from the WKUP pin 4. * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event - * was received from the WKUP pin 5. + * was received from the WKUP pin 5. * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system * entered StandBy mode. + * @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates + * that external switch can be closed to connect to the external SMPS, when the Range 2 + * of internal regulator is ready. * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on * the internal wakeup line. - * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the + * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the * low-power regulator is ready. - * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the - * regulator is ready in main mode or is in low-power mode. - * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready + * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the + * regulator is ready in main mode or is in low-power mode. + * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready * in the selected voltage range or is still changing to the required voltage level. * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is * below or above the selected PVD threshold. @@ -196,13 +183,13 @@ typedef struct * is below or above PVM1 threshold (applicable when USB feature is supported). @if STM32L486xx * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is - * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). + * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). @endif * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is - * is below or above PVM3 threshold. + * is below or above PVM3 threshold. * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is - * is below or above PVM4 threshold. - * + * is below or above PVM4 threshold. + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ @@ -225,7 +212,7 @@ typedef struct * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system * entered Standby mode. - * @retval None + * @retval None */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ (PWR->SCR = (__FLAG__)) :\ @@ -321,7 +308,7 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @addtogroup PWR_Private_Macros PWR Private Macros @@ -332,25 +319,25 @@ typedef struct ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - + #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) - + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) + #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) - + #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) - + /** * @} - */ + */ /* Include PWR HAL Extended module */ #include "stm32l4xx_hal_pwr_ex.h" @@ -360,11 +347,11 @@ typedef struct /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - + /* Initialization and de-initialization functions *******************************/ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); @@ -374,7 +361,7 @@ void HAL_PWR_DisableBkUpAccess(void); * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ @@ -404,10 +391,6 @@ void HAL_PWR_PVDCallback(void); /** * @} */ - -/** - * @} - */ /** * @} @@ -416,7 +399,11 @@ void HAL_PWR_PVDCallback(void); /** * @} */ - + +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c index 1c08c0feff..220939faea 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c @@ -7,33 +7,17 @@ * functionalities of the Power Controller (PWR) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -55,7 +39,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ @@ -72,10 +56,10 @@ /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ - + /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask * @{ - */ + */ #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ @@ -83,16 +67,16 @@ /** * @} */ - + /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value * @{ - */ -#define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ + */ +#define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */ /** * @} */ - - + + /** * @} @@ -104,7 +88,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - + /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ @@ -121,13 +105,13 @@ @endverbatim * @{ */ - + /** * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) - */ + */ uint32_t HAL_PWREx_GetVoltageRange(void) { #if defined(PWR_CR5_R1MODE) @@ -146,10 +130,10 @@ uint32_t HAL_PWREx_GetVoltageRange(void) } #else return (PWR->CR1 & PWR_CR1_VOS); -#endif +#endif } - + /** * @brief Configure the main internal regulator output voltage. @@ -158,28 +142,28 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * This parameter can be one of the following values: @if STM32L4S9xx * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, - * typical output voltage at 1.2 V, - * system frequency up to 120 MHz. + * typical output voltage at 1.2 V, + * system frequency up to 120 MHz. @endif * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, + * typical output voltage at 1.2 V, * system frequency up to 80 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, + * typical output voltage at 1.0 V, * system frequency up to 26 MHz. * @note When moving from Range 1 to Range 2, the system frequency must be decreased to * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 2 to Range 1, the system frequency can be increased to * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For - * some devices, the system frequency can be increased up to 120 MHz. + * some devices, the system frequency can be increased up to 120 MHz. * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be * cleared before returning the status. If the flag is not cleared within - * 50 microseconds, HAL_TIMEOUT status is reported. + * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { - uint32_t wait_loop_index = 0; + uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); @@ -191,21 +175,21 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - + /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; - } - } + } + } /* If current range is range 1 normal or boost mode */ else { @@ -220,36 +204,36 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - + /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; - } - } + } + } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - } + } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); /* No need to wait for VOSF to be cleared for this transition */ - /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ + /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } - + #else /* If Set Range 1 */ @@ -259,10 +243,10 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } @@ -281,47 +265,47 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No need to wait for VOSF to be cleared for this transition */ } } -#endif - +#endif + return HAL_OK; -} +} /** * @brief Enable battery charging. - * When VDD is present, charge the external battery on VBAT thru an internal resistor. + * When VDD is present, charge the external battery on VBAT thru an internal resistor. * @param ResistorSelection: specifies the resistor impedance. * This parameter can be one of the following values: * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor - * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor * @retval None */ void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) { assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); - + /* Specify resistor selection */ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); - + /* Enable battery charging */ SET_BIT(PWR->CR4, PWR_CR4_VBE); } /** - * @brief Disable battery charging. + * @brief Disable battery charging. * @retval None */ void HAL_PWREx_DisableBatteryCharging(void) { - CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); -} + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} #if defined(PWR_CR2_USV) /** - * @brief Enable VDDUSB supply. - * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. * @retval None */ void HAL_PWREx_EnableVddUSB(void) @@ -331,7 +315,7 @@ void HAL_PWREx_EnableVddUSB(void) /** - * @brief Disable VDDUSB supply. + * @brief Disable VDDUSB supply. * @retval None */ void HAL_PWREx_DisableVddUSB(void) @@ -342,8 +326,8 @@ void HAL_PWREx_DisableVddUSB(void) #if defined(PWR_CR2_IOSV) /** - * @brief Enable VDDIO2 supply. - * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. + * @brief Enable VDDIO2 supply. + * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. * @retval None */ void HAL_PWREx_EnableVddIO2(void) @@ -353,7 +337,7 @@ void HAL_PWREx_EnableVddIO2(void) /** - * @brief Disable VDDIO2 supply. + * @brief Disable VDDIO2 supply. * @retval None */ void HAL_PWREx_DisableVddIO2(void) @@ -364,7 +348,7 @@ void HAL_PWREx_DisableVddIO2(void) /** - * @brief Enable Internal Wake-up Line. + * @brief Enable Internal Wake-up Line. * @retval None */ void HAL_PWREx_EnableInternalWakeUpLine(void) @@ -374,7 +358,7 @@ void HAL_PWREx_EnableInternalWakeUpLine(void) /** - * @brief Disable Internal Wake-up Line. + * @brief Disable Internal Wake-up Line. * @retval None */ void HAL_PWREx_DisableInternalWakeUpLine(void) @@ -386,27 +370,29 @@ void HAL_PWREx_DisableInternalWakeUpLine(void) /** * @brief Enable GPIO pull-up state in Standby and Shutdown modes. - * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in - * pull-up state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PDy bit of PWR_PDCRx register is cleared unless it is reserved. - * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input + * parameter at the same time are set. + * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); @@ -452,9 +438,9 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); #if defined (STM32L496xx) || defined (STM32L4A6xx) CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else +#else CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif +#endif break; #if defined(GPIOI) case PWR_GPIO_I: @@ -463,10 +449,11 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } @@ -474,22 +461,24 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O * in pull-up state in Standby and Shutdown modes. - * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input + * parameter at the same time are reset. + * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: @@ -521,7 +510,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber CLEAR_BIT(PWR->PUCRG, GPIONumber); break; #endif - case PWR_GPIO_H: + case PWR_GPIO_H: CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); break; #if defined(GPIOI) @@ -530,40 +519,43 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Enable GPIO pull-down state in Standby and Shutdown modes. - * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in - * pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PUy bit of PWR_PUCRx register is cleared unless it is reserved. - * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input + * parameter at the same time are set. + * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: @@ -605,9 +597,9 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe case PWR_GPIO_H: #if defined (STM32L496xx) || defined (STM32L4A6xx) SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else +#else SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif +#endif CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); break; #if defined(GPIOI) @@ -617,33 +609,36 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Disable GPIO pull-down state in Standby and Shutdown modes. * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * in pull-down state in Standby and Shutdown modes. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * parameter at the same time are reset. + * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: @@ -651,7 +646,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb break; case PWR_GPIO_B: CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - break; + break; case PWR_GPIO_C: CLEAR_BIT(PWR->PDCRC, GPIONumber); break; @@ -665,7 +660,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb CLEAR_BIT(PWR->PDCRE, GPIONumber); break; #endif -#if defined(GPIOF) +#if defined(GPIOF) case PWR_GPIO_F: CLEAR_BIT(PWR->PDCRF, GPIONumber); break; @@ -678,32 +673,33 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb case PWR_GPIO_H: #if defined (STM32L496xx) || defined (STM32L4A6xx) CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else +#else CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - break; +#endif + break; #if defined(GPIOI) case PWR_GPIO_I: CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); break; #endif default: - return HAL_ERROR; + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Enable pull-up and pull-down configuration. - * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding - * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there - * is no conflict when setting PUy or PDy bit. + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there + * is no conflict when setting PUy or PDy bit. * @retval None */ void HAL_PWREx_EnablePullUpPullDownConfig(void) @@ -714,8 +710,8 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void) /** * @brief Disable pull-up and pull-down configuration. - * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. * @retval None */ void HAL_PWREx_DisablePullUpPullDownConfig(void) @@ -727,8 +723,8 @@ void HAL_PWREx_DisablePullUpPullDownConfig(void) /** * @brief Enable SRAM2 content retention in Standby mode. - * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in - * Standby mode and its content is kept. + * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in + * Standby mode and its content is kept. * @retval None */ void HAL_PWREx_EnableSRAM2ContentRetention(void) @@ -739,8 +735,8 @@ void HAL_PWREx_EnableSRAM2ContentRetention(void) /** * @brief Disable SRAM2 content retention in Standby mode. - * @note When RRS bit is reset, SRAM2 is powered off in Standby mode - * and its content is lost. + * @note When RRS bit is reset, SRAM2 is powered off in Standby mode + * and its content is lost. * @retval None */ void HAL_PWREx_DisableSRAM2ContentRetention(void) @@ -749,11 +745,61 @@ void HAL_PWREx_DisableSRAM2ContentRetention(void) } +#if defined(PWR_CR3_ENULP) +/** + * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes. + * @note All the other modes are not affected by this bit. + * @retval None + */ +void HAL_PWREx_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_ENULP); +} + + +/** + * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes. + * @note All the other modes are not affected by this bit + * @retval None + */ +void HAL_PWREx_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP); +} +#endif /* PWR_CR3_ENULP */ + + +#if defined(PWR_CR4_EXT_SMPS_ON) +/** + * @brief Enable the CFLDO working @ 0.95V. + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @retval None + */ +void HAL_PWREx_EnableExtSMPS_0V95(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Disable the CFLDO working @ 0.95V + * @note Before SMPS is switched off, the regulated voltage of the + * internal CFLDO shall be set to 1.00V. + * 1.00V. is also default operating Range 2 voltage. + * @retval None + */ +void HAL_PWREx_DisableExtSMPS_0V95(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} +#endif /* PWR_CR4_EXT_SMPS_ON */ + + #if defined(PWR_CR1_RRSTP) /** * @brief Enable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in - * Stop 2 mode and its content is kept. + * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in + * Stop 2 mode and its content is kept. * @retval None */ void HAL_PWREx_EnableSRAM3ContentRetention(void) @@ -764,8 +810,8 @@ void HAL_PWREx_EnableSRAM3ContentRetention(void) /** * @brief Disable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode - * and its content is lost. + * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode + * and its content is lost. * @retval None */ void HAL_PWREx_DisableSRAM3ContentRetention(void) @@ -776,7 +822,7 @@ void HAL_PWREx_DisableSRAM3ContentRetention(void) #if defined(PWR_CR3_DSIPDEN) /** - * @brief Enable pull-down activation on DSI pins. + * @brief Enable pull-down activation on DSI pins. * @retval None */ void HAL_PWREx_EnableDSIPinsPDActivation(void) @@ -786,7 +832,7 @@ void HAL_PWREx_EnableDSIPinsPDActivation(void) /** - * @brief Disable pull-down activation on DSI pins. + * @brief Disable pull-down activation on DSI pins. * @retval None */ void HAL_PWREx_DisableDSIPinsPDActivation(void) @@ -802,7 +848,7 @@ void HAL_PWREx_DisableDSIPinsPDActivation(void) */ void HAL_PWREx_EnablePVM1(void) { - SET_BIT(PWR->CR2, PWR_PVM_1); + SET_BIT(PWR->CR2, PWR_PVM_1); } /** @@ -811,7 +857,7 @@ void HAL_PWREx_EnablePVM1(void) */ void HAL_PWREx_DisablePVM1(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_1); + CLEAR_BIT(PWR->CR2, PWR_PVM_1); } #endif /* PWR_CR2_PVME1 */ @@ -823,7 +869,7 @@ void HAL_PWREx_DisablePVM1(void) */ void HAL_PWREx_EnablePVM2(void) { - SET_BIT(PWR->CR2, PWR_PVM_2); + SET_BIT(PWR->CR2, PWR_PVM_2); } /** @@ -832,7 +878,7 @@ void HAL_PWREx_EnablePVM2(void) */ void HAL_PWREx_DisablePVM2(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_2); + CLEAR_BIT(PWR->CR2, PWR_PVM_2); } #endif /* PWR_CR2_PVME2 */ @@ -843,7 +889,7 @@ void HAL_PWREx_DisablePVM2(void) */ void HAL_PWREx_EnablePVM3(void) { - SET_BIT(PWR->CR2, PWR_PVM_3); + SET_BIT(PWR->CR2, PWR_PVM_3); } /** @@ -852,7 +898,7 @@ void HAL_PWREx_EnablePVM3(void) */ void HAL_PWREx_DisablePVM3(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_3); + CLEAR_BIT(PWR->CR2, PWR_PVM_3); } @@ -862,7 +908,7 @@ void HAL_PWREx_DisablePVM3(void) */ void HAL_PWREx_EnablePVM4(void) { - SET_BIT(PWR->CR2, PWR_PVM_4); + SET_BIT(PWR->CR2, PWR_PVM_4); } /** @@ -871,7 +917,7 @@ void HAL_PWREx_EnablePVM4(void) */ void HAL_PWREx_DisablePVM4(void) { - CLEAR_BIT(PWR->CR2, PWR_PVM_4); + CLEAR_BIT(PWR->CR2, PWR_PVM_4); } @@ -881,8 +927,8 @@ void HAL_PWREx_DisablePVM4(void) * @brief Configure the Peripheral Voltage Monitoring (PVM). * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the * PVM configuration information. - * @note The API configures a single PVM according to the information contained - * in the input structure. To configure several PVMs, the API must be singly + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly * called for each PVM used. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each @@ -890,7 +936,9 @@ void HAL_PWREx_DisablePVM4(void) * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) -{ +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); @@ -901,12 +949,12 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_PVME1) case PWR_PVM_1: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM1_EXTI_DISABLE_IT(); - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -914,32 +962,32 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM1_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); } - break; -#endif /* PWR_CR2_PVME1 */ - -#if defined(PWR_CR2_PVME2) + break; +#endif /* PWR_CR2_PVME1 */ + +#if defined(PWR_CR2_PVME2) case PWR_PVM_2: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM2_EXTI_DISABLE_IT(); - __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -947,31 +995,31 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM2_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); } break; -#endif /* PWR_CR2_PVME2 */ - +#endif /* PWR_CR2_PVME2 */ + case PWR_PVM_3: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM3_EXTI_DISABLE_IT(); - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -979,30 +1027,30 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM3_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); } break; - + case PWR_PVM_4: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM4_EXTI_DISABLE_IT(); - __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ @@ -1010,71 +1058,70 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { __HAL_PWR_PVM4_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); } - break; - - default: - return HAL_ERROR; - - } + break; - - return HAL_OK; + default: + status = HAL_ERROR; + break; + } + + return status; } /** * @brief Enter Low-power Run mode - * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. - * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. + * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { /* Set Regulator parameter */ - SET_BIT(PWR->CR1, PWR_CR1_LPR); + SET_BIT(PWR->CR1, PWR_CR1_LPR); } /** * @brief Exit Low-power Run mode. - * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that - * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode * returns HAL_TIMEOUT status). The system clock frequency can then be - * increased above 2 MHz. + * increased above 2 MHz. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { - uint32_t wait_loop_index = 0; - + uint32_t wait_loop_index; + /* Clear LPR bit */ - CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); /* Wait until REGLPF is reset */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) { wait_loop_index--; } @@ -1082,7 +1129,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -1091,16 +1138,16 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) * @brief Enter Stop 0 mode. * @note In Stop 0 mode, main and low voltage regulators are ON. * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note By keeping the internal regulator ON during Stop 0 mode, the consumption * is higher although the startup time is reduced. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. @@ -1113,7 +1160,7 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Stop 0 mode with Main Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); @@ -1143,16 +1190,16 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) * @brief Enter Stop 1 mode. * @note In Stop 1 mode, only low power voltage regulator is ON. * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: @@ -1164,7 +1211,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Stop 1 mode with Low-Power Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); @@ -1194,18 +1241,18 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) * @brief Enter Stop 2 mode. * @note In Stop 2 mode, only low power voltage regulator is ON. * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability - * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after - * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only + * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability + * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after + * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only * to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. + * The BOR is available. * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. - * Otherwise, Stop 1 mode is entered. + * Otherwise, Stop 1 mode is entered. * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction @@ -1246,20 +1293,20 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) /** - * @brief Enter Shutdown mode. - * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched - * off. The voltage regulator is disabled and Vcore domain is powered off. + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. - * The BOR is not available. - * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * @retval None */ void HAL_PWREx_EnterSHUTDOWNMode(void) { - + /* Set Shutdown mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); - + /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); @@ -1276,13 +1323,13 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) /** * @brief This function handles the PWR PVD/PVMx interrupt request. - * @note This API should be called under the PVD_PVM_IRQHandler(). + * @note This API should be called under the PVD_PVM_IRQHandler(). * @retval None */ void HAL_PWREx_PVD_PVM_IRQHandler(void) { /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); @@ -1291,42 +1338,42 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void) __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } /* Next, successively check PVMx exti flags */ -#if defined(PWR_CR2_PVME1) - if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) +#if defined(PWR_CR2_PVME1) + if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM1 interrupt user callback */ HAL_PWREx_PVM1Callback(); - + /* Clear PVM1 exti pending bit */ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); } #endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) - if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) +#if defined(PWR_CR2_PVME2) + if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM2 interrupt user callback */ HAL_PWREx_PVM2Callback(); - + /* Clear PVM2 exti pending bit */ __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); } -#endif /* PWR_CR2_PVME2 */ - if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) +#endif /* PWR_CR2_PVME2 */ + if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM3 interrupt user callback */ HAL_PWREx_PVM3Callback(); - + /* Clear PVM3 exti pending bit */ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); } - if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) + if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U) { /* PWR PVM4 interrupt user callback */ HAL_PWREx_PVM4Callback(); - + /* Clear PVM4 exti pending bit */ __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); - } + } } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h index 2830478169..5cc2acc768 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -65,13 +49,13 @@ */ typedef struct { - uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. - This parameter can be a value of @ref PWREx_PVM_Type. - @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). @if STM32L486xx - @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). + @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). @endif - @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. + @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. @@ -80,7 +64,7 @@ typedef struct /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ @@ -94,12 +78,12 @@ typedef struct #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ /** * @} - */ + */ /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins * @{ - */ + */ #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ @@ -122,18 +106,18 @@ typedef struct /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type * @{ */ -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_PVME1) #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ #endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) +#if defined(PWR_CR2_PVME2) #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ #endif /* PWR_CR2_PVME2 */ #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ /** * @} - */ - + */ + /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode * @{ */ @@ -147,8 +131,8 @@ typedef struct /** * @} */ - - + + /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale * @{ @@ -162,7 +146,7 @@ typedef struct * @} */ - + /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection * @{ */ @@ -171,7 +155,7 @@ typedef struct /** * @} */ - + /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging * @{ */ @@ -179,8 +163,8 @@ typedef struct #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE /** * @} - */ - + */ + /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode * @{ */ @@ -202,64 +186,64 @@ typedef struct #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ /** * @} - */ - + */ + /** @defgroup PWREx_GPIO GPIO port * @{ */ -#define PWR_GPIO_A 0x00000000 /*!< GPIO port A */ -#define PWR_GPIO_B 0x00000001 /*!< GPIO port B */ -#define PWR_GPIO_C 0x00000002 /*!< GPIO port C */ -#if defined(GPIOD_BASE) -#define PWR_GPIO_D 0x00000003 /*!< GPIO port D */ +#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ +#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ +#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ +#if defined(GPIOD_BASE) +#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ #endif -#if defined(GPIOE_BASE) -#define PWR_GPIO_E 0x00000004 /*!< GPIO port E */ +#if defined(GPIOE_BASE) +#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ #endif -#if defined(GPIOF_BASE) -#define PWR_GPIO_F 0x00000005 /*!< GPIO port F */ +#if defined(GPIOF_BASE) +#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ #endif -#if defined(GPIOG_BASE) -#define PWR_GPIO_G 0x00000006 /*!< GPIO port G */ +#if defined(GPIOG_BASE) +#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ #endif -#define PWR_GPIO_H 0x00000007 /*!< GPIO port H */ -#if defined(GPIOI_BASE) -#define PWR_GPIO_I 0x00000008 /*!< GPIO port I */ +#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ +#if defined(GPIOI_BASE) +#define PWR_GPIO_I 0x00000008U /*!< GPIO port I */ #endif /** * @} - */ - + */ + /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines * @{ - */ -#if defined(PWR_CR2_PVME1) + */ +#if defined(PWR_CR2_PVME1) #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ #endif /* PWR_CR2_PVME2 */ #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ -#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ +#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ /** * @} - */ - + */ + /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines * @{ - */ -#if defined(PWR_CR2_PVME1) + */ +#if defined(PWR_CR2_PVME1) #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ #endif /* PWR_CR2_PVME2 */ #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ -#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ +#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ /** * @} - */ - + */ + /** @defgroup PWREx_Flag PWR Status Flags * Elements values convention: 0000 0000 0XXY YYYYb * - Y YYYY : Flag position in the XX register (5 bits) @@ -267,9 +251,9 @@ typedef struct * - 01: SR1 register * - 10: SR2 register * The only exception is PWR_FLAG_WU, encompassing all - * wake-up flags and set to PWR_SR1_WUF. - * @{ - */ + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ @@ -277,6 +261,9 @@ typedef struct #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ +#if defined(PWR_SR1_EXT_SMPS_RDY) +#define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */ +#endif /* PWR_SR1_EXT_SMPS_RDY */ #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */ #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ @@ -293,11 +280,11 @@ typedef struct #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ /** * @} - */ + */ /** * @} - */ + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros @@ -456,7 +443,7 @@ typedef struct __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) - + /** * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. * @retval None @@ -547,7 +534,7 @@ typedef struct __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) - + /** * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. * @retval None @@ -638,7 +625,7 @@ typedef struct __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) - + /** * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. * @retval None @@ -674,14 +661,14 @@ typedef struct * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, + * typical output voltage at 1.2 V, * system frequency up to 80 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, - * system frequency up to 26 MHz. + * typical output voltage at 1.0 V, + * system frequency up to 26 MHz. * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check * whether or not VOSF flag is cleared when moving from range 2 to range 1. User - * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. + * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. * @retval None */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ @@ -695,7 +682,7 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ @@ -716,7 +703,7 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ ((PIN) == PWR_WAKEUP_PIN5_LOW)) - + #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) @@ -730,14 +717,14 @@ typedef struct ((TYPE) == PWR_PVM_4)) #endif -#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_3) ||\ ((TYPE) == PWR_PVM_4)) #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ ((TYPE) == PWR_PVM_4)) -#endif +#endif #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ @@ -745,8 +732,8 @@ typedef struct ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) - + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) + #if defined(PWR_CR5_R1MODE) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ @@ -754,20 +741,26 @@ typedef struct #else #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#endif +#endif + - #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) - + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) - + ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) + #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) - - -#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + + +#if defined (STM32L412xx) || defined (STM32L422xx) +#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ + ((GPIO) == PWR_GPIO_B) ||\ + ((GPIO) == PWR_GPIO_C) ||\ + ((GPIO) == PWR_GPIO_D) ||\ + ((GPIO) == PWR_GPIO_H)) +#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ @@ -804,14 +797,14 @@ typedef struct /** * @} - */ - + */ + /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ - -/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @{ */ @@ -820,7 +813,7 @@ typedef struct uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); -void HAL_PWREx_DisableBatteryCharging(void); +void HAL_PWREx_DisableBatteryCharging(void); #if defined(PWR_CR2_USV) void HAL_PWREx_EnableVddUSB(void); void HAL_PWREx_DisableVddUSB(void); @@ -860,6 +853,14 @@ void HAL_PWREx_DisablePVM3(void); void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +#if defined(PWR_CR3_ENULP) +void HAL_PWREx_EnableBORPVD_ULP(void); +void HAL_PWREx_DisableBORPVD_ULP(void); +#endif /* PWR_CR3_ENULP */ +#if defined(PWR_CR4_EXT_SMPS_ON) +void HAL_PWREx_EnableExtSMPS_0V95(void); +void HAL_PWREx_DisableExtSMPS_0V95(void); +#endif /* PWR_CR4_EXT_SMPS_ON */ /* Low Power modes configuration functions ************************************/ @@ -871,7 +872,7 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSHUTDOWNMode(void); void HAL_PWREx_PVD_PVM_IRQHandler(void); -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_PVME1) void HAL_PWREx_PVM1Callback(void); #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c index 27ae77c567..a3fc073efb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c @@ -3,7 +3,7 @@ * @file stm32l4xx_hal_qspi.c * @author MCD Application Team * @brief QSPI HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). * + Initialization and de-initialization functions * + Indirect functional mode management @@ -24,14 +24,14 @@ [..] (#) As prerequisite, fill in the HAL_QSPI_MspInit() : (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). + (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt mode is used, enable and configure QuadSPI global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure + (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#) Configure the flash size, the clock prescaler, the fifo threshold, the clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function. @@ -39,47 +39,47 @@ *** Indirect functional mode *** ================================ [..] - (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() + (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() functions : (++) Instruction phase : the mode used and if present the instruction opcode. (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate + (++) Alternate-bytes phase : the mode used and if present the size and the alternate bytes values. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used and if present the number of bytes. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay if activated. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (#) If no data is required for the command, it is sent directly to the memory : (++) In polling mode, the output of the function is done when the transfer is complete. (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or + (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or HAL_QSPI_Transmit_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or + (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or HAL_QSPI_Receive_IT() after the command configuration : (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold + (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and + (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== [..] - (#) Configure the command sequence and the auto-polling functional mode using the + (#) Configure the command sequence and the auto-polling functional mode using the HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions : (++) Instruction phase : the mode used and if present the instruction opcode. (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate + (++) Alternate-bytes phase : the mode used and if present the size and the alternate bytes values. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay if activated. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), @@ -92,31 +92,31 @@ *** Memory-mapped functional mode *** ===================================== [..] - (#) Configure the command sequence and the memory-mapped functional mode using the + (#) Configure the command sequence and the memory-mapped functional mode using the HAL_QSPI_MemoryMapped() functions : (++) Instruction phase : the mode used and if present the instruction opcode. (++) Address phase : the mode used and the size. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate + (++) Alternate-bytes phase : the mode used and if present the size and the alternate bytes values. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay if activated. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. (++) The timeout activation and the timeout period. - (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on + (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer + (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. + (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. *** Control functions *** ========================= @@ -124,7 +124,67 @@ (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. - (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : QSPI MspInit. + (+) MspDeInitCallback : QSPI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : QSPI MspInit. + (+) MspDeInitCallback : QSPI MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init + and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit + or @ref HAL_QSPI_Init function. + + When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. *** Workarounds linked to Silicon Limitation *** ==================================================== @@ -136,37 +196,21 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) +#if defined(QUADSPI) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -177,14 +221,14 @@ * @{ */ #ifdef HAL_QSPI_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Constants QSPI Private Constants * @{ */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!Init.FlashSize)); assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); -#if defined(QUADSPI_CR_DFM) +#if defined(QUADSPI_CR_DFM) assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) @@ -271,25 +315,47 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); } #endif - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hqspi->Lock = HAL_UNLOCKED; +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ + hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; + hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; + hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + + if(hqspi->MspInitCallback == NULL) + { + hqspi->MspInitCallback = HAL_QSPI_MspInit; + } + + /* Init the low level hardware */ + hqspi->MspInitCallback(hqspi); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_QSPI_MspInit(hqspi); - +#endif + /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); + HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); } - + /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); @@ -297,31 +363,31 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) if(status == HAL_OK) { /* Configure QSPI Clock Prescaler and Sample Shift */ -#if defined(QUADSPI_CR_DFM) - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), - ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | +#if defined(QUADSPI_CR_DFM) + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); #else - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), - ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting)); #endif - + /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ __HAL_QSPI_ENABLE(hqspi); - + /* Set QSPI error code to none */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; /* Initialize the QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; } - + /* Release Lock */ __HAL_UNLOCK(hqspi); @@ -330,7 +396,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) } /** - * @brief De-Initialize the QSPI peripheral. + * @brief De-Initialize the QSPI peripheral. * @param hqspi : QSPI handle * @retval HAL status */ @@ -348,8 +414,18 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /* Disable the QSPI Peripheral Clock */ __HAL_QSPI_DISABLE(hqspi); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + if(hqspi->MspDeInitCallback == NULL) + { + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + } + + /* DeInit the low level hardware */ + hqspi->MspDeInitCallback(hqspi); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_QSPI_MspDeInit(hqspi); +#endif /* Set QSPI error code to none */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; @@ -368,14 +444,14 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_MspInit can be implemented in the user file - */ + */ } /** @@ -383,24 +459,24 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions - * @brief QSPI Transmit/Receive functions +/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief QSPI Transmit/Receive functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -429,19 +505,20 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT) != 0) && ((itsource & QSPI_IT_FT) !=0 )) + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) { data_reg = &hqspi->Instance->DR; if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { /* Transmission process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { - if (hqspi->TxXferCount > 0) + if (hqspi->TxXferCount > 0U) { /* Fill the FIFO until the threshold is reached */ - *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } else @@ -456,12 +533,13 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { /* Receiving Process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { - if (hqspi->RxXferCount > 0) + if (hqspi->RxXferCount > 0U) { /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -473,62 +551,75 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } } - + else + { + /* Nothing to do */ + } + /* FIFO Threshold callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->FifoThresholdCallback(hqspi); +#else HAL_QSPI_FifoThresholdCallback(hqspi); +#endif } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC) != 0) && ((itsource & QSPI_IT_TC) != 0)) + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); - + /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Disable the DMA channel */ __HAL_DMA_DISABLE(hqspi->hdma); } - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) + +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Clear Busy bit */ HAL_QSPI_Abort_IT(hqspi); #endif - + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; /* TX Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TxCpltCallback(hqspi); +#else HAL_QSPI_TxCpltCallback(hqspi); +#endif } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Disable the DMA channel */ __HAL_DMA_DISABLE(hqspi->hdma); } else { data_reg = &hqspi->Instance->DR; - while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0) + while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) { - if (hqspi->RxXferCount > 0) + if (hqspi->RxXferCount > 0U) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -539,7 +630,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); #endif @@ -548,7 +639,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; /* RX Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->RxCpltCallback(hqspi); +#else HAL_QSPI_RxCpltCallback(hqspi); +#endif } else if(hqspi->State == HAL_QSPI_STATE_BUSY) { @@ -556,10 +651,17 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; /* Command Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->CmdCpltCallback(hqspi); +#else HAL_QSPI_CmdCpltCallback(hqspi); +#endif } else if(hqspi->State == HAL_QSPI_STATE_ABORT) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -568,26 +670,38 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Abort called by the user */ /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else HAL_QSPI_AbortCpltCallback(hqspi); +#endif } - else + else { /* Abort due to an error (eg : DMA error) */ /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } + else + { + /* Nothing to do */ + } } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM) != 0) && ((itsource & QSPI_IT_SM) != 0)) + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); - + /* Check if the automatic poll mode stop is activated */ - if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0) + if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); @@ -597,29 +711,47 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* Status match callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->StatusMatchCallback(hqspi); +#else HAL_QSPI_StatusMatchCallback(hqspi); +#endif } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE) != 0) && ((itsource & QSPI_IT_TE) != 0)) + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); - + /* Disable all the QSPI Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Disable the DMA channel */ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hqspi->hdma); + if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) + { + /* Set error code to DMA */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } } else { @@ -627,23 +759,36 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO) != 0) && ((itsource & QSPI_IT_TO) != 0)) + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); - + /* Timeout callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TimeOutCallback(hqspi); +#else HAL_QSPI_TimeOutCallback(hqspi); +#endif + } + + else + { + /* Nothing to do */ } } /** - * @brief Set the command configuration. + * @brief Set the command configuration. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration @@ -652,9 +797,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) */ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -680,51 +825,51 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - + hqspi->State = HAL_QSPI_STATE_BUSY; + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + if (cmd->DataMode == QSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done + /* When there is no data phase, the transfer start as soon as the configuration is done so wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } } else { /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } } } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -733,7 +878,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe } /** - * @brief Set the command configuration in interrupt mode. + * @brief Set the command configuration in interrupt mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes @@ -741,9 +886,9 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe */ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -769,20 +914,20 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - + hqspi->State = HAL_QSPI_STATE_BUSY; + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - + if (status == HAL_OK) { if (cmd->DataMode == QSPI_DATA_NONE) @@ -790,13 +935,13 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); } - + /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + if (cmd->DataMode == QSPI_DATA_NONE) { - /* When there is no data phase, the transfer start as soon as the configuration is done + /* When there is no data phase, the transfer start as soon as the configuration is done so activate TC and TE interrupts */ /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -807,7 +952,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp else { /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -821,8 +966,8 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp } else { - status = HAL_BUSY; - + status = HAL_BUSY; + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -832,7 +977,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp } /** - * @brief Transmit an amount of data in blocking mode. + * @brief Transmit an amount of data in blocking mode. * @param hqspi : QSPI handle * @param pData : pointer to data buffer * @param Timeout : Timeout duration @@ -851,34 +996,35 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - + /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; - + /* Configure QSPI: CCR register with functional as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - while(hqspi->TxXferCount > 0) + while(hqspi->TxXferCount > 0U) { /* Wait until FT flag is set to send data */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); if (status != HAL_OK) - { + { break; } - *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } - + if (status == HAL_OK) { /* Wait until TC flag is set to go back in idle state */ @@ -888,16 +1034,16 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) + +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Clear Busy bit */ status = HAL_QSPI_Abort(hqspi); #endif } } - + /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } else { @@ -938,15 +1084,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; /* Configure QSPI: CCR register with functional as indirect read */ @@ -954,21 +1100,22 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - - while(hqspi->RxXferCount > 0) + + while(hqspi->RxXferCount > 0U) { /* Wait until FT or TC flag is set to read received data */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); if (status != HAL_OK) - { + { break; } - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } - + if (status == HAL_OK) { /* Wait until TC flag is set to go back in idle state */ @@ -979,7 +1126,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) +#if (defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ status = HAL_QSPI_Abort(hqspi); #endif @@ -987,7 +1134,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui } /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; + hqspi->State = HAL_QSPI_STATE_READY; } else { @@ -999,7 +1146,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui { status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1014,7 +1161,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ +{ HAL_StatusTypeDef status = HAL_OK; /* Process locked */ @@ -1030,19 +1177,19 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); } @@ -1084,26 +1231,26 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1121,7 +1268,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) } else { - status = HAL_BUSY; + status = HAL_BUSY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1131,31 +1278,30 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) } /** - * @brief Send an amount of data in non-blocking mode with DMA. + * @brief Send an amount of data in non-blocking mode with DMA. * @param hqspi : QSPI handle * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); - + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { - /* Clear the error code */ + /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) + + if(pData != NULL ) { /* Configure counters of the handle */ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) @@ -1164,9 +1310,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1176,27 +1322,31 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - hqspi->TxXferCount = (data_size >> 1); + hqspi->TxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } else { - hqspi->TxXferCount = (data_size >> 2); + hqspi->TxXferCount = (data_size >> 2U); } } - + else + { + /* Nothing to do */ + } + if (status == HAL_OK) { /* Update state */ @@ -1208,20 +1358,20 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /* Configure size and pointer of the handle */ hqspi->TxXferSize = hqspi->TxXferCount; hqspi->pTxBuffPtr = pData; - + /* Configure QSPI: CCR register with functional mode as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; /* Configure the direction of the DMA */ @@ -1229,18 +1379,27 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)((void*)&pData); - HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } } else { @@ -1253,7 +1412,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - status = HAL_BUSY; + status = HAL_BUSY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1263,32 +1422,31 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } /** - * @brief Receive an amount of data in non-blocking mode with DMA. + * @brief Receive an amount of data in non-blocking mode with DMA. * @param hqspi : QSPI handle * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number + * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number + * @note If DMA peripheral access is configured as word, the number * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); - + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { - /* Clear the error code */ + /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) + + if(pData != NULL ) { /* Configure counters of the handle */ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) @@ -1297,44 +1455,48 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on halfword + /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } else { - hqspi->RxXferCount = (data_size >> 1); + hqspi->RxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { - /* The number of data or the fifo threshold is not aligned on word + /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } else { - hqspi->RxXferCount = (data_size >> 2); + hqspi->RxXferCount = (data_size >> 2U); } } - + else + { + /* Nothing to do */ + } + if (status == HAL_OK) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); @@ -1344,14 +1506,14 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ + + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; /* Configure the direction of the DMA */ @@ -1359,23 +1521,32 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); /* Enable the DMA Channel */ - tmp = (uint32_t*)((void*)&pData); - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + { + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } } else @@ -1389,7 +1560,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else { - status = HAL_BUSY; + status = HAL_BUSY; /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1399,7 +1570,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } /** - * @brief Configure the QSPI Automatic Polling Mode in blocking mode. + * @brief Configure the QSPI Automatic Polling Mode in blocking mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information. * @param cfg : structure that contains the polling configuration information. @@ -1409,9 +1580,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData */ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -1441,47 +1612,47 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy assert_param(IS_QSPI_INTERVAL(cfg->Interval)); assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - + if (status == HAL_OK) { /* Configure QSPI: PSMAR register with the status match value */ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - + /* Configure QSPI: PSMKR register with the status mask value */ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - + /* Configure QSPI: PIR register with the interval value */ WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - - /* Configure QSPI: CR register with Match mode and Automatic stop enabled + + /* Configure QSPI: CR register with Match mode and Automatic stop enabled (otherwise there will be an infinite loop in blocking mode) */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); - + /* Call the configuration function */ cmd->NbData = cfg->StatusBytesSize; QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - + /* Wait until SM flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); - + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -1489,18 +1660,18 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Return function status */ - return status; + return status; } /** - * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. + * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information. * @param cfg : structure that contains the polling configuration information. @@ -1509,9 +1680,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy */ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -1542,35 +1713,35 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - + if (status == HAL_OK) { /* Configure QSPI: PSMAR register with the status match value */ WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - + /* Configure QSPI: PSMKR register with the status mask value */ WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - + /* Configure QSPI: PIR register with the interval value */ WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - + /* Configure QSPI: CR register with Match mode and Automatic stop mode */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), (cfg->MatchMode | cfg->AutomaticStop)); - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); @@ -1580,7 +1751,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI Transfer Error and status match Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); @@ -1593,18 +1764,18 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman } else { - status = HAL_BUSY; - + status = HAL_BUSY; + /* Process unlocked */ __HAL_UNLOCK(hqspi); } - + /* Return function status */ - return status; + return status; } /** - * @brief Configure the Memory Mapped mode. + * @brief Configure the Memory Mapped mode. * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information. * @param cfg : structure that contains the memory mapped configuration information. @@ -1613,9 +1784,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman */ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); - + /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -1643,53 +1814,53 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); - + /* Process locked */ __HAL_LOCK(hqspi); - + if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; - + /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - + if (status == HAL_OK) { /* Configure QSPI: CR register with timeout counter enable */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - + /* Configure QSPI: LPTR register with the low-power timeout value */ WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); /* Enable the QSPI TimeOut Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); } - + /* Call the configuration function */ QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); } } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Return function status */ - return status; + return status; } /** @@ -1757,14 +1928,14 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1787,14 +1958,14 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file - */ + */ } /** @@ -1841,25 +2012,246 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) the HAL_QSPI_TimeOutCallback could be implemented in the user file */ } +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User QSPI Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hqspi : QSPI handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID + * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID + * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID + * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID + * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID + * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID + * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID + * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID + * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID + * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID + * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID + * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + switch (CallbackId) + { + case HAL_QSPI_ERROR_CB_ID : + hqspi->ErrorCallback = pCallback; + break; + case HAL_QSPI_ABORT_CB_ID : + hqspi->AbortCpltCallback = pCallback; + break; + case HAL_QSPI_FIFO_THRESHOLD_CB_ID : + hqspi->FifoThresholdCallback = pCallback; + break; + case HAL_QSPI_CMD_CPLT_CB_ID : + hqspi->CmdCpltCallback = pCallback; + break; + case HAL_QSPI_RX_CPLT_CB_ID : + hqspi->RxCpltCallback = pCallback; + break; + case HAL_QSPI_TX_CPLT_CB_ID : + hqspi->TxCpltCallback = pCallback; + break; + case HAL_QSPI_RX_HALF_CPLT_CB_ID : + hqspi->RxHalfCpltCallback = pCallback; + break; + case HAL_QSPI_TX_HALF_CPLT_CB_ID : + hqspi->TxHalfCpltCallback = pCallback; + break; + case HAL_QSPI_STATUS_MATCH_CB_ID : + hqspi->StatusMatchCallback = pCallback; + break; + case HAL_QSPI_TIMEOUT_CB_ID : + hqspi->TimeOutCallback = pCallback; + break; + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = pCallback; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hqspi->State == HAL_QSPI_STATE_RESET) + { + switch (CallbackId) + { + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = pCallback; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hqspi); + return status; +} + +/** + * @brief Unregister a User QSPI Callback + * QSPI Callback is redirected to the weak (surcharged) predefined callback + * @param hqspi : QSPI handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID + * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID + * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID + * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID + * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID + * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID + * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID + * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID + * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID + * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID + * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID + * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + switch (CallbackId) + { + case HAL_QSPI_ERROR_CB_ID : + hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + break; + case HAL_QSPI_ABORT_CB_ID : + hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + break; + case HAL_QSPI_FIFO_THRESHOLD_CB_ID : + hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + break; + case HAL_QSPI_CMD_CPLT_CB_ID : + hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + break; + case HAL_QSPI_RX_CPLT_CB_ID : + hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + break; + case HAL_QSPI_TX_CPLT_CB_ID : + hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + break; + case HAL_QSPI_RX_HALF_CPLT_CB_ID : + hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; + break; + case HAL_QSPI_TX_HALF_CPLT_CB_ID : + hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; + break; + case HAL_QSPI_STATUS_MATCH_CB_ID : + hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + break; + case HAL_QSPI_TIMEOUT_CB_ID : + hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + break; + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = HAL_QSPI_MspInit; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hqspi->State == HAL_QSPI_STATE_RESET) + { + switch (CallbackId) + { + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = HAL_QSPI_MspInit; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hqspi); + return status; +} +#endif /** * @} */ -/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief QSPI control and State functions +/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief QSPI control and State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control and State functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. + (+) Check in run-time the state of the driver. (+) Check the error code set during last operation. (+) Abort any operation. - + @endverbatim * @{ */ @@ -1894,14 +2286,14 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart = HAL_GetTick(); - + /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -1912,24 +2304,27 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) { hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; } - } - + } + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if (status == HAL_OK) - { + if (status == HAL_OK) + { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Wait until BUSY flag is reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); } if (status == HAL_OK) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -1946,36 +2341,47 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { HAL_StatusTypeDef status = HAL_OK; - + /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_ABORT; + hqspi->State = HAL_QSPI_STATE_ABORT; /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort DMA channel */ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - HAL_DMA_Abort_IT(hqspi->hdma); - } + if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else + HAL_QSPI_AbortCpltCallback(hqspi); +#endif + } + } else { /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Enable the QSPI Transfer Complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } @@ -2009,16 +2415,16 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t { /* Synchronize init structure with new FIFO threshold value */ hqspi->Init.FifoThreshold = Threshold; - + /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); } else { - status = HAL_BUSY; + status = HAL_BUSY; } - + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -2032,51 +2438,102 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) { - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1); + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } +#if defined(QUADSPI_CR_DFM) +/** @brief Set FlashID. + * @param hqspi : QSPI handle. + * @param FlashID : Index of the flash memory to be accessed. + * This parameter can be a value of @ref QSPI_Flash_Select. + * @note The FlashID is ignored when dual flash mode is enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameter */ + assert_param(IS_QSPI_FLASH_ID(FlashID)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FlashID value */ + hqspi->Init.FlashID = FlashID; + + /* Configure QSPI FlashID */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +#endif /** * @} */ /** - * @brief DMA QSPI receive process complete callback. + * @} + */ + +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ + +/** + * @brief DMA QSPI receive process complete callback. * @param hdma : DMA handle * @retval None */ -static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) +static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->RxXferCount = 0; - + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); + hqspi->RxXferCount = 0U; + /* Enable the QSPI transfer complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** - * @brief DMA QSPI transmit process complete callback. + * @brief DMA QSPI transmit process complete callback. * @param hdma : DMA handle * @retval None */ -static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) +static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->TxXferCount = 0; - + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); + hqspi->TxXferCount = 0U; + /* Enable the QSPI transfer complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** - * @brief DMA QSPI receive process half complete callback. + * @brief DMA QSPI receive process half complete callback. * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); - HAL_QSPI_RxHalfCpltCallback(hqspi); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->RxHalfCpltCallback(hqspi); +#else + HAL_QSPI_RxHalfCpltCallback(hqspi); +#endif } /** @@ -2086,9 +2543,13 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TxHalfCpltCallback(hqspi); +#else HAL_QSPI_TxHalfCpltCallback(hqspi); +#endif } /** @@ -2096,19 +2557,20 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void QSPI_DMAError(DMA_HandleTypeDef *hdma) +static void QSPI_DMAError(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort the QSPI */ - HAL_QSPI_Abort_IT(hqspi); + (void)HAL_QSPI_Abort_IT(hqspi); + } /** @@ -2116,22 +2578,22 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) * @param hdma : DMA handle * @retval None */ -static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; if(hqspi->State == HAL_QSPI_STATE_ABORT) { /* DMA Abort called by QSPI abort */ /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Enable the QSPI Transfer Complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } @@ -2142,7 +2604,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) hqspi->State = HAL_QSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } @@ -2151,24 +2617,24 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) * @param hqspi : QSPI handle * @param Flag : Flag checked * @param State : Value of the flag expected + * @param Tickstart : Tick start value * @param Timeout : Duration of the timeout - * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { - /* Wait until flag is in expected state */ + /* Wait until flag is in expected state */ while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout)) + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hqspi->State = HAL_QSPI_STATE_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - + return HAL_ERROR; } } @@ -2195,7 +2661,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) { /* Configure QSPI: DLR register with the number of data to read or write */ - WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1)); + WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); } if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -2209,10 +2675,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with instruction, address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2225,10 +2691,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with instruction and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } @@ -2238,9 +2704,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with instruction and address ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2253,9 +2719,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with only instruction ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } @@ -2271,10 +2737,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2287,9 +2753,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with only alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } } @@ -2299,9 +2765,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /*---- Command with only address ----*/ /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressSize | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2316,9 +2782,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin if (cmd->DataMode != QSPI_DATA_NONE) { /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressMode | + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } } @@ -2326,6 +2792,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin } } +/** + * @} + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h index cef4014d75..1f10f89e88 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_QSPI_H -#define __STM32L4xx_HAL_QSPI_H +#ifndef STM32L4xx_HAL_QSPI_H +#define STM32L4xx_HAL_QSPI_H #ifdef __cplusplus extern "C" { @@ -44,7 +28,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" -#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) +#if defined(QUADSPI) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -52,63 +36,67 @@ /** @addtogroup QSPI * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup QSPI_Exported_Types QSPI Exported Types * @{ */ -/** - * @brief QSPI Init structure definition +/** + * @brief QSPI Init structure definition */ typedef struct { uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. - This parameter can be a number between 0 and 255 */ + This parameter can be a number between 0 and 255 */ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) This parameter can be a value between 1 and 16 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to + uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits - required to address the flash memory. The flash capacity can be up to 4GB - (addressed using 32 bits) in indirect mode, but the addressable space in + uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits + required to address the flash memory. The flash capacity can be up to 4GB + (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number + uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number of clock cycles which the chip select must remain high between commands. - This parameter can be a value of @ref QSPI_ChipSelectHighTime */ + This parameter can be a value of @ref QSPI_ChipSelectHighTime */ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ -#if defined(QUADSPI_CR_DFM) +#if defined(QUADSPI_CR_DFM) uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ uint32_t DualFlash; /* Specifies the Dual Flash Mode State - This parameter can be a value of @ref QSPI_DualFlash_Mode */ + This parameter can be a value of @ref QSPI_DualFlash_Mode */ #endif }QSPI_InitTypeDef; -/** - * @brief HAL QSPI State structures definition - */ +/** + * @brief HAL QSPI State structures definition + */ typedef enum { - HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ - HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ - HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ - HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ - HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ - HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ - HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ - HAL_QSPI_STATE_ABORT = 0x08, /*!< Peripheral with abort request ongoing */ - HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ + HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ + HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ + HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ + HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ + HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ + HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ + HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ + HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ + HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ }HAL_QSPI_StateTypeDef; -/** - * @brief QSPI Handle Structure definition - */ +/** + * @brief QSPI Handle Structure definition + */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +typedef struct __QSPI_HandleTypeDef +#else typedef struct +#endif { QUADSPI_TypeDef *Instance; /* QSPI registers base address */ QSPI_InitTypeDef Init; /* QSPI communication parameters */ @@ -122,11 +110,26 @@ typedef struct __IO HAL_LockTypeDef Lock; /* Locking object */ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ __IO uint32_t ErrorCode; /* QSPI Error code */ - uint32_t Timeout; /* Timeout for the QSPI memory access */ + uint32_t Timeout; /* Timeout for the QSPI memory access */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); + void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); + + void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); +#endif }QSPI_HandleTypeDef; -/** - * @brief QSPI Command structure definition +/** + * @brief QSPI Command structure definition */ typedef struct { @@ -151,25 +154,26 @@ typedef struct uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) This parameter can be a value of @ref QSPI_DataMode */ uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) - This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length + This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length until end of memory)*/ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of - system clock in DDR mode. Not available on STM32L4x6 devices but in future devices. + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. + Not available on all devices. This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ uint32_t SIOOMode; /* Specifies the send instruction only once mode This parameter can be a value of @ref QSPI_SIOOMode */ }QSPI_CommandTypeDef; -/** - * @brief QSPI Auto Polling mode configuration structure definition +/** + * @brief QSPI Auto Polling mode configuration structure definition */ typedef struct { uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. This parameter can be any value between 0 and 0xFFFFFFFF */ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. This parameter can be any value between 0 and 0xFFFF */ @@ -180,18 +184,44 @@ typedef struct uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. This parameter can be a value of @ref QSPI_AutomaticStop */ }QSPI_AutoPollingTypeDef; - -/** - * @brief QSPI Memory Mapped mode configuration structure definition + +/** + * @brief QSPI Memory Mapped mode configuration structure definition */ typedef struct { uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref QSPI_TimeOutActivation */ }QSPI_MemoryMappedTypeDef; +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL QSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ + HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ + HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ + HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ + HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ + HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ + HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ + HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ + HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ + HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ + + HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ + HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ +}HAL_QSPI_CallbackIDTypeDef; + +/** + * @brief HAL QSPI Callback pointer definition + */ +typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); +#endif /** * @} */ @@ -203,29 +233,32 @@ typedef struct /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ - */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */ + */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ +#endif /** * @} - */ + */ /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!State = HAL_QSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) +#endif /** @brief Enable the QSPI peripheral. * @param __HANDLE__ : specifies the QSPI Handle. * @retval None - */ + */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. @@ -449,8 +490,8 @@ typedef struct #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -463,8 +504,8 @@ typedef struct /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -476,8 +517,8 @@ typedef struct #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -486,12 +527,12 @@ typedef struct * @arg QSPI_IT_TE: QSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -501,11 +542,11 @@ typedef struct * @arg QSPI_FLAG_TE: QSPI Transfer error flag * @retval None */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -518,16 +559,26 @@ typedef struct * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup QSPI_Exported_Functions * @{ */ + +/** @addtogroup QSPI_Exported_Functions_Group1 + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); +/** + * @} + */ +/** @addtogroup QSPI_Exported_Functions_Group2 + * @{ + */ /* IO operation functions *****************************************************/ /* QSPI IRQ handler method */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); @@ -567,6 +618,18 @@ void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); /* QSPI memory-mapped mode */ void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/* QSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); +#endif +/** + * @} + */ + +/** @addtogroup QSPI_Exported_Functions_Group3 + * @{ + */ /* Peripheral Control and State functions ************************************/ HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); @@ -575,23 +638,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +#if defined(QUADSPI_CR_DFM) +HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); +#endif /** * @} */ -/* End of exported functions -------------------------------------------------*/ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Macros QSPI Private Macros -* @{ -*/ -#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) + * @{ + */ +#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) -#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16)) +#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) -#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) +#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ @@ -605,15 +675,15 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ ((CLKMODE) == QSPI_CLOCK_MODE_3)) -#if defined(QUADSPI_CR_DFM) -#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \ - ((FLASH) == QSPI_FLASH_ID_2)) - +#if defined(QUADSPI_CR_DFM) +#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ + ((FLASH_ID) == QSPI_FLASH_ID_2)) + #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ ((MODE) == QSPI_DUALFLASH_DISABLE)) -#endif -#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) +#endif +#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ @@ -625,7 +695,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) -#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) +#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ @@ -650,42 +720,43 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) -#if defined(QUADSPI_CCR_DHHC) +#if defined(QUADSPI_CCR_DHHC) #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) + #else #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) -#endif +#endif #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) -#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) +#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) -#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) +#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ - ((MODE) == QSPI_MATCH_MODE_OR)) + ((MODE) == QSPI_MATCH_MODE_OR)) #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ - ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) + ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) + ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) -#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) +#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) /** * @} -*/ +*/ /* End of private macros -----------------------------------------------------*/ /** * @} - */ + */ /** * @} - */ + */ #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ @@ -693,6 +764,6 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); } #endif -#endif /* __STM32L4xx_HAL_QSPI_H */ +#endif /* STM32L4xx_HAL_QSPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c index 50e2470772..f7eab11f8d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c @@ -38,29 +38,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -87,7 +71,11 @@ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#if defined(RCC_CSR_LSIPREDIV) +#define LSI_TIMEOUT_VALUE 17U /* 17 ms (16 ms starting time + 1) */ +#else #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_CSR_LSIPREDIV */ #define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ @@ -172,7 +160,7 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); (++) The Third output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. - (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks: + (+) PLLSAI2 (clocked by HSI, HSE or MSI) providing up to two independent output clocks: (++) The first output is used to generate SAR ADC2 clock. (++) The second output is used to generate an accurate clock to achieve high-quality audio performance on SAI interface. @@ -263,20 +251,21 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source - * - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF - * - AHB, APB1 and APB2 prescaler set to 1. + * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF + * - AHB, APB1 and APB2 prescalers set to 1. * - CSS, MCO1 OFF * - All interrupts disabled * - All interrupt and reset flags cleared - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks + * @note This function does not modify the configuration of the + * - Peripheral clock sources + * - LSI, LSE and RTC clocks (Backup domain) * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { - uint32_t tickstart = 0; + uint32_t tickstart; + /* Reset to default System clock */ /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); @@ -285,7 +274,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) tickstart = HAL_GetTick(); /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { @@ -303,7 +292,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = MSI_VALUE; /* Configure the source of time base considering new system clock settings */ - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if(HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -326,10 +315,14 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); -#else +#elif defined(RCC_PLLSAI1_SUPPORT) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); +#else + + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON); + #endif /* RCC_PLLSAI2_SUPPORT */ /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ @@ -340,10 +333,14 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) -#else +#elif defined(RCC_PLLSAI1_SUPPORT) while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) +#else + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + #endif { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) @@ -356,10 +353,14 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) CLEAR_REG(RCC->PLLCFGR); SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); +#if defined(RCC_PLLSAI1_SUPPORT) + /* Reset PLLSAI1CFGR register */ CLEAR_REG(RCC->PLLSAI1CFGR); SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2CFGR register */ @@ -399,12 +400,22 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0; + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) { @@ -413,10 +424,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - /* When the MSI is used as system clock it will not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) + /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_CFGR_SWS_MSI) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI))) { - if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) { return HAL_ERROR; } @@ -456,10 +468,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); + status = HAL_InitTick(uwTickPrio); + if(status != HAL_OK) + { + return status; + } } } else @@ -474,7 +490,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { @@ -496,7 +512,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { @@ -513,10 +529,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + if((sysclk_source == RCC_CFGR_SWS_HSE) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE))) { - if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } @@ -533,7 +549,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSE is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { @@ -547,7 +563,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { @@ -565,11 +581,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + if((sysclk_source == RCC_CFGR_SWS_HSI) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not be disabled */ - if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) { return HAL_ERROR; } @@ -592,7 +608,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { @@ -612,7 +628,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { @@ -631,6 +647,45 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { +#if defined(RCC_CSR_LSIPREDIV) + uint32_t csr_temp = RCC->CSR; + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPREDIV)) + { + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) + { + /* If LSIRDY is set while LSION is not enabled, + LSIPREDIV can't be updated */ + return HAL_ERROR; + } + + /* Turn off LSI before changing RCC_CSR_LSIPREDIV */ + if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) + { + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv); + } +#endif /* RCC_CSR_LSIPREDIV */ + /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); @@ -638,7 +693,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSI is ready */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET) + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { @@ -655,7 +710,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET) + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { @@ -698,7 +753,32 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Set the new LSE configuration -----------------------------------------*/ +#if defined(RCC_BDCR_LSESYSDIS) + if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U) + { + /* Set LSESYSDIS bit according to LSE propagation option (enabled or disabled) */ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSESYSDIS, (RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSDIS)); + + if((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U) + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + } + else + { + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + } + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + } +#else __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); +#endif /* RCC_BDCR_LSESYSDIS */ /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) @@ -707,7 +787,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { @@ -721,13 +801,18 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET) + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } + +#if defined(RCC_BDCR_LSESYSDIS) + /* By default, stop disabling LSE propagation */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +#endif /* RCC_BDCR_LSESYSDIS */ } /* Restore clock configuration if changed */ @@ -753,7 +838,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET) + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { @@ -770,7 +855,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI48 is disabled */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET) + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { @@ -787,7 +872,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if(sysclk_source != RCC_CFGR_SWS_PLL) { if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) { @@ -795,7 +880,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); +#if defined(RCC_PLLP_SUPPORT) assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); +#endif /* RCC_PLLP_SUPPORT */ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); @@ -806,7 +893,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -818,7 +905,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM, RCC_OscInitStruct->PLL.PLLN, +#if defined(RCC_PLLP_SUPPORT) RCC_OscInitStruct->PLL.PLLP, +#endif RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); @@ -826,13 +915,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PLL_ENABLE(); /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -846,27 +935,33 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PLL_DISABLE(); /* Disable all PLL outputs to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) -#if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) +#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY) + if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } +#elif defined(RCC_PLLSAI1_SUPPORT) + if(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) + { + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); + } +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); +#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */ #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); -#else +#elif defined(RCC_PLLSAI1_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); +#else + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK); #endif /* RCC_PLLSAI2_SUPPORT */ /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { @@ -877,31 +972,31 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - /* MBED patch - ST internal ticket 42806 */ - if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { return HAL_ERROR; } - - if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) { - return HAL_ERROR; + else + { + pll_config = RCC->PLLCFGR; + /* Do not return HAL_ERROR if request repeats the current configuration */ + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || +#if defined(RCC_PLLP_SUPPORT) +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) || +#else + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) || +#endif +#endif + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) + { + return HAL_ERROR; + } } - - if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) { - return HAL_ERROR; - } - - if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) { - return HAL_ERROR; - } - - if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) { - return HAL_ERROR; - } - - if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR) { - return HAL_ERROR; - } - /* MBED patch - ST internal ticket 42806 */ } } return HAL_OK; @@ -959,14 +1054,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0; + uint32_t tickstart; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t pllfreq = 0; uint32_t hpre = RCC_SYSCLK_DIV1; #endif + HAL_StatusTypeDef status; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); @@ -975,14 +1075,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) + if(FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } @@ -997,23 +1097,31 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { return HAL_ERROR; } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ - pllfreq = RCC_GetSysClockFreqFromPLLSource(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ - if((pllfreq > 80000000U) && - (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) - || - ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) + if(RCC_GetSysClockFreqFromPLLSource() > 80000000U) { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - hpre = RCC_SYSCLK_DIV2; + if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + { + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } + else if((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) + { + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } + else + { + /* nothing to do */ + } } #endif } @@ -1023,7 +1131,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { return HAL_ERROR; } @@ -1032,7 +1140,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) { /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) { return HAL_ERROR; } @@ -1041,18 +1149,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui else { /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { return HAL_ERROR; } } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ - pllfreq = HAL_RCC_GetSysClockFreq(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ - if(pllfreq > 80000000U) + if(HAL_RCC_GetSysClockFreq() > 80000000U) { + /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); hpre = RCC_SYSCLK_DIV2; } @@ -1065,47 +1171,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Get Start Tick*/ tickstart = HAL_GetTick(); - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } + return HAL_TIMEOUT; } } } @@ -1128,14 +1198,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) + if(FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } @@ -1156,12 +1226,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); + status = HAL_InitTick(uwTickPrio); - return HAL_OK; + return status; } /** @@ -1217,11 +1287,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(RCC_MCOx); + /* MCO Clock Enable */ __MCO1_CLK_ENABLE(); @@ -1271,16 +1345,20 @@ void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_ */ uint32_t HAL_RCC_GetSysClockFreq(void) { - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; + uint32_t msirange = 0U, sysclockfreq = 0U; + uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */ + uint32_t sysclk_source, pll_oscsource; - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI))) + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + + if((sysclk_source == RCC_CFGR_SWS_MSI) || + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI))) { /* MSI or PLL with MSI source used as system clock source */ /* Get SYSCLK source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) { /* MSISRANGE from RCC_CSR applies */ msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } @@ -1291,50 +1369,55 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) + if(sysclk_source == RCC_CFGR_SWS_MSI) { /* MSI used as system clock source */ sysclockfreq = msirange; } } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + else if(sysclk_source == RCC_CFGR_SWS_HSI) { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + else if(sysclk_source == RCC_CFGR_SWS_HSE) { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; } + else + { + /* unexpected case: sysclockfreq at 0 */ + } - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) + if(sysclk_source == RCC_CFGR_SWS_PLL) { /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = HSI_VALUE; break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = HSE_VALUE; break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: - pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = msirange; break; } + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm; pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - sysclockfreq = pllvco/pllr; + sysclockfreq = pllvco / pllr; } return sysclockfreq; @@ -1362,7 +1445,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); } /** @@ -1374,7 +1457,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); } /** @@ -1387,7 +1470,7 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); + assert_param(RCC_OscInitStruct != (void *)NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ #if defined(RCC_HSI48_SUPPORT) @@ -1440,11 +1523,29 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get the LSE configuration -----------------------------------------------*/ if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; +#if defined(RCC_BDCR_LSESYSDIS) + if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY; + } + else +#endif /* RCC_BDCR_LSESYSDIS */ + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } } else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; +#if defined(RCC_BDCR_LSESYSDIS) + if((RCC->BDCR & RCC_BDCR_LSESYSDIS) == RCC_BDCR_LSESYSDIS) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY; + } + else +#endif /* RCC_BDCR_LSESYSDIS */ + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } } else { @@ -1460,6 +1561,18 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } +#if defined(RCC_CSR_LSIPREDIV) + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV) + { + RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128; + } + else + { + RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1; + } +#endif /* RCC_CSR_LSIPREDIV */ #if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration ---------------------------------------------*/ @@ -1489,10 +1602,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); +#if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; #else - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; } @@ -1501,6 +1615,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7; } #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLP_SUPPORT */ } /** @@ -1514,8 +1629,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; @@ -1533,7 +1648,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); + *pFLatency = __HAL_FLASH_GET_LATENCY(); } /** @@ -1600,7 +1715,7 @@ __weak void HAL_RCC_CSSCallback(void) */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { - uint32_t vos = 0; + uint32_t vos; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ if(__HAL_RCC_PWR_IS_CLK_ENABLED()) @@ -1676,7 +1791,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) + if(__HAL_FLASH_GET_LATENCY() != latency) { return HAL_ERROR; } @@ -1691,13 +1806,13 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; + uint32_t msirange = 0U; + uint32_t pllvco, pllsource, pllr, pllm, sysclockfreq; /* no init needed */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) { /* Get MSI range source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) { /* MSISRANGE from RCC_CSR applies */ msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } @@ -1709,30 +1824,30 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) msirange = MSIRangeTable[msirange]; } - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = HSI_VALUE; break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = HSE_VALUE; break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: - pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = msirange; break; } - + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm; pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - sysclockfreq = pllvco/pllr; + sysclockfreq = pllvco / pllr; return sysclockfreq; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h index 9c8014cdef..05b8dde24a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -75,14 +59,17 @@ typedef struct uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ +#if defined(RCC_PLLP_SUPPORT) uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ +#endif /* RCC_PLLP_SUPPORT */ uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ uint32_t PLLR; /*!< PLLR: Division for the main system clock. - User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. + User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ + on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ }RCC_PLLInitTypeDef; @@ -110,6 +97,11 @@ typedef struct uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ +#if defined(RCC_CSR_LSIPREDIV) + + uint32_t LSIDiv; /*!< The division factor of the LSI. + This parameter can be a value of @ref RCC_LSI_Div */ +#endif /* RCC_CSR_LSIPREDIV */ uint32_t MSIState; /*!< The new state of the MSI. This parameter can be a value of @ref RCC_MSI_Config */ @@ -196,9 +188,13 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +#if defined(RCC_BDCR_LSESYSDIS) +#define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< LSE clock activation without propagation to system */ +#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON) /*!< External clock source for LSE clock without propagation to system */ +#endif /* RCC_BDCR_LSESYSDIS */ /** * @} */ @@ -228,6 +224,17 @@ typedef struct /** * @} */ +#if defined(RCC_CSR_LSIPREDIV) + +/** @defgroup RCC_LSI_Div LSI Div + * @{ + */ +#define RCC_LSI_DIV1 0x00000000U /*!< LSI clock not divided */ +#define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV /*!< LSI clock divided by 128 */ +/** + * @} + */ +#endif /* RCC_CSR_LSIPREDIV */ /** @defgroup RCC_MSI_Config MSI Config * @{ @@ -269,6 +276,7 @@ typedef struct * @} */ +#if defined(RCC_PLLP_SUPPORT) /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider * @{ */ @@ -310,6 +318,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLP_SUPPORT */ /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ @@ -349,7 +358,7 @@ typedef struct */ #if defined(RCC_PLLSAI2_SUPPORT) #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ -#else +#elif defined(RCC_PLLSAI1_SUPPORT) #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ #endif /* RCC_PLLSAI2_SUPPORT */ #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ @@ -357,6 +366,7 @@ typedef struct /** * @} */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output * @{ @@ -367,6 +377,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) @@ -527,7 +538,9 @@ typedef struct #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -551,11 +564,13 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -566,7 +581,6 @@ typedef struct /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ @@ -1068,6 +1082,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ @@ -1075,6 +1090,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_ENABLE() do { \ @@ -1114,6 +1130,7 @@ typedef struct } while(0) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ @@ -1121,6 +1138,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1206,6 +1224,7 @@ typedef struct } while(0) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ @@ -1213,6 +1232,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ @@ -1242,6 +1262,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ @@ -1249,6 +1270,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1309,7 +1331,9 @@ typedef struct #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); @@ -1323,7 +1347,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) @@ -1355,7 +1381,9 @@ typedef struct #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) @@ -1367,7 +1395,9 @@ typedef struct #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) @@ -1480,6 +1510,7 @@ typedef struct } while(0) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ @@ -1487,6 +1518,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ @@ -1553,7 +1585,9 @@ typedef struct #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) @@ -1583,49 +1617,49 @@ typedef struct * @{ */ -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) -#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) +#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) #endif /* GFXMMU */ -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) -#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) #endif /* GFXMMU */ /** @@ -1640,102 +1674,102 @@ typedef struct * @{ */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) #endif /* GPIOI */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) #endif /* GPIOI */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) /** * @} @@ -1750,19 +1784,19 @@ typedef struct */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) +#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) #endif /* QUADSPI */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) #endif /* QUADSPI */ /** @@ -1777,186 +1811,202 @@ typedef struct * @{ */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) +#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U) #endif /* LCD */ #if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) #endif /* RCC_APB1ENR1_RTCAPBEN */ -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) -#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) +#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U) #endif /* LCD */ #if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) #endif /* RCC_APB1ENR1_RTCAPBEN */ -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) -#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) /** * @} @@ -1970,91 +2020,95 @@ typedef struct * @{ */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) -#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) +#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U) #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U) #endif /* DSI */ -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U) #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U) #endif /* DSI */ /** @@ -2309,7 +2363,9 @@ typedef struct #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) +#if defined(TIM7) #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) @@ -2319,7 +2375,9 @@ typedef struct #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) +#endif /* SPI3 */ #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) @@ -2351,7 +2409,9 @@ typedef struct #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) @@ -2363,7 +2423,9 @@ typedef struct #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) +#if defined(DAC1) #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) @@ -2396,7 +2458,9 @@ typedef struct #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) +#if defined(TIM7) #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) @@ -2406,7 +2470,9 @@ typedef struct #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) +#endif /* SPI3 */ #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) @@ -2438,7 +2504,9 @@ typedef struct #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) @@ -2450,7 +2518,9 @@ typedef struct #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) +#if defined(DAC1) #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) @@ -2498,7 +2568,9 @@ typedef struct #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) @@ -2543,7 +2615,9 @@ typedef struct #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) @@ -2835,7 +2909,9 @@ typedef struct #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) @@ -2851,7 +2927,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) @@ -2883,7 +2961,9 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) @@ -2895,7 +2975,9 @@ typedef struct #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) @@ -2926,7 +3008,9 @@ typedef struct #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) +#if defined(TIM7) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) +#endif /* TIM7 */ #if defined(LCD) #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) @@ -2942,7 +3026,9 @@ typedef struct #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #endif /* SPI2 */ +#if defined(SPI3) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) +#endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) @@ -2974,7 +3060,9 @@ typedef struct #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #endif /* CRS */ +#if defined(CAN1) #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) +#endif /* CAN1 */ #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) @@ -2986,7 +3074,9 @@ typedef struct #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) +#if defined(DAC1) #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) +#endif /* DAC1 */ #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) @@ -3037,7 +3127,9 @@ typedef struct #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) @@ -3080,7 +3172,9 @@ typedef struct #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #endif /* TIM17 */ +#if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#endif /* SAI1 */ #if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) @@ -3111,53 +3205,53 @@ typedef struct * @{ */ -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) -#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) +#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U) #endif /* GFXMMU */ -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) #if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) #endif /* DMAMUX1 */ -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) -#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) +#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) #if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U) #endif /* DMA2D */ #if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U) #endif /* GFXMMU */ /** @@ -3173,129 +3267,129 @@ typedef struct * @{ */ -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U) #endif /* GPIOI */ -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) #if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U) #endif /* SRAM3 */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) #if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U) #endif /* OCTOSPIM */ #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) #if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) #endif /* GPIOD */ #if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) #endif /* GPIOE */ #if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) #endif /* GPIOF */ #if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) #endif /* GPIOG */ -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) #if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U) #endif /* GPIOI */ -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) #if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U) #endif /* SRAM3 */ #if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U) #endif /* USB_OTG_FS */ -#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) #if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U) #endif /* DCMI */ #if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) #endif /* AES */ #if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) #endif /* HASH */ -#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) #if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U) #endif /* OCTOSPIM */ #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ /** @@ -3312,36 +3406,36 @@ typedef struct */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) #endif /* QUADSPI */ #if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U) #endif /* OCTOSPI1 */ #if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U) #endif /* OCTOSPI2 */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) #endif /* QUADSPI */ #if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U) #endif /* OCTOSPI1 */ #if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U) #endif /* OCTOSPI2 */ #if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) #endif /* FMC_BANK1 */ /** @@ -3357,186 +3451,202 @@ typedef struct * @{ */ -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) +#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U) #endif /* LCD */ #if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) #if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) #endif /* TIM3 */ #if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) #endif /* TIM4 */ #if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) #endif /* TIM5 */ -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) +#endif /* TIM7 */ #if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) +#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U) #endif /* LCD */ #if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) #if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) #endif /* SPI2 */ -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) +#endif /* SPI3 */ -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) #if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) #endif /* USART3 */ #if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) #endif /* UART4 */ #if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) #endif /* UART5 */ -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) #if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) #endif /* I2C2 */ -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) #if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) #endif /* I2C4 */ #if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) #endif /* CRS */ -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) +#if defined(CAN1) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U) +#endif /* CAN1 */ #if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U) #endif /* CAN2 */ #if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) #endif /* USB */ -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) +#endif /* DAC1 */ -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) #if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U) #endif /* SWPMI1 */ -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) /** * @} @@ -3551,89 +3661,93 @@ typedef struct * @{ */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U) #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U) #endif /* DSI */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U) #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) #if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) #endif /* TIM8 */ -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) #if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) #endif /* TIM17 */ -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) +#endif /* SAI1 */ #if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) #endif /* SAI2 */ #if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) #endif /* DFSDM1_Filter0 */ #if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U) #endif /* LTDC */ #if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U) #endif /* DSI */ /** @@ -3830,9 +3944,9 @@ typedef struct * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz */ #define __HAL_RCC_GET_MSI_RANGE() \ - ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ + ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ - READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) + (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -4043,7 +4157,7 @@ typedef struct * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * - * @param __PLLP__ specifies the division factor for SAI clock. + * @param __PLLP__ specifies the division factor for SAI clock when SAI available on device. * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x * else (2 to 31). * @@ -4061,15 +4175,40 @@ typedef struct #if defined(RCC_PLLP_DIV_2_31_SUPPORT) #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - ((uint32_t)(__PLLP__) << 27U)) -#else + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \ + ((__PLLSOURCE__) | \ + (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ + ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) + +#elif defined(RCC_PLLP_SUPPORT) #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \ + ((__PLLSOURCE__) | \ + (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ + (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos))) + +#else + +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ + ((__PLLSOURCE__) | \ + (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ @@ -4208,7 +4347,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @if STM32L443xx @@ -4230,7 +4369,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @if STM32L443xx @@ -4252,7 +4391,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @@ -4275,7 +4414,7 @@ typedef struct * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt + * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt for devices with PLLSAI1 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt @@ -4303,7 +4442,7 @@ typedef struct * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready - * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready + * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready for devices with PLLSAI1 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 @if STM32L443xx * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 @@ -4318,7 +4457,6 @@ typedef struct * @arg @ref RCC_FLAG_OBLRST OBLRST reset * @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_FWRST FIREWALL reset - * @arg @ref RCC_FLAG_RMVF Remove reset Flag * @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset @@ -4330,12 +4468,12 @@ typedef struct ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) #else #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) #endif /* RCC_HSI48_SUPPORT */ /** @@ -4388,8 +4526,13 @@ typedef struct #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ ((__HSE__) == RCC_HSE_BYPASS)) +#if defined(RCC_BDCR_LSESYSDIS) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ + ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS)) +#else #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) +#endif /* RCC_BDCR_LSESYSDIS */ #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) @@ -4397,6 +4540,10 @@ typedef struct #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#if defined(RCC_CSR_LSIPREDIV) +#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) +#endif /* RCC_CSR_LSIPREDIV */ + #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) @@ -4433,10 +4580,12 @@ typedef struct #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c index 7c31e73fb5..521ead4f31 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -79,14 +63,23 @@ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) + static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider); +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider); #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(SAI1) + +static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency); + +#endif /* SAI1 */ /** * @} */ @@ -148,7 +141,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1) @if STM32L486xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif @@ -202,14 +195,15 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t tmpregister = 0; - uint32_t tickstart = 0U; + uint32_t tmpregister, tickstart; /* no init needed */ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ HAL_StatusTypeDef status = HAL_OK; /* Final status */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); +#if defined(SAI1) + /*-------------------------- SAI1 clock source configuration ---------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) { @@ -268,6 +262,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } +#endif /* SAI1 */ + #if defined(SAI2) /*-------------------------- SAI2 clock source configuration ---------------------*/ @@ -330,7 +326,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; @@ -342,7 +338,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { @@ -374,7 +370,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { @@ -557,6 +553,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } else { +#if defined(RCC_PLLSAI1_SUPPORT) if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ @@ -568,6 +565,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /* RCC_PLLSAI1_SUPPORT */ } } @@ -604,6 +602,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } + else + { + /* nothing to do */ + } } #endif /* SDMMC1 */ @@ -619,6 +621,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } +#if defined(RCC_PLLSAI1_SUPPORT) else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ @@ -630,9 +633,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /* RCC_PLLSAI1_SUPPORT */ + else + { + /* nothing to do */ + } } /*-------------------------- ADC clock source configuration ----------------------*/ +#if !defined(STM32L412xx) && !defined(STM32L422xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { /* Check the parameters */ @@ -641,6 +650,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); +#if defined(RCC_PLLSAI1_SUPPORT) if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ @@ -652,6 +662,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) @@ -670,6 +681,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ } +#endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) @@ -727,7 +739,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -815,7 +827,15 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ -#if defined(STM32L431xx) +#if defined(STM32L412xx) || defined(STM32L422xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC ; + +#elif defined(STM32L431xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ @@ -905,6 +925,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) #endif /* STM32L431xx */ +#if defined(RCC_PLLSAI1_SUPPORT) + /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; @@ -918,6 +940,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ @@ -982,8 +1006,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the LPTIM2 clock source ---------------------------------------------*/ PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); +#if defined(SAI1) /* Get the SAI1 clock source -----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#endif /* SAI1 */ #if defined(SAI2) /* Get the SAI2 clock source -----------------------------------------------*/ @@ -1006,8 +1032,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if !defined(STM32L412xx) && !defined(STM32L422xx) /* Get the ADC clock source ------------------------------------------------*/ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); +#endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) /* Get the SWPMI1 clock source ---------------------------------------------*/ @@ -1072,7 +1100,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1) @if STM32L486xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif @@ -1124,8 +1152,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { uint32_t frequency = 0U; - uint32_t srcclk = 0U; - uint32_t pllvco = 0U, plln = 0U, pllp = 0U; + uint32_t srcclk, pll_oscsource, pllvco, plln; /* no init needed */ +#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) + uint32_t pllp; /* no init needed */ +#endif /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); @@ -1135,34 +1165,52 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the current RTC source */ srcclk = __HAL_RCC_GET_RTC_SOURCE(); - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + switch(srcclk) { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 32U; - } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; + case RCC_RTCCLKSOURCE_LSE: + /* Check if LSE is ready */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + case RCC_RTCCLKSOURCE_LSI: + /* Check if LSI is ready */ + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { +#if defined(RCC_CSR_LSIPREDIV) + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV)) + { + frequency = LSI_VALUE/128U; + } + else +#endif /* RCC_CSR_LSIPREDIV */ + { + frequency = LSI_VALUE; + } + } + break; + case RCC_RTCCLKSOURCE_HSE_DIV32: + /* Check if HSE is ready */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE / 32U; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } } else { /* Other external peripheral clock source than RTC */ + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); /* Compute PLL clock input */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ + switch(pll_oscsource) { + case RCC_PLLSOURCE_MSI: /* MSI ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) { /*MSI frequency range in HZ*/ @@ -1172,9 +1220,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { pllvco = 0U; } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ - { + break; + case RCC_PLLSOURCE_HSI: /* HSI ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { pllvco = HSI_VALUE; @@ -1183,9 +1230,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { pllvco = 0U; } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ - { + break; + case RCC_PLLSOURCE_HSE: /* HSE ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { pllvco = HSE_VALUE; @@ -1194,240 +1240,31 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { pllvco = 0U; } - } - else /* No source */ - { + break; + default: + /* No source */ pllvco = 0U; + break; } -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - switch(PeriphClk) { -#if defined(SAI2) +#if defined(SAI1) case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: - - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - else /* RCC_PERIPHCLK_SAI2 */ - { - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - - if(srcclk == RCC_SAI2CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI2_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - -#else - - case RCC_PERIPHCLK_SAI1: - - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); - - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - -#endif /* SAI2 */ - - if(frequency == 0U) - { -#if defined(SAI2) - if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) - { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) - { - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } - else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - } -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#else - if(srcclk == RCC_SAI1CLKSOURCE_PLL) - { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) - { - /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - - frequency = (pllvco * plln) / pllp; - } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; - } - else - { - /* No clock source */ - frequency = 0U; - } - } - else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - - frequency = (pllvco * plln) / pllp; - } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; - } - else - { - /* No clock source */ - frequency = 0U; - } - } -#endif /* SAI2 */ - -#if defined(RCC_PLLSAI2_SUPPORT) - - else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#endif - /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } - -#endif /* RCC_PLLSAI2_SUPPORT */ - - else - { - /* No clock source */ - frequency = 0U; - } - } + frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco); break; +#endif + +#if defined(SAI2) + + case RCC_PERIPHCLK_SAI2: + frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco); + break; + +#endif + #if defined(USB_OTG_FS) || defined(USB) case RCC_PERIPHCLK_USB: @@ -1441,71 +1278,66 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_SDMMC1: #endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ + { + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + switch(srcclk) { + case RCC_CCIPR_CLK48SEL: /* MSI ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + break; + case RCC_CCIPR_CLK48SEL_1: /* PLL ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) * PLLN / PLLM */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) / PLLQ */ + frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)); + } + } + break; +#if defined(RCC_PLLSAI1_SUPPORT) + case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY)) + { + if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + { + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } -#if defined(RCC_HSI48_SUPPORT) - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */ + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); #else - else /* No clock source */ - { - frequency = 0U; - } + /* f(PLL Source) * PLLSAI1N / PLLM */ + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */ + frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)); + } + } + break; +#endif /* RCC_PLLSAI1_SUPPORT */ +#if defined(RCC_HSI48_SUPPORT) + case 0U: + if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */ + { + frequency = HSI48_VALUE; + } + break; #endif /* RCC_HSI48_SUPPORT */ - break; + default: + /* No clock source, frequency default init at 0 */ + break; + } /* switch(srcclk) */ + break; + } #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) @@ -1513,574 +1345,676 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + /* f(PLL Source) * PLLN / PLLM */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLLSAI3CLK) = f(VCO input) / PLLP */ + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; + if(pllp == 0U) { - pllp = 17U; - } - else - { - pllp = 7U; + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } } + frequency = (pllvco / pllp); } - frequency = (pllvco * plln) / pllp; - } - else - { - frequency = 0U; } } else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ { srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ + switch(srcclk) { + case RCC_CCIPR_CLK48SEL: /* MSI ? */ if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) { /*MSI frequency range in HZ*/ frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; } - else + break; + case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { - frequency = 0U; + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) * PLLN / PLLM */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) / PLLQ */ + frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)); + } } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + break; + case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY)) { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + { + /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); + /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */ + frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)); + } } - else + break; + case 0U: + if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */ { - frequency = 0U; + frequency = HSI48_VALUE; } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } /* switch(srcclk) */ } break; #endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ case RCC_PERIPHCLK_USART1: - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); - if(srcclk == RCC_USART1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); + switch(srcclk) + { + case RCC_USART1CLKSOURCE_PCLK2: + frequency = HAL_RCC_GetPCLK2Freq(); + break; + case RCC_USART1CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_USART1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_USART1CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART1 */ - else - { - frequency = 0U; - } - break; case RCC_PERIPHCLK_USART2: - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); - if(srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_USART2CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_USART2CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_USART2CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_USART2CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART2 */ - else - { - frequency = 0U; - } - break; #if defined(USART3) case RCC_PERIPHCLK_USART3: - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); - if(srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_USART3CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_USART3CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_USART3CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_USART3CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } - break; #endif /* USART3 */ #if defined(UART4) case RCC_PERIPHCLK_UART4: - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); + { + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); - if(srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_UART4CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_UART4CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_UART4CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_UART4CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } - break; #endif /* UART4 */ #if defined(UART5) case RCC_PERIPHCLK_UART5: - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); + { + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); - if(srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_UART5CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_UART5CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_UART5CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_UART5CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART5 */ - else - { - frequency = 0U; - } - break; #endif /* UART5 */ case RCC_PERIPHCLK_LPUART1: - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + { + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_LPUART1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPUART1CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_LPUART1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_LPUART1CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPUART1 */ - else - { - frequency = 0U; - } - break; case RCC_PERIPHCLK_ADC: - - srcclk = __HAL_RCC_GET_ADC_SOURCE(); - - if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + switch(srcclk) { + case RCC_ADCCLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; +#if defined(RCC_PLLSAI1_SUPPORT) + case RCC_ADCCLKSOURCE_PLLSAI1: + if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U) + { + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */ + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) * PLLSAI1N / PLLM */ + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif - /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); - } - } + /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */ + frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)); + } + break; +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) - { + case RCC_ADCCLKSOURCE_PLLSAI2: + if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U) + { + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); + /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ + /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */ + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#else + /* f(PLL Source) * PLLSAI2N / PLLM */ + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); #endif - /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); - } - } + /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */ + frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U)); + } + break; #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - /* Clock not enabled for ADC */ - else - { - frequency = 0U; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - break; #if defined(DFSDM1_Filter0) case RCC_PERIPHCLK_DFSDM1: - /* Get the current DFSDM1 source */ - srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); + { + /* Get the current DFSDM1 source */ + srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); + if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else + { + frequency = HAL_RCC_GetSysClockFreq(); + } + + break; } - else - { - frequency = HAL_RCC_GetSysClockFreq(); - } - break; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) case RCC_PERIPHCLK_DFSDM1AUDIO: - /* Get the current DFSDM1 audio source */ - srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + { + /* Get the current DFSDM1 audio source */ + srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); - if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) - { - frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); + switch(srcclk) + { + case RCC_DFSDM1AUDIOCLKSOURCE_SAI1: + frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco); + break; + case RCC_DFSDM1AUDIOCLKSOURCE_MSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + break; + case RCC_DFSDM1AUDIOCLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for DFSDM1 audio source */ - else - { - frequency = 0U; - } - break; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ case RCC_PERIPHCLK_I2C1: - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_I2C1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C1CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C1 */ - else - { - frequency = 0U; - } - break; #if defined(I2C2) case RCC_PERIPHCLK_I2C2: - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + { + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_I2C2CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C2CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C2CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C2 */ - else - { - frequency = 0U; - } - break; #endif /* I2C2 */ case RCC_PERIPHCLK_I2C3: - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + { + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_I2C3CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C3CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C3CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C3 */ - else - { - frequency = 0U; - } - break; #if defined(I2C4) case RCC_PERIPHCLK_I2C4: - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); + { + /* Get the current I2C4 source */ + srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_I2C4CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C4CLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_I2C4CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C4 */ - else - { - frequency = 0U; - } - break; #endif /* I2C4 */ case RCC_PERIPHCLK_LPTIM1: - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + { + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPTIM1CLKSOURCE_LSI: + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { +#if defined(RCC_CSR_LSIPREDIV) + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV)) + { + frequency = LSI_VALUE/128U; + } + else +#endif /* RCC_CSR_LSIPREDIV */ + { + frequency = LSI_VALUE; + } + } + break; + case RCC_LPTIM1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_LPTIM1CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ - else - { - frequency = 0U; - } - break; case RCC_PERIPHCLK_LPTIM2: - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + { + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_LPTIM2CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPTIM2CLKSOURCE_LSI: + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { +#if defined(RCC_CSR_LSIPREDIV) + if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV)) + { + frequency = LSI_VALUE/128U; + } + else +#endif /* RCC_CSR_LSIPREDIV */ + { + frequency = LSI_VALUE; + } + } + break; + case RCC_LPTIM2CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + case RCC_LPTIM2CLKSOURCE_LSE: + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) + { + frequency = LSE_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM2 */ - else - { - frequency = 0U; - } - break; #if defined(SWPMI1) case RCC_PERIPHCLK_SWPMI1: - /* Get the current SWPMI1 source */ - srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); + { + /* Get the current SWPMI1 source */ + srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); + switch(srcclk) + { + case RCC_SWPMI1CLKSOURCE_PCLK1: + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_SWPMI1CLKSOURCE_HSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; + } + + break; } - else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for SWPMI1 */ - else - { - frequency = 0U; - } - break; #endif /* SWPMI1 */ #if defined(OCTOSPI1) || defined(OCTOSPI2) case RCC_PERIPHCLK_OSPI: - /* Get the current OctoSPI clock source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); + { + /* Get the current OctoSPI clock source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if(srcclk == RCC_OSPICLKSOURCE_PLL) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + switch(srcclk) { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; + case RCC_OSPICLKSOURCE_SYSCLK: + frequency = HAL_RCC_GetSysClockFreq(); + break; + case RCC_OSPICLKSOURCE_MSI: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + break; + case RCC_OSPICLKSOURCE_PLL: + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) * PLLN / PLLM */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) / PLLQ */ + frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)); + } + } + break; + default: + /* No clock source, frequency default init at 0 */ + break; } + + break; } - /* Clock not enabled for OctoSPI */ - else - { - frequency = 0U; - } - break; #endif /* OCTOSPI1 || OCTOSPI2 */ @@ -2111,6 +2045,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) + /** * @brief Enable PLLSAI1. * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that @@ -2119,7 +2055,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ @@ -2138,7 +2074,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -2168,7 +2104,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -2187,7 +2123,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Disable the PLLSAI1 */ @@ -2197,7 +2133,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -2210,19 +2146,23 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) + if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } +#else + if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); + } +#endif /* RCC_PLLSAI2_SUPPORT */ return status; } +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -2233,7 +2173,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ @@ -2254,7 +2194,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -2292,7 +2232,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -2311,7 +2251,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Disable the PLLSAI2 */ @@ -2321,7 +2261,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -2338,10 +2278,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - ) + if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } @@ -2642,7 +2579,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { - uint32_t value = 0; + uint32_t value; /* no init needed */ /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); @@ -2669,7 +2606,8 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise + according to RCC_CRS_HSI48CalibrationValue value */ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); /* START AUTOMATIC SYNCHRONIZATION*/ @@ -2695,7 +2633,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) { /* Check the parameter */ - assert_param(pSynchroInfo != NULL); + assert_param(pSynchroInfo != (void *)NULL); /* Get the reload value */ pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); @@ -2728,7 +2666,7 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0U; + uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); @@ -2738,7 +2676,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { crsstatus = RCC_CRS_TIMEOUT; } @@ -2816,7 +2754,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) uint32_t itsources = READ_REG(CRS->CR); /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) + if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) { /* Clear CRS SYNC event OK flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); @@ -2825,7 +2763,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) HAL_RCCEx_CRS_SyncOkCallback(); } /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) + else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) { /* Clear CRS SYNCWARN flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); @@ -2834,7 +2772,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) HAL_RCCEx_CRS_SyncWarnCallback(); } /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) + else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) { /* frequency error counter reached a zero value */ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); @@ -2845,17 +2783,17 @@ void HAL_RCCEx_CRS_IRQHandler(void) /* Check CRS Error flags */ else { - if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) + if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) { - if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) + if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) { crserror |= RCC_CRS_SYNCERR; } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) + if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) { crserror |= RCC_CRS_SYNCMISS; } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) + if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) { crserror |= RCC_CRS_TRIMOVF; } @@ -2935,6 +2873,8 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) + /** * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s). * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that @@ -2947,7 +2887,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) */ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ @@ -2991,9 +2931,12 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } break; case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) { - status = HAL_ERROR; + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + { + status = HAL_ERROR; + } } break; default: @@ -3022,7 +2965,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -3113,7 +3056,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { @@ -3133,6 +3076,8 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u return status; } +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -3147,7 +3092,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u */ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ @@ -3191,9 +3136,12 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } break; case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) { - status = HAL_ERROR; + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + { + status = HAL_ERROR; + } } break; default: @@ -3222,7 +3170,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -3315,7 +3263,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u tickstart = HAL_GetTick(); /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) { if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { @@ -3337,6 +3285,238 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(SAI1) + +static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency) +{ + uint32_t frequency = 0U; + uint32_t srcclk = 0U; + uint32_t pllvco, plln; /* no init needed */ +#if defined(RCC_PLLP_SUPPORT) + uint32_t pllp = 0U; +#endif /* RCC_PLLP_SUPPORT */ + + /* Handle SAIs */ + if(PeriphClk == RCC_PERIPHCLK_SAI1) + { + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); + if(srcclk == RCC_SAI1CLKSOURCE_PIN) + { + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + } + /* Else, PLL clock output to check below */ + } +#if defined(SAI2) + else + { + if(PeriphClk == RCC_PERIPHCLK_SAI2) + { + srcclk = __HAL_RCC_GET_SAI2_SOURCE(); + if(srcclk == RCC_SAI2CLKSOURCE_PIN) + { + frequency = EXTERNAL_SAI2_CLOCK_VALUE; + } + /* Else, PLL clock output to check below */ + } + } +#endif /* SAI2 */ + + if(frequency == 0U) + { + pllvco = InputFrequency; + +#if defined(SAI2) + if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) + { + if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + } + else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ + { + if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#else + if(srcclk == RCC_SAI1CLKSOURCE_PLL) + { + if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + /* HSI automatically selected as clock source if PLLs not enabled */ + frequency = HSI_VALUE; + } + else + { + /* No clock source, frequency default init at 0 */ + } + } + else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) + { + if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + /* HSI automatically selected as clock source if PLLs not enabled */ + frequency = HSI_VALUE; + } + else + { + /* No clock source, frequency default init at 0 */ + } + } +#endif /* SAI2 */ + +#if defined(RCC_PLLSAI2_SUPPORT) + + else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) + { + if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U) + { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#else + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + } + +#endif /* RCC_PLLSAI2_SUPPORT */ + + else + { + /* No clock source, frequency default init at 0 */ + } + } + + + return frequency; +} + +#endif /* SAI1 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h index b0000a7abe..41b5fda794 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -58,6 +42,7 @@ * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief PLLSAI1 Clock structure definition */ @@ -90,9 +75,9 @@ typedef struct uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ }RCC_PLLSAI1InitTypeDef; +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) - /** * @brief PLLSAI2 Clock structure definition */ @@ -137,10 +122,11 @@ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ +#if defined(RCC_PLLSAI1_SUPPORT) RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ - +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. @@ -203,9 +189,11 @@ typedef struct uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ +#if defined(SAI1) uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ +#endif /* SAI1 */ #if defined(SAI2) @@ -231,8 +219,10 @@ typedef struct uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ +#if !defined(STM32L412xx) && !defined(STM32L422xx) uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ +#endif /* !STM32L412xx && !STM32L422xx */ #if defined(SWPMI1) @@ -303,7 +293,8 @@ typedef struct This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise, + or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ }RCC_CRSInitTypeDef; @@ -316,7 +307,7 @@ typedef struct This parameter must be a number between 0 and 0xFFFF */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ + This parameter must be a number between 0 and 0x7F for STM32L412xx/L422xx, between 0 and 0x3F otherwise */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. @@ -370,7 +361,9 @@ typedef struct #define RCC_PERIPHCLK_I2C3 0x00000100U #define RCC_PERIPHCLK_LPTIM1 0x00000200U #define RCC_PERIPHCLK_LPTIM2 0x00000400U +#if defined(SAI1) #define RCC_PERIPHCLK_SAI1 0x00000800U +#endif #if defined(SAI2) #define RCC_PERIPHCLK_SAI2 0x00001000U #endif @@ -525,6 +518,7 @@ typedef struct */ #endif /* I2C4 */ +#if defined(SAI1) /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ @@ -547,6 +541,7 @@ typedef struct /** * @} */ +#endif /* SAI1 */ #if defined(SAI2) /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source @@ -618,7 +613,9 @@ typedef struct #else #define RCC_RNGCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 +#endif /* RCC_PLLSAI1_SUPPORT */ #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL /** @@ -634,7 +631,9 @@ typedef struct #else #define RCC_USBCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 +#endif /* RCC_PLLSAI1_SUPPORT */ #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL /** @@ -645,12 +644,18 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ -#define RCC_ADCCLKSOURCE_NONE 0x00000000U +#define RCC_ADCCLKSOURCE_NONE 0x00000000U +#if defined(RCC_PLLSAI1_SUPPORT) #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#if defined(RCC_CCIPR_ADCSEL) #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL +#else +#define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U +#endif /* RCC_CCIPR_ADCSEL */ /** * @} */ @@ -807,9 +812,15 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value + corresponds to a higher output frequency */ +#else +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value + corresponds to a higher output frequency */ +#endif /** * @} */ @@ -864,6 +875,7 @@ typedef struct * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. @@ -903,20 +915,26 @@ typedef struct #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) + MODIFY_REG(RCC->PLLSAI1CFGR, \ + (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ + RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ + ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ + ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) #else #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) + MODIFY_REG(RCC->PLLSAI1CFGR, \ + (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ + RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \ + ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ + ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos))) #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ @@ -925,18 +943,24 @@ typedef struct #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + MODIFY_REG(RCC->PLLSAI1CFGR, \ + (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ + RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ + (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) #else #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) + MODIFY_REG(RCC->PLLSAI1CFGR, \ + (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \ + RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \ + (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos))) #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ @@ -1075,6 +1099,8 @@ typedef struct */ #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -1116,27 +1142,36 @@ typedef struct # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ + RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ + ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ + ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ + RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ + ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ + ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) # else #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ + RCC_PLLSAI2CFGR_PLLSAI2R), \ + ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ + ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos))) # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ @@ -1145,24 +1180,33 @@ typedef struct # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ + RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ + (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ + RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ + (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) # else #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \ + RCC_PLLSAI2CFGR_PLLSAI2R), \ + (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos))) # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ @@ -1318,6 +1362,8 @@ typedef struct #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(SAI1) + /** * @brief Macro to configure the SAI1 clock source. * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived @@ -1366,6 +1412,8 @@ typedef struct #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* SAI1 */ + #if defined(SAI2) /** @@ -1757,7 +1805,7 @@ typedef struct */ #if defined(RCC_CCIPR2_SDMMCSEL) #define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) #else #define __HAL_RCC_GET_SDMMC1_SOURCE() \ (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) @@ -1837,6 +1885,8 @@ typedef struct #endif /* USB_OTG_FS || USB */ +#if defined(RCC_CCIPR_ADCSEL) + /** @brief Macro to configure the ADC interface clock. * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. * This parameter can be one of the following values: @@ -1861,6 +1911,16 @@ typedef struct * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock */ #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) +#else + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE) + +#endif /* RCC_CCIPR_ADCSEL */ #if defined(SWPMI1) @@ -2008,6 +2068,7 @@ typedef struct * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @brief Enable PLLSAI1RDY interrupt. * @retval None @@ -2034,6 +2095,8 @@ typedef struct */ #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) /** @brief Enable PLLSAI2RDY interrupt. @@ -2189,7 +2252,7 @@ typedef struct * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) /** @brief Clear the CRS interrupt pending bits * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @@ -2206,7 +2269,7 @@ typedef struct #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ } \ @@ -2250,7 +2313,7 @@ typedef struct #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ } \ @@ -2339,10 +2402,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** @addtogroup RCCEx_Exported_Functions_Group2 * @{ */ +#if defined(RCC_PLLSAI1_SUPPORT) HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); @@ -2400,7 +2466,24 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) -#if defined(STM32L431xx) +#if defined(STM32L412xx) || defined(STM32L422xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) + +#elif defined(STM32L431xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -2652,7 +2735,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) -#endif /* STM32L431xx */ +#endif /* STM32L412xx || STM32L422xx */ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ @@ -2747,7 +2830,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#else +#elif defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ @@ -2817,11 +2900,18 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) +#else +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) +#endif /* RCC_PLLSAI1_SUPPORT */ #else @@ -2836,11 +2926,18 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(USB_OTG_FS) || defined(USB) #if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) +#else +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) +#endif /* RCC_PLLSAI1_SUPPORT */ #else @@ -2863,10 +2960,16 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #else +#if defined(RCC_PLLSAI1_SUPPORT) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#else +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) +#endif /* RCC_PLLSAI1_SUPPORT */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ @@ -2922,6 +3025,8 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(RCC_PLLSAI1_SUPPORT) + #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) @@ -2944,6 +3049,8 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) +#endif /* RCC_PLLSAI1_SUPPORT */ + #if defined(RCC_PLLSAI2_SUPPORT) #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c index 469c6af21d..3784dc4e5d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c @@ -23,33 +23,71 @@ random data using (polling/interrupt) mode. (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. + Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + + [..] + For specific callback ReadyDataCallback, use dedicated register callbacks: + respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + + [..] + By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + example @ref HAL_RNG_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() + and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() + or @ref HAL_RNG_Init() function. + + [..] + When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -126,6 +164,24 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); #endif /* defined(RNG_CR_CED) */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if(hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + + if(hrng->MspInitCallback == NULL) + { + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hrng->MspInitCallback(hrng); + } +#else if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -134,6 +190,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; @@ -149,6 +206,9 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + /* Return function status */ return HAL_OK; } @@ -177,12 +237,25 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /* Clear RNG interrupt status flags */ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if(hrng->MspDeInitCallback == NULL) + { + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hrng->MspDeInitCallback(hrng); +#else /* DeInit the low level hardware */ HAL_RNG_MspDeInit(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Update the RNG state */ hrng->State = HAL_RNG_STATE_RESET; + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + /* Release Lock */ __HAL_UNLOCK(hrng); @@ -220,6 +293,233 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) */ } +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RNG Callback + * To be used instead of the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief Unregister an RNG Callback + * RNG callabck is redirected to the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief Register Data Ready RNG Callback + * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @param pCallback pointer to the Data Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = pCallback; + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief UnRegister the Data Ready RNG Callback + * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if(HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + } + else + { + /* Update the error code */ + hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + /** * @} */ @@ -346,8 +646,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) * not have enough entropy. In this case, it is recommended to clear the * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable * the RNG peripheral to reinitialize and restart the RNG. - * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS - * or CEIS are set. + * @note RNG ErrorCallback() API is called once whether SEIS or CEIS are set. * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval None @@ -360,7 +659,13 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_ERROR; +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI); @@ -381,8 +686,13 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_READY; - /* Data Ready callback */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Data Ready callback */ + hrng->ReadyDataCallback(hrng, hrng->RandomNumber); +#else + /* Call legacy weak Data Ready callback */ HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ } } } @@ -486,10 +796,12 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * @verbatim =============================================================================== - ##### Peripheral State functions ##### + ##### Peripheral State and Error functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral. + This subsection permits to : + (+) Return in run-time the status of the peripheral. + (+) Return the RNG handle error code @endverbatim * @{ @@ -506,6 +818,16 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) return hrng->State; } +/** + * @brief Return the RNG handle error code. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval RNG Error Code +*/ +uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +{ + /* Return RNG Error Code */ + return hrng->ErrorCode; +} /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h index 4eedd1bb24..691012698b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -83,22 +67,53 @@ typedef enum /** * @brief RNG Handle Structure definition */ -typedef struct +typedef struct __RNG_HandleTypeDef { - RNG_TypeDef *Instance; /*!< Register base address */ + RNG_TypeDef *Instance; /*!< Register base address */ #if defined(RNG_CR_CED) - RNG_InitTypeDef Init; /*!< RNG configuration parameters */ + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ #endif /* defined(RNG_CR_CED) */ - HAL_LockTypeDef Lock; /*!< RNG locking object */ + HAL_LockTypeDef Lock; /*!< RNG locking object */ - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - uint32_t RandomNumber; /*!< Last Generated RNG Data */ + __IO uint32_t ErrorCode; /*!< RNG Error code */ + + uint32_t RandomNumber; /*!< Last Generated RNG Data */ + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */ + void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */ + + void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */ + void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ }RNG_HandleTypeDef; +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RNG Callback ID enumeration definition + */ +typedef enum +{ + HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */ + + HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */ + HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */ + +} HAL_RNG_CallbackIDTypeDef; + +/** + * @brief HAL RNG Callback pointer definition + */ +typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */ +typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef * hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */ + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + /** * @} */ @@ -139,6 +154,17 @@ typedef struct */ #endif /* defined(RNG_CR_CED) */ +/** @defgroup RNG_Error_Definition RNG Error Definition + * @{ + */ +#define HAL_RNG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define HAL_RNG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000001U) /*!< Invalid Callback error */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +/** + * @} + */ + /** * @} */ @@ -152,7 +178,15 @@ typedef struct * @param __HANDLE__: RNG Handle * @retval None */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_RNG_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) +#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enable the RNG peripheral. @@ -180,7 +214,6 @@ typedef struct */ #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - /** * @brief Clear the selected RNG flag status. * @param __HANDLE__: RNG handle @@ -191,8 +224,6 @@ typedef struct */ #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ - - /** * @brief Enable the RNG interrupt. * @param __HANDLE__: RNG Handle @@ -249,6 +280,16 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng); void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + /** * @} */ @@ -272,10 +313,11 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit); */ /* Peripheral State functions **************************************************/ -/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions +/** @defgroup RNG_Exported_Functions_Group3 Peripheral State and Error functions * @{ */ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c index 73ffaf2f11..f1b74345f4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c @@ -5,41 +5,46 @@ * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization + * + Initialization/de-initialization functions * + Calendar (Time and Date) configuration * + Alarms (Alarm A and Alarm B) configuration * + WakeUp Timer configuration * + TimeStamp configuration * + Tampers configuration - * + Backup Data Registers configuration - * + RTC Tamper and TimeStamp Pins Selection + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection * + Interrupts and flags management - * + * @verbatim - =============================================================================== + =============================================================================== ##### RTC Operating Condition ##### =============================================================================== [..] The real-time clock (RTC) and the RTC backup registers can be powered from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC + To retain the content of the RTC backup registers and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. ##### Backup Domain Reset ##### =============================================================================== [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. + to their reset values. A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the + (#) Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). (#) VDD or VBAT power on, if both supplies have previously been powered off. (#) Tamper detection event resets all data backup registers. ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. + ================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data registers) + is protected against possible unwanted write accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for @@ -49,71 +54,114 @@ ##### How to use RTC Driver ##### =================================================================== [..] - (#) Enable the RTC domain access (see description in the section above). - (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour format using the HAL_RTC_Init() function. *** Time and Date configuration *** =================================== - [..] - (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() and HAL_RTC_SetDate() functions. - (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. *** Alarm configuration *** =========================== [..] - (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. - (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. ##### RTC and low power modes ##### - =================================================================== + ================================================================== [..] The MCU can be woken up from a low power mode by an RTC alternate function. [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and + These RTC alternate functions can wake up the system from the Stop and Standby low power modes. [..] The system can also wake up from low power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. [..] The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source is LSE or LSI. - @endverbatim + *** Callback registration *** + ============================================= + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. This is the recommended configuration + in order to optimize memory/code consumption footprint/performances. + The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() + or @ref HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -123,7 +171,8 @@ * @{ */ -/** @defgroup RTC RTC + +/** @addtogroup RTC * @brief RTC HAL module driver * @{ */ @@ -137,38 +186,38 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Functions RTC Exported Functions +/** @addtogroup RTC_Exported_Functions * @{ */ -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup RTC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This section provide functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers Write protection, enter and exit the RTC initialization mode, RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the + (++) When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize power consumption. (#) All RTC registers are Write protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter + (#) To configure the RTC Calendar, user application should enter initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is + and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar + (#) To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function implements the above software sequence (RSF clear and RSF check). @endverbatim @@ -176,206 +225,434 @@ */ /** - * @brief Initialize the RTC according to the specified parameters - * in the RTC_InitTypeDef structure and initialize the associated handle. - * @param hrtc: RTC handle + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status = HAL_ERROR; + /* Check the RTC peripheral state */ - if(hrtc == NULL) + if (hrtc != NULL) { - return HAL_ERROR; - } + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); +#if defined(STM32L412xx) || defined(STM32L422xx) + assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); +#endif - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ +#if defined(RTC_TAMPER1_SUPPORT) + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#endif /* RTC_TAMPER1_SUPPORT */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#if defined(RTC_TAMPER3_SUPPORT) + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ +#endif /* RTC_TAMPER3_SUPPORT */ + + if (hrtc->MspInitCallback == NULL) { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Process TAMP ip offset from RTC one */ + hrtc->TampOffset = (TAMP_BASE - RTC_BASE); +#endif + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + + if (status == HAL_OK) + { +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */ + hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE); +#else + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL); +#endif + /* Set RTC_CR register */ + hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + if (status == HAL_OK) + { +#if defined(STM32L412xx) || defined(STM32L422xx) + hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN); + hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); +#else + hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); + hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); +#endif + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } } } - - hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); - hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; } + + return status; } /** * @brief DeInitialize the RTC peripheral. - * @param hrtc: RTC handle - * @note This function doesn't reset the RTC Backup Data registers. + * @note This function does not reset the RTC Backup Data registers. + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + HAL_StatusTypeDef status = HAL_ERROR; - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) + /* Check the RTC peripheral state */ + if (hrtc != NULL) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + hrtc->State = HAL_RTC_STATE_BUSY; - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= RTC_CR_WUCKSEL; + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - tickstart = HAL_GetTick(); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) + if (status == HAL_OK) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + /* Reset all RTC CR register bits */ + hrtc->Instance->TR = 0x00000000U; + hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + hrtc->Instance->CR &= 0x00000000U; + + hrtc->Instance->WUTR = RTC_WUTR_WUT; + hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + hrtc->Instance->ALRMAR = 0x00000000U; + hrtc->Instance->ALRMBR = 0x00000000U; + hrtc->Instance->SHIFTR = 0x00000000U; + hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->ALRMASSR = 0x00000000U; + hrtc->Instance->ALRMBSSR = 0x00000000U; + + /* Exit initialization mode */ + status = RTC_ExitInitMode(hrtc); + + + if (status == HAL_OK) { +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Reset TAMP registers */ + ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset))->CR1 = 0xFFFF0000U; + ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset))->CR2 = 0x00000000U; +#else + /* Reset Tamper configuration register */ + hrtc->Instance->TAMPCR = 0x00000000U; + + /* Reset Option register */ + hrtc->Instance->OR = 0x00000000U; +#endif + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } - return HAL_TIMEOUT; - } - } + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; + hrtc->State = HAL_RTC_STATE_RESET; - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; - - /* Reset Tamper configuration register */ - hrtc->Instance->TAMPCR = 0x00000000; - - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000; - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; + /* Release Lock */ + __HAL_UNLOCK(hrtc); } } } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + return status; +} - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + +#if defined(RTC_TAMPER1_SUPPORT) + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; +#endif /* RTC_TAMPER1_SUPPORT */ + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + +#if defined(RTC_TAMPER3_SUPPORT) + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; +#endif /* RTC_TAMPER3_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } - hrtc->State = HAL_RTC_STATE_RESET; - /* Release Lock */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } +/** + * @brief Unregister an RTC Callback + * RTC callback is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + +#if defined(RTC_TAMPER1_SUPPORT) + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; +#endif /* RTC_TAMPER1_SUPPORT */ + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; + +#if defined(RTC_TAMPER3_SUPPORT) + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + break; +#endif /* RTC_TAMPER3_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /** * @brief Initialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -387,31 +664,31 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitialize the RTC MSP. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTC_MspDeInit could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions +/** @addtogroup RTC_Exported_Functions_Group2 * @brief RTC Time and Date functions * @verbatim =============================================================================== ##### RTC Time and Date functions ##### =============================================================================== - + [..] This section provides functions allowing to configure Time and Date features @endverbatim @@ -420,152 +697,127 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Set RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg; + HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sTime->Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); - } - /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if (Format == RTC_FORMAT_BIN) + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + else + { + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + } - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; + status = RTC_ExitInitMode(hrtc); } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; } /** * @brief Get RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned - * with input format (BIN or BCD), also SubSeconds field returning the - * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler - * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds * value in second fraction ratio with time unit following generic formula: * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers to ensure consistency between the time and date values. * Reading RTC current time locks the values in calendar shadow registers until Current date is read * to ensure consistency between the time and date values. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -575,18 +827,18 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Get SecondFraction structure field from the corresponding register field*/ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - + /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); @@ -599,128 +851,101 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Set RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg; + HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Process Locked */ + __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); } else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; + status = RTC_ExitInitMode(hrtc); } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY ; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; } /** * @brief Get RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers to ensure consistency between the time and date values. * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -729,13 +954,13 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the date structure parameters to Binary format */ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); @@ -749,14 +974,14 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions +/** @addtogroup RTC_Exported_Functions_Group3 * @brief RTC Alarm functions * -@verbatim +@verbatim =============================================================================== ##### RTC Alarm functions ##### - =============================================================================== - + =============================================================================== + [..] This section provides functions allowing to configure Alarm feature @endverbatim @@ -764,18 +989,17 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Set the specified RTC Alarm. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg, subsecondtmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -790,22 +1014,22 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); } @@ -813,50 +1037,48 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } else { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + ((uint32_t)sAlarm->AlarmMask)); } /* Configure the Alarm A or Alarm B Sub Second registers */ @@ -866,51 +1088,21 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) + if (sAlarm->Alarm == RTC_ALARM_A) { /* Disable the Alarm A interrupt */ __HAL_RTC_ALARMA_DISABLE(hrtc); - + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - tickstart = HAL_GetTick(); +#if defined (RTC_FLAG_ALRAWF) + uint32_t tickstart = HAL_GetTick(); /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -923,6 +1115,42 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA return HAL_TIMEOUT; } } +#endif + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + /* Clear flag alarm B */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + +#if defined (RTC_FLAG_ALRBWF) + uint32_t tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } +#endif hrtc->Instance->ALRMBR = (uint32_t)tmpreg; /* Configure the Alarm B Sub Second register */ @@ -945,21 +1173,20 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg, subsecondtmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -969,27 +1196,27 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); } @@ -997,48 +1224,49 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } + } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } else { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + ((uint32_t)sAlarm->AlarmMask)); } /* Configure the Alarm A or Alarm B Sub Second registers */ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); @@ -1047,53 +1275,20 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) + if (sAlarm->Alarm == RTC_ALARM_A) { /* Disable the Alarm A interrupt */ __HAL_RTC_ALARMA_DISABLE(hrtc); - + /* Clear flag alarm A */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - tickstart = HAL_GetTick(); +#if defined (RTC_FLAG_ALRAWF) + uint32_t tickstart = HAL_GetTick(); /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear flag alarm B */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1106,6 +1301,43 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef return HAL_TIMEOUT; } } +#endif + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* Clear flag alarm B */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + +#if defined (RTC_FLAG_ALRBWF) + uint32_t tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } +#endif hrtc->Instance->ALRMBR = (uint32_t)tmpreg; /* Configure the Alarm B Sub Second register */ @@ -1118,13 +1350,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* RTC Alarm Interrupt Configuration: EXTI configuration */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1134,8 +1365,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactivate the specified RTC Alarm. - * @param hrtc: RTC handle - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB @@ -1143,8 +1374,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { - uint32_t tickstart = 0; - /* Check the parameters */ assert_param(IS_RTC_ALARM(Alarm)); @@ -1156,7 +1385,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - if(Alarm == RTC_ALARM_A) + if (Alarm == RTC_ALARM_A) { /* AlarmA */ __HAL_RTC_ALARMA_DISABLE(hrtc); @@ -1164,12 +1393,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - tickstart = HAL_GetTick(); - +#if defined (RTC_FLAG_ALRAWF) + uint32_t tickstart = HAL_GetTick(); /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if( (HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1182,6 +1411,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar return HAL_TIMEOUT; } } +#endif } else { @@ -1189,14 +1419,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar __HAL_RTC_ALARMB_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) +#if defined (RTC_FLAG_ALRBWF) + uint32_t tickstart = HAL_GetTick(); + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1209,6 +1439,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar return HAL_TIMEOUT; } } +#endif } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1218,38 +1449,48 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return HAL_OK; } /** * @brief Get the RTC Alarm value and masks. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg, subsecondtmpreg; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_ALARM(Alarm)); - if(Alarm == RTC_ALARM_A) + if (Alarm == RTC_ALARM_A) { /* AlarmA */ sAlarm->Alarm = RTC_ALARM_A; tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } else { @@ -1257,20 +1498,19 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } - /* Fill the structure with the read parameters */ - /* ALRMAR/ALRMBR registers have same mapping) */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); @@ -1283,38 +1523,80 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Handle Alarm interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { /* Clear the EXTI's line Flag for RTC Alarm */ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - /* As alarms are sharing the same EXTI line, exit when no more pending Alarm event */ - while(((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) || - ((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET))) +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Get interrupt status */ + uint32_t tmp = hrtc->Instance->MISR; + + if ((tmp & RTC_MISR_ALRAMF) != 0u) { - /* Get the AlarmA interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) + /* Clear the AlarmA interrupt pending bit */ + hrtc->Instance->SCR = RTC_SCR_CALRAF; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0u) + { + /* Clear the AlarmB interrupt pending bit */ + hrtc->Instance->SCR = RTC_SCR_CALRBF; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif + } + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + /* Get the AlarmA interrupt source enable status */ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) + { + /* Get the pending status of the AlarmA Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) { /* Clear the AlarmA interrupt pending bit */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - /* AlarmA callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmAEventCallback(hrtc); +#else HAL_RTC_AlarmAEventCallback(hrtc); +#endif } + } - /* Get the AlarmB interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)) + /* Get the AlarmB interrupt source enable status */ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) + { + /* Get the pending status of the AlarmB Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) { /* Clear the AlarmB interrupt pending bit */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - /* AlarmB callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmBEventCallback(hrtc); +#else HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif } } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1322,7 +1604,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) @@ -1337,20 +1619,20 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle AlarmA Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + uint32_t tickstart = HAL_GetTick(); + + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1371,8 +1653,8 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @} */ -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions +/** @addtogroup RTC_Exported_Functions_Group4 + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -1389,30 +1671,38 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the + * @note The RTC Resynchronization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar + * @note To read the calendar through the shadow registers after Calendar * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Clear RSF flag */ +#if defined(STM32L412xx) || defined(STM32L422xx) + hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; +#else hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; +#endif tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) + while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U) +#else + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) +#endif { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -1425,13 +1715,13 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions +/** @addtogroup RTC_Exported_Functions_Group5 + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Get RTC state @@ -1441,10 +1731,10 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Return the RTC handle state. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) { /* Return RTC handle state */ return hrtc->State; @@ -1458,69 +1748,134 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Private_Functions RTC Private functions +/** @addtogroup RTC_Private_Functions * @{ */ /** * @brief Enter the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) + if ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) + { + /* Set the Initialization mode */ + SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + } + } +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) { /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT)) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + status = HAL_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; } } } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ - return HAL_OK; + return status; } +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Exit Initialization mode */ +#if defined(STM32L412xx) || defined(STM32L422xx) + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); +#else + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ISR, RTC_ISR_INIT); +#endif + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + } + + return status; +} + + /** * @brief Convert a 2 digit decimal to BCD format. - * @param Value: Byte to be converted + * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) { - uint32_t bcdhigh = 0; + uint32_t bcdhigh = 0U; + uint8_t temp = Value; - while(Value >= 10) + while (temp >= 10U) { bcdhigh++; - Value -= 10; + temp -= 10U; } - return ((uint8_t)(bcdhigh << 4) | Value); + return ((uint8_t)(bcdhigh << 4U) | temp); } /** * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted + * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) { - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); + uint8_t tmp; + tmp = ((Value & 0xF0U) >> 4U) * 10U; + return (tmp + (Value & 0x0FU)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h index 25f40e0447..5b055ce772 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h @@ -6,50 +6,33 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_H -#define __STM32L4xx_HAL_RTC_H +#ifndef STM32L4xx_HAL_RTC_H +#define STM32L4xx_HAL_RTC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" -#include "stm32l4xx_ll_rtc.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ */ -/** @addtogroup RTC +/** @defgroup RTC RTC * @{ */ @@ -57,20 +40,21 @@ /** @defgroup RTC_Exported_Types RTC Exported Types * @{ */ -/** - * @brief HAL State structures definition + +/** + * @brief HAL State structures definition */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ -}HAL_RTCStateTypeDef; +} HAL_RTCStateTypeDef; -/** +/** * @brief RTC Configuration Structure definition */ typedef struct @@ -80,25 +64,29 @@ typedef struct uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ - uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. + uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -}RTC_InitTypeDef; +#if defined(STM32L412xx) || defined(STM32L422xx) + uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. + This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ +#endif +} RTC_InitTypeDef; -/** - * @brief RTC Time structure definition +/** + * @brief RTC Time structure definition */ typedef struct { @@ -114,26 +102,26 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity */ - + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit in CR register to store the operation. This parameter can be a value of @ref RTC_StoreOperation_Definitions */ -}RTC_TimeTypeDef; +} RTC_TimeTypeDef; -/** +/** * @brief RTC Date structure definition */ typedef struct @@ -150,9 +138,9 @@ typedef struct uint8_t Year; /*!< Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ -}RTC_DateTypeDef; +} RTC_DateTypeDef; -/** +/** * @brief RTC Alarm structure definition */ typedef struct @@ -161,7 +149,7 @@ typedef struct uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ @@ -174,22 +162,68 @@ typedef struct uint32_t Alarm; /*!< Specifies the alarm . This parameter can be a value of @ref RTC_Alarms_Definitions */ -}RTC_AlarmTypeDef; +} RTC_AlarmTypeDef; -/** - * @brief Time Handle Structure definition +/** + * @brief RTC Handle Structure definition */ -typedef struct +typedef struct __RTC_HandleTypeDef { RTC_TypeDef *Instance; /*!< Register base address */ +#if defined(STM32L412xx) || defined(STM32L422xx) + uint32_t TampOffset; /*!< Offset to TAMP instance */ +#endif RTC_InitTypeDef Init; /*!< RTC required parameters */ HAL_LockTypeDef Lock; /*!< RTC locking object */ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ -}RTC_HandleTypeDef; +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ +#if defined(RTC_TAMPER1_SUPPORT) + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ +#endif /* RTC_TAMPER1_SUPPORT */ + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#if defined(RTC_TAMPER3_SUPPORT) + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ +#endif /* RTC_TAMPER3_SUPPORT */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0u, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 1u, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u, /*!< RTC WakeUp Timer Event Callback ID */ +#if defined(RTC_TAMPER1_SUPPORT) + HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, /*!< RTC Tamper 1 Callback ID */ +#endif /* RTC_TAMPER1_SUPPORT */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, /*!< RTC Tamper 2 Callback ID */ +#if defined(RTC_TAMPER3_SUPPORT) + HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, /*!< RTC Tamper 3 Callback ID */ +#endif /* RTC_TAMPER3_SUPPORT */ + HAL_RTC_MSPINIT_CB_ID = 7u, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 8u /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ /** * @} @@ -200,11 +234,25 @@ typedef struct * @{ */ -/** @defgroup RTC_Hour_Formats RTC Hour Formats +/** @defgroup RTC_Hour_Formats_Definitions RTC Hour Formats Definitions * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) +#define RTC_HOURFORMAT_24 0x00000000u +#define RTC_HOURFORMAT_12 RTC_CR_FMT +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definitions + * @{ + */ +#define RTC_OUTPUT_DISABLE 0x00000000u +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE +#endif /** * @} */ @@ -212,8 +260,8 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} */ @@ -221,8 +269,24 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) -#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u +#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE +#else +#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMOUTTYPE +#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000u +#endif +/** + * @} + */ + +/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_PULLUP_NONE 0x00000000u +#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU +#endif /** * @} */ @@ -230,8 +294,13 @@ typedef struct /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000) -#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN +#else +#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_POS1 RTC_OR_OUT_RMP +#endif /** * @} */ @@ -240,26 +309,26 @@ typedef struct * @{ */ #define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x01) /** * @} */ -/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H +#define RTC_DAYLIGHTSAVING_NONE 0x00000000u /** * @} */ -/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) +#define RTC_STOREOPERATION_RESET 0x00000000u +#define RTC_STOREOPERATION_SET RTC_CR_BKP /** * @} */ @@ -267,29 +336,30 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x00000000) -#define RTC_FORMAT_BCD ((uint32_t)0x00000001) +#define RTC_FORMAT_BIN 0x00000000u +#define RTC_FORMAT_BCD 0x00000001u /** * @} */ -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format) * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) + /** * @} */ @@ -297,36 +367,38 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) + /** * @} */ -/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL + /** * @} */ - -/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define RTC_ALARMMASK_NONE 0x00000000u +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS) + /** * @} */ @@ -334,48 +406,50 @@ typedef struct /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions * @{ */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + /** * @} */ + /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison. Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison. Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match + to activate alarm. */ /** * @} */ @@ -383,42 +457,85 @@ typedef struct /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */ -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */ -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */ -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */ -#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */ -#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */ -#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */ +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +/** + * @} + */ + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */ /** * @} */ /** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * Elements values convention: 000000XX000YYYYYb + * - YYYYY : Interrupt flag position in the XX register (5bits) + * - XX : Interrupt status register (2bits) + * - 01: ICSR register + * - 10: SR or SCR or MISR or SMISR registers * @{ */ -#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) -#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) -#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) -#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) -#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) -#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) -#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF) -#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) -#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) -#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) -#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) -#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) -#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) -#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) -#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) -#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) -#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) +#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */ +#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */ +#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */ +#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */ +#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */ +#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */ +#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */ +#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */ /** * @} */ +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ + +/** + * @} + */ + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * @{ + */ +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF +#define RTC_FLAG_TSF RTC_ISR_TSF +#define RTC_FLAG_ITSF RTC_ISR_ITSF +#define RTC_FLAG_WUTF RTC_ISR_WUTF +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF +#define RTC_FLAG_INITF RTC_ISR_INITF +#define RTC_FLAG_RSF RTC_ISR_RSF +#define RTC_FLAG_INITS RTC_ISR_INITS +#define RTC_FLAG_SHPF RTC_ISR_SHPF +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF +/** + * @} + */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** * @} */ @@ -428,129 +545,193 @@ typedef struct * @{ */ -/** @brief Reset RTC handle state. - * @param __HANDLE__: RTC handle. +/** @brief Reset RTC handle state + * @param __HANDLE__ RTC handle. * @retval None */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0u) +#else #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0u) /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) - + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0u) /** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @brief Add 1 hour (summer time change). + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET * @retval None */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H); \ + MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0u); + +/** + * @brief Subtract 1 hour (winter time change). + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H); \ + MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0u); + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) /** * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U) +#else +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U) +#endif +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @arg @ref RTC_FLAG_ALRAWF + * @arg @ref RTC_FLAG_ALRBWF * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Check whether the specified RTC Alarm interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF))) : \ + ((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF))) +#else +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))) +#endif /** * @brief Enable interrupt on the RTC Alarm associated Exti line. @@ -566,57 +747,57 @@ typedef struct /** * @brief Enable event on the RTC Alarm associated Exti line. - * @retval None + * @retval None. */ #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) /** * @brief Disable event on the RTC Alarm associated Exti line. - * @retval None + * @retval None. */ #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) /** - * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) /** - * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) /** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0u) /** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0u) /** * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. @@ -644,23 +825,30 @@ typedef struct #include "stm32l4xx_hal_rtc_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions +/** @defgroup RTC_Exported_Functions RTC Exported Functions * @{ */ -/** @addtogroup RTC_Exported_Functions_Group1 +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ /** * @} */ -/** @addtogroup RTC_Exported_Functions_Group2 +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions * @{ */ /* RTC Time and Date functions ************************************************/ @@ -672,7 +860,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @addtogroup RTC_Exported_Functions_Group3 +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions * @{ */ /* RTC Alarm functions ********************************************************/ @@ -681,27 +869,26 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} */ -/** @addtogroup RTC_Exported_Functions_Group4 +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); /** * @} */ -/** @addtogroup RTC_Exported_Functions_Group5 +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions * @{ */ /* Peripheral State functions *************************************************/ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); - /** * @} */ @@ -710,21 +897,31 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @} */ -/* Private types -------------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup RTC_Private_Constants RTC Private Constants * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK 0x007F7F7FU -#define RTC_DR_RESERVED_MASK 0x00FFFF3FU -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) -#define RTC_TIMEOUT_VALUE 1000 - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ +#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) + +#define RTC_INIT_MASK 0xFFFFFFFFu +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) +#else +#define RTC_RSF_MASK (~(RTC_ISR_INIT | RTC_ISR_RSF)) +#endif + +#define RTC_TIMEOUT_VALUE 1000u + +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Alarm event */ /** * @} @@ -737,7 +934,19 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); /** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters * @{ - */ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) +#else +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP)) +#endif #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ ((FORMAT) == RTC_HOURFORMAT_24)) @@ -748,10 +957,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ + ((TYPE) == RTC_OUTPUT_PULLUP_ON)) +#endif + #define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ ((REMAP) == RTC_OUTPUT_REMAP_POS1)) -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ @@ -760,13 +975,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ ((OPERATION) == RTC_STOREOPERATION_SET)) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ + ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u)) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -776,7 +992,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -789,40 +1005,27 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \ + ((ALARM) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0u) || \ + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u) /** * @} @@ -832,14 +1035,18 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @} */ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup RTC_Private_Functions +/* Private functions -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions * @{ */ - -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); uint8_t RTC_ByteToBcd2(uint8_t Value); uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + /** * @} @@ -857,6 +1064,7 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); } #endif -#endif /* __STM32L4xx_HAL_RTC_H */ +#endif /* STM32L4xx_HAL_RTC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c index 31a6fe7de1..880b66f487 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c @@ -3,13 +3,13 @@ * @file stm32l4xx_hal_rtc_ex.c * @author MCD Application Team * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: * + RTC Time Stamp functions - * + RTC Tamper functions + * + RTC Tamper functions * + RTC Wake-up functions * + Extended Control functions - * + Extended RTC features functions + * + Extended RTC features functions * @verbatim ============================================================================== @@ -22,31 +22,31 @@ *** RTC Wakeup configuration *** ================================ - [..] + [..] (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode + function. You can also configure the RTC Wakeup timer with interrupt mode using the HAL_RTCEx_SetWakeUpTimer_IT() function. (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() function. - + *** Outputs configuration *** ============================= [..] The RTC has 2 different outputs: (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B and WaKeUp signals. - To output the selected RTC signal, use the HAL_RTC_Init() function. + To output the selected RTC signal, use the HAL_RTC_Init() function. (+) RTC_CALIB: this output is 512Hz signal or 1Hz. To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. - (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on + (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on the RTC_OR register. (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is - automatically configured in output alternate function. + automatically configured in output alternate function. *** Smooth digital Calibration configuration *** ================================================ [..] (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() function. *** TimeStamp configuration *** @@ -66,54 +66,46 @@ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() function. - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, NoErase, MaskFlag, precharge or discharge and - Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper - with interrupt mode using HAL_RTCEx_SetTamper_IT() function. - (+) The default configuration of the Tamper erases the backup registers. To avoid - erase, enable the NoErase field on the RTC_TAMPCR register. + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the RTC_TAMPCR register. + (+) STM32L412xx and STM32L422xx only : With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + (+) STM32L412xx and STM32L422xx only : If you don't intend to have tamper using RTC clock, you can bypass its initialization + by setting ClockEnable inti field to RTC_CLOCK_DISABLE. + (+) STM32L412xx and STM32L422xx only : Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using + setting Interrupt field. - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + (+) STM32L412xx and STM32L422xx only : Before calling these functions you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -123,7 +115,7 @@ * @{ */ -/** @defgroup RTCEx RTCEx +/** @addtogroup RTCEx * @brief RTC Extended HAL module driver * @{ */ @@ -132,6 +124,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(STM32L412xx) || defined(STM32L422xx) +#else #if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) #define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ @@ -157,26 +151,27 @@ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF) #endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions +/** @addtogroup RTCEx_Exported_Functions * @{ */ -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @brief RTC TimeStamp and Tamper functions * @verbatim =============================================================================== ##### RTC TimeStamp and Tamper functions ##### =============================================================================== - - [..] This section provide functions allowing to configure TimeStamp feature + + [..] This section provides functions allowing to configure TimeStamp feature @endverbatim * @{ @@ -185,15 +180,15 @@ /** * @brief Set TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * The RTC TimeStamp Pin is per default PC13, but for reasons of @@ -202,12 +197,15 @@ */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(RTC_TimeStampPin); + /* Process Locked */ __HAL_LOCK(hrtc); @@ -216,7 +214,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - tmpreg|= TimeStampEdge; + tmpreg |= TimeStampEdge; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -230,9 +228,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; @@ -240,16 +238,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Set TimeStamp with Interrupt. - * @param hrtc: RTC handle * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * The RTC TimeStamp Pin is per default PC13, but for reasons of @@ -258,13 +256,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - /* Process Locked */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -283,11 +284,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti __HAL_RTC_TIMESTAMP_ENABLE(hrtc); /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS); /* RTC timestamp Interrupt Configuration: EXTI configuration */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivate TimeStamp. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) { - uint32_t tmpreg = 0; + uint32_t tmpreg; /* Process Locked */ __HAL_LOCK(hrtc); @@ -341,8 +341,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Set Internal TimeStamp. * @note This API must be called before enabling the internal TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) @@ -364,7 +363,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; @@ -372,8 +371,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Deactivate Internal TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) @@ -402,18 +400,18 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Get the RTC TimeStamp value. - * @param hrtc: RTC handle - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. + * @param hrtc RTC handle + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0, tmpdate = 0; + uint32_t tmptime, tmpdate; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -423,20 +421,20 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the TimeStamp structure parameters to Binary format */ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); @@ -456,317 +454,172 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe return HAL_OK; } -/** - * @brief Set Tamper. - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate Tamper. - * @param hrtc: RTC handle - * @param Tamper: Selected tamper pin. - * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); - -#if defined(RTC_TAMPER1_SUPPORT) - if ((Tamper & RTC_TAMPER_1) != 0) - { - /* Disable the Tamper1 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); - } -#endif /* RTC_TAMPER1_SUPPORT */ - if ((Tamper & RTC_TAMPER_2) != 0) - { - /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); - } -#if defined(RTC_TAMPER3_SUPPORT) - if ((Tamper & RTC_TAMPER_3) != 0) - { - /* Disable the Tamper3 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); - } -#endif /* RTC_TAMPER3_SUPPORT */ - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - /** * @brief Handle TimeStamp interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ +#if defined(STM32L412xx) || defined(STM32L422xx) + void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ +{ + + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - /* As Tampers and TimeStamp are sharing the same EXTI line, exit when no more pending event */ - while( - ((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) -#if defined(RTC_TAMPER1_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) -#endif /* RTC_TAMPER1_SUPPORT */ - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) -#if defined(RTC_TAMPER3_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) -#endif /* RTC_TAMPER3_SUPPORT */ - ) + if ((hrtc->Instance->MISR & RTC_MISR_TSMF) != 0u) { - - /* Get the TimeStamp interrupt source enable status and pending flag status */ - if((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) - { - /* TIMESTAMP callback */ - HAL_RTCEx_TimeStampEventCallback(hrtc); - - /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - } +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif + /* Not immediatly clear flags because the content of RTC_TSTR and RTC_TSDR arecleared when TSF bit is reset.*/ + hrtc->Instance->SCR = RTC_SCR_CTSF; + } + + /* Get interrupt status */ + uint32_t tmp = tamp->MISR; + + /* Immediatly clear flags */ + tamp->SCR = tmp; #if defined(RTC_TAMPER1_SUPPORT) - /* Get the Tamper1 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) - { - /* Clear the Tamper1 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Tamper1 callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); - } + /* Check Tamper1 status */ + if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif + } #endif /* RTC_TAMPER1_SUPPORT */ - - /* Get the Tamper2 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) - { - /* Clear the Tamper2 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Tamper2 callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); - } + + /* Check Tamper2 status */ + if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif + } #if defined(RTC_TAMPER3_SUPPORT) - /* Get the Tamper3 interrupts source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) - { - /* Clear the Tamper3 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Tamper3 callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); - } -#endif /* RTC_TAMPER3_SUPPORT */ - + /* Check Tamper3 status */ + if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif } - + +#endif /* RTC_TAMPER3_SUPPORT */ + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); + + /* Get the TimeStamp interrupt source enable status and pending flag status */ + if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) + { + if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U) + { + /* TIMESTAMP callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->TimeStampEventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + + /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + } + } + +#if defined(RTC_TAMPER1_SUPPORT) + /* Get the Tamper1 interrupt source enable status and pending flag status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) + { + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) + { + /* Clear the Tamper1 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + + /* Tamper1 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper1EventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + } + } +#endif /* RTC_TAMPER1_SUPPORT */ + + /* Get the Tamper2 interrupt source enable status and pending flag status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) + { + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) + { + /* Clear the Tamper2 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + + /* Tamper2 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper2EventCallback(hrtc); +#else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ + } + } + +#if defined(RTC_TAMPER3_SUPPORT) + /* Get the Tamper3 interrupts source enable status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) + { + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) + { + /* Clear the Tamper3 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + + /* Tamper3 callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper3EventCallback(hrtc); +#else + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + } +#endif /* RTC_TAMPER3_SUPPORT */ + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** - * @brief TimeStamp callback. - * @param hrtc: RTC handle + * @brief TimeStamp callback. + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) @@ -776,84 +629,35 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ -} - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Tamper 1 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file */ } -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Tamper 2 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ -} - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Tamper 3 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} -#endif /* RTC_TAMPER3_SUPPORT */ /** * @brief Handle TimeStamp polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ +{ uint32_t tickstart = HAL_GetTick(); - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) { /* Clear the TIMESTAMP OverRun Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; + hrtc->State = HAL_RTC_STATE_ERROR; - return HAL_ERROR; + return HAL_ERROR; } - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -861,125 +665,25 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 } } - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Handle Tamper 1 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Handle Tamper 2 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; return HAL_OK; } -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Handle Tamper 3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER3_SUPPORT */ - /** * @} */ -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions +/** @addtogroup RTCEx_Exported_Functions_Group2 * @brief RTC Wake-up functions * -@verbatim +@verbatim =============================================================================== ##### RTC Wake-up functions ##### - =============================================================================== + =============================================================================== - [..] This section provide functions allowing to configure Wake-up feature + [..] This section provides functions allowing to configure Wake-up feature @endverbatim * @{ @@ -987,20 +691,20 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Set wake up timer. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1008,22 +712,33 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ +#if defined(STM32L412xx) || defined(STM32L422xx) + if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U) +#else + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) +#endif { tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) +#if defined(STM32L412xx) || defined(STM32L422xx) + while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U) +#else + while (READ_BIT(hrtc->Instance->ISR, RTC_ISR_WUTWF) == 0U) +#endif { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_TIMEOUT; @@ -1031,38 +746,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } } - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; + MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + WRITE_REG(hrtc->Instance->WUTR, (uint32_t)WakeUpCounter); - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + /* Enable the Wakeup Timer */ + SET_BIT(hrtc->Instance->CR, RTC_CR_WUTE); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1077,20 +768,33 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /** * @brief Set wake up timer with interrupt. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual) + * - Only available for STM32L412xx and STM32L422xx + * - No effect if WakeUpAutoClr is set to zero + * - This feature is meaningful in case of Low power mode to avoid any RTC software execution after Wake Up. + * That is why when WakeUpAutoClr is set, EXTI is configured as EVENT instead of Interrupt to avoid useless IRQ handler execution. * @retval HAL status */ +#if defined(STM32L412xx) || defined(STM32L422xx) +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr) +#else HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +#endif { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); +#if defined(STM32L412xx) || defined(STM32L422xx) + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); +#endif - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1098,77 +802,82 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE); + + /* Clear flag Wake-Up */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ +#if defined(STM32L412xx) || defined(STM32L422xx) + if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U) +#else + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) +#endif { tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) +#if defined(STM32L412xx) || defined(STM32L422xx) + while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U) +#else + while (READ_BIT(hrtc->Instance->ISR, RTC_ISR_WUTWF) == 0U) +#endif { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_TIMEOUT; } } } - /* Disable the Wake-Up timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Clear flag Wake-Up */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Configure the Wakeup Timer counter and auto clear value */ + hrtc->Instance->WUTR = (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos)); +#else /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; +#endif /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; + MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ +#if defined(STM32L412xx) || defined(STM32L422xx) + /* In case of WUT autoclr, the IRQ handler should not be called */ + if (WakeUpAutoClr != 0u) + { + /* RTC WakeUpTimer EXTI Configuration: Event configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT(); + } + else + { + /* RTC WakeUpTimer EXTI Configuration: Interrupt configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + } +#else /* defined(STM32L412xx) || defined(STM32L422xx) */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); +#endif /* defined(STM32L412xx) || defined(STM32L422xx) */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1178,14 +887,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /** * @brief Deactivate wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart; - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1197,13 +906,13 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1230,7 +939,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Get wake up timer counter. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval Counter value */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -1241,22 +950,35 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Handle Wake Up Timer interrupt request. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { /* Clear the EXTI's line Flag for RTC WakeUpTimer */ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - + + +#if defined(STM32L412xx) || defined(STM32L422xx) + if ((hrtc->Instance->MISR & RTC_MISR_WUTMF) != 0u) + { + /* Immediately clear flags */ + hrtc->Instance->SCR = RTC_SCR_CWUTF; +#else /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET) - { + if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) + { /* Clear the WAKEUPTIMER interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); +#endif - /* WAKEUPTIMER callback */ + /* WAKEUPTIMER callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call WakeUpTimerEvent registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } /* Change RTC state */ @@ -1265,7 +987,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief Wake Up Timer callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) @@ -1278,24 +1000,24 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) */ } + /** * @brief Handle Wake Up Timer Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; } } @@ -1303,7 +1025,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /* Clear the WAKEUPTIMER Flag */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1315,13 +1037,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin */ -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions +/** @addtogroup RTCEx_Exported_Functions_Group3 * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Write a data in a specified RTC Backup data register @@ -1329,6 +1051,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin (+) Set the Coarse calibration parameters. (+) Deactivate the Coarse calibration parameters (+) Set the Smooth calibration parameters. + (+) STM32L412xx and STM32L422xx only : Set Low Power calibration parameter. (+) Configure the Synchronization Shift Control Settings. (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). @@ -1341,80 +1064,36 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @{ */ -/** - * @brief Write a data in a specified RTC Backup data register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Read data from the specified RTC Backup data Register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} /** * @brief Set the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field * SmoothCalibMinusPulsesValue must be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1423,21 +1102,29 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) + if ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) +#else + if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) +#endif { tickstart = HAL_GetTick(); /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) + while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) +#else + while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) +#endif { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - + hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1447,13 +1134,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); + MODIFY_REG(hrtc->Instance->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1461,27 +1148,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo return HAL_OK; } +#if defined(STM32L412xx) || defined(STM32L422xx) /** - * @brief Configure the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. + * @brief Select the low power Calibration mode. + * @param hrtc: RTC handle + * @param LowPowerCalib: Low power Calibration mode. + * This parameter can be can be one of the following values : + * @arg RTC_LPCAL_SET: Low power mode. + * @arg RTC_LPCAL_RESET: High consumption mode. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib) { - uint32_t tickstart = 0; - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib)); - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1489,61 +1171,109 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - tickstart = HAL_GetTick(); + /* Configure the Smooth calibration settings */ + MODIFY_REG(hrtc->Instance->CALR, RTC_CALR_LPCAL, LowPowerCalib); - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/** + * @brief Configure the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values: + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed*/ +#if defined(STM32L412xx) || defined(STM32L422xx) + while ((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U) +#else + while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) +#endif + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Check if the reference clock detection is disabled */ + if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; + return HAL_ERROR; } } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1559,14 +1289,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /** * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) { /* Check the parameters */ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); @@ -1601,12 +1331,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /** * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) { - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1630,11 +1360,13 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) /** * @brief Enable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1643,47 +1375,39 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) { __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1691,49 +1415,39 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) { __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** * @brief Enable the Bypass Shadow feature. - * @param hrtc: RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1744,7 +1458,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + SET_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1760,12 +1474,12 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Disable the Bypass Shadow feature. - * @param hrtc: RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. + * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1775,8 +1489,8 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + /* Clear the BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1794,24 +1508,24 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions +/** @addtogroup RTCEx_Exported_Functions_Group4 * @brief Extended features functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) RTC Alarm B callback (+) RTC Poll for Alarm B request - + @endverbatim * @{ */ /** * @brief Alarm B callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) @@ -1826,19 +1540,19 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Handle Alarm B Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ +{ uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1855,6 +1569,700 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t return HAL_OK; } +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @brief Extended RTC Tamper functions + * +@verbatim + ============================================================================== + ##### Tamper functions ##### + ============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + (+) Enable the Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function. + You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the TAMP_TAMPCR register. + [..] + (+) Enable Internal Tamper and configure it with interrupt, timestamp using + the HAL_RTCEx_SetInternalTamper() function. + +@endverbatim + * @{ + */ + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Set Tamper + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) + || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = tamp->CR2; + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + /* Configure the tamper trigger bit */ + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + /* Configure the tamper flags masking bit */ + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + /* Configure the tamper backup registers erasure bit */ + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + tamp->CR2 = tmpreg; + + /* Configure filtering parameters */ + tamp->FLTCR = (sTamper->Filter) | (sTamper->SamplingFrequency) | \ + (sTamper->PrechargeDuration) | (sTamper->TamperPullUp); + + /* Configure Timestamp saving on tamper detection */ + if ((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection)) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS); + hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection)); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* Enable selected tamper */ + tamp->CR1 |= (sTamper->Tamper); + + return HAL_OK; +} +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @brief Set Tamper. + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the tamper trigger */ + if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + sTamper->NoErase = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if ((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } +#if defined(RTC_TAMPER3_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + sTamper->MaskFlag = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if ((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } +#if defined(RTC_TAMPER3_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase | \ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | \ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); + + hrtc->Instance->TAMPCR |= tmpreg; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Set Tamper with interrupt. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Copy configuration register into temporary variable */ + tmpreg = tamp->CR2; + + /* Clear the bits that are going to be configured and leave the others unchanged */ + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + /* Configure the tamper flags masking bit */ + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + /* Configure the tamper backup registers erasure bit */ + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + tamp->CR2 = tmpreg; + + /* Configure filtering parameters */ + tamp->FLTCR = (sTamper->Filter) | (sTamper->SamplingFrequency) | \ + (sTamper->PrechargeDuration) | (sTamper->TamperPullUp); + + /* Configure Timestamp saving on tamper detection */ + if ((hrtc->Instance->CR & RTC_CR_TAMPTS) != (sTamper->TimeStampOnTamperDetection)) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + tmpreg = (hrtc->Instance->CR & ~RTC_CR_TAMPTS); + hrtc->Instance->CR = (tmpreg | (sTamper->TimeStampOnTamperDetection)); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* Configure RTC Tamper Interrupt: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE(); + + /* Enable interrupt on selected tamper */ + tamp->IER |= sTamper->Tamper; + + /* Enable selected tamper */ + tamp->CR1 |= sTamper->Tamper; + + return HAL_OK; +} +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/** + * @brief Set Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the tamper trigger */ + if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + sTamper->NoErase = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if ((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } +#if defined(RTC_TAMPER3_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + sTamper->MaskFlag = 0; +#if defined(RTC_TAMPER1_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } +#endif /* RTC_TAMPER1_SUPPORT */ + if ((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } +#if defined(RTC_TAMPER3_SUPPORT) + if ((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } +#endif /* RTC_TAMPER3_SUPPORT */ + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase | \ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | \ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); + + hrtc->Instance->TAMPCR |= tmpreg; + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); + + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Disable the selected Tamper pin */ + tamp->CR1 &= ~Tamper; + + /* Clear tamper mask/noerase/trigger configuration */ + tamp->CR2 &= ~((Tamper << 24) | (Tamper << 16) | Tamper); + + /* Clear tamper interrupt mode configuration */ + tamp->IER &= ~Tamper; + + /* Clear tamper interrupt and event flags (WO register) */ + tamp->SCR = Tamper; + + return HAL_OK; +} +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the selected Tamper pin */ + hrtc->Instance->TAMPCR &= ~Tamper; + +#if defined(RTC_TAMPER1_SUPPORT) + if ((Tamper & RTC_TAMPER_1) != 0U) + { + /* Disable the Tamper1 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); + } +#endif /* RTC_TAMPER1_SUPPORT */ + if ((Tamper & RTC_TAMPER_2) != 0U) + { + /* Disable the Tamper2 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); + } +#if defined(RTC_TAMPER3_SUPPORT) + if ((Tamper & RTC_TAMPER_3) != 0U) + { + /* Disable the Tamper3 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); + } +#endif /* RTC_TAMPER3_SUPPORT */ + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + +#if defined(RTC_TAMPER1_SUPPORT) +/** + * @brief Handle Tamper 1 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} +#endif /* RTC_TAMPER1_SUPPORT */ + +/** + * @brief Handle Tamper 2 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +#if defined(RTC_TAMPER3_SUPPORT) +/** + * @brief Handle Tamper 3 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} +#endif /* RTC_TAMPER3_SUPPORT */ + + + +#if defined(RTC_TAMPER1_SUPPORT) +/** + * @brief Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} +#endif /* RTC_TAMPER1_SUPPORT */ + +/** + * @brief Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +#if defined(RTC_TAMPER3_SUPPORT) +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} +#endif /* RTC_TAMPER3_SUPPORT */ + +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group6 + * @brief Extended RTC Backup register functions + * +@verbatim + =============================================================================== + ##### Extended RTC Backup register functions ##### + =============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register +@endverbatim + * @{ + */ + + +/** + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to + * specify the register. + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t __IO tmp; +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (tamp->BKP0R); +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (hrtc->Instance->BKP0R); +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + + +/** + * @brief Read data from the specified RTC Backup data Register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 31 to + * specify the register. + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp; +#if defined(STM32L412xx) || defined(STM32L422xx) + /* Process TAMP instance pointer */ + TAMP_TypeDef *tamp = (TAMP_TypeDef *)((uint32_t)hrtc->Instance + hrtc->TampOffset); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (tamp->BKP0R); +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (hrtc->Instance->BKP0R); +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + + /** * @} */ @@ -1864,6 +2272,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t */ #endif /* HAL_RTC_MODULE_ENABLED */ + /** * @} */ @@ -1873,3 +2282,4 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h index 102703f1e9..595457d6bc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_EX_H -#define __STM32L4xx_HAL_RTC_EX_H +#ifndef STM32L4xx_HAL_RTC_EX_H +#define STM32L4xx_HAL_RTC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,7 +32,7 @@ * @{ */ -/** @addtogroup RTCEx +/** @defgroup RTCEx RTCEx * @{ */ @@ -56,27 +40,28 @@ /** @defgroup RTCEx_Exported_Types RTCEx Exported Types * @{ */ -/** - * @brief RTC Tamper structure definition + +/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition + * @{ */ typedef struct { uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ uint32_t Interrupt; /*!< Specifies the Tamper Interrupt. This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. + uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. @@ -90,94 +75,327 @@ typedef struct uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -}RTC_TamperTypeDef; +} RTC_TamperTypeDef; +/** + * @} + */ /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants * @{ */ -/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions +/* ========================================================================== */ +/* ##### RTC TimeStamp exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges Definitions + * * @{ */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) +#define RTC_TIMESTAMPEDGE_RISING 0x00000000u +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} */ -/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions +/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u /** * @} */ -/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions +/* ========================================================================== */ +/* ##### RTC Wake-up exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) /** * @} */ -/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection +/* ========================================================================== */ +/* ##### Extended RTC Peripheral Control exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 8s, else 2exp18 RTCCLK pulses */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions * @{ */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ +/** + * @} + */ + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @defgroup RTCEx_Smooth_Calib_Low_Power_Definitions RTCEx Smooth Calib Low Power Definitions + * @{ + */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 220 ck_apre, + which is the required configuration for + ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0x00000000u /*!< Calibration window is 220 RTCCLK, + which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ +/** + * @} + */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ 0x00000000u +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL +/** + * @} + */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET 0x00000000u +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +/** + * @} + */ + + +/* ========================================================================== */ +/* ##### RTC Tamper exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) #if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E #endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E #if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E #endif /* RTC_TAMPER3_SUPPORT */ +#define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#if defined(RTC_TAMPER1_SUPPORT) +#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E +#endif /* RTC_TAMPER1_SUPPORT */ +#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E +#if defined(RTC_TAMPER3_SUPPORT) +#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E +#endif /* RTC_TAMPER3_SUPPORT */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#else +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE +#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE +#endif +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper Mask Flag Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +#else +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00000000u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x00040000u +#endif +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions +* @{ +*/ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#else +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x00020000u +#endif +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level */ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000u /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level. */ +#endif /*#if defined(STM32L412xx) || defined(STM32L422xx) */ + +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK TAMP_FLTCR_TAMPFREQ /*!< Masking all bits except those of + field TAMPFREQ[2:0]*/ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000u /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAMPCR_TAMPFREQ /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAMPCR_TAMPFREQ /*!< Masking all bits except those of + field TAMPFREQ[2:0]*/ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000u /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAMPCR_TAMPPRCH /*!< Masking all bits except those of + field TAMPPRCH[1:0] */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull Up Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ +#else +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< TimeStamp on Tamper Detection event is not saved */ +#endif + +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#else +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#endif /** * @} */ @@ -185,6 +403,104 @@ typedef struct /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_IT_TAMP (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE) /*!< Enable all Tamper Interrupt */ +#define RTC_IT_TAMP1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ +#define RTC_IT_TAMP2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ +#define RTC_IT_TAMPALL RTC_IT_TAMP +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /*!< Enable all Tamper Interrupt */ +#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */ +#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */ +#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /*!< Enable Tamper 3 Interrupt */ +#define RTC_IT_TAMPALL RTC_IT_TAMP +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + +/** @defgroup RTCEx_Flags RTCEx Flags + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_FLAG_TAMP1F TAMP_SR_TAMP1F +#define RTC_FLAG_TAMP2F TAMP_SR_TAMP2F +#define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + +/* ========================================================================== */ +/* ##### Extended RTC Backup registers exported constants ##### */ +/* ========================================================================== */ + +/** @defgroup RTCEx_Backup_Data_Registers_Number_Definitions RTC Backup Data Registers Number Definitions + * @{ + */ +#if defined(RTC_BKP_NUMBER) +#define BKP_REG_NUMBER RTC_BKP_NUMBER +#endif /* RTC_BKP_NUMBER */ +#if defined(TAMP_BKP_NUMBER) +#define BKP_REG_NUMBER TAMP_BKP_NUMBER +#endif /* TAMP_BKP_NUMBER */ +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Data_Registers_Definitions RTCEx Backup Data Registers Definitions + * @{ + */ +#define RTC_BKP_DR0 0x00u +#define RTC_BKP_DR1 0x01u +#define RTC_BKP_DR2 0x02u +#define RTC_BKP_DR3 0x03u +#define RTC_BKP_DR4 0x04u +#define RTC_BKP_DR5 0x05u +#define RTC_BKP_DR6 0x06u +#define RTC_BKP_DR7 0x07u +#define RTC_BKP_DR8 0x08u +#define RTC_BKP_DR9 0x09u +#define RTC_BKP_DR10 0x0Au +#define RTC_BKP_DR11 0x0Bu +#define RTC_BKP_DR12 0x0Cu +#define RTC_BKP_DR13 0x0Du +#define RTC_BKP_DR14 0x0Eu +#define RTC_BKP_DR15 0x0Fu +#define RTC_BKP_DR16 0x10u +#define RTC_BKP_DR17 0x11u +#define RTC_BKP_DR18 0x12u +#define RTC_BKP_DR19 0x13u +#define RTC_BKP_DR20 0x14u +#define RTC_BKP_DR21 0x15u +#define RTC_BKP_DR22 0x16u +#define RTC_BKP_DR23 0x17u +#define RTC_BKP_DR24 0x18u +#define RTC_BKP_DR25 0x19u +#define RTC_BKP_DR26 0x1Au +#define RTC_BKP_DR27 0x1Bu +#define RTC_BKP_DR28 0x1Cu +#define RTC_BKP_DR29 0x1Du +#define RTC_BKP_DR30 0x1Eu +#define RTC_BKP_DR31 0x1Fu +/** + * @} + */ + + + + +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions + * @{ + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define RTC_TAMPER1_INTERRUPT TAMP_IER_TAMP1IE +#define RTC_TAMPER2_INTERRUPT TAMP_IER_TAMP2IE +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ #if defined(RTC_TAMPER1_SUPPORT) #define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE #endif /* RTC_TAMPER1_SUPPORT */ @@ -193,162 +509,9 @@ typedef struct #define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE #endif /* RTC_TAMPER3_SUPPORT */ #define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE -/** - * @} - */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -/** - * @} - */ -/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions -* @{ -*/ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions -* @{ -*/ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions - * @{ - */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions - * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions - * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions - * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ -/** - * @} - */ - -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions - * @{ - */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK seconds */ -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ -/** - * @} - */ - -/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) -/** - * @} - */ - -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions - * @{ - */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) /** * @} */ @@ -362,356 +525,140 @@ typedef struct * @{ */ -/** - * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @brief Clear the specified RTC pending flag. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag + * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag + * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag + * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag + * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag + * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__)) + +/** @brief Check whether the specified RTC flag is set or not. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag + * @arg @ref RTC_FLAG_INITF Initialization flag + * @arg @ref RTC_FLAG_RSF Registers synchronization flag + * @arg @ref RTC_FLAG_INITS Initialization status flag + * @arg @ref RTC_FLAG_SHPF Shift operation pending flag + * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag + * @arg @ref RTC_FLAG_ALRBWF Alarm B write flag + * @arg @ref RTC_FLAG_ALRAWF Alarm A write flag + * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag + * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag + * @arg @ref RTC_FLAG_TSF Time-stamp flag + * @arg @ref RTC_FLAG_WUTF Wakeup timer flag + * @arg @ref RTC_FLAG_ALRBF Alarm B flag + * @arg @ref RTC_FLAG_ALRAF Alarm A flag + * @retval None + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ + ((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK)))) +#endif /*#if defined(STM32L412xx) || defined(STM32L422xx) */ + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) -/** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) /** - * @brief Check whether the specified RTC Wake Up timer interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U) +#else +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4)) != 0U) ? 1U : 0U) +#endif + +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None + * @arg @ref RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTWF + * @retval Flag status */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#else +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: - * @arg RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) - -/** - * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) - -/** - * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) - -/** - * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ - (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) #else -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) -#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif -/** - * @brief Check whether the specified RTC Tamper interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) - -/** - * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) - -/** - * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC Time Stamp interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) - -/** - * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) - -/** - * @brief Get the selected RTC Internal Time Stamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_ITSF - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Internal Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear. - * This parameter can be: - * @arg RTC_FLAG_ITSF - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) - -/** - * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) - -/** - * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) - -/** - * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) - -/** - * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF - * @retval None - */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ /** * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. * @retval None @@ -737,7 +684,7 @@ typedef struct #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) /** - * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) @@ -797,6 +744,397 @@ typedef struct */ #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +/** + * @} + */ + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U) +#else +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4)) != 0U) ? 1U : 0U) +#endif +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) + +/** + * @brief Get the selected RTC TimeStamp's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval Flag status + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#else +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif + +/** + * @brief Clear the RTC Time Stamp's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__))) +#else +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif + +/** + * @brief Enable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) + +/** + * @brief Disable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) + +/** + * @brief Get the selected RTC Internal Time Stamp's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) +#else +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif + +/** + * @brief Clear the RTC Internal Time Stamp's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF)) +#else +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif + + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Enable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS)) + +/** + * @brief Disable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS)) + +/** + * @brief Enable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE)) + +/** + * @brief Disable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE)) + + +/** + * @} + */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) + +/** + * @brief Get the selected RTC shift operation's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SHPF + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#else +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif + +/** + * @} + */ + + +/* ------------------------------Tamper----------------------------------*/ +/** @defgroup RTCEx_Tamper RTCEx tamper + * @{ + */ +#if defined(RTC_TAMPER1_SUPPORT) +/** + * @brief Enable the RTC Tamper1 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (TAMP_CR1_TAMP1E)) +#else +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) +#endif + +/** + * @brief Disable the RTC Tamper1 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(RTC_TAMPCR_TAMP1E)) +#else +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) +#endif +#endif /* RTC_TAMPER1_SUPPORT */ + +/** + * @brief Enable the RTC Tamper2 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 |= (TAMP_CR1_TAMP2E)) +#else +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) +#endif + +/** + * @brief Disable the RTC Tamper2 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->CR1 &= ~(RTC_TAMPCR_TAMP2E)) +#else +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) +#endif + +#if defined(RTC_TAMPER3_SUPPORT) +/** + * @brief Enable the RTC Tamper3 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) + +/** + * @brief Disable the RTC Tamper3 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) +#endif /* RTC_TAMPER3_SUPPORT */ + +/**************************************************************************************************/ +/** + * @brief Enable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER |= (__INTERRUPT__)) +#else +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) +#endif +/** + * @brief Disable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER &= ~(__INTERRUPT__)) +#else +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) +#endif + + +/**************************************************************************************************/ +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->MISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMPALL: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#else +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#endif + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SR) & (__FLAG__)) != 0U) +#else +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @retval None + */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) = (__FLAG__)) +#else +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#endif + /** * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. * @retval None @@ -822,7 +1160,7 @@ typedef struct #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) /** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. * @retval None */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) @@ -856,7 +1194,6 @@ typedef struct /** * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * This parameter can be: * @retval None */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ @@ -882,17 +1219,27 @@ typedef struct */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +/** + * @} + */ + /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ -/* RTC TimeStamp and Tamper functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group1 +/* ========================================================================== */ +/* ##### RTC TimeStamp exported functions ##### */ +/* ========================================================================== */ + +/* RTC TimeStamp functions ****************************************************/ + +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions * @{ */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); @@ -901,39 +1248,29 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); - -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -#if defined(RTC_TAMPER1_SUPPORT) -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER1_SUPPORT */ -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(RTC_TAMPER3_SUPPORT) -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER3_SUPPORT */ void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER1_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER1_SUPPORT */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER3_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER3_SUPPORT */ /** * @} */ +/* ========================================================================== */ +/* ##### RTC Wake-up exported functions ##### */ +/* ========================================================================== */ + /* RTC Wake-up functions ******************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @{ - */ + +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +#if defined(STM32L412xx) || defined(STM32L422xx) +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr); +#else HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +#endif +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); @@ -942,14 +1279,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @} */ -/* Extended Control functions ************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/* ========================================================================== */ +/* ##### Extended RTC Peripheral Control exported functions ##### */ +/* ========================================================================== */ +/* Extended RTC Peripheral Control functions **********************************/ + +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +#if defined(STM32L412xx) || defined(STM32L422xx) +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib); +#endif HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); @@ -962,27 +1304,65 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); */ /* Extended RTC features functions *******************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group4 +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions * @{ */ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); + +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} */ +/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); + +#if defined(RTC_TAMPER1_SUPPORT) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER1_SUPPORT */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(RTC_TAMPER3_SUPPORT) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER3_SUPPORT */ + +#if defined(RTC_TAMPER1_SUPPORT) +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER1_SUPPORT */ +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(RTC_TAMPER3_SUPPORT) +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER3_SUPPORT */ + + /** * @} */ -/* Private types -------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */ /** * @} @@ -995,68 +1375,22 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters * @{ - */ - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) - + */ #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - -#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET)) +#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != 0U)) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) - -#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ - ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) - -#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \ - ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE)) - -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) - -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) - -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) - -#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) - -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ @@ -1065,12 +1399,63 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \ + ((LPCAL) == RTC_LPCAL_RESET)) +#endif + +#if defined(STM32L412xx) || defined(STM32L422xx) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) +#else +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != 0U)) +#endif + + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) + +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) + +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) + +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ ((SEL) == RTC_SHIFTADD1S_SET)) -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) @@ -1093,8 +1478,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ -#endif /* __STM32L4xx_HAL_RTC_EX_H */ +#endif /* STM32L4xx_HAL_RTC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c index 02f941c970..15ac4e47f4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c @@ -94,7 +94,7 @@ (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_SAI_RxCpltCallback() - (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_SAI_ErrorCallback() *** DMA mode IO operation *** @@ -137,33 +137,76 @@ enabled or disabled (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_SAI_RegisterCallback() to register a user callback. + + [..] + Function HAL_SAI_RegisterCallback() allows to register following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + + [..] + By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit + or HAL_SAI_Init function. + + [..] + When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -175,35 +218,33 @@ * @{ */ +#ifdef HAL_SAI_MODULE_ENABLED +#if !defined(STM32L412xx) && !defined(STM32L422xx) + /** @defgroup SAI SAI * @brief SAI HAL module driver * @{ */ -#ifdef HAL_SAI_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ - /** @defgroup SAI_Private_Typedefs SAI Private Typedefs * @{ */ -typedef enum { +typedef enum +{ SAI_MODE_DMA, SAI_MODE_IT -}SAI_ModeTypedef; +} SAI_ModeTypedef; /** * @} */ /* Private define ------------------------------------------------------------*/ - /** @defgroup SAI_Private_Constants SAI Private Constants * @{ */ -#define SAI_FIFO_SIZE 8 -#define SAI_DEFAULT_TIMEOUT 4 -#define SAI_LONG_TIMEOUT 1000 - +#define SAI_DEFAULT_TIMEOUT 4U +#define SAI_LONG_TIMEOUT 1000U /** * @} */ @@ -211,12 +252,11 @@ typedef enum { /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - /** @defgroup SAI_Private_Functions SAI Private Functions * @{ */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode); static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); @@ -239,14 +279,13 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); */ /* Exported functions ---------------------------------------------------------*/ - /** @defgroup SAI_Exported_Functions SAI Exported Functions * @{ */ /** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -281,7 +320,7 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param protocol one of the supported protocol @ref SAI_Protocol * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. @@ -290,33 +329,33 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { - HAL_StatusTypeDef status = HAL_OK; - + HAL_StatusTypeDef status; + /* Check the parameters */ assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - - switch(protocol) + + switch (protocol) { - case SAI_I2S_STANDARD : - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - status = SAI_InitI2S(hsai, protocol, datasize, nbslot); - break; - case SAI_PCM_LONG : - case SAI_PCM_SHORT : - status = SAI_InitPCM(hsai, protocol, datasize, nbslot); - break; - default : - status = HAL_ERROR; - break; + case SAI_I2S_STANDARD : + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + status = SAI_InitI2S(hsai, protocol, datasize, nbslot); + break; + case SAI_PCM_LONG : + case SAI_PCM_SHORT : + status = SAI_InitPCM(hsai, protocol, datasize, nbslot); + break; + default : + status = HAL_ERROR; + break; } - - if(status == HAL_OK) + + if (status == HAL_OK) { status = HAL_SAI_Init(hsai); } - + return status; } @@ -324,24 +363,24 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { - uint32_t tmpregisterGCR = 0; - uint32_t ckstr_bits = 0; - uint32_t syncen_bits = 0; - + uint32_t tmpregisterGCR; + uint32_t ckstr_bits; + uint32_t syncen_bits; + /* Check the SAI handle allocation */ - if(hsai == NULL) + if (hsai == NULL) { return HAL_ERROR; } - + /* check the instance */ assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); - + /* Check the SAI Block parameters */ assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); @@ -360,54 +399,73 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling)); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Check the SAI Block Frame parameters */ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength)); assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition)); assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity)); assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset)); - + /* Check the SAI Block Slot parameters */ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset)); assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize)); assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Check the SAI PDM parameters */ assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation)); - if(hsai->Init.PdmInit.Activation == ENABLE) + if (hsai->Init.PdmInit.Activation == ENABLE) { assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr)); assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable)); /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */ - if((hsai->Instance != SAI1_Block_A) || - (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || - (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) + if ((hsai->Instance != SAI1_Block_A) || + (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || + (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) { return HAL_ERROR; } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - if(hsai->State == HAL_SAI_STATE_RESET) + + if (hsai->State == HAL_SAI_STATE_RESET) { /* Allocate lock resource and initialize it */ hsai->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + if (hsai->MspInitCallback == NULL) + { + hsai->MspInitCallback = HAL_SAI_MspInit; + } + hsai->MspInitCallback(hsai); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SAI_MspInit(hsai); +#endif } - - hsai->State = HAL_SAI_STATE_BUSY; - + /* Disable the selected SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + return HAL_ERROR; + } + + hsai->State = HAL_SAI_STATE_BUSY; + /* SAI Block Synchro Configuration -----------------------------------------*/ /* This setting must be done with both audio block (A & B) disabled */ - switch(hsai->Init.SynchroExt) + switch (hsai->Init.SynchroExt) { case SAI_SYNCEXT_DISABLE : tmpregisterGCR = 0; @@ -418,105 +476,106 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) case SAI_SYNCEXT_OUTBLOCKB_ENABLE : tmpregisterGCR = SAI_GCR_SYNCOUT_1; break; + default : + tmpregisterGCR = 0; + break; } - - switch(hsai->Init.Synchro) + + switch (hsai->Init.Synchro) { case SAI_ASYNCHRONOUS : - { - syncen_bits = 0; - } + syncen_bits = 0; break; case SAI_SYNCHRONOUS : - { - syncen_bits = SAI_xCR1_SYNCEN_0; - } + syncen_bits = SAI_xCR1_SYNCEN_0; break; case SAI_SYNCHRONOUS_EXT_SAI1 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - } + syncen_bits = SAI_xCR1_SYNCEN_1; break; case SAI_SYNCHRONOUS_EXT_SAI2 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } + syncen_bits = SAI_xCR1_SYNCEN_1; + tmpregisterGCR |= SAI_GCR_SYNCIN_0; + break; + default : + syncen_bits = 0; break; } - + #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - - if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) + + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { SAI1->GCR = tmpregisterGCR; } - else + else { SAI2->GCR = tmpregisterGCR; } - + #else - + SAI1->GCR = tmpregisterGCR; - + #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + + if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { - uint32_t freq = 0; + uint32_t freq; uint32_t tmpval; - + /* In this case, the MCKDIV value is calculated to get AudioFrequency */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - - if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) + + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); } - if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B )) + else { + /* SAI2_Block_A or SAI2_Block_B */ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); } - + #else - + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - + #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Configure Master Clock Divider using the following formula : - If NOMCK = 1 : MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1)) - If NOMCK = 0 : MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */ - if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) - { /* NOMCK = 1 */ + if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) + { + /* NOMCK = 1 */ /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); } else - { /* NOMCK = 0 */ - uint32_t tmposr; - tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2 : 1; - /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256); - } - hsai->Init.Mckdiv = tmpval / 10; - - /* Round result to the nearest integer */ - if((tmpval % 10) > 8) { - hsai->Init.Mckdiv+= 1; + /* NOMCK = 0 */ + uint32_t tmposr; + tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U; + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U); + } + hsai->Init.Mckdiv = tmpval / 10U; + + /* Round result to the nearest integer */ + if ((tmpval % 10U) > 8U) + { + hsai->Init.Mckdiv += 1U; } #else /* Configure Master Clock using the following formula : @@ -524,167 +583,188 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 MCKDIV[3:0] = SAI_CK_x / FS * 512 */ /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256); - hsai->Init.Mckdiv = tmpval / 10; - + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * 2U * 256U); + hsai->Init.Mckdiv = tmpval / 10U; + /* Round result to the nearest integer */ - if((tmpval % 10) > 8) + if ((tmpval % 10U) > 8U) { - hsai->Init.Mckdiv+= 1; + hsai->Init.Mckdiv += 1U; } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } - + /* Check the SAI Block master clock divider parameter */ + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); + /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR; + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR; } else - { /* Receive */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0; + { + /* Receive */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U; } - + /* SAI Block Configuration -------------------------------------------------*/ /* SAI CR1 Configuration */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR); - - hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ - hsai->Init.MckOverSampling); + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR); + + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ + hsai->Init.MckOverSampling); #else - hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); - - hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); + + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* SAI CR2 Configuration */ - hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); - hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); - + hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); + hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); + /* SAI Frame Configuration -----------------------------------------*/ - hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ - SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); - hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | - hsai->FrameInit.FSOffset | - hsai->FrameInit.FSDefinition | - hsai->FrameInit.FSPolarity | - ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); - + hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ + SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); + hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) | + hsai->FrameInit.FSOffset | + hsai->FrameInit.FSDefinition | + hsai->FrameInit.FSPolarity | + ((hsai->FrameInit.ActiveFrameLength - 1U) << 8)); + /* SAI Block_x SLOT Configuration ------------------------------------------*/ /* This register has no meaning in AC 97 and SPDIF audio protocol */ - hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ - SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN )); - - hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize - | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); - + hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ + SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN)); + + hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \ + (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) << 8); + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* SAI PDM Configuration ---------------------------------------------------*/ - if(hsai->Instance == SAI1_Block_A) + if (hsai->Instance == SAI1_Block_A) { /* Disable PDM interface */ SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); - if(hsai->Init.PdmInit.Activation == ENABLE) + if (hsai->Init.PdmInit.Activation == ENABLE) { /* Configure and enable PDM interface */ - SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | - ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_Pos)); + SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | + ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos)); SAI1->PDMCR |= SAI_PDMCR_PDMEN; } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Initialize the SAI state */ - hsai->State= HAL_SAI_STATE_READY; - + hsai->State = HAL_SAI_STATE_READY; + /* Release Lock */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief DeInitialize the SAI peripheral. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) { /* Check the SAI handle allocation */ - if(hsai == NULL) + if (hsai == NULL) { return HAL_ERROR; } - + hsai->State = HAL_SAI_STATE_BUSY; - + /* Disabled All interrupt and clear all the flag */ hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable the SAI */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + /* Reset SAI state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Disable SAI PDM interface */ - if(hsai->Instance == SAI1_Block_A) + if (hsai->Instance == SAI1_Block_A) { /* Reset PDM delays */ SAI1->PDMDLY = 0U; - + /* Disable PDM interface */ SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + if (hsai->MspDeInitCallback == NULL) + { + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + } + hsai->MspDeInitCallback(hsai); +#else HAL_SAI_MspDeInit(hsai); - +#endif + /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Initialize the SAI state */ hsai->State = HAL_SAI_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief Initialize the SAI MSP. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_MspInit could be implemented in the user file */ @@ -693,26 +773,202 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_MspDeInit could be implemented in the user file */ } +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user SAI callback + * to be used instead of the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = pCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = pCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = pCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = pCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = pCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user SAI callback. + * SAI callback is redirected to the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup SAI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -755,95 +1011,108 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->XferSize = Size; hsai->XferCount = Size; hsai->pBuffPtr = pData; hsai->State = HAL_SAI_STATE_BUSY_TX; hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* fill the fifo with data before to enabled the SAI */ SAI_FillFifo(hsai); /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - - while(hsai->XferCount > 0) + + while (hsai->XferCount > 0U) { /* Write data if the FIFO is not full */ - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { - hsai->Instance->DR = (*hsai->pBuffPtr++); + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } else { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))) + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - + /* Clear all the flags */ hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + /* Change the SAI state */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_ERROR; } } } - + hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -855,7 +1124,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be received * @param Timeout Timeout duration @@ -864,84 +1133,97 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - - if((pData == NULL ) || (Size == 0)) + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->State = HAL_SAI_STATE_BUSY_RX; hsai->ErrorCode = HAL_SAI_ERROR_NONE; - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Receive data */ - while(hsai->XferCount > 0) + while (hsai->XferCount > 0U) { - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { - (*hsai->pBuffPtr++) = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 2; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; } else { - *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 4; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; } hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))) + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - + /* Clear all the flags */ hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + /* Change the SAI state */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_ERROR; } } } - + hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -953,34 +1235,34 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; } @@ -988,22 +1270,22 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u { hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; } - + /* Fill the fifo before starting the communication */ SAI_FillFifo(hsai); - + /* Enable FRQ and OVRUDR interrupts */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1015,34 +1297,34 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; } @@ -1050,20 +1332,20 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui { hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; } - + /* Enable TXE and OVRUDR interrupts */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1075,152 +1357,186 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Pause the audio file playing by disabling the SAI DMA requests */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief Resume the audio stream playing from the Media. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) { /* Process Locked */ __HAL_LOCK(hsai); - + /* Enable the SAI DMA requests */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* If the SAI peripheral is still not enabled, enable it */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } /** * @brief Stop the audio stream playing from the Media. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) { + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hsai); - + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } - - if(hsai->hdmarx != NULL) + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + /* Set hsai state to ready */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - - return HAL_OK; + + return status; } /** * @brief Abort the current transfer and disable the SAI. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) { + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hsai); - + /* Check SAI DMA is enabled or not */ - if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } - - if(hsai->hdmarx != NULL) + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { - return HAL_ERROR; + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } } } } - + /* Disabled All interrupt and clear all the flag */ hsai->Instance->IMR = 0; hsai->Instance->CLRFR = 0xFFFFFFFFU; - + /* Disable SAI peripheral */ - SAI_Disable(hsai); - + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - + + /* Set hsai state to ready */ hsai->State = HAL_SAI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - - return HAL_OK; + + return status; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1229,73 +1545,73 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, { uint32_t tickstart = HAL_GetTick(); - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - + /* Set the SAI Tx DMA Half transfer complete callback */ hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; - + /* Set the SAI TxDMA transfer complete callback */ hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; - + /* Set the DMA error callback */ hsai->hdmatx->XferErrorCallback = SAI_DMAError; - + /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = NULL; - + /* Enable the Tx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) { __HAL_UNLOCK(hsai); return HAL_ERROR; } - + /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + /* Enable SAI Tx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* Wait untill FIFO is not empty */ - while((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) + while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) + if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); return HAL_TIMEOUT; } } - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1307,7 +1623,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param pData Pointer to data buffer * @param Size Amount of data to be received * @retval HAL status @@ -1315,57 +1631,57 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(hsai->State == HAL_SAI_STATE_READY) + + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); - + hsai->pBuffPtr = pData; hsai->XferSize = Size; hsai->XferCount = Size; hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - + /* Set the SAI Rx DMA Half transfer complete callback */ hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; - + /* Set the SAI Rx DMA transfer complete callback */ hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; - + /* Set the DMA error callback */ hsai->hdmarx->XferErrorCallback = SAI_DMAError; - + /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = NULL; - + /* Enable the Rx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) { __HAL_UNLOCK(hsai); return HAL_ERROR; } - + /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } - + /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + /* Enable SAI Rx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsai); - + return HAL_OK; } else @@ -1377,18 +1693,18 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) { assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); - - if(hsai->State != HAL_SAI_STATE_RESET) + + if (hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); - SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val); + SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val); return HAL_OK; } return HAL_ERROR; @@ -1397,12 +1713,12 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); return HAL_OK; @@ -1413,7 +1729,7 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param callback function called when the mute is detected. * @param counter number a data before mute detection max 63. * @retval HAL status @@ -1421,8 +1737,8 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) { assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); - - if(hsai->State != HAL_SAI_STATE_RESET) + + if (hsai->State != HAL_SAI_STATE_RESET) { /* set the mute counter */ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); @@ -1438,15 +1754,15 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { /* set the mutecallback to NULL */ - hsai->mutecallback = (SAIcallback)NULL; + hsai->mutecallback = NULL; /* enable the IT interrupt */ __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET); return HAL_OK; @@ -1457,25 +1773,25 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { uint32_t itflags = hsai->Instance->SR; uint32_t itsources = hsai->Instance->IMR; uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - - /* SAI Fifo request interrupt occured ------------------------------------*/ - if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) + + /* SAI Fifo request interrupt occurred -----------------------------------*/ + if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); } /* SAI Overrun error interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) + else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) { /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); @@ -1484,117 +1800,197 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /* Change the SAI error code */ hsai->ErrorCode |= tmperror; /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } /* SAI mutedet interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) { /* Clear the SAI mutedet flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); /* call the call back function */ - if(hsai->mutecallback != (SAIcallback)NULL) + if (hsai->mutecallback != NULL) { /* inform the user that an RX mute event has been detected */ hsai->mutecallback(); } } /* SAI AFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) { /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; - + /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif + } } - else if(hsai->hdmarx != NULL) + if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif + } } } else { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - + /* Abort SAI */ + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); + /* Set error callback */ - HAL_SAI_ErrorCallback(hsai); +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif } } /* SAI LFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) { /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; - + /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif + } } - else if(hsai->hdmarx != NULL) + if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif + } } } else { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - + /* Abort SAI */ + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); + /* Set error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } } /* SAI WCKCFG interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) { /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; - + /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif + } } - else if(hsai->hdmarx != NULL) + if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - + /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif + } } } else @@ -1605,23 +2001,31 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) hsai->Instance->CLRFR = 0xFFFFFFFFU; /* Set the SAI state to ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; - + /* Initialize XferCount */ hsai->XferCount = 0U; - + /* SAI error Callback */ - HAL_SAI_ErrorCallback(hsai); +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif } } /* SAI CNRDY interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) { /* Clear the SAI CNRDY flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } else { @@ -1633,14 +2037,14 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_TxCpltCallback could be implemented in the user file */ @@ -1649,14 +2053,14 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_TxHalfCpltCallback could be implemented in the user file */ @@ -1665,14 +2069,14 @@ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_RxCpltCallback could be implemented in the user file */ @@ -1681,14 +2085,14 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_RxHalfCpltCallback could be implemented in the user file */ @@ -1697,14 +2101,14 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SAI_ErrorCallback could be implemented in the user file */ @@ -1714,10 +2118,9 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * @} */ - /** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1733,7 +2136,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval HAL state */ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) @@ -1742,15 +2145,16 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) } /** -* @brief Return the SAI error code. -* @param hsai pointer to a SAI_HandleTypeDef structure that contains + * @brief Return the SAI error code. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. -* @retval SAI Error Code -*/ + * @retval SAI Error Code + */ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } + /** * @} */ @@ -1760,7 +2164,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) */ /** @addtogroup SAI_Private_Functions - * @brief Private functions + * @brief Private functions * @{ */ @@ -1768,84 +2172,89 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param protocol one of the supported protocol. - * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize. * @param nbslot number of slot minimum value is 2 and max is 16. - * the value must be a multiple of 2. + * the value must be a multiple of 2. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { + HAL_StatusTypeDef status = HAL_OK; + hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; } else - { /* Receive */ + { + /* Receive */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; } hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; hsai->SlotInit.FirstBitOffset = 0; hsai->SlotInit.SlotNumber = nbslot; - + /* in IS2 the number of slot must be even */ - if((nbslot & 0x1) != 0 ) + if ((nbslot & 0x1U) != 0U) { return HAL_ERROR; } - - switch(protocol) + + switch (protocol) { - case SAI_I2S_STANDARD : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - break; - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - break; - default : - return HAL_ERROR; + case SAI_I2S_STANDARD : + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + break; + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; + break; + default : + status = HAL_ERROR; + break; } - + /* Frame definition */ - switch(datasize) + switch (datasize) { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT: - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT: + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; } - if(protocol == SAI_I2S_LSBJUSTIFIED) + if (protocol == SAI_I2S_LSBJUSTIFIED) { if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) { @@ -1856,14 +2265,14 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.FirstBitOffset = 8; } } - return HAL_OK; + return status; } /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param protocol one of the supported protocol * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * @param nbslot number of slot minimum value is 1 and the max is 16. @@ -1871,15 +2280,19 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) { + HAL_StatusTypeDef status = HAL_OK; + hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; } else - { /* Receive */ + { + /* Receive */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; } hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; @@ -1888,72 +2301,87 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.FirstBitOffset = 0; hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - - switch(protocol) + + switch (protocol) { - case SAI_PCM_SHORT : - hsai->FrameInit.ActiveFrameLength = 1; - break; - case SAI_PCM_LONG : - hsai->FrameInit.ActiveFrameLength = 13; - break; - default : - return HAL_ERROR; + case SAI_PCM_SHORT : + hsai->FrameInit.ActiveFrameLength = 1; + break; + case SAI_PCM_LONG : + hsai->FrameInit.ActiveFrameLength = 13; + break; + default : + status = HAL_ERROR; + break; } - - switch(datasize) + + switch (datasize) { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 16 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT : - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 16U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT : + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; } - - return HAL_OK; + + return status; } /** * @brief Fill the fifo. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) { + uint32_t temp; + /* fill the fifo with data before to enabled the SAI */ - while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) + while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U)) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { - hsai->Instance->DR = (*hsai->pBuffPtr++); + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } else { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; } hsai->XferCount--; } @@ -1962,33 +2390,33 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable - */ -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) + */ +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode) { uint32_t tmpIT = SAI_IT_OVRUDR; - - if(mode == SAI_MODE_IT) + + if (mode == SAI_MODE_IT) { - tmpIT|= SAI_IT_FREQ; + tmpIT |= SAI_IT_FREQ; } - - if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && - ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) + + if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && + ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) { - tmpIT|= SAI_IT_CNRDY; + tmpIT |= SAI_IT_CNRDY; } - - if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + + if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) { - tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET; + tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET; } else { /* hsai has been configured in master mode */ - tmpIT|= SAI_IT_WCKCFG; + tmpIT |= SAI_IT_WCKCFG; } return tmpIT; } @@ -1996,49 +2424,59 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) { - uint32_t tickstart = HAL_GetTick(); + register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); HAL_StatusTypeDef status = HAL_OK; - + + /* Disable the SAI instance */ __HAL_SAI_DISABLE(hsai); - while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET) + + do { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > SAI_DEFAULT_TIMEOUT) + if (count == 0U) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - return HAL_TIMEOUT; + status = HAL_TIMEOUT; + break; } + count--; } + while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U); + return status; } /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } else { /* Write data on DR register */ - hsai->Instance->DR = (*hsai->pBuffPtr++); + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; hsai->XferCount--; } } @@ -2046,24 +2484,32 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } else { /* Write data on DR register */ - hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=2; + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; hsai->XferCount--; } } @@ -2071,24 +2517,36 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } else { /* Write data on DR register */ - hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=4; + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; hsai->XferCount--; } } @@ -2096,228 +2554,286 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) { /* Receive data */ - (*hsai->pBuffPtr++) = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; hsai->XferCount--; - + /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } } /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) { + uint32_t temp; + /* Receive data */ - *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=2; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; hsai->XferCount--; - + /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } } + /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. + * the configuration information for SAI module. * @retval None */ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) { + uint32_t temp; + /* Receive data */ - *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=4; + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; hsai->XferCount--; - + /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0U) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - + /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } } /** * @brief DMA SAI transmit process complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; - - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma->Init.Mode != DMA_CIRCULAR) { hsai->XferCount = 0; - + /* Disable SAI Tx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); - + /* Stop the interrupts error handling */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - hsai->State= HAL_SAI_STATE_READY; + + hsai->State = HAL_SAI_STATE_READY; } +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else HAL_SAI_TxCpltCallback(hsai); +#endif } /** * @brief DMA SAI transmit process half complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxHalfCpltCallback(hsai); +#else HAL_SAI_TxHalfCpltCallback(hsai); +#endif } /** * @brief DMA SAI receive process complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma->Init.Mode != DMA_CIRCULAR) { /* Disable Rx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); hsai->XferCount = 0; - + /* Stop the interrupts error handling */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - + hsai->State = HAL_SAI_STATE_READY; } +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else HAL_SAI_RxCpltCallback(hsai); +#endif } /** * @brief DMA SAI receive process half complete callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxHalfCpltCallback(hsai); +#else HAL_SAI_RxHalfCpltCallback(hsai); +#endif } + /** * @brief DMA SAI communication error callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMAError(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Disable SAI peripheral */ - SAI_Disable(hsai); - + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); + /* Set the SAI state ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; /* Initialize XferCount */ hsai->XferCount = 0U; - /* SAI error Callback */ + /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } /** * @brief DMA SAI Abort callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Disable DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Disable all interrupts and clear all flags */ hsai->Instance->IMR = 0U; hsai->Instance->CLRFR = 0xFFFFFFFFU; - - if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) + + if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) { /* Disable SAI peripheral */ - SAI_Disable(hsai); + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); } /* Set the SAI state to ready to be able to start again the process */ hsai->State = HAL_SAI_STATE_READY; - + /* Initialize XferCount */ hsai->XferCount = 0U; /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else HAL_SAI_ErrorCallback(hsai); +#endif } /** * @} */ -#endif /* HAL_SAI_MODULE_ENABLED */ /** * @} */ +#endif /* !STM32L412xx && !STM32L422xx */ +#endif /* HAL_SAI_MODULE_ENABLED */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h index 1c956e7348..1e8809f17a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h @@ -6,41 +6,27 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SAI_H -#define __STM32L4xx_HAL_SAI_H +#ifndef STM32L4xx_HAL_SAI_H +#define STM32L4xx_HAL_SAI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif +#if !defined(STM32L412xx) && !defined(STM32L422xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -67,7 +53,7 @@ typedef enum HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ -}HAL_SAI_StateTypeDef; +} HAL_SAI_StateTypeDef; /** * @brief SAI Callback prototype @@ -75,17 +61,21 @@ typedef enum typedef void (*SAIcallback)(void); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/** +/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition * @brief SAI PDM Init structure definition - */ + * @{ + */ typedef struct { - FunctionalState Activation; /*!< Enable/disable PDM interface */ - uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. - This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ - uint32_t ClockEnable; /*!< Specifies which clock must be enabled. - This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ -}SAI_PdmInitTypeDef; + FunctionalState Activation; /*!< Enable/disable PDM interface */ + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + uint32_t ClockEnable; /*!< Specifies which clock must be enabled. + This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ +} SAI_PdmInitTypeDef; +/** + * @} + */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition @@ -103,29 +93,29 @@ typedef struct uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common for BlockA and BlockB This parameter can be a value of @ref SAI_Block_SyncExt - @note: If both audio blocks of same SAI are used, this parameter has - to be set to the same value for each audio block */ + @note If both audio blocks of same SAI are used, this parameter has + to be set to the same value for each audio block */ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. This parameter can be a value of @ref SAI_Block_Output_Drive - @note this value has to be set before enabling the audio block - but after the audio block configuration. */ + @note This value has to be set before enabling the audio block + but after the audio block configuration. */ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. This parameter can be a value of @ref SAI_Block_NoDivider - @note: For STM32L4Rx/STM32L4Sx devices : - If bit NOMCK in the SAI_xCR1 register is cleared, the frame length - should be aligned to a number equal to a power of 2, from 8 to 256. - If bit NOMCK in the SAI_xCR1 register is set, the frame length can - take any of the values without constraint. There is no MCLK_x clock - which can be output. - For other devices : - If bit NODIV in the SAI_xCR1 register is cleared, the frame length - should be aligned to a number equal to a power of 2, from 8 to 256. - If bit NODIV in the SAI_xCR1 register is set, the frame length can - take any of the values without constraint since the input clock of - the audio block should be equal to the bit clock. - There is no MCLK_x clock which can be output. */ + @note For STM32L4Rx/STM32L4Sx devices : + If bit NOMCK in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NOMCK in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint. There is no MCLK_x clock + which can be output. + For other devices : + If bit NODIV in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NODIV in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint since the input clock of + the audio block should be equal to the bit clock. + There is no MCLK_x clock which can be output. */ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ @@ -133,10 +123,11 @@ typedef struct uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. This parameter can be a value of @ref SAI_Audio_Frequency */ - uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for - AudioFrequency the user choice + uint32_t Mckdiv; /*!< Specifies the master clock divider. This parameter must be a number between Min_Data = 0 and Max_Data = 63 on STM32L4Rx/STM32L4Sx devices. - This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. + @note This parameter is used only if AudioFrequency is set to + SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. @@ -170,7 +161,7 @@ typedef struct uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of @ref SAI_Block_Clock_Strobing */ -}SAI_InitTypeDef; +} SAI_InitTypeDef; /** * @} */ @@ -184,9 +175,9 @@ typedef struct uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. This parameter must be a number between Min_Data = 8 and Max_Data = 256. - @note: If master clock MCLK_x pin is declared as an output, the frame length - should be aligned to a number equal to power of 2 in order to keep - in an audio frame, an integer number of MCLK pulses by bit Clock. */ + @note If master clock MCLK_x pin is declared as an output, the frame length + should be aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. */ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) @@ -202,7 +193,7 @@ typedef struct uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. This parameter can be a value of @ref SAI_Block_FS_Offset */ -}SAI_FrameInitTypeDef; +} SAI_FrameInitTypeDef; /** * @} */ @@ -224,7 +215,7 @@ typedef struct uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. This parameter can be a value of @ref SAI_Block_Slot_Active */ -}SAI_SlotInitTypeDef; +} SAI_SlotInitTypeDef; /** * @} */ @@ -262,17 +253,47 @@ typedef struct __SAI_HandleTypeDef __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ __IO uint32_t ErrorCode; /*!< SAI Error code */ -}SAI_HandleTypeDef; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ + void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ + void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ + void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ + void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ + void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ + void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ +#endif +} SAI_HandleTypeDef; /** * @} */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief SAI callback ID enumeration definition + */ +typedef enum +{ + HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ + HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ + HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ + HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ + HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ + HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ + HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ +} HAL_SAI_CallbackIDTypeDef; + +/** + * @brief SAI callback pointer definition + */ +typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); +#endif + /** * @} */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup SAI_Exported_Constants SAI Exported Constants * @{ */ @@ -280,15 +301,18 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Error_Code SAI Error Code * @{ */ -#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */ -#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */ -#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */ -#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */ -#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */ -#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */ -#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ -#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */ +#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ +#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ +#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ +#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ +#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ +#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ +#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ +#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /** * @} */ @@ -296,9 +320,9 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_SyncExt SAI External synchronisation * @{ */ -#define SAI_SYNCEXT_DISABLE 0 -#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 -#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 +#define SAI_SYNCEXT_DISABLE 0U +#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U +#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U /** * @} */ @@ -306,11 +330,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Protocol SAI Supported protocol * @{ */ -#define SAI_I2S_STANDARD 0 -#define SAI_I2S_MSBJUSTIFIED 1 -#define SAI_I2S_LSBJUSTIFIED 2 -#define SAI_PCM_LONG 3 -#define SAI_PCM_SHORT 4 +#define SAI_I2S_STANDARD 0U +#define SAI_I2S_MSBJUSTIFIED 1U +#define SAI_I2S_LSBJUSTIFIED 2U +#define SAI_PCM_LONG 3U +#define SAI_PCM_SHORT 4U /** * @} */ @@ -318,10 +342,10 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Protocol_DataSize SAI protocol data size * @{ */ -#define SAI_PROTOCOL_DATASIZE_16BIT 0 -#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 -#define SAI_PROTOCOL_DATASIZE_24BIT 2 -#define SAI_PROTOCOL_DATASIZE_32BIT 3 +#define SAI_PROTOCOL_DATASIZE_16BIT 0U +#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U +#define SAI_PROTOCOL_DATASIZE_24BIT 2U +#define SAI_PROTOCOL_DATASIZE_32BIT 3U /** * @} */ @@ -329,16 +353,16 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Audio_Frequency SAI Audio Frequency * @{ */ -#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) -#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) -#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) -#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) -#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) -#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) -#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) -#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) -#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) -#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) +#define SAI_AUDIO_FREQUENCY_192K 192000U +#define SAI_AUDIO_FREQUENCY_96K 96000U +#define SAI_AUDIO_FREQUENCY_48K 48000U +#define SAI_AUDIO_FREQUENCY_44K 44100U +#define SAI_AUDIO_FREQUENCY_32K 32000U +#define SAI_AUDIO_FREQUENCY_22K 22050U +#define SAI_AUDIO_FREQUENCY_16K 16000U +#define SAI_AUDIO_FREQUENCY_11K 11025U +#define SAI_AUDIO_FREQUENCY_8K 8000U +#define SAI_AUDIO_FREQUENCY_MCKDIV 0U /** * @} */ @@ -347,8 +371,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling * @{ */ -#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U) -#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR) +#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U +#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR /** * @} */ @@ -356,8 +380,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable * @{ */ -#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1) -#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2) +#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 +#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 /** * @} */ @@ -366,10 +390,10 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mode SAI Block Mode * @{ */ -#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) -#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) -#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) -#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) +#define SAI_MODEMASTER_TX 0x00000000U +#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 +#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 +#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) /** * @} @@ -378,9 +402,9 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Protocol SAI Block Protocol * @{ */ -#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) -#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) -#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) +#define SAI_FREE_PROTOCOL 0x00000000U +#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 +#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 /** * @} */ @@ -388,12 +412,12 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Data_Size SAI Block Data Size * @{ */ -#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) -#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) -#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) -#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) +#define SAI_DATASIZE_8 SAI_xCR1_DS_1 +#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_16 SAI_xCR1_DS_2 +#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) +#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) /** * @} */ @@ -401,8 +425,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission * @{ */ -#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) -#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) +#define SAI_FIRSTBIT_MSB 0x00000000U +#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST /** * @} */ @@ -410,8 +434,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing * @{ */ -#define SAI_CLOCKSTROBING_FALLINGEDGE 0 -#define SAI_CLOCKSTROBING_RISINGEDGE 1 +#define SAI_CLOCKSTROBING_FALLINGEDGE 0U +#define SAI_CLOCKSTROBING_RISINGEDGE 1U /** * @} */ @@ -419,19 +443,19 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Synchronization SAI Block Synchronization * @{ */ -#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */ -#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */ -#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */ -#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */ +#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ +#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ +#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ +#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ /** * @} - */ + */ /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive * @{ */ -#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) -#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) +#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U +#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV /** * @} */ @@ -439,22 +463,21 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_NoDivider SAI Block NoDivider * @{ */ -#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) +#define SAI_MASTERDIVIDER_ENABLE 0x00000000U #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK) +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NOMCK #else -#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ - /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition * @{ */ -#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) -#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) +#define SAI_FS_STARTFRAME 0x00000000U +#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF /** * @} */ @@ -462,8 +485,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity * @{ */ -#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) -#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) +#define SAI_FS_ACTIVE_LOW 0x00000000U +#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL /** * @} */ @@ -471,19 +494,18 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset * @{ */ -#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) -#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) +#define SAI_FS_FIRSTBIT 0x00000000U +#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF /** * @} */ - - /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size +/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size * @{ */ -#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) -#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) -#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) +#define SAI_SLOTSIZE_DATASIZE 0x00000000U +#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 +#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 /** * @} */ @@ -491,24 +513,24 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active * @{ */ -#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) -#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) -#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) -#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) -#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) -#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) -#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) -#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) -#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) -#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) -#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) -#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) -#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) -#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) -#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) -#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) -#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) -#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) +#define SAI_SLOT_NOTACTIVE 0x00000000U +#define SAI_SLOTACTIVE_0 0x00000001U +#define SAI_SLOTACTIVE_1 0x00000002U +#define SAI_SLOTACTIVE_2 0x00000004U +#define SAI_SLOTACTIVE_3 0x00000008U +#define SAI_SLOTACTIVE_4 0x00000010U +#define SAI_SLOTACTIVE_5 0x00000020U +#define SAI_SLOTACTIVE_6 0x00000040U +#define SAI_SLOTACTIVE_7 0x00000080U +#define SAI_SLOTACTIVE_8 0x00000100U +#define SAI_SLOTACTIVE_9 0x00000200U +#define SAI_SLOTACTIVE_10 0x00000400U +#define SAI_SLOTACTIVE_11 0x00000800U +#define SAI_SLOTACTIVE_12 0x00001000U +#define SAI_SLOTACTIVE_13 0x00002000U +#define SAI_SLOTACTIVE_14 0x00004000U +#define SAI_SLOTACTIVE_15 0x00008000U +#define SAI_SLOTACTIVE_ALL 0x0000FFFFU /** * @} */ @@ -516,8 +538,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode * @{ */ -#define SAI_STEREOMODE ((uint32_t)0x00000000U) -#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) +#define SAI_STEREOMODE 0x00000000U +#define SAI_MONOMODE SAI_xCR1_MONO /** * @} */ @@ -525,8 +547,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_TRIState_Management SAI TRIState Management * @{ */ -#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) -#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) +#define SAI_OUTPUT_NOTRELEASED 0x00000000U +#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS /** * @} */ @@ -534,11 +556,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold * @{ */ -#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) -#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) +#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U +#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 +#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 +#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) +#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 /** * @} */ @@ -546,11 +568,11 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode * @{ */ -#define SAI_NOCOMPANDING ((uint32_t)0x00000000U) -#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) -#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) -#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) -#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) +#define SAI_NOCOMPANDING 0x00000000U +#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 +#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) +#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) +#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) /** * @} */ @@ -558,8 +580,8 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value * @{ */ -#define SAI_ZERO_VALUE ((uint32_t)0x00000000U) -#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) +#define SAI_ZERO_VALUE 0x00000000U +#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL /** * @} */ @@ -567,13 +589,13 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition * @{ */ -#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) -#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) -#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) -#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) -#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) -#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) -#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) +#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE +#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE +#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE +#define SAI_IT_FREQ SAI_xIMR_FREQIE +#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE +#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE +#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE /** * @} */ @@ -581,13 +603,13 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition * @{ */ -#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) -#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) -#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) -#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) -#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) -#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) -#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) +#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR +#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET +#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG +#define SAI_FLAG_FREQ SAI_xSR_FREQ +#define SAI_FLAG_CNRDY SAI_xSR_CNRDY +#define SAI_FLAG_AFSDET SAI_xSR_AFSDET +#define SAI_FLAG_LFSDET SAI_xSR_LFSDET /** * @} */ @@ -595,12 +617,12 @@ typedef struct __SAI_HandleTypeDef /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level * @{ */ -#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) -#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) -#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) -#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) -#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) +#define SAI_FIFOSTATUS_EMPTY 0x00000000U +#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U +#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U +#define SAI_FIFOSTATUS_HALFFULL 0x00030000U +#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U +#define SAI_FIFOSTATUS_FULL 0x00050000U /** * @} */ @@ -610,19 +632,26 @@ typedef struct __SAI_HandleTypeDef */ /* Exported macro ------------------------------------------------------------*/ - /** @defgroup SAI_Exported_Macros SAI Exported Macros - * @brief macros to handle interrupts and specific configurations - * @{ - */ + * @brief macros to handle interrupts and specific configurations + * @{ + */ /** @brief Reset SAI handle state. * @param __HANDLE__ specifies the SAI Handle. * @retval None */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) +#endif -/** @brief Enable or disable the specified SAI interrupts. +/** @brief Enable the specified SAI interrupts. * @param __HANDLE__ specifies the SAI Handle. * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: @@ -636,6 +665,20 @@ typedef struct __SAI_HandleTypeDef * @retval None */ #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) + +/** @brief Disable the specified SAI interrupts. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval None + */ #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. @@ -684,10 +727,19 @@ typedef struct __SAI_HandleTypeDef */ #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) +/** @brief Enable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) + +/** @brief Disable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) - /** +/** * @} */ @@ -697,28 +749,33 @@ typedef struct __SAI_HandleTypeDef #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup SAI_Exported_Functions * @{ */ /* Initialization/de-initialization functions ********************************/ - /** @addtogroup SAI_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/* SAI callbacks register/unregister functions ********************************/ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID); +#endif /** * @} */ /* I/O operation functions ***************************************************/ - /** @addtogroup SAI_Exported_Functions_Group2 * @{ */ @@ -772,7 +829,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); */ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup SAI_Private_Macros +/** @defgroup SAI_Private_Macros SAI Private Macros * @{ */ #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ @@ -813,7 +870,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ - ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) + ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ ((DATASIZE) == SAI_DATASIZE_10) || \ @@ -839,10 +896,10 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) -#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ - ((VALUE) == SAI_LAST_SENT_VALUE)) + ((VALUE) == SAI_LAST_SENT_VALUE)) #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ @@ -854,7 +911,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) + ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ ((STATE) == SAI_OUTPUT_RELEASED)) @@ -864,13 +921,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ ((SIZE) == SAI_SLOTSIZE_16B) || \ ((SIZE) == SAI_SLOTSIZE_32B)) -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) @@ -881,11 +938,15 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) +#else +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) +#endif -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) /** * @} @@ -908,10 +969,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); * @} */ +#endif /* !STM32L412xx && !STM32L422xx */ + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_SAI_H */ +#endif /* STM32L4xx_HAL_SAI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c index 44bd907dc5..e7bca47077 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32l4xx_hal_sai_ex.c * @author MCD Application Team - * @brief SAI Extended HAL module driver. + * @brief SAI Extended HAL module driver. * This file provides firmware functions to manage the following * functionality of the SAI Peripheral Controller: * + Modify PDM microphone delays. @@ -10,32 +10,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -54,22 +38,26 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ - -#define SAI_PDM_DELAY_MASK 0x77U -#define SAI_PDM_DELAY_OFFSET 8U -#define SAI_PDM_RIGHT_DELAY_OFFSET 4U +/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines + * @{ + */ +#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_OFFSET 8U +#define SAI_PDM_RIGHT_DELAY_OFFSET 4U +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions * @{ */ /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @brief SAIEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -90,9 +78,10 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) { HAL_StatusTypeDef status = HAL_OK; - + uint32_t offset; + /* Check that SAI sub-block is SAI1 sub-block A */ - if(hsai->Instance != SAI1_Block_A) + if (hsai->Instance != SAI1_Block_A) { status = HAL_ERROR; } @@ -102,16 +91,18 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair)); assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay)); assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay)); - - /* Check SAI state */ - if(hsai->State != HAL_SAI_STATE_RESET) + + /* Compute offset on PDMDLY register according mic pair number */ + offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U); + + /* Check SAI state and offset */ + if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U)) { /* Reset current delays for specified microphone */ - SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); - + SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset); + /* Apply new microphone delays */ - SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \ - (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); + SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset); } else { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h index 3a3828dad1..4abf097385 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h @@ -6,46 +6,30 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SAI_EX_H -#define __STM32L4xx_HAL_SAI_EX_H +#ifndef STM32L4xx_HAL_SAI_EX_H +#define STM32L4xx_HAL_SAI_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -55,7 +39,6 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup SAIEx_Exported_Types SAIEx Exported Types * @{ */ @@ -73,7 +56,7 @@ typedef struct uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ -}SAIEx_PdmMicDelayParamTypeDef; +} SAIEx_PdmMicDelayParamTypeDef; /** * @} @@ -82,7 +65,6 @@ typedef struct /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions * @{ */ @@ -90,32 +72,27 @@ typedef struct /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); +/** + * @} + */ /** * @} - */ - -/** - * @} - */ + */ /* Private macros ------------------------------------------------------------*/ - /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros * @{ */ - #define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) +/** + * @} + */ /** * @} - */ - -/** - * @} - */ + */ /** * @} @@ -127,6 +104,6 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm } #endif -#endif /* __STM32L4xx_HAL_SAI_EX_H */ +#endif /* STM32L4xx_HAL_SAI_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c index d76c7386a1..fdaf320f94 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c @@ -3,176 +3,178 @@ * @file stm32l4xx_hal_sd.c * @author MCD Application Team * @brief SD card HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + SD card Control functions - * + * + Peripheral Control functions + * + Peripheral State functions + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - This driver implements a high level communication layer for read and write from/to - this memory. The needed STM32 hardware resources (SDMMC1 and GPIO) are performed by - the user in HAL_SD_MspInit() function (MSP layer). - Basically, the MSP layer configuration should be the same as we provide in the + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_SD_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the examples. You can easily tailor this configuration according to hardware resources. [..] - This driver is a generic layered driver for SDMMC memories which uses the HAL - SDMMC driver functions to interface with SD and uSD cards devices. + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with SD and uSD cards devices. It is used as follows: - - (#)Initialize the SDMMC1 low level resources by implementing the HAL_SD_MspInit() API: + + (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: (##) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_SDMMC1 for PeriphClockSelection and select SDMMC1 clock source (MSI, main PLL or PLLSAI1) - (##) Enable the SDMMC1 interface clock using __HAL_RCC_SDMMC1_CLK_ENABLE(); + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC1_CLK_ENABLE(); (##) SDMMC pins configuration for SD card - (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; - (##) On STM32L4Rx/STM32L4Sxx devices, no DMA configuration is need, an internal DMA for SDMMC IP is used. + (##) On STM32L4Rx/STM32L4Sxx devices, no DMA configuration is need, an internal DMA for SDMMC Peripheral is used. (##) On other devices, perform DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() and HAL_SD_WriteBlocks_DMA() APIs). - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); - (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. (##) NVIC configuration if you need to use interrupt process when using DMA transfer. (+++) Configure the SDMMC and DMA interrupt priorities using functions HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() and __HAL_SD_DISABLE_IT() inside the communication process. (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() and __HAL_SD_CLEAR_IT() (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() and HAL_SD_WriteBlocks_IT() APIs). - (+++) Configure the SDMMC interrupt priorities using function - HAL_NVIC_SetPriority(); + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() and __HAL_SD_DISABLE_IT() inside the communication process. (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() and __HAL_SD_CLEAR_IT() - (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + - *** SD Card Initialization and configuration *** - ================================================ + ================================================ [..] - To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - SDMMC IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - - (#) Initialize the SDMMC peripheral interface with defaullt configuration. - The initialization process is done at 400KHz. You can change or adapt - this frequency by adjusting the "ClockDiv" field. + + (#) Apply the SD Card initialization process at 400KHz and check the SD Card + type (Standard Capacity or High Capacity). You can change or adapt this + frequency by adjusting the "ClockDiv" field. The SD Card frequency (SDMMC_CK) is computed as follows: - SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) on STM32L4Rx/STM32L4Sxx devices + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) on other devices - In initialization mode and according to the SD Card standard, - make sure that the SDMMC_CK frequency doesn't exceed 400KHz. - - This phase of initialization is done through SDMMC_Init() and + In initialization mode and according to the SD Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and SDMMC_PowerState_ON() SDMMC low level APIs. - + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). - This phase allows the card initialization and identification + This phase allows the card initialization and identification and check the SD Card type (Standard Capacity or High Capacity) The initialization flow is compatible with SD standard. - This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case of plug-off plug-in. - - (#) Configure the SD Card Data transfer frequency. By Default, the card transfer - frequency is set to 24MHz. You can change or adapt this frequency by adjusting - the "ClockDiv" field. - In transfer mode and according to the SD Card standard, make sure that the - SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. - To be able to use a frequency higher than 24MHz, you should use the SDMMC - peripheral in bypass mode. Refer to the corresponding reference manual - for more details. - + + (#) Configure the SD Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + In transfer mode and according to the SD Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch. + (#) Select the corresponding SD Card according to the address read with the step 2. - + (#) Configure the SD Card in wide bus mode: 4-bits data. - + *** SD Card Read operation *** ============================== - [..] - (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + [..] + (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. You could also check the DMA transfer process through the SD Rx interrupt event. (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. You could also check the IT transfer process through the SD Rx interrupt event. - + *** SD Card Write operation *** - =============================== - [..] - (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + =============================== + [..] + (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. - You could also check the DMA transfer process through the SD Tx interrupt event. + You could also check the DMA transfer process through the SD Tx interrupt event. (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. You could also check the IT transfer process through the SD Tx interrupt event. - + *** SD card status *** - ====================== + ====================== [..] - (+) The SD Status contains status bits that are related to the SD Memory + (+) The SD Status contains status bits that are related to the SD Memory Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). *** SD card information *** - =========================== + =========================== [..] (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). It returns useful information about the SD card such as block size, card type, block number ... *** SD card CSD register *** - ============================ + ============================ (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. Some of the CSD parameters are useful for card initialization and identification. *** SD card CID register *** - ============================ + ============================ (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. Some of the CSD parameters are useful for card initialization and identification. @@ -180,7 +182,7 @@ ================================== [..] Below the list of most used macros in SD HAL driver. - + (+) __HAL_SD_ENABLE : Enable the SD device (+) __HAL_SD_DISABLE : Disable the SD device (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer @@ -189,39 +191,82 @@ (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags - - (@) You can refer to the SD HAL driver header file for more useful macros - + + (@) You can refer to the SD HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_SD_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + For specific callbacks TransceiverCallback use dedicated register callbacks: + respectively @ref HAL_SD_RegisterTransceiverCallback(). + + Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + For specific callbacks TransceiverCallback use dedicated unregister callbacks: + respectively @ref HAL_SD_UnRegisterTransceiverCallback(). + + By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init + and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit + or @ref HAL_SD_Init function. + + When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -232,10 +277,9 @@ * @{ */ -/** @defgroup SD SD - * @brief SD HAL module driver +/** @addtogroup SD * @{ - */ + */ #ifdef HAL_SD_MODULE_ENABLED @@ -248,7 +292,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -256,22 +300,26 @@ /** @defgroup SD_Private_Functions SD Private Functions * @{ */ -static uint32_t SD_InitCard (SD_HandleTypeDef *hsd); -static uint32_t SD_PowerON (SD_HandleTypeDef *hsd); -static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd); -static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR); -static HAL_StatusTypeDef SD_PowerOFF (SD_HandleTypeDef *hsd); -static HAL_StatusTypeDef SD_Write_IT (SD_HandleTypeDef *hsd); -static HAL_StatusTypeDef SD_Read_IT (SD_HandleTypeDef *hsd); +static uint32_t SD_InitCard (SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON (SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd); +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF (SD_HandleTypeDef *hsd); +static void SD_Write_IT (SD_HandleTypeDef *hsd); +static void SD_Read_IT (SD_HandleTypeDef *hsd); #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) -static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SD_DMAReceiveCplt (DMA_HandleTypeDef *hdma); -static void SD_DMAError (DMA_HandleTypeDef *hdma); -static void SD_DMATxAbort (DMA_HandleTypeDef *hdma); -static void SD_DMARxAbort (DMA_HandleTypeDef *hdma); +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAReceiveCplt (DMA_HandleTypeDef *hdma); +static void SD_DMAError (DMA_HandleTypeDef *hdma); +static void SD_DMATxAbort (DMA_HandleTypeDef *hdma); +static void SD_DMARxAbort (DMA_HandleTypeDef *hdma); +#else +uint32_t SD_HighSpeed (SD_HandleTypeDef *hsd); +static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd); +static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @} @@ -283,28 +331,34 @@ static void SD_DMARxAbort (DMA_HandleTypeDef *hdma); */ /** @addtogroup SD_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the SD card device to be ready for use. - + @endverbatim * @{ */ /** - * @brief Initializes the SD according to the specified parameters in the + * @brief Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle. - * @param hsd: Pointer to the SD handle + * @param hsd: Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) -{ +{ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + HAL_SD_CardStatusTypeDef CardStatus; + uint32_t speedgrade, unitsize; + uint32_t tickstart; +#endif + /* Check the SD handle allocation */ if(hsd == NULL) { @@ -326,8 +380,31 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SD_STATE_RESET only */ + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + hsd->ErrorCallback = HAL_SD_ErrorCallback; + hsd->AbortCpltCallback = HAL_SD_AbortCallback; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuffer0CpltCallback; + hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuffer1CpltCallback; + hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback; + hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback; + hsd->DriveTransceiver_1_8V_Callback = HAL_SDEx_DriveTransceiver_1_8V_Callback; +#endif + + if(hsd->MspInitCallback == NULL) + { + hsd->MspInitCallback = HAL_SD_MspInit; + } + + /* Init the low level hardware */ + hsd->MspInitCallback(hsd); +#else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SD_MspInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } hsd->State = HAL_SD_STATE_BUSY; @@ -339,33 +416,54 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) + { + return HAL_ERROR; + } + /* Get Initial Card Speed from Card Status*/ + speedgrade = CardStatus.UhsSpeedGrade; + unitsize = CardStatus.UhsAllocationUnitSize; + if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U))) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + } + else + { + if (hsd->SdCard.CardType == CARD_SDHC_SDXC) + { + hsd->SdCard.CardSpeed = CARD_HIGH_SPEED; + } + else + { + hsd->SdCard.CardSpeed = CARD_NORMAL_SPEED; + } + + } /* Configure the bus wide */ if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) { return HAL_ERROR; } - - if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + + /* Verify that SD card is ready to use after Initialization */ + tickstart = HAL_GetTick(); + while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + if((HAL_GetTick()-tickstart) >= SDMMC_DATATIMEOUT) { - hsd->Instance->CLKCR |= 0x00100000; - /* Enable High Speed */ - if(HAL_SDEx_HighSpeed(hsd) != HAL_OK) - { - return HAL_ERROR; - } + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_TIMEOUT; } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; - + /* Initialize the SD operation */ hsd->Context = SD_CONTEXT_NONE; - + /* Initialize the SD state */ hsd->State = HAL_SD_STATE_READY; @@ -375,16 +473,16 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD Card. * @param hsd: Pointer to SD handle - * @note This function initializes the SD card. It could be used when a card + * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; - HAL_StatusTypeDef status = HAL_OK; + uint32_t errorstate; + HAL_StatusTypeDef status; SD_InitTypeDef Init; - + /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) @@ -398,11 +496,11 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) { - /* Set Transceiver polarity */ + /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Initialize SDMMC peripheral interface with default configuration */ status = SDMMC_Init(hsd->Instance, Init); if(status != HAL_OK) @@ -412,23 +510,20 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Disable SDMMC Clock */ - __HAL_SD_DISABLE(hsd); + __HAL_SD_DISABLE(hsd); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - + /* Set Power State to ON */ status = SDMMC_PowerState_ON(hsd->Instance); if(status != HAL_OK) { return HAL_ERROR; } - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Enable SDMMC Clock */ __HAL_SD_ENABLE(hsd); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - - /* Required power up waiting time before starting the SD initialization sequence */ - HAL_Delay(2U); /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); @@ -463,21 +558,47 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); hsd->State = HAL_SD_STATE_BUSY; - - /* Set SD power state to off */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Desactivate the 1.8V Mode */ + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if(hsd->DriveTransceiver_1_8V_Callback == NULL) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SDEx_DriveTransceiver_1_8V_Callback; + } + hsd->DriveTransceiver_1_8V_Callback(RESET); +#else + HAL_SDEx_DriveTransceiver_1_8V_Callback(RESET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } +#endif + + /* Set SD power state to off */ SD_PowerOFF(hsd); - + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if(hsd->MspDeInitCallback == NULL) + { + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + } + + /* DeInit the low level hardware */ + hsd->MspDeInitCallback(hsd); +#else /* De-Initialize the MSP layer */ HAL_SD_MspDeInit(hsd); - +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_RESET; - + return HAL_OK; } @@ -517,14 +638,14 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) */ /** @addtogroup SD_Exported_Functions_Group2 - * @brief Data transfer functions + * @brief Data transfer functions * -@verbatim +@verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] - This subsection provides a set of functions allowing to manage the data + This subsection provides a set of functions allowing to manage the data transfer from/to SD card. @endverbatim @@ -532,50 +653,52 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) */ /** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). * @param hsd: Pointer to SD handle * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of SD blocks to read + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0, *tempbuff = (uint32_t *)pData; - + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + if(NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - + if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - + hsd->Instance->DCTRL = 0U; + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } - + /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) @@ -586,7 +709,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * BLOCKSIZE; @@ -598,25 +721,25 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 #else config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) + if(NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); } else { hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; - + /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -624,38 +747,52 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) { /* Read data from SDMMC Rx FIFO */ for(count = 0U; count < 8U; count++) { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; } - tempbuff += 8U; } - - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_DISABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Send stop transmission command in case of multiblock read */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) - { + { if(hsd->SdCard.CardType != CARD_SECURED) { /* Send stop transmission command */ @@ -666,11 +803,12 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } } - + /* Get error state */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { @@ -678,6 +816,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -686,6 +825,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) @@ -694,32 +834,49 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + else + { + /* Nothing to do */ + } + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Empty FIFO if there is still any data */ - while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); tempbuff++; - - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - + /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + hsd->State = HAL_SD_STATE_READY; - + return HAL_OK; } else @@ -731,24 +888,25 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /** * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. + * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). * @param hsd: Pointer to SD handle * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of SD blocks to write + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; - uint32_t *tempbuff = (uint32_t *)pData; - + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + if(NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; @@ -758,35 +916,35 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - + hsd->Instance->DCTRL = 0U; + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } - - /* Set Block Size for Card */ + + /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - - /* Configure the SD DPSM (Data Path State Machine) */ + + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; @@ -797,7 +955,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint #else config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -806,45 +964,59 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint if(NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; - + /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) { /* Write data to SDMMC Tx FIFO */ for(count = 0U; count < 8U; count++) { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - tempbuff += 8U; } - - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -854,7 +1026,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Send stop transmission command in case of multiblock write */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) - { + { if(hsd->SdCard.CardType != CARD_SECURED) { /* Send stop transmission command */ @@ -862,14 +1034,15 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } } - + /* Get error state */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { @@ -877,6 +1050,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -885,6 +1059,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) @@ -893,14 +1068,19 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + else + { + /* Nothing to do */ + } + /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + hsd->State = HAL_SD_STATE_READY; - + return HAL_OK; } else @@ -911,60 +1091,61 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed in interrupt mode. + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @note You could also check the IT transfer process through the SD Rx + * @note You could also check the IT transfer process through the SD Rx * interrupt event. - * @param hsd: Pointer to SD handle + * @param hsd: Pointer to SD handle * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read + * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t add = BlockAdd; + if(NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - + if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - - hsd->pRxBuffPtr = (uint32_t *)pData; + + hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; - + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); - + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } - - /* Set Block Size for Card */ + + /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; @@ -981,35 +1162,36 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui #else config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Read Blocks in IT mode */ if(NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); - + /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); - + /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + return HAL_OK; } else @@ -1019,75 +1201,76 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui } /** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed in interrupt mode. + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @note You could also check the IT transfer process through the SD Tx - * interrupt event. + * @note You could also check the IT transfer process through the SD Tx + * interrupt event. * @param hsd: Pointer to SD handle * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written + * @param BlockAdd: Block Address where data will be written * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t add = BlockAdd; + if(NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - + if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - - hsd->pTxBuffPtr = (uint32_t *)pData; + + hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; - + /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); - + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } - - /* Set Block Size for Card */ + + /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Configure the SD DPSM (Data Path State Machine) */ + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); __SDMMC_CMDTRANS_ENABLE( hsd->Instance); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -1096,37 +1279,38 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u if(NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - /* Configure the SD DPSM (Data Path State Machine) */ + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - + return HAL_OK; } else @@ -1136,132 +1320,145 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u } /** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @note You could also check the DMA transfer process through the SD Rx + * @note You could also check the DMA transfer process through the SD Rx * interrupt event. - * @param hsd: Pointer SD handle + * @param hsd: Pointer SD handle * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read + * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t add = BlockAdd; + if(NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - + if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - + /* Set the DMA transfer complete callback */ hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; - + /* Set the DMA error callback */ hsd->hdmarx->XferErrorCallback = SD_DMAError; - + /* Set the DMA Abort callback */ hsd->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Enable SD DMA transfer */ - __HAL_SD_DMA_ENABLE(hsd); -#else - hsd->pRxBuffPtr = (uint32_t*)pData; - hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; -#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) { - BlockAdd *= 512U; - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - config.DPSM = SDMMC_DPSM_DISABLE; -#else - config.DPSM = SDMMC_DPSM_ENABLE; -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_ConfigData(hsd->Instance, &config); - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); - hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; - hsd->Instance->IDMABASE0 = (uint32_t) pData ; -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); - } else { - hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); +#else + hsd->pRxBuffPtr = pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; + (void)SDMMC_ConfigData(hsd->Instance, &config); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + hsd->Instance->IDMABASE0 = (uint32_t) pData ; + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) } - - return HAL_OK; +#endif } else { @@ -1270,72 +1467,73 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u } /** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @note You could also check the DMA transfer process through the SD Tx + * @note You could also check the DMA transfer process through the SD Tx * interrupt event. * @param hsd: Pointer to SD handle * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written + * @param BlockAdd: Block Address where data will be written * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t add = BlockAdd; + if(NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - + if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - hsd->pTxBuffPtr = (uint32_t*)pData; + hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; #else /* Enable SD Error interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); - + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + /* Set the DMA transfer complete callback */ hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; - + /* Set the DMA error callback */ hsd->hdmatx->XferErrorCallback = SD_DMAError; - + /* Set the DMA Abort callback */ hsd->hdmatx->XferAbortCallback = NULL; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } - - /* Set Block Size for Card */ + + /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; @@ -1348,62 +1546,75 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); - + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); - hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; hsd->Instance->IDMABASE0 = (uint32_t) pData ; + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); - + /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Enable SDMMC DMA transfer */ __HAL_SD_DMA_ENABLE(hsd); - + /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - - return HAL_OK; + + return HAL_OK; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + } +#endif } else { @@ -1415,33 +1626,35 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, * @brief Erases the specified memory area of the given SD card. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle + * @param hsd: Pointer to SD handle * @param BlockStartAdd: Start Block address * @param BlockEndAdd: End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + if(hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if(BlockEndAdd < BlockStartAdd) + + if(end_add < start_add) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - - if(BlockEndAdd > (hsd->SdCard.LogBlockNbr)) + + if(end_add > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_BUSY; - + /* Check if the card command class supports erase command */ if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) { @@ -1451,62 +1664,62 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - + /* Get start and end block for high capacity cards */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockStartAdd *= 512U; - BlockEndAdd *= 512U; + start_add *= 512U; + end_add *= 512U; } - + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ if(hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd); + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd); + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } } - + /* Send CMD38 ERASE */ errorstate = SDMMC_CmdErase(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - + hsd->State = HAL_SD_STATE_READY; - + return HAL_OK; } else @@ -1521,115 +1734,156 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) -{ - uint32_t errorstate = HAL_SD_ERROR_NONE; - +{ + uint32_t errorstate; + uint32_t context = hsd->Context; + /* Check for SDMMC interrupt flags */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET) + if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SD_Read_IT(hsd); + } + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); + + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ SDMMC_IT_RXFIFOHF); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#else + hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - if((hsd->Context & SD_CONTEXT_IT) != RESET) + + if((context & SD_CONTEXT_IT) != 0U) { - if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - + /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + hsd->State = HAL_SD_STATE_READY; - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else HAL_SD_RxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } else { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + else if((context & SD_CONTEXT_DMA) != 0U) { #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) hsd->Instance->DLEN = 0; hsd->Instance->DCTRL = 0; hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; - /* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */ - if((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } hsd->State = HAL_SD_STATE_READY; - if(((hsd->Context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { - HAL_SD_TxCpltCallback(hsd); - } - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) - { - HAL_SD_RxCpltCallback(hsd); - } +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); #else - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } +#else + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) { /* Disable the DMA transfer for transmit request by setting the DMAEN bit in the SD DCTRL register */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - + hsd->State = HAL_SD_STATE_READY; - + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } + else + { + /* Nothing to do */ + } } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) + + else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { SD_Write_IT(hsd); } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) - { - SD_Read_IT(hsd); - } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) { - hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; } if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) { @@ -1641,23 +1895,39 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) { - hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; } - + /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + /* Disable all interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - if((hsd->Context & SD_CONTEXT_IT) != RESET) + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + + if((context & SD_CONTEXT_IT) != 0U) { /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; - HAL_SD_ErrorCallback(hsd); + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + else if((context & SD_CONTEXT_DMA) != 0U) { #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if(hsd->ErrorCode != HAL_SD_ERROR_NONE) @@ -1665,14 +1935,18 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) /* Disable Internal DMA */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; - + /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } #else /* Abort the SD DMA channel */ - if(hsd->hdmatx != NULL) + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { /* Set the DMA Tx abort callback */ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; @@ -1682,7 +1956,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) SD_DMATxAbort(hsd->hdmatx); } } - else if(hsd->hdmarx != NULL) + else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { /* Set the DMA Rx abort callback */ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; @@ -1696,42 +1970,71 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } + else + { + /* Nothing to do */ + } } - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) { - if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0) + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); + if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->Write_DMADblBuf1CpltCallback(hsd); +#else HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->Read_DMADblBuf1CpltCallback(hsd); +#else HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } else /* SD_DMA_BUFFER1 */ { /* Current buffer is buffer1, Transfer complete for buffer0 */ - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->Write_DMADblBuf0CpltCallback(hsd); +#else HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->Read_DMADblBuf0CpltCallback(hsd); +#else HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + else + { + /* Nothing to do */ + } } /** @@ -1760,7 +2063,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) * @param hsd: Pointer to SD handle * @retval None */ - __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); @@ -1797,7 +2100,7 @@ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SD_ErrorCallback can be implemented in the user file - */ + */ } /** @@ -1809,26 +2112,305 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_ErrorCallback can be implemented in the user file - */ + the HAL_SD_AbortCallback can be implemented in the user file + */ } +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SD Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Rx Double buffer 0 Callback ID + * @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Rx Double buffer 1 Callback ID + * @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID + * @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = pCallback; + break; +#endif + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Callback + * SD Callback is redirected to the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Rx Double buffer 0 Callback ID + * @arg @ref HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Rx Double buffer 1 Callback ID + * @arg @ref HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID SD DMA Tx Double buffer 0 Callback ID + * @arg @ref HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID SD DMA Tx Double buffer 1 Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuffer0CpltCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuffer1CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback; + break; +#endif + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Register a User SD Transceiver Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->DriveTransceiver_1_8V_Callback = pCallback; + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Transceiver Callback + * SD Callback is redirected to the weak (surcharged) predefined callback + * @param hsd : SD handle + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SDEx_DriveTransceiver_1_8V_Callback; + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} +#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup SD_Exported_Functions_Group3 - * @brief management functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] - This subsection provides a set of functions allowing to control the SD card + This subsection provides a set of functions allowing to control the SD card operations and get the related information @endverbatim @@ -1839,80 +2421,32 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) * @brief Returns information the information of the card which are stored on * the CID register. * @param hsd: Pointer to SD handle - * @param pCID: Pointer to a HAL_SD_CIDTypedef structure that - * contains all CID register parameters + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that + * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); - pCID->ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCID->OEM_AppliID = tmp << 8; - - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x0000FF00) >> 8); - pCID->OEM_AppliID |= tmp; - - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCID->ProdName1 = tmp << 24; - - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); - pCID->ProdName1 |= tmp << 16; - - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCID->ProdName1 |= tmp << 8; - - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCID->ProdName1 |= tmp; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCID->ProdName2 = tmp; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); - pCID->ProdRev = tmp; - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCID->ProdSN = tmp << 24; - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCID->ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCID->ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); - pCID->ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCID->Reserved1 |= (tmp & 0xF0) >> 4; - pCID->ManufactDate = (tmp & 0x0F) << 8; - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCID->ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCID->CID_CRC = (tmp & 0xFE) >> 1; - pCID->Reserved2 = 1; - + pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + return HAL_OK; } @@ -1920,243 +2454,176 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef * @brief Returns information the information of the card which are stored on * the CSD register. * @param hsd: Pointer to SD handle - * @param pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that - * contains all CSD register parameters + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD) +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; - pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCSD->Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCSD->TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCSD->NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hsd->CSD[0] & 0x000000FF; - pCSD->MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; - pCSD->CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; - pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; - pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCSD->Reserved2 = 0; /*!< Reserved */ - + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + if(hsd->SdCard.CardType == CARD_SDSC) { - pCSD->DeviceSize = (tmp & 0x03) << 10; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCSD->DeviceSize |= (tmp) << 2; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - pCSD->DeviceSize |= (tmp & 0xC0) >> 6; - - pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCSD->MaxRdCurrentVDDMax = (tmp & 0x07); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCSD->DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7; - - hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1) ; - hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2)); - hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen); + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512); - hsd->SdCard.LogBlockSize = 512; + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); + + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockSize = 512U; } else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) { /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCSD->DeviceSize = (tmp & 0x3F) << 16; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - - pCSD->DeviceSize |= (tmp << 8); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - - pCSD->DeviceSize |= (tmp); - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - - hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024); - hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512; + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + hsd->SdCard.BlockSize = 512U; + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; } else { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - - pCSD->EraseGrSize = (tmp & 0x40) >> 6; - pCSD->EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCSD->EraseGrMul |= (tmp & 0x80) >> 7; - pCSD->WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); - pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7; - pCSD->ManDeflECC = (tmp & 0x60) >> 5; - pCSD->WrSpeedFact = (tmp & 0x1C) >> 2; - pCSD->MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCSD->Reserved3 = 0; - pCSD->ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCSD->FileFormatGrouop = (tmp & 0x80) >> 7; - pCSD->CopyFlag = (tmp & 0x40) >> 6; - pCSD->PermWrProtect = (tmp & 0x20) >> 5; - pCSD->TempWrProtect = (tmp & 0x10) >> 4; - pCSD->FileFormat = (tmp & 0x0C) >> 2; - pCSD->ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCSD->CSD_CRC = (tmp & 0xFE) >> 1; + + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + pCSD->Reserved4 = 1; - + return HAL_OK; } /** * @brief Gets the SD status info. - * @param hsd: Pointer to SD handle - * @param pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that - * will contain the SD card status information + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus) +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { - uint32_t tmp = 0; uint32_t sd_status[16]; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + errorstate = SD_SendSDStatus(hsd, sd_status); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } else { - /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pStatus->DataBusWidth = (uint8_t)tmp; - - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pStatus->SecuredMode = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (sd_status[0] & 0x00FF0000U) >> 16; - pStatus->CardType = (uint16_t)(tmp << 8); - - /* Byte 3 */ - tmp = (sd_status[0] & 0xFF000000U) >> 24; - pStatus->CardType |= (uint16_t)tmp; - - /* Byte 4 */ - tmp = (sd_status[1] & 0xFF); - pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24); - - /* Byte 5 */ - tmp = (sd_status[1] & 0xFF00) >> 8; - pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16); - - /* Byte 6 */ - tmp = (sd_status[1] & 0xFF0000) >> 16; - pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8); - - /* Byte 7 */ - tmp = (sd_status[1] & 0xFF000000U) >> 24; - pStatus->ProtectedAreaSize |= (uint32_t)tmp; - - /* Byte 8 */ - tmp = (sd_status[2] & 0xFF); - pStatus->SpeedClass = (uint8_t)tmp; - - /* Byte 9 */ - tmp = (sd_status[2] & 0xFF00) >> 8; - pStatus->PerformanceMove = (uint8_t)tmp; - - /* Byte 10 */ - tmp = (sd_status[2] & 0xF00000) >> 20; - pStatus->AllocationUnitSize = (uint8_t)tmp; - - /* Byte 11 */ - tmp = (sd_status[2] & 0xFF000000U) >> 24; - pStatus->EraseSize = (uint16_t)(tmp << 8); - - /* Byte 12 */ - tmp = (sd_status[3] & 0xFF); - pStatus->EraseSize |= (uint16_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0xFC00) >> 10; - pStatus->EraseTimeout = (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0x0300) >> 8; - pStatus->EraseOffset = (uint8_t)tmp; + pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); + + pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); + + pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); + + pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | + ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); + + pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); + + pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); + + pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); + + pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); + + pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); + + pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U); + pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ; + pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U); +#endif } - + return HAL_OK; } /** * @brief Gets the SD card info. - * @param hsd: Pointer to SD handle - * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that - * will contain the SD card status information + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) @@ -2169,15 +2636,15 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); - + return HAL_OK; } /** - * @brief Enables wide bus operation for the requested card if supported by + * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hsd: Pointer to SD handle - * @param WideMode: Specifies the SD card wide bus mode + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode * This parameter can be one of the following values: * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer @@ -2187,15 +2654,15 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) { SDMMC_InitTypeDef Init; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - + /* Change State */ hsd->State = HAL_SD_STATE_BUSY; - - if(hsd->SdCard.CardType != CARD_SECURED) + + if(hsd->SdCard.CardType != CARD_SECURED) { if(WideMode == SDMMC_BUS_WIDE_8B) { @@ -2204,13 +2671,13 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t else if(WideMode == SDMMC_BUS_WIDE_4B) { errorstate = SD_WideBus_Enable(hsd); - + hsd->ErrorCode |= errorstate; } else if(WideMode == SDMMC_BUS_WIDE_1B) { errorstate = SD_WideBus_Disable(hsd); - + hsd->ErrorCode |= errorstate; } else @@ -2218,13 +2685,13 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t /* WideMode is not a valid argument*/ hsd->ErrorCode |= HAL_SD_ERROR_PARAM; } - } + } else { /* MMC Card does not support this feature */ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ @@ -2242,63 +2709,259 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t Init.ClockPowerSave = hsd->Init.ClockPowerSave; Init.BusWide = WideMode; Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#if 0 /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ - // if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV) - if(hsd->Init.ClockDiv >= SDMMC_TRANSFER_CLK_DIV) + if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV) { Init.ClockDiv = hsd->Init.ClockDiv; } + else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + /* UltraHigh speed SD card,user Clock div */ + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* High speed SD card, Max Frequency = 50Mhz */ + Init.ClockDiv = SDMMC_HSpeed_CLK_DIV; + } else { - if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) - { - Init.ClockDiv = hsd->Init.ClockDiv; - } - else - { - /* No High speed SD card */ - // Init.ClockDiv = SDMMC_NSpeed_CLK_DIV; - Init.ClockDiv = SDMMC_TRANSFER_CLK_DIV; - } + /* No High speed SD card, Max Frequency = 25Mhz */ + Init.ClockDiv = SDMMC_NSpeed_CLK_DIV; } -#else - Init.ClockDiv = hsd->Init.ClockDiv; -#endif #else Init.ClockDiv = hsd->Init.ClockDiv; #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - SDMMC_Init(hsd->Instance, Init); + (void)SDMMC_Init(hsd->Instance, Init); } /* Change State */ hsd->State = HAL_SD_STATE_READY; - + return HAL_OK; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Configure the speed bus mode + * @param hsd: Pointer to the SD handle + * @param SpeedMode: Specifies the SD card speed bus mode + * This parameter can be one of the following values: + * @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card + * @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode + * @arg SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode + * @arg SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SDMMC_SPEED_MODE(SpeedMode)); + /* Change State */ + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= 0x00100000U; + /* Enable Ultra High Speed */ + if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + /*Nothing to do, Use defaultSpeed */ + } + break; + } + case SDMMC_SPEED_MODE_ULTRA: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= 0x00100000U; + /* Enable UltraHigh Speed */ + if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DDR: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= 0x00100000U; + /* Enable DDR Mode*/ + if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + break; + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; + } + } + else + { + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + /*Nothing to do, Use defaultSpeed */ + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + break; + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; + } + } + + + /* Verify that SD card is ready to use after Speed mode switch*/ + tickstart = HAL_GetTick(); + while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; + return status; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @brief Gets the current sd card data state. * @param hsd: pointer to SD handle * @retval Card state */ -HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypedef cardstate = HAL_SD_CARD_TRANSFER; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t cardstate; + uint32_t errorstate; uint32_t resp1 = 0; - + errorstate = SD_SendStatus(hsd, &resp1); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; } - cardstate = (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); - - return cardstate; + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_SD_CardStateTypeDef)cardstate; } /** @@ -2309,38 +2972,57 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypedef CardState; - + HAL_SD_CardStateTypeDef CardState; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + uint32_t context = hsd->Context; +#endif + /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - + /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; #else - if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - + /* Abort the SD DMA Tx channel */ - if(hsd->hdmatx != NULL) + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { - HAL_DMA_Abort(hsd->hdmatx); + if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } } /* Abort the SD DMA Rx channel */ - if(hsd->hdmarx != NULL) + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { - HAL_DMA_Abort(hsd->hdmarx); + if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + else + { + /* Nothing to do */ } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + CardState = HAL_SD_GetCardState(hsd); if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { @@ -2361,69 +3043,82 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypedef CardState; - + HAL_SD_CardStateTypeDef CardState; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + uint32_t context = hsd->Context; +#endif + /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; - + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) { return HAL_ERROR; } else { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } #else - if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - + /* Abort the SD DMA Tx channel */ - if(hsd->hdmatx != NULL) + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { - hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) { hsd->hdmatx = NULL; } } /* Abort the SD DMA Rx channel */ - if(hsd->hdmarx != NULL) + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { - hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) { hsd->hdmarx = NULL; } } + else + { + /* Nothing to do */ + } } - /* No transfer ongoing on both DMA channels*/ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) + else { /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); @@ -2434,11 +3129,15 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) } else { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + return HAL_OK; } @@ -2449,36 +3148,36 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /** * @} */ - -/* Private function ----------------------------------------------------------*/ + +/* Private function ----------------------------------------------------------*/ /** @addtogroup SD_Private_Functions * @{ */ - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** - * @brief DMA SD transmit process complete callback + * @brief DMA SD transmit process complete callback * @param hdma: DMA handle * @retval None */ -static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - + /* Enable DATAEND Interrupt */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND)); } /** - * @brief DMA SD receive process complete callback + * @brief DMA SD receive process complete callback * @param hdma: DMA handle * @retval None */ -static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + /* Send stop command in multiblock write */ if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) { @@ -2486,129 +3185,146 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } } - + /* Disable the DMA transfer for transmit request by setting the DMAEN bit in the SD DCTRL register */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - + /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - hsd->State = HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->RxCpltCallback(hsd); +#else HAL_SD_RxCpltCallback(hsd); +#endif } /** - * @brief DMA SD communication error callback + * @brief DMA SD communication error callback * @param hdma: DMA handle * @retval None */ -static void SD_DMAError(DMA_HandleTypeDef *hdma) +static void SD_DMAError(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - HAL_SD_CardStateTypedef CardState; - - if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) + HAL_SD_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; + + RxErrorCode = hsd->hdmarx->ErrorCode; + TxErrorCode = hsd->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) { /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - + /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - + hsd->ErrorCode |= HAL_SD_ERROR_DMA; CardState = HAL_SD_GetCardState(hsd); if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } - + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; } +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else HAL_SD_ErrorCallback(hsd); +#endif } /** - * @brief DMA SD Tx Abort callback + * @brief DMA SD Tx Abort callback * @param hdma: DMA handle * @retval None */ -static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - HAL_SD_CardStateTypedef CardState; - - if(hsd->hdmatx != NULL) + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - hsd->hdmatx = NULL; + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } - - /* All DMA channels are aborted */ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if(hsd->ErrorCode == HAL_SD_ERROR_NONE) - { - HAL_SD_AbortCallback(hsd); - } - else - { - HAL_SD_ErrorCallback(hsd); - } - } +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif } } /** - * @brief DMA SD Rx Abort callback + * @brief DMA SD Rx Abort callback * @param hdma: DMA handle * @retval None */ -static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - HAL_SD_CardStateTypedef CardState; - - if(hsd->hdmarx != NULL) - { - hsd->hdmarx = NULL; - } - - /* All DMA channels are aborted */ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) - { - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + HAL_SD_CardStateTypeDef CardState; - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if(hsd->ErrorCode == HAL_SD_ERROR_NONE) - { - HAL_SD_AbortCallback(hsd); - } - else - { - HAL_SD_ErrorCallback(hsd); - } - } + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif } } #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ @@ -2620,18 +3336,18 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { - HAL_SD_CardCSDTypedef CSD; - uint32_t errorstate = HAL_SD_ERROR_NONE; - uint16_t sd_rca = 1; - + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t sd_rca = 1U; + /* Check the power State */ - if(SDMMC_GetPowerState(hsd->Instance) == 0) + if(SDMMC_GetPowerState(hsd->Instance) == 0U) { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - - if(hsd->SdCard.CardType != CARD_SECURED) + + if(hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hsd->Instance); @@ -2642,14 +3358,14 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) else { /* Get Card identification number data */ - hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); } } - - if(hsd->SdCard.CardType != CARD_SECURED) + + if(hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ @@ -2659,11 +3375,11 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) return errorstate; } } - if(hsd->SdCard.CardType != CARD_SECURED) + if(hsd->SdCard.CardType != CARD_SECURED) { /* Get the SD card RCA */ hsd->SdCard.RelCardAdd = sd_rca; - + /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) @@ -2679,25 +3395,28 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); } } - + /* Get the Card Class */ - hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20); - + hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); + /* Get CSD parameters */ - HAL_SD_GetCardCSD(hsd, &CSD); + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Configure SDMMC peripheral interface */ - SDMMC_Init(hsd->Instance, hsd->Init); + (void)SDMMC_Init(hsd->Instance, hsd->Init); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - + /* All cards are initialized */ return HAL_SD_ERROR_NONE; } @@ -2711,268 +3430,227 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { - __IO uint32_t count = 0; - uint32_t response = 0, validvoltage = 0; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t tickstart = HAL_GetTick(); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->SdCard.CardVersion = CARD_V1_X; - -#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while(validvoltage == 0) + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - if(count++ == SDMMC_MAX_VOLT_TRIAL) - { - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + return errorstate; } - /* Card type is SDSC */ - hsd->SdCard.CardType = CARD_SDSC; -#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + } else { hsd->SdCard.CardVersion = CARD_V2_X; - -#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while(validvoltage == 0) - { - if(count++ == SDMMC_MAX_VOLT_TRIAL) - { - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); - } - - if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->SdCard.CardType = CARD_SDHC_SDXC; - } - else - { - hsd->SdCard.CardType = CARD_SDSC; - } -#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) + if( hsd->SdCard.CardVersion == CARD_V2_X) { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + } + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + + count++; + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + + /* Start switching procedue */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; + + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Check to CKSTOP */ + while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) + { + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear CKSTOP Flag */ + hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; + + /* Check to BusyD0 */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + { + /* Error when activate Voltage Switch in SDMMC Peripheral */ + return SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Enable Transceiver Switch PIN */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); +#endif + + /* Switch ready */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; + + /* Check VSWEND Flag */ + while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) + { + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear VSWEND Flag */ + hsd->Instance->ICR = SDMMC_FLAG_VSWEND; + + /* Check BusyD0 status */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + { + /* Error when enabling 1.8V mode */ + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + /* Switch to 1.8V OK */ + + /* Disable VSWITCH FLAG from SDMMC Peripheral */ + hsd->Instance->POWER = 0x13U; + + /* Clean Status flags */ + hsd->Instance->ICR = 0xFFFFFFFFU; + } + + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } else { - /* SD CARD */ - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((!validvoltage) && (count < SDMMC_MAX_VOLT_TRIAL)) - { - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); - - count++; - } - - if(count >= SDMMC_MAX_VOLT_TRIAL) - { - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - - if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->SdCard.CardType = CARD_SDHC_SDXC; - - if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) - { - if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) - { - hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; - - /* Start switching procedue */ - hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; - - /* Send CMD11 to switch 1.8V mode */ - errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Check to CKSTOP */ - while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP); - - /* Clear CKSTOP Flag */ - hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; - - /* Check to BusyD0 */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) - { - /* Error when activate Voltage Switch in SDMMC IP */ - return SDMMC_ERROR_UNSUPPORTED_FEATURE; - } - else - { - /* Enable Transceiver Switch PIN */ - HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); - - /* Switch ready */ - hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; - - /* Check VSWEND Flag */ - while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND); - - /* Clear VSWEND Flag */ - hsd->Instance->ICR = SDMMC_FLAG_VSWEND; - - /* Check BusyD0 status */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) - { - /* Error when enabling 1.8V mode */ - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - /* Switch to 1.8V OK */ - - /* Disable VSWITCH FLAG from SDMMC IP */ - hsd->Instance->POWER = 0x13; - /* Clean Status flags */ - hsd->Instance->ICR = 0xFFFFFFFF; - } - } - } - } + hsd->SdCard.CardType = CARD_SDSC; } -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + + return HAL_SD_ERROR_NONE; } /** * @brief Turns the SDMMC output signals off. * @param hsd: Pointer to SD handle - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) +static void SD_PowerOFF(SD_HandleTypeDef *hsd) { /* Set Power State to OFF */ - SDMMC_PowerState_OFF(hsd->Instance); - - return HAL_OK; + (void)SDMMC_PowerState_OFF(hsd->Instance); } /** * @brief Send Status info command. * @param hsd: pointer to SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * @param pSDstatus: Pointer to the buffer that will contain the SD card status * SD Status register) * @retval error state */ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; - + uint32_t count; + uint32_t *pData = pSDstatus; + /* Check SD response */ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } - + /* Set block size for card if it is not equal to current block size for card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - + /* Send CMD55 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - - /* Configure the SD DPSM (Data Path State Machine) */ + + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 64; + config.DataLength = 64U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - + (void)SDMMC_ConfigData(hsd->Instance, &config); + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) @@ -2980,7 +3658,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - + /* Get status data */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) @@ -2990,20 +3668,19 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { - for(count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { - *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance); + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; } - - pSDstatus += 8; } - + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } - + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { return HAL_SD_ERROR_DATA_TIMEOUT; @@ -3016,6 +3693,10 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { return HAL_SD_ERROR_RX_OVERRUN; } + else + { + /* Nothing to do */ + } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) @@ -3023,47 +3704,47 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { - *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); - pSDstatus++; - + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } - + /* Clear all the static status flags*/ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - + return HAL_SD_ERROR_NONE; } /** * @brief Returns the current card's status. * @param hsd: Pointer to SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card - * status (Card Status register) + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) * @retval error state */ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + if(pCardStatus == NULL) { return HAL_SD_ERROR_PARAM; } - + /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + /* Get SD card status */ *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - + return HAL_SD_ERROR_NONE; } @@ -3074,34 +3755,34 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - uint32_t scr[2] = {0, 0}; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } - + /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + /* If requested card supports wide bus operation */ - if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3112,7 +3793,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } -} +} /** * @brief Disables the SDMMC wide bus mode. @@ -3121,38 +3802,38 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - uint32_t scr[2] = {0, 0}; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } - + /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + /* If requested card supports 1 bit mode operation */ - if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + return HAL_SD_ERROR_NONE; } else @@ -3160,62 +3841,63 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } } - - + + /** * @brief Finds the SD card SCR register value. * @param hsd: Pointer to SD handle - * @param pSCR: pointer to the buffer that will contain the SCR value + * @param pSCR: pointer to the buffer that will contain the SCR value * @retval error state */ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t index = 0; - uint32_t tempscr[2] = {0, 0}; - + uint32_t index = 0U; + uint32_t tempscr[2U] = {0U, 0U}; + uint32_t *scr = pSCR; + /* Set Block Size To 8 Bytes */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 8; + config.DataLength = 8U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - + (void)SDMMC_ConfigData(hsd->Instance, &config); + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) { - if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0)) + if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) { tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); index++; } - + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; @@ -3229,30 +3911,30 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); index++; } - + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - + return HAL_SD_ERROR_DATA_TIMEOUT; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - + return HAL_SD_ERROR_DATA_CRC_FAIL; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - + return HAL_SD_ERROR_RX_OVERRUN; } else @@ -3261,11 +3943,12 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); - - *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24); + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + scr++; + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + } return HAL_SD_ERROR_NONE; @@ -3275,51 +3958,459 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) * @brief Wrap up reading in non-blocking mode. * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) +static void SD_Read_IT(SD_HandleTypeDef *hsd) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data, dataremaining; + uint8_t* tmp; - tmp = (uint32_t*)hsd->pRxBuffPtr; - - /* Read data from SDMMC Rx FIFO */ - for(count = 0; count < 8; count++) + tmp = hsd->pRxBuffPtr; + dataremaining = hsd->RxXferSize; + + if (dataremaining > 0U) { - *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance); + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } + + hsd->pRxBuffPtr = tmp; + hsd->RxXferSize = dataremaining; } - - hsd->pRxBuffPtr += 8; - - return HAL_OK; } /** * @brief Wrap up writing in non-blocking mode. * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd) +static void SD_Write_IT(SD_HandleTypeDef *hsd) { - uint32_t count = 0; - uint32_t* tmp; - - tmp = (uint32_t*)hsd->pTxBuffPtr; - - /* Write data to SDMMC Tx FIFO */ - for(count = 0; count < 8; count++) + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pTxBuffPtr; + dataremaining = hsd->TxXferSize; + + if (dataremaining > 0U) { - SDMMC_WriteFIFO(hsd->Instance, (tmp + count)); + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } + + hsd->pTxBuffPtr = tmp; + hsd->TxXferSize = dataremaining; } - - hsd->pTxBuffPtr += 8; - - return HAL_OK; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Switches the SD card to High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock between 50 and 120 MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint32_t SD_hs[16] = {0}; + uint32_t count, loop = 0 ; + uint32_t Timeout = HAL_GetTick(); + if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + + if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } + + + errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + } + loop ++; + } + + if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + errorstate = 0; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + + } + + return errorstate; +} + +/** + * @brief Switches the SD card to Ultra High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock between 50 and 120 MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint32_t SD_hs[16] = {0}; + uint32_t count, loop = 0 ; + uint32_t Timeout = HAL_GetTick(); + + if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) && + (hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE)) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + + if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } + + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + } + loop ++; + } + + if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + errorstate = 0; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) + /* Enable DelayBlock Peripheral */ + /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */ + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1); + if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } +#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */ + } + } + + return errorstate; +} + +/** + * @brief Switches the SD card to Double Data Rate (DDR) mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock less than 50MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint32_t SD_hs[16] = {0}; + uint32_t count, loop = 0 ; + uint32_t Timeout = HAL_GetTick(); + + if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) && + (hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE)) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + + if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } + + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + } + loop ++; + } + + if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + errorstate = 0; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode is ok */ + if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) + /* Enable DelayBlock Peripheral */ + /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */ + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1); + if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } +#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */ + } + } + + return errorstate; +} + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h index b1748fe7a8..3cee33d3f4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SD_H -#define __STM32L4xx_HAL_SD_H +#ifndef STM32L4xx_HAL_SD_H +#define STM32L4xx_HAL_SD_H #ifdef __cplusplus extern "C" { @@ -50,18 +34,19 @@ * @{ */ -/** @addtogroup SD +/** @defgroup SD SD + * @brief SD HAL module driver * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SD_Exported_Types SD Exported Types * @{ */ /** @defgroup SD_Exported_Types_Group1 SD State enumeration structure * @{ - */ + */ typedef enum { HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */ @@ -73,110 +58,130 @@ typedef enum HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */ HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ }HAL_SD_StateTypeDef; -/** +/** * @} */ /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure * @{ - */ -typedef enum -{ - HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ - HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ - HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ - HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ - HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ - HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ - HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ - HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ - HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */ -}HAL_SD_CardStateTypedef; -/** + */ +typedef uint32_t HAL_SD_CardStateTypeDef; + +#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** * @} */ -/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition +/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition * @{ */ -#define SD_InitTypeDef SDMMC_InitTypeDef +#define SD_InitTypeDef SDMMC_InitTypeDef #define SD_TypeDef SDMMC_TypeDef -/** +/** * @brief SD Card Information Structure definition - */ + */ typedef struct { uint32_t CardType; /*!< Specifies the card Type */ - + uint32_t CardVersion; /*!< Specifies the card version */ uint32_t Class; /*!< Specifies the class of the card class */ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ - + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ uint32_t BlockSize; /*!< Specifies one block size in bytes */ - + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - + uint32_t CardSpeed; /*!< Specifies the card Speed */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ }HAL_SD_CardInfoTypeDef; -/** +/** * @brief SD handle Structure definition - */ + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +typedef struct __SD_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ { SD_TypeDef *Instance; /*!< SD registers base address */ - + SD_InitTypeDef Init; /*!< SD required parameters */ - + HAL_LockTypeDef Lock; /*!< SD locking object */ - - uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ - + + uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + uint32_t TxXferSize; /*!< SD Tx Transfer size */ - - uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ - + + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + uint32_t RxXferSize; /*!< SD Rx Transfer size */ - + __IO uint32_t Context; /*!< SD transfer context */ - + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ - - __IO uint32_t ErrorCode; /*!< SD Card Error codes */ - + + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ - + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ - + #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ - + uint32_t CSD[4]; /*!< SD card specific data table */ - + uint32_t CID[4]; /*!< SD card identification number table */ - + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); + + void (* DriveTransceiver_1_8V_Callback) (FlagStatus status); +#endif + + void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ }SD_HandleTypeDef; -/** +/** * @} */ -/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register +/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register * @{ - */ + */ typedef struct { __IO uint8_t CSDStruct; /*!< CSD structure */ @@ -208,7 +213,7 @@ typedef struct __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ __IO uint8_t Reserved3; /*!< Reserved */ __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t FileFormatGroup; /*!< File format group */ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ __IO uint8_t PermWrProtect; /*!< Permanent write protection */ __IO uint8_t TempWrProtect; /*!< Temporary write protection */ @@ -216,9 +221,8 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ - -}HAL_SD_CardCSDTypedef; -/** +}HAL_SD_CardCSDTypeDef; +/** * @} */ @@ -238,12 +242,12 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_SD_CardCIDTypedef; -/** +}HAL_SD_CardCIDTypeDef; +/** * @} */ -/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 +/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 * @{ */ typedef struct @@ -258,77 +262,119 @@ typedef struct __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ - -}HAL_SD_CardStatusTypedef; -/** +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */ + __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */ + __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */ +#endif +}HAL_SD_CardStatusTypeDef; +/** * @} */ -/** +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ + HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ + HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ + HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */ + HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */ + HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */ + HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */ +#endif + + HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ + HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ +}HAL_SD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition + * @{ + */ +typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); +#endif +/** + * @} + */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** * @} */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants Exported Constants +/** @defgroup SD_Exported_Constants Exported Constants * @{ */ #define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ -/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition +/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition * @{ - */ -#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ -#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ -#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ -#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ - -/** + */ +#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** * @} */ /** @defgroup SD_Exported_Constansts_Group2 SD context enumeration * @{ - */ -#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ -#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ -#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ -#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ -#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ -#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ -#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ + */ +#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ /** * @} @@ -338,16 +384,16 @@ typedef struct * @{ */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ -#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ -#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards - and <104Mo/s for SDR104, Spec version 3.01 */ +#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ +#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ +#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards + and <104Mo/s for SDR104, Spec version 3.01 */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#define CARD_SDSC ((uint32_t)0x00000000U) -#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) +#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */ +#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ #define CARD_SECURED ((uint32_t)0x00000003U) - + /** * @} */ @@ -364,18 +410,31 @@ typedef struct /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup SD_Exported_macros SD Exported Macros * @brief macros to handle interrupts and specific clock configurations * @{ */ - +/** @brief Reset SD handle state. + * @param __HANDLE__ : SD handle. + * @retval None + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief Enable the SD device. * @retval None - */ + */ #define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) /** @@ -387,7 +446,7 @@ typedef struct /** * @brief Enable the SDMMC DMA transfer. * @retval None - */ + */ #define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) /** @@ -396,201 +455,192 @@ typedef struct */ #define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - + /** * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle + * @param __HANDLE__: SD Handle * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @retval None */ #define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle + * @param __HANDLE__: SD Handle * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @retval None */ #define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** - * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. + * @brief Check whether the specified SD flag is set or not. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_CMDACT: Command transfer in progress - * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full - * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 - * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure * @arg SDMMC_FLAG_IDMATE: IDMA transfer error * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDMMC_FLAG_TXACT: Data transmit in progress - * @arg SDMMC_FLAG_RXACT: Data receive in progress - * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO * @retval The new state of SD FLAG (SET or RESET). */ #define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to clear. * This parameter can be one or a combination of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure * @arg SDMMC_FLAG_IDMATE: IDMA transfer error * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) * @retval None */ #define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt - * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt - * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt - * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy) + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @retval The new state of SD IT (SET or RESET). */ #define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -598,29 +648,27 @@ typedef struct /** * @brief Clear the SD's interrupt pending bits. * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt * @retval None */ #define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -628,16 +676,17 @@ typedef struct /** * @} */ - + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Include SD HAL Extension module */ #include "stm32l4xx_hal_sd_ex.h" #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup SD_Exported_Functions SD Exported Functions * @{ */ - + /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -649,7 +698,7 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /** * @} */ - + /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions * @{ */ @@ -672,26 +721,38 @@ void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd); void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd); void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd); +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/* SD callback registering/unregistering */ +HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd); +#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + /** * @} */ - + /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions * @{ */ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); +HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode); /** * @} */ - + /** @defgroup SD_Exported_Functions_Group4 SD card related functions * @{ */ HAL_StatusTypeDef HAL_SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -HAL_SD_CardStateTypedef HAL_SD_GetCardState (SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID); -HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD); -HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus); +HAL_SD_CardStateTypeDef HAL_SD_GetCardState (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} @@ -705,7 +766,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); /** * @} */ - + /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management * @{ */ @@ -714,7 +775,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ - + /* Private types -------------------------------------------------------------*/ /** @defgroup SD_Private_Types SD Private Types * @{ @@ -722,7 +783,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} - */ + */ /* Private defines -----------------------------------------------------------*/ /** @defgroup SD_Private_Defines SD Private Defines @@ -731,8 +792,8 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} - */ - + */ + /* Private variables ---------------------------------------------------------*/ /** @defgroup SD_Private_Variables SD Private Variables * @{ @@ -740,7 +801,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup SD_Private_Constants SD Private Constants @@ -749,7 +810,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup SD_Private_Macros SD Private Macros @@ -781,11 +842,11 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} - */ + */ /** * @} - */ + */ /** * @} @@ -798,6 +859,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); #endif -#endif /* __STM32L4xx_HAL_SD_H */ +#endif /* STM32L4xx_HAL_SD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c index 4ee5298889..e693509461 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c @@ -3,10 +3,10 @@ * @file stm32l4xx_hal_sd_ex.c * @author MCD Application Team * @brief SD card Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: * + Extended features functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,37 +16,21 @@ (+) Set card in High Speed mode using HAL_SDEx_HighSpeed() function. (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. - + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -58,9 +42,9 @@ */ /** @defgroup SDEx SDEx - * @brief SD HAL extended module driver + * @brief SD Extended HAL module driver * @{ - */ + */ #ifdef HAL_SD_MODULE_ENABLED @@ -70,21 +54,22 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +extern uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd); /* Exported functions --------------------------------------------------------*/ /** @addtogroup SDEx_Exported_Functions * @{ */ /** @addtogroup SDEx_Exported_Functions_Group1 - * @brief High Speed function + * @brief High Speed function * -@verbatim +@verbatim ============================================================================== ##### High Speed function ##### ============================================================================== - [..] + [..] This section provides function allowing to configure the card in High Speed mode. - + @endverbatim * @{ */ @@ -92,129 +77,18 @@ /** * @brief Switches the SD card to High Speed mode. * This API must be used after "Transfer State" - * @note This operation should be followed by the configuration + * @note This operation should be followed by the configuration * of PLL to have SDMMCCK clock between 50 and 120 MHz * @param hsd: SD handle * @retval SD Card error state */ uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_OK; - SDMMC_DataInitTypeDef sdmmc_datainitstructure; - uint8_t SD_hs[64] = {0}; - uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; - uint32_t Timeout = HAL_GetTick(); - - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) - { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; - } - - if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) && - (hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE)) - { - /* Initialize the Data control register */ - hsd->Instance->DCTRL = 0; - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); - - if (errorstate != HAL_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; - sdmmc_datainitstructure.DataLength = 64; - sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; - sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - - errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); - if(errorstate != HAL_OK) - { - return errorstate; - } - - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) - { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } - } - - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - errorstate = 0; - - return errorstate; - } - else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - errorstate = SDMMC_ERROR_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - errorstate = SDMMC_ERROR_RX_OVERRUN; - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - /* Test if the switch mode HS is ok */ - if ((SD_hs[13]& 2) != 2) - { - errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; - } - else - { - HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->State = HAL_SD_STATE_READY; - hsd->ErrorCode |= errorstate; - return HAL_ERROR; - } - } - - return errorstate; + return SD_HighSpeed (hsd); } /** - * @brief Enable/Disable the SD Transciver 1.8V Mode Callback. + * @brief Enable/Disable the SD Transceiver 1.8V Mode Callback. * @param status: Voltage Switch State * @retval None */ @@ -222,7 +96,7 @@ __weak void HAL_SDEx_DriveTransceiver_1_8V_Callback(FlagStatus status) { /* Prevent unused argument(s) compilation warning */ UNUSED(status); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_EnableTransciver could be implemented in the user file */ @@ -231,18 +105,18 @@ __weak void HAL_SDEx_DriveTransceiver_1_8V_Callback(FlagStatus status) /** * @} */ - + /** @addtogroup SDEx_Exported_Functions_Group2 - * @brief Multibuffer functions + * @brief Multibuffer functions * -@verbatim +@verbatim ============================================================================== ##### Multibuffer functions ##### ============================================================================== - [..] - This section provides functions allowing to configure the multibuffer mode and start read and write + [..] + This section provides functions allowing to configure the multibuffer mode and start read and write multibuffer mode for SD HAL driver. - + @endverbatim * @{ */ @@ -259,10 +133,10 @@ HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t { if(hsd->State == HAL_SD_STATE_READY) { - hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0; - hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1; - hsd->Instance->IDMABSIZE = (uint32_t) (BLOCKSIZE * BufferSize); - + hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0; + hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1; + hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize); + return HAL_OK; } else @@ -270,184 +144,198 @@ HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t return HAL_BUSY; } } - + /** * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. * @param hsd: SD handle - * @param BlockAdd: Block Address from where data is to be read + * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t add = BlockAdd; + if(hsd->State == HAL_SD_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - - if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + + DmaBase0_reg = hsd->Instance->IDMABASE0; + DmaBase1_reg = hsd->Instance->IDMABASE1; + if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) { hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + /* Initialize data control register */ hsd->Instance->DCTRL = 0; - + /* Clear old Flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_BUSY; if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } - - /* Configure the SD DPSM (Data Path State Machine) */ + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); - - hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; - -// /* Set Block Size for Card */ -// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); -// if(errorstate != HAL_SD_ERROR_NONE) -// { -// hsd->State = HAL_SD_STATE_READY; -// hsd->ErrorCode |= errorstate; -// return HAL_ERROR; -// } - - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); - - hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); - /* Read Blocks in DMA mode */ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - + /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); if(errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; return HAL_ERROR; } - + return HAL_OK; } else { return HAL_BUSY; } - + } /** * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1. * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. * @param hsd: SD handle - * @param BlockAdd: Block Address from where data is to be read + * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; - + uint32_t errorstate; + uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t add = BlockAdd; + if(hsd->State == HAL_SD_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - - if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + + DmaBase0_reg = hsd->Instance->IDMABASE0; + DmaBase1_reg = hsd->Instance->IDMABASE1; + if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) { hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } - + /* Initialize data control register */ hsd->Instance->DCTRL = 0; - + hsd->ErrorCode = HAL_SD_ERROR_NONE; - + hsd->State = HAL_SD_STATE_BUSY; if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } - - /* Configure the SD DPSM (Data Path State Machine) */ + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; - SDMMC_ConfigData(hsd->Instance, &config); - -// /* Set Block Size for Card */ -// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); -// if(errorstate != HAL_SD_ERROR_NONE) -// { -// hsd->State = HAL_SD_STATE_READY; -// hsd->ErrorCode |= errorstate; -// return HAL_ERROR; -// } - + (void)SDMMC_ConfigData(hsd->Instance, &config); + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); - - hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; - + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); - + /* Write Blocks in DMA mode */ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - + /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); if(errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; return HAL_ERROR; } - + return HAL_OK; } else { return HAL_BUSY; - } + } } - + /** * @brief Change the DMA Buffer0 or Buffer1 address on the fly. * @param hsd: pointer to a SD_HandleTypeDef structure. - * @param Buffer: the buffer to be changed, This parameter can be one of + * @param Buffer: the buffer to be changed, This parameter can be one of * the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1 * @param pDataBuffer: The new address * @note The BUFFER0 address can be changed only when the current transfer use - * BUFFER1 and the BUFFER1 address can be changed only when the current + * BUFFER1 and the BUFFER1 address can be changed only when the current * transfer use BUFFER0. * @retval HAL status */ @@ -463,7 +351,7 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu /* change the memory1 address */ hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer; } - + return HAL_OK; } @@ -476,7 +364,7 @@ __weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file */ @@ -491,7 +379,7 @@ __weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file */ @@ -506,7 +394,7 @@ __weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file */ @@ -521,7 +409,7 @@ __weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h index a187e6143b..5fff321d1c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SD_EX_H -#define __STM32L4xx_HAL_SD_EX_H +#ifndef STM32L4xx_HAL_SD_EX_H +#define STM32L4xx_HAL_SD_EX_H #ifdef __cplusplus extern "C" { @@ -51,6 +35,7 @@ */ /** @addtogroup SDEx + * @brief SD HAL extended module driver * @{ */ @@ -61,7 +46,7 @@ /** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure * @{ - */ + */ typedef enum { SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */ @@ -70,20 +55,20 @@ typedef enum }HAL_SDEx_DMABuffer_MemoryTypeDef; -/** +/** * @} */ - -/** + +/** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup SDEx_Exported_Functions SDEx Exported Functions * @{ */ - + /** @defgroup SDEx_Exported_Functions_Group1 HighSpeed functions * @{ */ @@ -111,11 +96,11 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); /** * @} */ - + /** * @} */ - + /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -123,7 +108,7 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ - + /** * @} */ @@ -139,6 +124,6 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); #endif -#endif /* __STM32L4xx_HAL_SDEx_H */ +#endif /* STM32L4xx_HAL_SDEx_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c index af7665a3d5..436e782471 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c @@ -26,8 +26,8 @@ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. @@ -99,33 +99,82 @@ [..] (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + + [..] + By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() + and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() + or @ref HAL_SMARTCARD_Init() function. + + [..] + When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -147,9 +196,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ + * @{ + */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #if defined(USART_CR1_FIFOEN) #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ @@ -158,7 +207,7 @@ #else #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#endif +#endif /* USART_CR1_FIFOEN */ #define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ @@ -170,7 +219,7 @@ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ #else #define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ -#endif +#endif /* USART_CR1_FIFOEN */ #define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ @@ -181,24 +230,18 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup SMARTCARD_Private_Variables SMARTCARD Private Variables - * @{ - */ -static const uint16_t SMARTCARDPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SMARTCARD_Private_Functions * @{ */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -212,12 +255,12 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); #if defined(USART_CR1_FIFOEN) static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); -#endif +#endif /* USART_CR1_FIFOEN */ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard); #if defined(USART_CR1_FIFOEN) static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -229,7 +272,7 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); */ /** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim ============================================================================== @@ -266,27 +309,27 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); The USART frame format is given in the following table: Table 1. USART frame format. - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 01 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ * @{ */ /** - * @brief Initialize the SMARTCARD mode according to the specified + * @brief Initialize the SMARTCARD mode according to the specified * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check the SMARTCARD handle allocation */ - if(hsmartcard == NULL) + if (hsmartcard == NULL) { return HAL_ERROR; } @@ -294,13 +337,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) /* Check the USART associated to the SMARTCARD handle */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmartcard->Lock = HAL_UNLOCKED; +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + SMARTCARD_InitCallbacksToDefault(hsmartcard); + + if (hsmartcard->MspInitCallback == NULL) + { + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + } + + /* Init the low level hardware */ + hsmartcard->MspInitCallback(hsmartcard); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_SMARTCARD_MspInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ } hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; @@ -322,8 +377,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) { return HAL_ERROR; } - - /* Set the SMARTCARD transmission completion indication */ + + /* Set the SMARTCARD transmission completion indication */ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard); if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) @@ -339,15 +394,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check the SMARTCARD handle allocation */ - if(hsmartcard == NULL) + if (hsmartcard == NULL) { return HAL_ERROR; } @@ -360,14 +415,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the Peripheral */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - WRITE_REG(hsmartcard->Instance->CR1, 0x0); - WRITE_REG(hsmartcard->Instance->CR2, 0x0); - WRITE_REG(hsmartcard->Instance->CR3, 0x0); - WRITE_REG(hsmartcard->Instance->RTOR, 0x0); - WRITE_REG(hsmartcard->Instance->GTPR, 0x0); + WRITE_REG(hsmartcard->Instance->CR1, 0x0U); + WRITE_REG(hsmartcard->Instance->CR2, 0x0U); + WRITE_REG(hsmartcard->Instance->CR3, 0x0U); + WRITE_REG(hsmartcard->Instance->RTOR, 0x0U); + WRITE_REG(hsmartcard->Instance->GTPR, 0x0U); /* DeInit the low level hardware */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + if (hsmartcard->MspDeInitCallback == NULL) + { + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + } + /* DeInit the low level hardware */ + hsmartcard->MspDeInitCallback(hsmartcard); +#else HAL_SMARTCARD_MspDeInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; @@ -380,43 +444,288 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief Initialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspInit can be implemented in the user file */ } /** - * @brief DeInitialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMARTCARD Callback + * To be used instead of the weak predefined callback + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hsmartcard); + + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + switch (CallbackID) + { + + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = pCallback; + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = pCallback; + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = pCallback; + break; +#endif /* USART_CR1_FIFOEN */ + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmartcard); + + return status; +} + +/** + * @brief Unregister an SMARTCARD callback + * SMARTCARD callback is redirected to the weak predefined callback + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsmartcard); + + if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; +#endif /* USART_CR1_FIFOEN */ + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmartcard); + + return status; +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions + * @brief SMARTCARD Transmit and Receive functions * @verbatim ============================================================================== @@ -480,7 +789,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. @@ -494,26 +803,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ /** - * @brief Send an amount of data in blocking mode. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one - * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and - * TXE are mapped on the same bit-field. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in blocking mode. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; + uint8_t *ptmpdata = pData; /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((ptmpdata == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -523,7 +834,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable the Peripheral first to update mode for TX master */ @@ -531,9 +842,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable Rx, enable Tx */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - + /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -541,21 +852,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - while(hsmartcard->TxXferCount > 0) + while (hsmartcard->TxXferCount > 0U) { hsmartcard->TxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); + ptmpdata++; } - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, + Timeout) != HAL_OK) { return HAL_TIMEOUT; } /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) { /* Disable the Peripheral first to update modes */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -563,7 +876,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); } - + /* At end of Tx process, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -579,26 +892,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui } /** - * @brief Receive an amount of data in blocking mode. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and - * RXNE are mapped on the same bit-field. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in blocking mode. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart; + uint8_t *ptmpdata = pData; /* Check that a Rx process is not already ongoing */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((ptmpdata == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -609,22 +924,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; /* Check the remain data to be received */ - while(hsmartcard->RxXferCount > 0) + while (hsmartcard->RxXferCount > 0U) { hsmartcard->RxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + ptmpdata++; } /* At end of Rx process, restore hsmartcard->RxState to Ready */ @@ -642,16 +958,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin } /** - * @brief Send an amount of data in interrupt mode. - * @note When FIFO mode is disabled, USART interrupt is generated whenever - * USART_TDR register is empty, i.e one interrupt per data to transmit. - * @note When FIFO mode is enabled, USART interrupt is generated whenever - * TXFIFO threshold reached. In that case the interrupt rate depends on - * TXFIFO threshold configuration. - * @note This function sets the hsmartcard->TxIsr function pointer according to - * the FIFO mode (data transmission processing depends on FIFO mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -661,69 +977,77 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - + hsmartcard->pTxBuffPtr = pData; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; - + /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - + /* Disable Rx, enable Tx */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - + /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - -#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ +#if defined(USART_CR1_FIFOEN) if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) - { + { /* Set the Tx ISR function pointer */ hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + /* Enable the TX FIFO threshold interrupt */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); } else -#endif { /* Set the Tx ISR function pointer */ hsmartcard->TxISR = SMARTCARD_TxISR; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); -#endif } - +#else + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); +#endif /* USART_CR1_FIFOEN */ + return HAL_OK; } else @@ -733,16 +1057,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Receive an amount of data in interrupt mode. - * @note When FIFO mode is disabled, USART interrupt is generated whenever - * USART_RDR register can be read, i.e one interrupt per data to receive. - * @note When FIFO mode is enabled, USART interrupt is generated whenever - * RXFIFO threshold reached. In that case the interrupt rate depends on - * RXFIFO threshold configuration. - * @note This function sets the hsmartcard->RxIsr function pointer according to - * the FIFO mode (data reception processing depends on FIFO mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @retval HAL status @@ -750,9 +1074,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -770,34 +1094,39 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Configure Rx interrupt processing */ #if defined(USART_CR1_FIFOEN) if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) - { + { /* Set the Rx ISR function pointer */ hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); } else -#endif { /* Set the Rx ISR function pointer */ hsmartcard->RxISR = SMARTCARD_RxISR; /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ -#if defined(USART_CR1_FIFOEN) - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); -#else - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); -#endif + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); } - +#else + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif /* USART_CR1_FIFOEN */ + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -810,9 +1139,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Send an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -822,7 +1151,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -842,9 +1171,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Disable Rx, enable Tx */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - + /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -858,22 +1187,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA channel */ - HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size); + if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, + Size) == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); - /* Clear the TC flag in the ICR register */ - CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Enable the UART Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - /* Enable the UART Error Interrupt: (Frame error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } } else { @@ -882,9 +1226,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard } /** - * @brief Receive an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), @@ -894,9 +1238,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -920,22 +1264,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size); + if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, + Size) == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } } else { @@ -946,8 +1305,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, /** * @brief Abort ongoing transfers (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -958,14 +1317,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) @@ -973,13 +1336,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmatx); + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } @@ -989,22 +1361,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmarx); + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Tx and Rx transfer counters */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1019,8 +1402,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1038,10 +1421,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar #else /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -1053,18 +1436,27 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmatx); + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); @@ -1078,8 +1470,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /** * @brief Abort ongoing Receive transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1098,10 +1490,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -1113,21 +1505,32 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback to Null. + /* Set the SMARTCARD DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(hsmartcard->hdmarx); + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0; + hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1138,8 +1541,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Abort ongoing transfers (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1152,26 +1555,29 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard */ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t abortcplt = 1; - + uint32_t abortcplt = 1U; + #if defined(USART_CR1_FIFOEN) /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; } @@ -1181,11 +1587,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) } } /* DMA Rx Handle is valid */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; } @@ -1196,25 +1602,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) } /* Disable the SMARTCARD DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* SMARTCARD Tx DMA Abort callback has already been initialised : + /* SMARTCARD Tx DMA Abort callback has already been initialised : will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { hsmartcard->hdmatx->XferAbortCallback = NULL; } else { - abortcplt = 0; + abortcplt = 0U; } } } @@ -1225,30 +1631,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* SMARTCARD Rx DMA Abort callback has already been initialised : + /* SMARTCARD Rx DMA Abort callback has already been initialised : will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { hsmartcard->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Clear ISR function pointers */ hsmartcard->RxISR = NULL; @@ -1258,14 +1664,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } return HAL_OK; @@ -1274,8 +1688,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1295,10 +1709,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart #else /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -1310,14 +1724,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback : + /* Set the SMARTCARD DMA Abort callback : will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); @@ -1326,7 +1740,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart else { /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Clear TxISR function pointers */ hsmartcard->TxISR = NULL; @@ -1335,25 +1749,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0; - + hsmartcard->TxXferCount = 0U; + /* Clear TxISR function pointers */ hsmartcard->TxISR = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - + /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } return HAL_OK; @@ -1362,8 +1788,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /** * @brief Abort ongoing Receive transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1373,7 +1799,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { #if defined(USART_CR1_FIFOEN) @@ -1384,29 +1810,29 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); @@ -1415,46 +1841,62 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc else { /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0; - + hsmartcard->RxXferCount = 0U; + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0; - + hsmartcard->RxXferCount = 0U; + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } - + return HAL_OK; } /** - * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Handle SMARTCARD interrupt requests. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1463,129 +1905,137 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); uint32_t errorflags; - + uint32_t errorcode; + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == RESET) + if (errorflags == 0U) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } return; } - } - + } + /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) #else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) -#endif + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) +#endif /* USART_CR1_FIFOEN */ { /* SMARTCARD parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; } - + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; } - + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET) - || ((cr3its & USART_CR3_EIE) != RESET)) ) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) #else - if( ((isrflags & USART_ISR_ORE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE) != RESET) - || ((cr3its & USART_CR3_EIE) != RESET)) ) -#endif + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) +#endif /* USART_CR1_FIFOEN */ { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } - + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; } - + /* Call SMARTCARD Error Call back function if need be --------------------------*/ - if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET) ) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } } - + /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception */ - if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET) - || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) - { + errorcode = hsmartcard->ErrorCode; + if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) + { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ SMARTCARD_EndRxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); @@ -1593,41 +2043,51 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } /* other error type to be considered as blocking : - - Frame error in Transmission + - Frame error in Transmission */ - else if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) + else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U)) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ SMARTCARD_EndTxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - + /* Abort the SMARTCARD DMA Tx channel */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); @@ -1635,122 +2095,161 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { - /* Call user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ - if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) + if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U)) { hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; __HAL_UNLOCK(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + to be available during HAL_SMARTCARD_RxCpltCallback() processing */ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); return; } - + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (hsmartcard->TxISR != NULL) {hsmartcard->TxISR(hsmartcard);} + if (hsmartcard->TxISR != NULL) + { + hsmartcard->TxISR(hsmartcard); + } return; } - + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if( (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) - && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) + if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { - SMARTCARD_EndTransmit_IT(hsmartcard); - return; + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; + } } - + #if defined(USART_CR1_FIFOEN) /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + hsmartcard->TxFifoEmptyCallback(hsmartcard); +#else + /* Call legacy weak Tx Fifo Empty Callback */ HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ return; } - + /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + hsmartcard->RxFifoFullCallback(hsmartcard); +#else + /* Call legacy weak Rx Fifo Full Callback */ HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ return; } -#endif +#endif /* USART_CR1_FIFOEN */ } /** - * @brief Tx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. */ } /** - * @brief SMARTCARD error callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. */ @@ -1759,10 +2258,10 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -1775,10 +2274,10 @@ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -1791,10 +2290,10 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs /** * @brief SMARTCARD Abort Receive Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -1809,7 +2308,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm */ /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions + * @brief SMARTCARD State and Errors functions * @verbatim ============================================================================== @@ -1829,26 +2328,27 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm /** * @brief Return the SMARTCARD handle state. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ - uint32_t temp1= 0x00, temp2 = 0x00; - temp1 = hsmartcard->gState; - temp2 = hsmartcard->RxState; - + uint32_t temp1; + uint32_t temp2; + temp1 = (uint32_t)hsmartcard->gState; + temp2 = (uint32_t)hsmartcard->RxState; + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } /** * @brief Return the SMARTCARD handle error code. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. -* @retval SMARTCARD handle Error Code -*/ + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle Error Code + */ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) { return hsmartcard->ErrorCode; @@ -1862,21 +2362,47 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions * @{ */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** - * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initialize the callbacks to their default values. + * @param hsmartcard SMARTCARD handle. + * @retval none + */ +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Init the SMARTCARD Callback settings */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ +#if defined(USART_CR1_FIFOEN) + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif /* USART_CR1_FIFOEN */ + +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief Configure the SMARTCARD associated USART peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpreg = 0x00000000; - SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; + uint32_t tmpreg; + SMARTCARD_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; +#if defined(USART_PRESC_PRESCALER) + const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +#endif /* USART_PRESC_PRESCALER */ /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); @@ -1894,7 +2420,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler)); -#endif +#endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART CR1 Configuration -----------------------*/ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). @@ -1902,7 +2428,12 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); +#if defined(USART_CR1_FIFOEN) + tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; + tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode; +#else + tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); +#endif /* USART_CR1_FIFOEN */ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -1919,8 +2450,9 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * according to hsmartcard->Init.OneBitSampling * - NACK transmission in case of parity error according * to hsmartcard->Init.NACKEnable - * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ - tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; + * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ + + tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); @@ -1929,67 +2461,66 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /* Configure * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */ MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler); -#endif +#endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART GTPR Configuration ----------------------*/ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); - MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); + MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg); + MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); - tmpreg = 0; + tmpreg = 0U; switch (clocksource) { - case SMARTCARD_CLOCKSOURCE_PCLK1: + case SMARTCARD_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); -#endif - break; - case SMARTCARD_CLOCKSOURCE_PCLK2: + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); +#endif /* USART_PRESC_PRESCALER */ + break; + case SMARTCARD_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); -#endif - break; - case SMARTCARD_CLOCKSOURCE_HSI: + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); +#endif /* USART_PRESC_PRESCALER */ + break; + case SMARTCARD_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HSI_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); -#endif - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: + tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); +#endif /* USART_PRESC_PRESCALER */ + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); -#endif - break; - case SMARTCARD_CLOCKSOURCE_LSE: + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); +#endif /* USART_PRESC_PRESCALER */ + break; + case SMARTCARD_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - tmpreg = (uint16_t)((LSE_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); #else - tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); -#endif - break; - case SMARTCARD_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); +#endif /* USART_PRESC_PRESCALER */ + break; + default: + ret = HAL_ERROR; + break; } - + /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { @@ -1999,12 +2530,12 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { ret = HAL_ERROR; } - + #if defined(USART_CR1_FIFOEN) /* Initialize the number of data to process during RX/TX ISR execution */ - hsmartcard->NbTxDataToProcess = 1; - hsmartcard->NbRxDataToProcess = 1; -#endif + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; +#endif /* USART_CR1_FIFOEN */ /* Clear ISR function pointers */ hsmartcard->RxISR = NULL; @@ -2084,29 +2615,31 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) */ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Initialize the SMARTCARD ErrorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2133,27 +2666,28 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) + while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); #else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); return HAL_TIMEOUT; @@ -2167,7 +2701,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2177,7 +2711,7 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); #else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* At end of Tx process, restore hsmartcard->gState to Ready */ @@ -2188,7 +2722,7 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2198,7 +2732,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore hsmartcard->RxState to Ready */ @@ -2207,15 +2741,15 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** - * @brief DMA SMARTCARD transmit process complete callback. + * @brief DMA SMARTCARD transmit process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); - hsmartcard->TxXferCount = 0; + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ @@ -2226,15 +2760,15 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SMARTCARD receive process complete callback. + * @brief DMA SMARTCARD receive process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); - hsmartcard->RxXferCount = 0; + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); @@ -2247,7 +2781,13 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2258,26 +2798,36 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); /* Stop SMARTCARD DMA Tx request if ongoing */ - if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) ) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - hsmartcard->TxXferCount = 0; - SMARTCARD_EndTxTransfer(hsmartcard); + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->TxXferCount = 0U; + SMARTCARD_EndTxTransfer(hsmartcard); + } } /* Stop SMARTCARD DMA Rx request if ongoing */ - if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) ) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - hsmartcard->RxXferCount = 0; - SMARTCARD_EndRxTransfer(hsmartcard); + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->RxXferCount = 0U; + SMARTCARD_EndRxTransfer(hsmartcard); + } } hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2288,11 +2838,17 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); - hsmartcard->RxXferCount = 0; - hsmartcard->TxXferCount = 0; + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + hsmartcard->TxXferCount = 0U; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2305,35 +2861,42 @@ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); - + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->hdmatx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hsmartcard->hdmarx != NULL) + if (hsmartcard->hdmarx != NULL) { - if(hsmartcard->hdmarx->XferAbortCallback != NULL) + if (hsmartcard->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Reset errorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } @@ -2347,35 +2910,42 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(hsmartcard->hdmatx != NULL) + if (hsmartcard->hdmatx != NULL) { - if(hsmartcard->hdmatx->XferAbortCallback != NULL) + if (hsmartcard->hdmatx->XferAbortCallback != NULL) { return; } } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hsmartcard->TxXferCount = 0; - hsmartcard->RxXferCount = 0; + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; /* Reset errorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } @@ -2389,9 +2959,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->TxXferCount = 0; + hsmartcard->TxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); @@ -2399,8 +2969,13 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** @@ -2413,27 +2988,34 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent); + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->RxXferCount = 0; + hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - /* Call user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** - * @brief Send an amount of data in non-blocking mode. + * @brief Send an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() * and when the FIFO mode is disabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2441,21 +3023,22 @@ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(hsmartcard->TxXferCount == 0) + if (hsmartcard->TxXferCount == 0U) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } else { - hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; hsmartcard->TxXferCount--; } } @@ -2463,45 +3046,50 @@ static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) #if defined(USART_CR1_FIFOEN) /** - * @brief Send an amount of data in non-blocking mode. + * @brief Send an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() * and when the FIFO mode is enabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) { - uint8_t nb_tx_data; + uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - for(nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(hsmartcard->TxXferCount == 0) + for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (hsmartcard->TxXferCount == 0U) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); - + /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } - else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; hsmartcard->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Wrap up transmission in non-blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2510,14 +3098,14 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) { /* Disable the Peripheral first to update modes */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -2532,16 +3120,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear TxISR function pointer */ hsmartcard->TxISR = NULL; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hsmartcard->TxCpltCallback(hsmartcard); +#else + /* Call legacy weak Tx complete callback */ HAL_SMARTCARD_TxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() * and when the FIFO mode is disabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) @@ -2549,32 +3143,40 @@ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - - if(--hsmartcard->RxXferCount == 0) + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; + + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) { #if defined(USART_CR1_FIFOEN) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); #else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE); -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD Parity Error Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } else @@ -2586,60 +3188,70 @@ static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) #if defined(USART_CR1_FIFOEN) /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() * and when the FIFO mode is enabled. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) { - uint8_t nb_rx_data; - + uint16_t nb_rx_data; + uint16_t rxdatacount; + /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - for(nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - - if(--hsmartcard->RxXferCount == 0) + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; + + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) { CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD Parity Error Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Clear RxISR function pointer */ hsmartcard->RxISR = NULL; - + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((hsmartcard->RxXferCount != 0U)) && (hsmartcard->RxXferCount < hsmartcard->NbRxDataToProcess)) + rxdatacount = hsmartcard->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ hsmartcard->RxISR = SMARTCARD_RxISR; - + /* Enable the UART Data Register Not Empty interrupt */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } @@ -2650,8 +3262,8 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); } } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h index b6fe5b0436..7e49040ff2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SMARTCARD_H -#define __STM32L4xx_HAL_SMARTCARD_H +#ifndef STM32L4xx_HAL_SMARTCARD_H +#define STM32L4xx_HAL_SMARTCARD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -97,7 +81,7 @@ typedef struct deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied + This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -124,9 +108,9 @@ typedef struct #if defined(USART_PRESC_PRESCALER) uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */ -#endif -}SMARTCARD_InitTypeDef; +#endif /* USART_PRESC_PRESCALER */ +} SMARTCARD_InitTypeDef; /** * @brief SMARTCARD advanced features initalization structure definition @@ -158,31 +142,31 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ -}SMARTCARD_AdvFeatureInitTypeDef; + This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ +} SMARTCARD_AdvFeatureInitTypeDef; /** - * @brief HAL SMARTCARD State structures definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. - * - gState contains SMARTCARD state information related to global Handle management + * @brief HAL SMARTCARD State definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : - * b7-b6 Error information + * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (Peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -192,9 +176,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -203,40 +187,7 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -}HAL_SMARTCARD_StateTypeDef; - -/** - * @brief HAL SMARTCARD Error Code structure definition - */ -typedef enum -{ - HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ - HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ - HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ - HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ - HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */ -}HAL_SMARTCARD_ErrorTypeDef; +typedef uint32_t HAL_SMARTCARD_StateTypeDef; /** * @brief SMARTCARD handle Structure definition @@ -262,13 +213,13 @@ typedef struct __SMARTCARD_HandleTypeDef __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ #if defined(USART_CR1_FIFOEN) - uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ -#endif +#endif /* USART_CR1_FIFOEN */ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -280,29 +231,82 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ - uint32_t ErrorCode; /*!< SmartCard Error code */ + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ -}SMARTCARD_HandleTypeDef; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ + + void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */ + + void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */ + + void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */ + +#if defined(USART_CR1_FIFOEN) + void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */ + + void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */ + +#endif /* USART_CR1_FIFOEN */ + void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */ + + void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +} SMARTCARD_HandleTypeDef; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMARTCARD Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */ + HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */ + HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */ + HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */ + HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */ + HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */ +#if defined(USART_CR1_FIFOEN) + HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */ + HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */ +#endif /* USART_CR1_FIFOEN */ + + HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */ + HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */ + +} HAL_SMARTCARD_CallbackIDTypeDef; + +/** + * @brief HAL SMARTCARD Callback pointer definition + */ +typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */ + +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @brief SMARTCARD clock sources */ typedef enum { - SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ -}SMARTCARD_ClockSourceTypeDef; + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */ +} SMARTCARD_ClockSourceTypeDef; /** * @} @@ -313,6 +317,47 @@ typedef enum * @{ */ +/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition + * @{ + */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition + * @{ + */ +#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ @@ -328,8 +373,8 @@ typedef enum #define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ /** * @} - */ - + */ + /** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ @@ -385,7 +430,6 @@ typedef enum * @} */ - /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ @@ -407,7 +451,7 @@ typedef enum #if defined(USART_PRESC_PRESCALER) /** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler * @{ - */ + */ #define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -420,12 +464,11 @@ typedef enum #define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ - /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion * @{ */ @@ -501,7 +544,11 @@ typedef enum /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask * @{ */ -#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */ +#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */ +#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */ +#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */ /** * @} */ @@ -519,20 +566,29 @@ typedef enum * @param __HANDLE__ SMARTCARD handle. * @retval None */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - } while(0) + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** @brief Flush the Smartcard Data registers. * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0) +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -547,7 +603,9 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag +#if defined(USART_CR1_FIFOEN) * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag +#endif * @retval None */ #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -558,7 +616,6 @@ typedef enum */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) - /** @brief Clear the SMARTCARD FE pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None @@ -587,22 +644,22 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) + * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref SMARTCARD_FLAG_BUSY Busy flag * @arg @ref SMARTCARD_FLAG_EOBF End of block flag * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag - * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag - * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag - * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag + * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag * @arg @ref SMARTCARD_FLAG_NE Noise error flag * @arg @ref SMARTCARD_FLAG_FE Framing error flag * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag + * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag @@ -618,23 +675,23 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -643,24 +700,23 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) - +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -669,21 +725,22 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -692,24 +749,23 @@ typedef enum * @arg @ref SMARTCARD_IT_EOB End of block interrupt * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != RESET) ? SET : RESET) - +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -720,10 +776,10 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag - * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag * @retval None @@ -736,22 +792,22 @@ typedef enum * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request - * * @retval None */ #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None - */ + */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None - */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -774,13 +830,141 @@ typedef enum * @{ */ -/** @brief Check the Baud rate range. - * @note The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz) +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#if defined (STM32L432xx) || defined (STM32L442xx) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#else +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#endif /* STM32L432xx || STM32L442xx */ + +/** @brief Check the Baud rate range. + * @note The maximum Baud Rate is derived from the maximum clock on L4 (120 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001) +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 7500001U) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. @@ -789,149 +973,108 @@ typedef enum */ #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) -/** @brief Check the receiver timeout value. +/** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) -/** @brief Check the SMARTCARD autoretry counter value. +/** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. * @param __COUNT__ number of retransmissions. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) -/** - * @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__ SMARTCARD frame length. +/** @brief Ensure that SMARTCARD frame length is valid. + * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ + */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) -/** - * @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__ SMARTCARD frame number of stop bits. +/** @brief Ensure that SMARTCARD frame number of stop bits is valid. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ + */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) -/** - * @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__ SMARTCARD frame parity. +/** @brief Ensure that SMARTCARD frame parity is valid. + * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ ((__PARITY__) == SMARTCARD_PARITY_ODD)) -/** - * @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__ SMARTCARD communication mode. +/** @brief Ensure that SMARTCARD communication mode is valid. + * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__ SMARTCARD frame polarity. +/** @brief Ensure that SMARTCARD frame polarity is valid. + * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) - */ -#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) + */ +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) -/** - * @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__ SMARTCARD frame phase. +/** @brief Ensure that SMARTCARD frame phase is valid. + * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) -/** - * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. +/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__ SMARTCARD frame sampling. +/** @brief Ensure that SMARTCARD frame sampling is valid. + * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) -/** - * @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__ SMARTCARD NACK transmission setting. +/** @brief Ensure that SMARTCARD NACK transmission setting is valid. + * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ ((__NACK__) == SMARTCARD_NACK_DISABLE)) -/** - * @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__ SMARTCARD receiver timeout setting. +/** @brief Ensure that SMARTCARD receiver timeout setting is valid. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) -/** - * @brief Ensure that SMARTCARD clock Prescaler is valid. - * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. +#if defined(USART_PRESC_PRESCALER) +/** @brief Ensure that SMARTCARD clock Prescaler is valid. + * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ -#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) -/** - * @brief Ensure that SMARTCARD FIFO mode is valid. - * @param __STATE__ SMARTCARD FIFO mode. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ - ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) - -/** - * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. - * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. - * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__ SMARTCARD advanced features initialization. +#endif /* USART_PRESC_PRESCALER */ +/** @brief Ensure that SMARTCARD advanced features initialization is valid. + * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ @@ -943,65 +1086,57 @@ typedef enum SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) -/** - * @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__ SMARTCARD frame TX inversion setting. +/** @brief Ensure that SMARTCARD frame TX inversion setting is valid. + * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__ SMARTCARD frame RX inversion setting. +/** @brief Ensure that SMARTCARD frame RX inversion setting is valid. + * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__ SMARTCARD frame data inversion setting. +/** @brief Ensure that SMARTCARD frame data inversion setting is valid. + * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. +/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) -/** - * @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__ SMARTCARD frame overrun setting. +/** @brief Ensure that SMARTCARD frame overrun setting is valid. + * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) -/** - * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. +/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) -/** - * @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__ SMARTCARD frame MSB first setting. +/** @brief Ensure that SMARTCARD frame MSB first setting is valid. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) -/** - * @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__ SMARTCARD request parameter. +/** @brief Ensure that SMARTCARD request parameter is valid. + * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ @@ -1014,7 +1149,6 @@ typedef enum /* Include SMARTCARD HAL Extended module */ #include "stm32l4xx_hal_smartcard_ex.h" - /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMARTCARD_Exported_Functions * @{ @@ -1030,6 +1164,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + /** * @} */ @@ -1039,8 +1181,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); @@ -1057,15 +1201,14 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); /** * @} */ -/* Peripheral Control functions ***********************************************/ /* Peripheral State and Error functions ***************************************/ /** @addtogroup SMARTCARD_Exported_Functions_Group4 * @{ @@ -1094,6 +1237,6 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmar } #endif -#endif /* __STM32L4xx_HAL_SMARTCARD_H */ +#endif /* STM32L4xx_HAL_SMARTCARD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c index 6f17643d67..8f6ca31e90 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c @@ -8,7 +8,6 @@ * + Initialization and de-initialization functions * + Peripheral Control functions * - * @verbatim ============================================================================= ##### SMARTCARD peripheral extended features ##### @@ -20,35 +19,23 @@ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut, auto-retry counter,...) in the hsmartcard AdvancedInit structure. + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -68,72 +55,25 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U + /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if defined(USART_CR1_FIFOEN) static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); -#endif +#endif /* USART_CR1_FIFOEN */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions * @{ */ -/** @defgroup SMARTCARDEx_Exported_Functions_Group2 IO operation functions - * @brief Extended SMARTCARD Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of FIFO mode related callback functions. - - (#) TX/RX Fifos Callbacks: - (+) HAL_SMARTCARDEx_RxFifoFullCallback() - (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() - -@endverbatim - * @{ - */ - -#if defined(USART_CR1_FIFOEN) -/** - * @brief SMARTCARD RX Fifo full callback. - * @param hsmartcard SMARTCARD handle. - * @retval None - */ -__weak void HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. - */ -} - -/** - * @brief SMARTCARD TX Fifo empty callback. - * @param hsmartcard SMARTCARD handle. - * @retval None - */ -__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. - */ -} -#endif - -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral Control functions +/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended control functions * @verbatim @@ -146,17 +86,12 @@ __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmart (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature - (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode - (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode - (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold - (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold @endverbatim * @{ */ -/** - * @brief Update on the fly the SMARTCARD block length in RTOR register. +/** @brief Update on the fly the SMARTCARD block length in RTOR register. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param BlockLength SMARTCARD block length (8-bit long at most) @@ -167,8 +102,7 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uin MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); } -/** - * @brief Update on the fly the receiver timeout value in RTOR register. +/** @brief Update on the fly the receiver timeout value in RTOR register. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout @@ -181,16 +115,14 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); } -/** - * @brief Enable the SMARTCARD receiver timeout feature. +/** @brief Enable the SMARTCARD receiver timeout feature. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmartcard); @@ -204,7 +136,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else @@ -213,16 +145,14 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef } } -/** - * @brief Disable the SMARTCARD receiver timeout feature. +/** @brief Disable the SMARTCARD receiver timeout feature. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmartcard); @@ -236,7 +166,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else @@ -245,6 +175,83 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef } } +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_SMARTCARDEx_RxFifoFullCallback() + (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief SMARTCARD RX Fifo full callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD TX Fifo empty callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +#endif /* USART_CR1_FIFOEN */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions + * @brief SMARTCARD control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SMARTCARD. + (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold +@endverbatim + * @{ + */ + #if defined(USART_CR1_FIFOEN) /** * @brief Enable the FIFO mode. @@ -253,37 +260,37 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE; - + /* Restore SMARTCARD configuration */ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); - + /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } @@ -294,34 +301,34 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmart */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE; - + /* Restore SMARTCARD configuration */ WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } @@ -340,37 +347,37 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmar */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Update TX threshold configuration */ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); - + /* Restore SMARTCARD configuration */ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } @@ -389,40 +396,41 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hs */ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - + /* Save actual SMARTCARD configuration */ tmpcr1 = READ_REG(hsmartcard->Instance->CR1); - + /* Disable SMARTCARD */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Update RX threshold configuration */ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ SMARTCARDEx_SetNbDataToProcess(hsmartcard); - + /* Restore SMARTCARD configuration */ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } -#endif +#endif /* USART_CR1_FIFOEN */ + /** * @} */ @@ -449,25 +457,27 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { - hsmartcard->NbTxDataToProcess = 1; - hsmartcard->NbRxDataToProcess = 1; + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; } else { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } -#endif + +#endif /* USART_CR1_FIFOEN */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h index e59ba1112c..1d09000ec8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SMARTCARD_EX_H -#define __STM32L4xx_HAL_SMARTCARD_EX_H +#ifndef STM32L4xx_HAL_SMARTCARD_EX_H +#define STM32L4xx_HAL_SMARTCARD_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,19 +36,19 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants * @{ */ - + /** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication * @{ */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */ -#endif /* USART_TCBGT_SUPPORT */ +#endif /* USART_TCBGT_SUPPORT */ #define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ /** * @} @@ -73,7 +57,7 @@ /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ #define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ #define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ #define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ @@ -89,8 +73,18 @@ */ #if defined(USART_CR1_FIFOEN) +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode + * @brief SMARTCARD FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level - * @brief SMARTCARD TXFIFO level + * @brief SMARTCARD TXFIFO level * @{ */ #define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ @@ -102,9 +96,9 @@ /** * @} */ - + /** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level - * @brief SMARTCARD RXFIFO level + * @brief SMARTCARD RXFIFO level * @{ */ #define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ @@ -116,8 +110,8 @@ /** * @} */ -#endif +#endif /* USART_CR1_FIFOEN */ /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register @@ -135,15 +129,15 @@ #define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */ #define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */ #else -#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ -#endif +#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ +#endif /* USART_CR1_FIFOEN */ #define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ #if defined(USART_CR1_FIFOEN) #define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */ #define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */ #else -#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ -#endif +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ +#endif /* USART_CR1_FIFOEN */ #define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ #define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ #define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ @@ -154,11 +148,11 @@ #define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */ #define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */ #define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ - + /** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition * Elements values convention: 000ZZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5 bits) @@ -172,259 +166,149 @@ #define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ #define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) -#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ -#endif +#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ +#endif /* USART_CR1_FIFOEN */ #define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ #define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ #if defined(USART_CR1_FIFOEN) -#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ -#endif +#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ +#endif /* USART_CR1_FIFOEN */ #define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ - + #define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ #define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ #define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ #define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ -#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ #define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) #define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ #define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */ #define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */ #define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ - + /** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags * @{ */ #define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ #define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */ #define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ #define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ #if defined(USART_CR1_FIFOEN) #define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ #define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Private_Constants SMARTCARDEx Private Constants - * @{ - */ -#if defined(USART_CR1_FIFOEN) -/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode - * @{ - */ -#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ -#endif /** * @} */ +/** + * @} + */ +/* Exported macros -----------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros * @{ */ - -/** @brief Report the SMARTCARD clock source. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __CLOCKSOURCE__: output variable. - * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. - */ -#if defined (STM32L432xx) || defined (STM32L442xx) -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#else -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#endif /* STM32L432xx || STM32L442xx */ /** @brief Set the Transmission Completion flag * @param __HANDLE__ specifies the SMARTCARD Handle. - * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if - * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced - * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). + * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if + * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced + * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). * @retval None */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ - do { \ - if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ - { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } \ - else \ - { \ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + } \ + else \ + { \ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ - } \ - } while(0) + } \ + } while(0U) #else #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ do { \ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } while(0) -#endif + } while(0U) +#endif /* USART_TCBGT_SUPPORT */ /** @brief Return the transmission completion flag. * @param __HANDLE__ specifies the SMARTCARD Handle. * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is - * reported. + * reported. * @retval Transmission completion flag */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) #else #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) -#endif +#endif /* USART_TCBGT_SUPPORT */ -/** - * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. - * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. +/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) - */ + */ #if defined(USART_TCBGT_SUPPORT) -#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\ +#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \ ((__TXCOMPLETE__) == SMARTCARD_TC)) #else #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC) -#endif +#endif /* USART_TCBGT_SUPPORT */ +#if defined(USART_CR1_FIFOEN) +/** @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__ SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + +/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -435,22 +319,9 @@ */ /* Initialization and de-initialization functions ****************************/ -/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 - * @{ - */ +/* IO operation methods *******************************************************/ -/* IO operation functions *****************************************************/ -#if defined(USART_CR1_FIFOEN) -void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); -#endif - -/** - * @} - */ - - -/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 * @{ */ @@ -460,12 +331,36 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 + * @{ + */ + +/* IO operation functions *****************************************************/ +#if defined(USART_CR1_FIFOEN) +void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* USART_CR1_FIFOEN */ + +/** + * @} + */ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -475,7 +370,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs * @} */ - /* Private functions ---------------------------------------------------------*/ /** @@ -490,6 +384,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs } #endif -#endif /* __STM32L4xx_HAL_SMARTCARD_EX_H */ +#endif /* STM32L4xx_HAL_SMARTCARD_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c index 8aeaa1b497..29618a0974 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c @@ -20,7 +20,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -33,91 +33,133 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: + (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. + by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can + using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() - (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() - to check the Error Code using function HAL_SMBUS_GetError() + (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function @ref HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError() + (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() + to check the Error Code using function @ref HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in SMBUS HAL driver. - (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral - (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral - (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not - (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt - (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. + [..] + Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. + [..] + By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() + or @ref HAL_SMBUS_Init() function. + [..] + When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros - @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -141,7 +183,7 @@ /** @defgroup SMBUS_Private_Define SMBUS Private Constants * @{ */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */ #define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ #define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ #define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ @@ -161,18 +203,18 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ @@ -255,8 +297,26 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + + if (hsmbus->MspInitCallback == NULL) + { + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hsmbus->MspInitCallback(hsmbus); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } hsmbus->State = HAL_SMBUS_STATE_BUSY; @@ -278,7 +338,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if (hsmbus->Init.OwnAddress1 != 0U) + if (hsmbus->Init.OwnAddress1 != 0UL) { if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { @@ -347,8 +407,18 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) /* Disable the SMBUS Peripheral Clock */ __HAL_SMBUS_DISABLE(hsmbus); +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + if (hsmbus->MspDeInitCallback == NULL) + { + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hsmbus->MspDeInitCallback(hsmbus); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_SMBUS_MspDeInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; @@ -447,7 +517,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint */ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) { - uint32_t tmpreg = 0U; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -490,6 +560,299 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin } } +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMBUS Callback + * To be used instead of the weak predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = pCallback; + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = pCallback; + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +/** + * @brief Unregister an SMBUS Callback + * SMBUS callback is redirected to the weak predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +/** + * @brief Register the Slave Address Match SMBUS Callback + * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +/** + * @brief UnRegister the Slave Address Match SMBUS Callback + * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsmbus); + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + return status; +} + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + /** * @} */ @@ -542,7 +905,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -550,6 +913,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -583,17 +948,21 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + + /* Store current volatile XferOptions, misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -602,12 +971,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -635,7 +1004,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -643,6 +1012,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint */ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -677,17 +1048,21 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + + /* Store current volatile XferOptions, Misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -696,7 +1071,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } @@ -722,7 +1097,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) @@ -752,7 +1127,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -768,6 +1143,10 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } + else + { + /* Nothing to do */ + } return HAL_OK; } @@ -791,11 +1170,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - if ((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0UL)) { - return HAL_ERROR; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -804,7 +1184,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN); hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Set SBC bit to manage Acknowledge at each bit */ @@ -831,18 +1211,18 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -866,7 +1246,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } else { - return HAL_ERROR; + return HAL_BUSY; } } @@ -884,11 +1264,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - if ((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0UL)) { - return HAL_ERROR; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -897,7 +1278,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Process Locked */ __HAL_LOCK(hsmbus); - hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN); hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Set SBC bit to manage Acknowledge at each bit */ @@ -920,13 +1301,13 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else { - SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); } /* Clear ADDR flag after prepare the transfer parameters */ @@ -946,7 +1327,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } else { - return HAL_ERROR; + return HAL_BUSY; } } @@ -1031,16 +1412,19 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; - __IO uint32_t SMBUS_Trials = 0U; + __IO uint32_t SMBUS_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; if (hsmbus->State == HAL_SMBUS_STATE_READY) { @@ -1063,20 +1447,30 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - return HAL_TIMEOUT; + return HAL_ERROR; } } + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); } /* Check if the NACKF flag has not been set */ @@ -1085,7 +1479,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ @@ -1104,7 +1498,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear NACK Flag */ @@ -1115,7 +1509,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t } /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials++ == Trials) + if (SMBUS_Trials == Trials) { /* Generate Stop */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; @@ -1123,21 +1517,27 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_ERROR; } /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } + + /* Increment Trials */ + SMBUS_Trials++; } while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - return HAL_TIMEOUT; + return HAL_ERROR; } else { @@ -1160,49 +1560,55 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - uint32_t tmpisrvalue = 0U; - /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ - tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); + uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR); + uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); } /* Master mode selected */ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { - SMBUS_Master_ISR(hsmbus); + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ } } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { - SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); } /* Master mode selected */ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { - SMBUS_Master_ISR(hsmbus); + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ } } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { - SMBUS_Slave_ISR(hsmbus); + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); } } } @@ -1392,16 +1798,17 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; /* Process Locked */ __HAL_LOCK(hsmbus); - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1414,9 +1821,13 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) { /* Check and treat errors if errors occurs during STOP process */ SMBUS_ITErrorHandler(hsmbus); @@ -1446,15 +1857,23 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* REenable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; if ((hsmbus->XferSize > 0U)) { @@ -1478,28 +1897,47 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ hsmbus->XferSize--; hsmbus->XferCount--; } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ - hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ hsmbus->XferSize--; hsmbus->XferCount--; } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET) { - if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) { - DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); + DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD); if (hsmbus->XferCount > MAX_NBYTE_SIZE) { @@ -1509,17 +1947,17 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) + else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) @@ -1535,7 +1973,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { @@ -1546,12 +1989,25 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } } + else + { + /* Nothing to do */ + } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET) { if (hsmbus->XferCount == 0U) { @@ -1578,7 +2034,12 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { @@ -1589,11 +2050,28 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } + else + { + /* Nothing to do */ + } } } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1604,17 +2082,18 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { - uint8_t TransferDirection = 0U; - uint16_t SlaveAddrCode = 0U; + uint8_t TransferDirection; + uint16_t SlaveAddrCode; /* Process Locked */ __HAL_LOCK(hsmbus); - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ @@ -1650,13 +2129,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET) { - TransferDirection = SMBUS_GET_DIR(hsmbus); - SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); + TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus)); + SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus)); /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ @@ -1666,14 +2149,22 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#else HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + hsmbus->XferSize--; hsmbus->XferCount--; @@ -1683,7 +2174,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else if (hsmbus->XferCount == 0U) { @@ -1697,13 +2188,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Rx complete callback to inform upper layer of the end of receive process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveRxCpltCallback(hsmbus); +#else HAL_SMBUS_SlaveRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -1711,20 +2206,20 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1732,8 +2227,12 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } + else + { + /* Nothing to do */ + } } - else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ @@ -1742,7 +2241,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ - hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + hsmbus->XferCount--; hsmbus->XferSize--; } @@ -1758,13 +2261,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveTxCpltCallback(hsmbus); +#else HAL_SMBUS_SlaveTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } + else + { + /* Nothing to do */ + } /* Check if STOPF is set */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { @@ -1772,7 +2283,10 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ - (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; if ((hsmbus->XferSize > 0U)) { @@ -1799,7 +2313,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear ADDR flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); - hsmbus->XferOptions = 0U; + hsmbus->XferOptions = 0; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1807,7 +2321,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ListenCpltCallback(hsmbus); +#else HAL_SMBUS_ListenCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } @@ -1823,9 +2341,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { - uint32_t tmpisr = 0U; + uint32_t tmpisr = 0UL; if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { @@ -1855,8 +2373,6 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid the risk of SMBUS interrupt handle execution before */ /* all interrupts requested done */ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); - - return HAL_OK; } /** * @brief Manage the disabling of Interrupts. @@ -1865,11 +2381,12 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { - uint32_t tmpisr = 0U; + uint32_t tmpisr = 0UL; + uint32_t tmpstate = hsmbus->State; - if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) + if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1877,48 +2394,48 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { - /* Disable TC, STOP, NACK, TXI interrupt */ + /* Disable TC, STOP, NACK and TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { - /* Disable STOPI, NACKI */ + /* Disable STOP and NACK interrupt */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { - /* Disable TC, STOP, NACK, RXI interrupt */ + /* Disable TC, STOP, NACK and RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { - /* Disable STOPI, NACKI */ + /* Disable STOP and NACK interrupt */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { - /* Enable ADDR, STOP interrupt */ + /* Disable ADDR, STOP and NACK interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1929,8 +2446,6 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); - - return HAL_OK; } /** @@ -1938,13 +2453,15 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + uint32_t tmpstate; + uint32_t tmperror; /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; @@ -1953,7 +2470,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; @@ -1962,7 +2479,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; @@ -1971,7 +2488,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; @@ -1980,7 +2497,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; @@ -1989,7 +2506,7 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; @@ -1997,14 +2514,20 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } + /* Store current volatile hsmbus->State, misra rule */ + tmperror = hsmbus->ErrorCode; + /* Call the Error Callback in case of Error detected */ - if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF)) { /* Do not Reset the HAL state in case of ALERT error */ - if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) { - if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + /* Store current volatile hsmbus->State, misra rule */ + tmpstate = hsmbus->State; + + if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) { /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ /* keep HAL_SMBUS_STATE_LISTEN if set */ @@ -2014,7 +2537,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } @@ -2027,51 +2554,32 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ - if (Status == RESET) + while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status) { - while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_ERROR; } } } - else - { - while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_TIMEOUT; - } - } - } - } return HAL_OK; } @@ -2095,7 +2603,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2103,7 +2611,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } @@ -2112,7 +2620,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus) { /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ @@ -2144,6 +2652,10 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; } + else + { + /* Nothing to do */ + } } /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h index bc7dba982d..9871c85dfa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SMBUS_H -#define __STM32L4xx_HAL_SMBUS_H +#ifndef STM32L4xx_HAL_SMBUS_H +#define STM32L4xx_HAL_SMBUS_H #ifdef __cplusplus extern "C" { @@ -136,6 +120,10 @@ typedef struct #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** * @} */ @@ -144,7 +132,7 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ -typedef struct +typedef struct __SMBUS_HandleTypeDef { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -166,7 +154,47 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } SMBUS_HandleTypeDef; + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMBUS Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ + HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ + HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ + HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ + + HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ + HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ + +} HAL_SMBUS_CallbackIDTypeDef; + +/** + * @brief HAL SMBUS Callback pointer definition + */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** * @} */ @@ -234,7 +262,7 @@ typedef struct * @} */ -/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode * @{ */ #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) @@ -373,7 +401,15 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) +#endif /** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__ specifies the SMBUS Handle. @@ -419,7 +455,7 @@ typedef struct * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable * - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __IT__ (SET or RESET). */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -444,10 +480,10 @@ typedef struct * @arg @ref SMBUS_FLAG_BUSY Bus busy * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) * - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -546,13 +582,13 @@ typedef struct ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ ((REQUEST) == SMBUS_NEXT_FRAME) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ - IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ @@ -571,8 +607,8 @@ typedef struct #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) @@ -590,7 +626,7 @@ typedef struct * @{ */ -/* Initialization and de-initialization functions **********************************/ +/* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); @@ -598,6 +634,14 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** * @} */ @@ -694,6 +738,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif -#endif /* __STM32L4xx_HAL_SMBUS_H */ +#endif /* STM32L4xx_HAL_SMBUS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c index b69650029c..619e7dde44 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c @@ -58,7 +58,66 @@ (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() [..] - Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, the following table resume the max SPI frequency reached with data size 8bits/16bits, according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. @@ -125,29 +184,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -191,7 +234,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma); static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart); @@ -308,8 +351,28 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; @@ -408,8 +471,18 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /* Disable the SPI Peripheral Clock */ __HAL_SPI_DISABLE(hspi); +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_RESET; @@ -452,6 +525,221 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) */ } +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -500,8 +788,9 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -511,6 +800,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); + initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { @@ -562,10 +852,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } /* Transmit data in 16 Bit mode */ @@ -574,14 +864,14 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -592,18 +882,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ else { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr ++; hspi->TxXferCount--; } } @@ -615,20 +906,21 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)pData); - pData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -684,10 +976,7 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ - uint32_t tickstart = 0U; + uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -774,14 +1063,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { /* read the received data */ - (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; - pData += sizeof(uint8_t); + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -797,14 +1086,14 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { - *((uint16_t *)pData) = hspi->Instance->DR; - pData += sizeof(uint16_t); + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; } else { /* Timeout management */ - if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -831,12 +1120,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Receive last data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - *((uint16_t *)pData) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; } /* Receive last data in 8 Bit mode */ else { - (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; } /* Wait the CRC data */ @@ -850,28 +1139,25 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Read CRC to Flush DR and RXNE flag */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); } else { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); errorcode = HAL_TIMEOUT; goto error; } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } } } @@ -916,14 +1202,19 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint32_t tmp = 0U, tmp1 = 0U; + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; #if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg = 0U; + uint32_t spi_cr1; + uint32_t spi_cr2; #endif /* USE_SPI_CRC */ - uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ - uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -934,11 +1225,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - tmp = hspi->State; - tmp1 = hspi->Init.Mode; + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + initial_RxXferCount = Size; +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ - if (!((tmp == HAL_SPI_STATE_READY) || \ - ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; @@ -978,7 +1276,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -999,19 +1297,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ - if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; @@ -1021,7 +1319,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } @@ -1031,15 +1329,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Check RXNE flag */ - if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { - *((uint16_t *)pRxData) = hspi->Instance->DR; - pRxData += sizeof(uint16_t); + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } - if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; goto error; @@ -1049,34 +1347,36 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Transmit and Receive data in 8 Bit mode */ else { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ - if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)pTxData); - pTxData += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } /* Next Data is a reception (Rx). Tx not allowed */ @@ -1087,7 +1387,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } @@ -1097,12 +1397,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Wait until RXNE flag is reset */ - if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { if (hspi->RxXferCount > 1U) { - *((uint16_t *)pRxData) = hspi->Instance->DR; - pRxData += sizeof(uint16_t); + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount -= 2U; if (hspi->RxXferCount <= 1U) { @@ -1112,13 +1412,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } else { - (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR; + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; hspi->RxXferCount--; } /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } - if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; goto error; @@ -1141,15 +1442,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); } else { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1160,9 +1459,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD errorcode = HAL_TIMEOUT; goto error; } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } } } @@ -1389,8 +1687,9 @@ error : */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmp = 0U, tmp1 = 0U; - HAL_StatusTypeDef errorcode = HAL_OK; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1398,11 +1697,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Process locked */ __HAL_LOCK(hspi); - tmp = hspi->State; - tmp1 = hspi->Init.Mode; + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; - if (!((tmp == HAL_SPI_STATE_READY) || \ - ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; @@ -1459,7 +1759,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p #endif /* USE_SPI_CRC */ /* Check if packing mode is enabled and if there is more than 2 data to receive */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) { /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1577,7 +1877,15 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, } /* Enable the Tx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1711,7 +2019,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1745,7 +2061,8 @@ error: HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmp = 0U, tmp1 = 0U; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ @@ -1758,10 +2075,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Process locked */ __HAL_LOCK(hspi); - tmp = hspi->State; - tmp1 = hspi->Init.Mode; - if (!((tmp == HAL_SPI_STATE_READY) || - ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; @@ -1867,7 +2186,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); @@ -1880,7 +2207,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmatx->XferAbortCallback = NULL; /* Enable the Tx DMA Stream/Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1923,6 +2258,9 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); count = resetcount; + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { @@ -1930,11 +2268,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ @@ -1947,22 +2286,20 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } - /* Clear ERRIE interrupts in case of DMA Mode */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - - /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ - if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) { /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmatx != NULL) @@ -1994,6 +2331,11 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ if (hspi->hdmarx != NULL) { @@ -2079,6 +2421,9 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); count = resetcount; + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) { @@ -2086,11 +2431,12 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ @@ -2103,20 +2449,18 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* Wait HAL_SPI_STATE_ABORT state */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } - /* Clear ERRIE interrupts in case of DMA Mode */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -2148,41 +2492,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } } - /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ - if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) - { - /* Abort the SPI DMA Tx Stream/Channel */ - if (hspi->hdmatx != NULL) - { - /* Abort DMA Tx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) - { - hspi->hdmatx->XferAbortCallback = NULL; - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - else - { - abortcplt = 0U; - } - } - /* Abort the SPI DMA Rx Stream/Channel */ - if (hspi->hdmarx != NULL) - { - /* Abort DMA Rx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) - { - hspi->hdmarx->XferAbortCallback = NULL; - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + /* Disable the SPI DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) { /* Abort the SPI DMA Tx Stream/Channel */ @@ -2200,7 +2510,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } } } - /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + /* Disable the SPI DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) { /* Abort the SPI DMA Rx Stream/Channel */ @@ -2245,7 +2555,11 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } return errorcode; @@ -2299,6 +2613,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { + HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated @@ -2308,18 +2623,26 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /* Abort the SPI DMA tx Stream/Channel */ if (hspi->hdmatx != NULL) { - HAL_DMA_Abort(hspi->hdmatx); + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } } /* Abort the SPI DMA rx Stream/Channel */ if (hspi->hdmarx != NULL) { - HAL_DMA_Abort(hspi->hdmarx); + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } } /* Disable the SPI DMA Tx & Rx requests */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); hspi->State = HAL_SPI_STATE_READY; - return HAL_OK; + return errorcode; } /** @@ -2334,25 +2657,25 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) uint32_t itflag = hspi->Instance->SR; /* SPI in mode Receiver ----------------------------------------------------*/ - if (((itflag & SPI_FLAG_OVR) == RESET) && - ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) { hspi->RxISR(hspi); return; } /* SPI in mode Transmitter -------------------------------------------------*/ - if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) { hspi->TxISR(hspi); return; } /* SPI in Error Treatment --------------------------------------------------*/ - if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) { /* SPI Overrun error interrupt occurred ----------------------------------*/ - if ((itflag & SPI_FLAG_OVR) != RESET) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) { if (hspi->State != HAL_SPI_STATE_BUSY_TX) { @@ -2367,14 +2690,14 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /* SPI Mode Fault error interrupt occurred -------------------------------*/ - if ((itflag & SPI_FLAG_MODF) != RESET) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); __HAL_SPI_CLEAR_MODFFLAG(hspi); } /* SPI Frame error interrupt occurred ------------------------------------*/ - if ((itflag & SPI_FLAG_FRE) != RESET) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); __HAL_SPI_CLEAR_FREFLAG(hspi); @@ -2397,7 +2720,10 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; - HAL_DMA_Abort_IT(hspi->hdmarx); + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } } /* Abort the SPI DMA Tx channel */ if (hspi->hdmatx != NULL) @@ -2405,13 +2731,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Set the SPI DMA Abort callback : will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - HAL_DMA_Abort_IT(hspi->hdmatx); + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } } } else { /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } return; @@ -2612,10 +2945,10 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t tickstart = 0U; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* DMA Normal Mode */ @@ -2644,11 +2977,21 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2659,11 +3002,8 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t tickstart = 0U; -#if (USE_SPI_CRC != 0U) - __IO uint16_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -2679,7 +3019,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -2687,26 +3027,23 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* Read CRC */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); } else { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } } } @@ -2735,11 +3072,21 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2750,11 +3097,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t tickstart = 0U; -#if (USE_SPI_CRC != 0U) - __IO int16_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -2777,9 +3122,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); } else { @@ -2789,9 +3132,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - tmpreg = hspi->Instance->DR; - /* To avoid GCC warning */ - UNUSED(tmpreg); + READ_REG(hspi->Instance->DR); } } #endif /* USE_SPI_CRC */ @@ -2820,11 +3161,21 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2835,9 +3186,14 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2848,9 +3204,14 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2861,9 +3222,14 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2874,14 +3240,19 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2892,11 +3263,16 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2909,7 +3285,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ hspi->hdmatx->XferAbortCallback = NULL; @@ -2958,7 +3334,11 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hspi->State = HAL_SPI_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -2971,7 +3351,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3021,7 +3401,11 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hspi->State = HAL_SPI_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } /** @@ -3035,7 +3419,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Receive data in packing mode */ if (hspi->RxXferCount > 1U) { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) @@ -3047,7 +3431,8 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Receive data in 8 Bit mode */ else { - *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; hspi->RxXferCount--; } @@ -3082,13 +3467,8 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC to flush Data Regsiter */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); hspi->CRCSize--; @@ -3124,7 +3504,8 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3161,7 +3542,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; @@ -3194,14 +3575,8 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Receive data in 16 Bit mode */ - __IO uint16_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = hspi->Instance->DR; - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC to flush Data Regsiter */ + READ_REG(hspi->Instance->DR); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3256,13 +3631,8 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC to flush Data Register */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); hspi->CRCSize--; @@ -3281,7 +3651,8 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; hspi->RxXferCount--; #if (USE_SPI_CRC != 0U) @@ -3314,13 +3685,8 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg = 0U; - - /* Read data register to flush CRC */ - tmpreg = hspi->Instance->DR; - - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 16bit CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3337,7 +3703,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; @@ -3370,7 +3736,8 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; hspi->TxXferCount--; if (hspi->TxXferCount == 0U) @@ -3422,14 +3789,14 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) * @param Tickstart tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3477,20 +3844,17 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { - __IO uint8_t tmpreg; - while ((hspi->Instance->SR & Fifo) != State) { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Read 8bit CRC to flush Data Register */ + READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); } if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3603,7 +3967,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); @@ -3624,7 +3988,12 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { @@ -3634,18 +4003,33 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) if (hspi->State == HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } else { hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } #if (USE_SPI_CRC != 0U) } @@ -3676,18 +4060,33 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { #endif /* USE_SPI_CRC */ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } #if (USE_SPI_CRC != 0U) } @@ -3702,7 +4101,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3725,11 +4124,21 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } else { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } } @@ -3748,17 +4157,18 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); /* Check RXNEIE is disabled */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); @@ -3789,17 +4199,18 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); /* Check TXEIE is disabled */ do { - if (count-- == 0U) + if (count == 0U) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); break; } + count--; } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); @@ -3817,6 +4228,36 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } + /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } hspi->State = HAL_SPI_STATE_ABORT; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h index 3aa540374e..100ec06f2a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SPI_H -#define __STM32L4xx_HAL_SPI_H +#ifndef STM32L4xx_HAL_SPI_H +#define STM32L4xx_HAL_SPI_H #ifdef __cplusplus extern "C" { @@ -163,8 +147,46 @@ typedef struct __SPI_HandleTypeDef __IO uint32_t ErrorCode; /*!< SPI Error code */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } SPI_HandleTypeDef; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -185,6 +207,9 @@ typedef struct __SPI_HandleTypeDef #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -326,13 +351,12 @@ typedef struct __SPI_HandleTypeDef * This parameter can be one of the following values: * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : * RXNE event is generated if the FIFO - * level is greater or equal to 1/2(16-bits). + * level is greater or equal to 1/4(8-bits). * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO - * level is greater or equal to 1/4(8 bits). */ + * level is greater or equal to 1/2(16 bits). */ #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) - /** * @} */ @@ -359,6 +383,7 @@ typedef struct __SPI_HandleTypeDef #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) /** * @} */ @@ -400,7 +425,15 @@ typedef struct __SPI_HandleTypeDef * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /** @brief Enable the specified SPI interrupts. * @param __HANDLE__ specifies the SPI Handle. @@ -546,6 +579,34 @@ typedef struct __SPI_HandleTypeDef #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode @@ -612,7 +673,7 @@ typedef struct __SPI_HandleTypeDef ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. - * @param __NSS__ specifies the SPI Slave Slelect management parameter. + * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ @@ -708,6 +769,12 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} */ @@ -774,6 +841,6 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); } #endif -#endif /* __STM32L4xx_HAL_SPI_H */ +#endif /* STM32L4xx_HAL_SPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c index 813a8ff429..a21bbceacf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c @@ -10,29 +10,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -55,7 +39,7 @@ /** @defgroup SPIEx_Private_Constants SPIEx Private Constants * @{ */ -#define SPI_FIFO_SIZE 4 +#define SPI_FIFO_SIZE 4UL /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h index 99261d60be..ce59e85347 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SPI_EX_H -#define __STM32L4xx_HAL_SPI_EX_H +#ifndef STM32L4xx_HAL_SPI_EX_H +#define STM32L4xx_HAL_SPI_EX_H #ifdef __cplusplus extern "C" { @@ -86,6 +70,6 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); } #endif -#endif /* __STM32L4xx_HAL_SPI_EX_H */ +#endif /* STM32L4xx_HAL_SPI_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c index 69aa39213e..a5d1adc49a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c @@ -62,29 +62,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -92,9 +76,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -103,9 +85,10 @@ #ifdef HAL_SRAM_MODULE_ENABLED /** @defgroup SRAM SRAM - * @brief SRAM HAL module driver. + * @brief SRAM driver modules * @{ */ + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -132,11 +115,11 @@ */ /** - * @brief Perform the SRAM device initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @brief Perform the SRAM device initialization sequence + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -151,7 +134,6 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp { /* Allocate lock resource and initialize it */ hsram->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); } @@ -173,7 +155,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp /** * @brief Perform the SRAM device de-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -195,7 +177,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) /** * @brief Initialize the SRAM MSP. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -211,7 +193,7 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) /** * @brief DeInitialize the SRAM MSP. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -227,7 +209,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -243,7 +225,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -277,11 +259,11 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Read 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) @@ -313,11 +295,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress /** * @brief Write 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) @@ -355,11 +337,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Read 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) @@ -391,11 +373,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Write 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) @@ -433,11 +415,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Read 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -467,11 +449,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Write 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -507,11 +489,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Read a Word data buffer from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -540,11 +522,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Write a Word data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -598,7 +580,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Enable dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -621,7 +603,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) /** * @brief Disable dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -665,8 +647,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) */ /** - * @brief Return the SRAM controller handle state. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @brief Return the SRAM controller state + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL state */ @@ -683,17 +665,17 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) /** * @} */ + /** * @} */ + #endif /* HAL_SRAM_MODULE_ENABLED */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* FMC_BANK1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h index 9eea5ab71b..d25f9a1af1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h @@ -6,32 +6,16 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L4xx_HAL_SRAM_H @@ -41,9 +25,7 @@ extern "C" { #endif -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(FMC_BANK1) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -51,47 +33,44 @@ /** @addtogroup STM32L4xx_HAL_Driver * @{ */ - /** @addtogroup SRAM * @{ - */ + */ /* Exported typedef ----------------------------------------------------------*/ /** @defgroup SRAM_Exported_Types SRAM Exported Types * @{ */ -/** - * @brief HAL SRAM State structures definition - */ +/** + * @brief HAL SRAM State structures definition + */ typedef enum { - HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ - + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ }HAL_SRAM_StateTypeDef; -/** - * @brief SRAM handle Structure definition - */ +/** + * @brief SRAM handle Structure definition + */ typedef struct { - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - + FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ - HAL_LockTypeDef Lock; /*!< SRAM locking object */ - + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ - + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ - -}SRAM_HandleTypeDef; +}SRAM_HandleTypeDef; /** * @} @@ -104,8 +83,8 @@ typedef struct * @{ */ -/** @brief Reset SRAM handle state. - * @param __HANDLE__: SRAM handle +/** @brief Reset SRAM handle state + * @param __HANDLE__ SRAM handle * @retval None */ #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) @@ -129,9 +108,6 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); - /** * @} */ @@ -150,10 +126,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + /** * @} */ - + /** @addtogroup SRAM_Exported_Functions_Group3 Control functions * @{ */ @@ -170,28 +149,26 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); * @{ */ -/* SRAM Peripheral State functions ********************************************/ +/* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); -/** - * @} - */ - /** * @} */ - -/** - * @} - */ /** * @} */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMC_BANK1 */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c index 68b1309688..388c5e67ff 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c @@ -42,34 +42,126 @@ (#) Program the Bite Rate, Tx Buffering mode, Rx Buffering mode in the Init structure. (#) Enable the SWPMI peripheral by calling the HAL_SWPMI_Init() function. - + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SWPMI_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SWPMI_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SWPMI_Transmit_IT() + (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SWPMI_Receive_IT() + (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback() + (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SWPMI_ErrorCallback() + + *** DMA mode IO operation *** + ============================= + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Transmit_DMA() + (+) At transmission end of transfer HAL_SWPMI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SWPMI_Receive_DMA() + (+) At reception end of transfer HAL_SWPMI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SWPMI_RxCpltCallback() + (+) In case of flag error, HAL_SWPMI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SWPMI_ErrorCallback() + (+) Stop the DMA Transfer using HAL_SWPMI_DMAStop() + + *** SWPMI HAL driver additional function list *** + =============================================== + [..] + Below the list the others API available SWPMI HAL driver : + + (+) HAL_SWPMI_EnableLoopback(): Enable the loopback mode for test purpose only + (+) HAL_SWPMI_DisableLoopback(): Disable the loopback mode + + *** SWPMI HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SWPMI HAL driver : + + (+) __HAL_SWPMI_ENABLE(): Enable the SWPMI peripheral + (+) __HAL_SWPMI_DISABLE(): Disable the SWPMI peripheral + (+) __HAL_SWPMI_ENABLE_IT(): Enable the specified SWPMI interrupts + (+) __HAL_SWPMI_DISABLE_IT(): Disable the specified SWPMI interrupts + (+) __HAL_SWPMI_GET_IT_SOURCE(): Check if the specified SWPMI interrupt source is + enabled or disabled + (+) __HAL_SWPMI_GET_FLAG(): Check whether the specified SWPMI flag is set or not + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + [..] + Use function HAL_SWPMI_RegisterCallback() to register a user callback. It allows + to register the following callbacks: + (+) RxCpltCallback : SWPMI receive complete. + (+) RxHalfCpltCallback : SWPMI receive half complete. + (+) TxCpltCallback : SWPMI transmit complete. + (+) TxHalfCpltCallback : SWPMI transmit half complete. + (+) ErrorCallback : SWPMI error. + (+) MspInitCallback : SWPMI MspInit. + (+) MspDeInitCallback : SWPMI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + [..] + Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + This function allows to reset following callbacks: + (+) RxCpltCallback : SWPMI receive complete. + (+) RxHalfCpltCallback : SWPMI receive half complete. + (+) TxCpltCallback : SWPMI transmit complete. + (+) TxHalfCpltCallback : SWPMI transmit half complete. + (+) ErrorCallback : SWPMI error. + (+) MspInitCallback : SWPMI MspInit. + (+) MspDeInitCallback : SWPMI MspDeInit. + [..] + By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init + and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit + or HAL_SWPMI_Init function. + [..] + When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -77,14 +169,12 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) - /** @addtogroup STM32L4xx_HAL_Driver * @{ */ +#if defined(SWPMI1) + /** @defgroup SWPMI SWPMI * @brief HAL SWPMI module driver * @{ @@ -97,7 +187,7 @@ /** @addtogroup SWPMI_Private_Constants SWPMI Private Constants * @{ */ -#define SWPMI_TIMEOUT_VALUE ((uint32_t) 22000) +#define SWPMI_TIMEOUT_VALUE 22000U /* End of transmission timeout */ /** * @} @@ -112,11 +202,11 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void SWPMI_DMAError(DMA_HandleTypeDef *hdma); static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); +static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout); /* Exported functions --------------------------------------------------------*/ @@ -142,13 +232,13 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs /** * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitTypeDef. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the SWPMI handle allocation */ if(hswpmi == NULL) @@ -167,9 +257,25 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) { /* Allocate lock resource and initialize it */ hswpmi->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback; + hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback; + hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback; + hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback; + hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + if(hswpmi->MspInitCallback == NULL) + { + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + } + hswpmi->MspInitCallback(hswpmi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SWPMI_MspInit(hswpmi); +#endif } hswpmi->State = HAL_SWPMI_STATE_BUSY; @@ -189,8 +295,8 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Insure 300 µs wait to insure SWPMI_IO output not higher than 1.8V */ /* Wait loop initialization and execution */ /* Note: Variable divided by 4 to compensate partially CPU processing cycles. */ - wait_loop_index = (300 * (SystemCoreClock / (1000000 * 4))) + 150; - while(wait_loop_index != 0) + wait_loop_index = (300U * (SystemCoreClock / (1000000U * 4U))) + 150U; + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -207,7 +313,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; hswpmi->State = HAL_SWPMI_STATE_READY; - /* Enable SWPMI peripheral if not */ + /* Enable SWPMI peripheral */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); } @@ -216,7 +322,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /** * @brief De-initialize the SWPMI peripheral. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) @@ -238,11 +344,22 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) /* Disable SWPMI interface */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); - /* DeInit the low level hardware */ + /* Disable Loopback mode */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); + + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + if(hswpmi->MspDeInitCallback == NULL) + { + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + } + hswpmi->MspDeInitCallback(hswpmi); +#else HAL_SWPMI_MspDeInit(hswpmi); +#endif hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; - hswpmi->State = HAL_SWPMI_STATE_RESET; /* Release Lock */ @@ -254,7 +371,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) /** * @brief Initialize the SWPMI MSP. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi) @@ -269,7 +386,7 @@ __weak void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi) /** * @brief DeInitialize the SWPMI MSP. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) @@ -282,6 +399,182 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) */ } +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user SWPMI callback + * to be used instead of the weak predefined callback. + * @param hswpmi SWPMI handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SWPMI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID, + pSWPMI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if(hswpmi->State == HAL_SWPMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_SWPMI_RX_COMPLETE_CB_ID : + hswpmi->RxCpltCallback = pCallback; + break; + case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : + hswpmi->RxHalfCpltCallback = pCallback; + break; + case HAL_SWPMI_TX_COMPLETE_CB_ID : + hswpmi->TxCpltCallback = pCallback; + break; + case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : + hswpmi->TxHalfCpltCallback = pCallback; + break; + case HAL_SWPMI_ERROR_CB_ID : + hswpmi->ErrorCallback = pCallback; + break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = pCallback; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hswpmi->State == HAL_SWPMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = pCallback; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user SWPMI callback. + * SWPMI callback is redirected to the weak predefined callback. + * @param hswpmi SWPMI handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_SWPMI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SWPMI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SWPMI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SWPMI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SWPMI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SWPMI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SWPMI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hswpmi->State == HAL_SWPMI_STATE_READY) + { + switch (CallbackID) + { + case HAL_SWPMI_RX_COMPLETE_CB_ID : + hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback; + break; + case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : + hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback; + break; + case HAL_SWPMI_TX_COMPLETE_CB_ID : + hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback; + break; + case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : + hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback; + break; + case HAL_SWPMI_ERROR_CB_ID : + hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; + break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hswpmi->State == HAL_SWPMI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ + /** * @} */ @@ -332,30 +625,33 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) (++) HAL_SWPMI_RxCpltCallback() (++) HAL_SWPMI_ErrorCallback() - (#) The capability to launch the above IO operations in loopback mode for - user application verification: + (#) The capability to launch the above IO operations in loopback mode for + user application verification: (++) HAL_SWPMI_EnableLoopback() (++) HAL_SWPMI_DisableLoopback() - + @endverbatim * @{ */ /** * @brief Transmit an amount of data in blocking mode. - * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains + * @param hswpmi pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for SWPMI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; + uint32_t *ptmp_data; + uint32_t tmp_size; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -364,10 +660,11 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Check if a non-blocking receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -385,31 +682,37 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX; } + ptmp_data = pData; + tmp_size = Size; do { /* Wait the TXE to write data */ if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE)) { - hswpmi->Instance->TDR = (*pData++); - Size--; + hswpmi->Instance->TDR = *ptmp_data; + ptmp_data++; + tmp_size--; } else { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { status = HAL_TIMEOUT; break; } } } - } while(Size != 0); + } while(tmp_size != 0U); /* Wait on TXBEF flag to be able to start a second transfer */ if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) { + /* Timeout occurred */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; + status = HAL_TIMEOUT; } @@ -444,19 +747,22 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat /** * @brief Receive an amount of data in blocking mode. - * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains + * @param hswpmi pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for SWPMI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; + uint32_t *ptmp_data; + uint32_t tmp_size; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -465,10 +771,11 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Check if a non-blocking transmit process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -483,28 +790,31 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData hswpmi->State = HAL_SWPMI_STATE_BUSY_TX_RX; } + ptmp_data = pData; + tmp_size = Size; do { /* Wait the RXNE to read data */ if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE)) { - (*pData++) = hswpmi->Instance->RDR; - Size--; + *ptmp_data = hswpmi->Instance->RDR; + ptmp_data++; + tmp_size--; } else { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { status = HAL_TIMEOUT; break; } } } - } while(Size != 0); - + } while(tmp_size != 0U); + if(status == HAL_OK) { if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF)) @@ -542,17 +852,18 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData /** * @brief Transmit an amount of data in non-blocking mode with interrupt. - * @param hswpmi: pointer to a SWPMI_HandleTypeDef structure that contains + * @param hswpmi pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for SWPMI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -561,7 +872,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Update handle */ hswpmi->pTxBuffPtr = pData; @@ -570,7 +882,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -597,7 +909,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p else { status = HAL_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hswpmi); } @@ -607,17 +919,18 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p } /** - * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hswpmi: SWPMI handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hswpmi SWPMI handle + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -626,7 +939,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Update handle */ hswpmi->pRxBuffPtr = pData; @@ -635,7 +949,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -658,7 +972,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD else { status = HAL_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hswpmi); } @@ -668,17 +982,18 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD } /** - * @brief Transmit an amount of data in non-blocking mode with DMA interrupt. - * @param hswpmi: SWPMI handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Transmit an amount of data in non-blocking mode with DMA interrupt. + * @param hswpmi SWPMI handle + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -687,7 +1002,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_RX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Update handle */ hswpmi->pTxBuffPtr = pData; @@ -696,7 +1012,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -717,23 +1033,33 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * /* Set the DMA error callback */ hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; - /* Enable the SWPMI transmit DMA Channel */ - HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size); + /* Enable the SWPMI transmit DMA channel */ + if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) + { + hswpmi->State = tmp_state; /* Back to previous state */ + hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hswpmi); + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); - /* Enable the SWPMI transmit underrun error */ - __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE); + /* Enable the SWPMI transmit underrun error */ + __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_TXUNRIE); - /* Enable the DMA transfer for transmit request by setting the TXDMA bit - in the SWPMI CR register */ - SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); + /* Enable the DMA transfer for transmit request by setting the TXDMA bit + in the SWPMI CR register */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); + } } else { status = HAL_BUSY; - + /* Process Unlocked */ __HAL_UNLOCK(hswpmi); } @@ -743,17 +1069,18 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * } /** - * @brief Receive an amount of data in non-blocking mode with DMA interrupt. - * @param hswpmi: SWPMI handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in non-blocking mode with DMA interrupt. + * @param hswpmi SWPMI handle + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { status = HAL_ERROR; } @@ -762,7 +1089,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /* Process Locked */ __HAL_LOCK(hswpmi); - if((hswpmi->State == HAL_SWPMI_STATE_READY) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)) + tmp_state = hswpmi->State; + if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Update handle */ hswpmi->pRxBuffPtr = pData; @@ -770,7 +1098,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if(tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -792,17 +1120,27 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError; /* Enable the DMA request */ - HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size); + if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) + { + hswpmi->State = tmp_state; /* Back to previous state */ + hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hswpmi); + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hswpmi); - /* Enable the SWPMI receive CRC Error and receive overrun interrupts */ - __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE); + /* Enable the SWPMI receive CRC Error and receive overrun interrupts */ + __HAL_SWPMI_ENABLE_IT(hswpmi, SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE); - /* Enable the DMA transfer for the receiver request by setting the RXDMA bit - in the SWPMI CR register */ - SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); + /* Enable the DMA transfer for the receiver request by setting the RXDMA bit + in the SWPMI CR register */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); + } } else { @@ -818,11 +1156,13 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p /** * @brief Stop all DMA transfers. - * @param hswpmi: SWPMI handle - * @retval HAL_OK + * @param hswpmi SWPMI handle + * @retval HAL status */ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) { + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hswpmi); @@ -832,12 +1172,20 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) /* Abort the SWPMI DMA tx channel */ if(hswpmi->hdmatx != NULL) { - HAL_DMA_Abort(hswpmi->hdmatx); + if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK) + { + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; + } } /* Abort the SWPMI DMA rx channel */ if(hswpmi->hdmarx != NULL) { - HAL_DMA_Abort(hswpmi->hdmarx); + if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK) + { + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; + status = HAL_ERROR; + } } /* Disable SWPMI interface */ @@ -848,13 +1196,13 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) /* Process Unlocked */ __HAL_UNLOCK(hswpmi); - return HAL_OK; + return status; } /** * @brief Enable the Loopback mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @note Loopback mode is to be used only for test purposes * @retval HAL_OK / HAL_BUSY */ @@ -865,16 +1213,14 @@ HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi) /* Process Locked */ __HAL_LOCK(hswpmi); - /* Check SWPMI not enabled */ - if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET) - { - status = HAL_BUSY; - } - else - { - /* Set Loopback */ - SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); - } + /* Make sure the SWPMI interface is not enabled to set the loopback mode */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); + + /* Set Loopback */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); + + /* Enable SWPMI interface in loopback mode */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); /* Process Unlocked */ __HAL_UNLOCK(hswpmi); @@ -884,7 +1230,7 @@ HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Disable the Loopback mode. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @note Loopback mode is to be used only for test purposes * @retval HAL_OK / HAL_BUSY */ @@ -895,16 +1241,14 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) /* Process Locked */ __HAL_LOCK(hswpmi); - /* Check SWPMI not enabled */ - if(READ_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT) != RESET) - { - status = HAL_BUSY; - } - else - { - /* Reset Loopback */ - CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); - } + /* Make sure the SWPMI interface is not enabled to reset the loopback mode */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); + + /* Reset Loopback */ + CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_LPBK); + + /* Re-enable SWPMI interface in normal mode */ + SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); /* Process Unlocked */ __HAL_UNLOCK(hswpmi); @@ -919,11 +1263,11 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks * @brief SWPMI IRQ handler. * -@verbatim +@verbatim ============================================================================== ##### SWPMI IRQ handler and callbacks ##### - ============================================================================== -[..] This section provides SWPMI IRQ handler and callback functions called within + ============================================================================== +[..] This section provides SWPMI IRQ handler and callback functions called within the IRQ handler. @endverbatim @@ -932,7 +1276,7 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Handle SWPMI interrupt request. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) @@ -942,7 +1286,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) uint32_t errcode = HAL_SWPMI_ERROR_NONE; /* SWPMI CRC error interrupt occurred --------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXBERF) != RESET) && ((regier & SWPMI_IT_RXBERIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U)) { /* Disable Receive CRC interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE); @@ -953,7 +1297,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI Over-Run interrupt occurred -----------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXOVRF) != RESET) && ((regier & SWPMI_IT_RXOVRIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U)) { /* Disable Receive overrun interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE); @@ -964,7 +1308,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI Under-Run interrupt occurred -----------------------------------------*/ - if(((regisr & SWPMI_FLAG_TXUNRF) != RESET) && ((regier & SWPMI_IT_TXUNRIE) != RESET)) + if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U)) { /* Disable Transmit under run interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE); @@ -978,19 +1322,19 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) if(errcode != HAL_SWPMI_ERROR_NONE) { hswpmi->ErrorCode |= errcode; - - if((errcode & HAL_SWPMI_ERROR_UDR) != RESET) + + if((errcode & HAL_SWPMI_ERROR_UDR) != 0U) { /* Check TXDMA transfer to abort */ if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA)) { /* Disable DMA TX at SWPMI level */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); - + /* Abort the USART DMA Tx channel */ if(hswpmi->hdmatx != NULL) { - /* Set the SWPMI Tx DMA Abort callback : + /* Set the SWPMI Tx DMA Abort callback : will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */ hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError; /* Abort DMA TX */ @@ -1005,7 +1349,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } else @@ -1013,7 +1361,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } else @@ -1023,11 +1375,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) { /* Disable DMA RX at SWPMI level */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); - + /* Abort the USART DMA Rx channel */ if(hswpmi->hdmarx != NULL) { - /* Set the SWPMI Rx DMA Abort callback : + /* Set the SWPMI Rx DMA Abort callback : will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */ hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError; /* Abort DMA RX */ @@ -1042,7 +1394,11 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } else @@ -1050,37 +1406,41 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /* Set the SWPMI state ready to be able to start again the process */ hswpmi->State = HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } } } /* SWPMI in mode Receiver ---------------------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXNE) != RESET) && ((regier & SWPMI_IT_RIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U)) { SWPMI_Receive_IT(hswpmi); } /* SWPMI in mode Transmitter ------------------------------------------------*/ - if(((regisr & SWPMI_FLAG_TXE) != RESET) && ((regier & SWPMI_IT_TIE) != RESET)) + if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U)) { SWPMI_Transmit_IT(hswpmi); } /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/ - if(((regisr & SWPMI_FLAG_TXBEF) != RESET) && ((regier & SWPMI_IT_TXBEIE) != RESET)) + if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U)) { SWPMI_EndTransmit_IT(hswpmi); } /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/ - if(((regisr & SWPMI_FLAG_RXBFF) != RESET) && ((regier & SWPMI_IT_RXBFIE) != RESET)) + if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U)) { SWPMI_EndReceive_IT(hswpmi); } /* Both Transmission and reception complete ---------------------------------*/ - if(((regisr & SWPMI_FLAG_TCF) != RESET) && ((regier & SWPMI_IT_TCIE) != RESET)) + if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U)) { SWPMI_EndTransmitReceive_IT(hswpmi); } @@ -1088,7 +1448,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) /** * @brief Tx Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1103,7 +1463,7 @@ __weak void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Tx Half Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1118,7 +1478,7 @@ __weak void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Rx Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1133,7 +1493,7 @@ __weak void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Rx Half Transfer completed callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1148,7 +1508,7 @@ __weak void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief SWPMI error callback. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval None */ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) @@ -1182,7 +1542,7 @@ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) /** * @brief Return the SWPMI handle state. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @retval HAL state */ HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi) @@ -1219,41 +1579,39 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi) /** * @brief Transmit an amount of data in interrupt mode. * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Transmit_IT() - * @param hswpmi: SWPMI handle - * @retval HAL status + * @param hswpmi SWPMI handle + * @retval None */ -static HAL_StatusTypeDef SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) { - HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State; - if ((hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)) + if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) { - if(hswpmi->TxXferCount == 0) + if(hswpmi->TxXferCount == 0U) { /* Disable the SWPMI TXE and Underrun Interrupts */ CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE)); } else { - hswpmi->Instance->TDR = (uint32_t)(*hswpmi->pTxBuffPtr++); + hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr; + hswpmi->pTxBuffPtr++; hswpmi->TxXferCount--; } } else { - status = HAL_BUSY; + /* nothing to do */ } - - return status; } /** * @brief Wraps up transmission in non-blocking mode. - * @param hswpmi: SWPMI handle - * @retval HAL status - * @retval HAL status + * @param hswpmi SWPMI handle + * @retval None */ -static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) { /* Clear the SWPMI Transmit buffer empty Flag */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TXBEF); @@ -1269,47 +1627,52 @@ static HAL_StatusTypeDef SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) { hswpmi->State = HAL_SWPMI_STATE_READY; } - - HAL_SWPMI_TxCpltCallback(hswpmi); - return HAL_OK; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxCpltCallback(hswpmi); +#else + HAL_SWPMI_TxCpltCallback(hswpmi); +#endif } /** * @brief Receive an amount of data in interrupt mode. * @note Function called under interruption only, once interruptions have been enabled by HAL_SWPMI_Receive_IT() - * @param hswpmi: SWPMI handle - * @retval HAL status + * @param hswpmi SWPMI handle + * @retval None */ -static HAL_StatusTypeDef SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) { - HAL_StatusTypeDef status = HAL_OK; + HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State; - if((hswpmi->State == HAL_SWPMI_STATE_BUSY_RX) || (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)) + if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) { - *hswpmi->pRxBuffPtr++ = (uint32_t)(hswpmi->Instance->RDR); + *hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR); + hswpmi->pRxBuffPtr++; - if(--hswpmi->RxXferCount == 0) + --hswpmi->RxXferCount; + if(hswpmi->RxXferCount == 0U) { /* Wait for RXBFF flag to update state */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->RxCpltCallback(hswpmi); +#else HAL_SWPMI_RxCpltCallback(hswpmi); +#endif } } else { - status = HAL_BUSY; + /* nothing to do */ } - - return status; } /** * @brief Wraps up reception in non-blocking mode. - * @param hswpmi: SWPMI handle - * @retval HAL status - * @retval HAL status + * @param hswpmi SWPMI handle + * @retval None */ -static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) { /* Clear the SWPMI Receive buffer full Flag */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF); @@ -1325,17 +1688,14 @@ static HAL_StatusTypeDef SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) { hswpmi->State = HAL_SWPMI_STATE_READY; } - - return HAL_OK; } /** * @brief Wraps up transmission and reception in non-blocking mode. - * @param hswpmi: SWPMI handle - * @retval HAL status - * @retval HAL status + * @param hswpmi SWPMI handle + * @retval None */ -static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi) +static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi) { /* Clear the SWPMI Transmission Complete Flag */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_TCF); @@ -1351,24 +1711,26 @@ static HAL_StatusTypeDef SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi { hswpmi->State = HAL_SWPMI_STATE_READY; } - - return HAL_OK; + else + { + /* nothing to do */ + } } /** * @brief DMA SWPMI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - uint32_t tickstart = 0; + uint32_t tickstart; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) != SET) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hswpmi->TxXferCount = 0; + hswpmi->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by setting the TXDMA bit in the SWPMI CR register */ @@ -1381,7 +1743,13 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } else { @@ -1396,32 +1764,44 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->State = HAL_SWPMI_STATE_READY; } +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxCpltCallback(hswpmi); +#else HAL_SWPMI_TxCpltCallback(hswpmi); +#endif } } /* DMA Circular mode */ else { +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxCpltCallback(hswpmi); +#else HAL_SWPMI_TxCpltCallback(hswpmi); +#endif } } /** * @brief DMA SWPMI transmit process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->TxHalfCpltCallback(hswpmi); +#else HAL_SWPMI_TxHalfCpltCallback(hswpmi); +#endif } /** * @brief DMA SWPMI receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1429,9 +1809,9 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == RESET) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hswpmi->RxXferCount = 0; + hswpmi->RxXferCount = 0U; /* Disable the DMA transfer for the receiver request by setting the RXDMA bit in the SWPMI CR register */ @@ -1447,24 +1827,32 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hswpmi->State = HAL_SWPMI_STATE_READY; } } +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->RxCpltCallback(hswpmi); +#else HAL_SWPMI_RxCpltCallback(hswpmi); +#endif } /** * @brief DMA SWPMI receive process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->RxHalfCpltCallback(hswpmi); +#else HAL_SWPMI_RxHalfCpltCallback(hswpmi); +#endif } /** * @brief DMA SWPMI communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) @@ -1472,17 +1860,21 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update handle */ - hswpmi->RxXferCount = 0; - hswpmi->TxXferCount = 0; + hswpmi->RxXferCount = 0U; + hswpmi->TxXferCount = 0U; hswpmi->State= HAL_SWPMI_STATE_READY; hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } /** * @brief DMA SWPMI communication abort callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) @@ -1490,16 +1882,20 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update handle */ - hswpmi->RxXferCount = 0; - hswpmi->TxXferCount = 0; + hswpmi->RxXferCount = 0U; + hswpmi->TxXferCount = 0U; hswpmi->State= HAL_SWPMI_STATE_READY; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + hswpmi->ErrorCallback(hswpmi); +#else HAL_SWPMI_ErrorCallback(hswpmi); +#endif } /** * @brief Handle SWPMI Communication Timeout. - * @param hswpmi: SWPMI handle + * @param hswpmi SWPMI handle * @param Flag: specifies the SWPMI flag to check. * @param Tickstart Tick start value * @param Timeout timeout duration. @@ -1513,15 +1909,13 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if ((((HAL_GetTick() - Tickstart) > Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - hswpmi->State = HAL_SWPMI_STATE_READY; + /* Set the SWPMI state ready to be able to start again the process */ + hswpmi->State = HAL_SWPMI_STATE_READY; - status = HAL_TIMEOUT; - break; - } + status = HAL_TIMEOUT; + break; } } @@ -1533,16 +1927,15 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs */ #endif /* HAL_SWPMI_MODULE_ENABLED */ -/** - * @} - */ /** * @} */ -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ +#endif /* SWPMI1 */ + +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h index 2df60ff9ac..2cce8d12f9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h @@ -6,45 +6,25 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_SWPMI_H -#define __STM32L4xx_HAL_SWPMI_H +#ifndef STM32L4xx_HAL_SWPMI_H +#define STM32L4xx_HAL_SWPMI_H #ifdef __cplusplus extern "C" { #endif -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -52,6 +32,8 @@ * @{ */ +#if defined(SWPMI1) + /** @addtogroup SWPMI * @{ */ @@ -70,7 +52,7 @@ typedef struct This parameter can be a value of @ref SWPMI_Voltage_Class */ uint32_t BitRate; /*!< Specifies the SWPMI Bitrate. - This parameter must be a number between 0 and 63. + This parameter must be a number between 0 and 63U. The Bitrate is computed using the following formula: SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) */ @@ -102,36 +84,71 @@ typedef enum /** * @brief SWPMI handle Structure definition */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +typedef struct __SWPMI_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ { - SWPMI_TypeDef *Instance; /* SWPMI registers base address */ + SWPMI_TypeDef *Instance; /*!< SWPMI registers base address */ - SWPMI_InitTypeDef Init; /* SWMPI communication parameters */ + SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */ - uint32_t *pTxBuffPtr; /* Pointer to SWPMI Tx transfer Buffer */ + uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ - uint32_t TxXferSize; /* SWPMI Tx Transfer size */ + uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */ - uint32_t TxXferCount; /* SWPMI Tx Transfer Counter */ + uint32_t TxXferCount; /*!< SWPMI Tx Transfer Counter */ - uint32_t *pRxBuffPtr; /* Pointer to SWPMI Rx transfer Buffer */ + uint32_t *pRxBuffPtr; /*!< Pointer to SWPMI Rx transfer Buffer */ - uint32_t RxXferSize; /* SWPMI Rx Transfer size */ + uint32_t RxXferSize; /*!< SWPMI Rx Transfer size */ - uint32_t RxXferCount; /* SWPMI Rx Transfer Counter */ + uint32_t RxXferCount; /*!< SWPMI Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* SWPMI Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SWPMI Tx DMA Handle parameters */ - DMA_HandleTypeDef *hdmarx; /* SWPMI Rx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SWPMI Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /* SWPMI object */ + HAL_LockTypeDef Lock; /*!< SWPMI object */ - __IO HAL_SWPMI_StateTypeDef State; /* SWPMI communication state */ + __IO HAL_SWPMI_StateTypeDef State; /*!< SWPMI communication state */ - __IO uint32_t ErrorCode; /* SWPMI Error code */ + __IO uint32_t ErrorCode; /*!< SWPMI Error code */ + +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) + void (*RxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */ + void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */ + void (*TxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */ + void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */ + void (*ErrorCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ + void (*MspInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ + void (*MspDeInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ +#endif }SWPMI_HandleTypeDef; +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +/** + * @brief SWPMI callback ID enumeration definition + */ +typedef enum +{ + HAL_SWPMI_RX_COMPLETE_CB_ID = 0x00U, /*!< SWPMI receive complete callback ID */ + HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SWPMI receive half complete callback ID */ + HAL_SWPMI_TX_COMPLETE_CB_ID = 0x02U, /*!< SWPMI transmit complete callback ID */ + HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SWPMI transmit half complete callback ID */ + HAL_SWPMI_ERROR_CB_ID = 0x04U, /*!< SWPMI error callback ID */ + HAL_SWPMI_MSPINIT_CB_ID = 0x05U, /*!< SWPMI MSP init callback ID */ + HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U /*!< SWPMI MSP de-init callback ID */ +}HAL_SWPMI_CallbackIDTypeDef; + +/** + * @brief SWPMI callback pointer definition + */ +typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); +#endif + /** * @} */ @@ -145,11 +162,16 @@ typedef struct * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap * @{ */ -#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */ -#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004) /*!< frame error */ +#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */ +#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */ +#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Transfer timeout */ +#define HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040) /*!< End Tx buffer timeout */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +#define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */ +#endif /** * @} */ @@ -231,123 +253,131 @@ typedef struct */ /** @brief Reset SWPMI handle state. - * @param __HANDLE__: specifies the SWPMI Handle. + * @param __HANDLE__ specifies the SWPMI Handle. * @retval None */ +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) +#endif /** * @brief Enable the SWPMI peripheral. - * @param __HANDLE__: SWPMI handle + * @param __HANDLE__ SWPMI handle * @retval None */ #define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT) /** * @brief Disable the SWPMI peripheral. - * @param __HANDLE__: SWPMI handle + * @param __HANDLE__ SWPMI handle * @retval None */ #define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT) /** @brief Check whether the specified SWPMI flag is set or not. - * @param __HANDLE__: specifies the SWPMI Handle. + * @param __HANDLE__ specifies the SWPMI Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg SWPMI_FLAG_RXBFF : Receive buffer full flag. - * @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag. - * @arg SWPMI_FLAG_RXBERF : Receive CRC error flag. - * @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag. - * @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag. - * @arg SWPMI_FLAG_RXNE : Receive data register not empty. - * @arg SWPMI_FLAG_TXE : Transmit data register empty. - * @arg SWPMI_FLAG_TCF : Transfer complete flag. - * @arg SWPMI_FLAG_SRF : Slave resume flag. - * @arg SWPMI_FLAG_SUSP : SUSPEND flag. - * @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag. + * @arg SWPMI_FLAG_RXBFF Receive buffer full flag. + * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag. + * @arg SWPMI_FLAG_RXBERF Receive CRC error flag. + * @arg SWPMI_FLAG_RXOVRF Receive overrun error flag. + * @arg SWPMI_FLAG_TXUNRF Transmit underrun error flag. + * @arg SWPMI_FLAG_RXNE Receive data register not empty. + * @arg SWPMI_FLAG_TXE Transmit data register empty. + * @arg SWPMI_FLAG_TCF Transfer complete flag. + * @arg SWPMI_FLAG_SRF Slave resume flag. + * @arg SWPMI_FLAG_SUSP SUSPEND flag. + * @arg SWPMI_FLAG_DEACTF DEACTIVATED flag. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SWPMI ISR flag. - * @param __HANDLE__: specifies the SWPMI Handle. + * @param __HANDLE__ specifies the SWPMI Handle. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: - * @arg SWPMI_FLAG_RXBFF : Receive buffer full flag. - * @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag. - * @arg SWPMI_FLAG_RXBERF : Receive CRC error flag. - * @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag. - * @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag. - * @arg SWPMI_FLAG_TCF : Transfer complete flag. - * @arg SWPMI_FLAG_SRF : Slave resume flag. + * @arg SWPMI_FLAG_RXBFF Receive buffer full flag. + * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag. + * @arg SWPMI_FLAG_RXBERF Receive CRC error flag. + * @arg SWPMI_FLAG_RXOVRF Receive overrun error flag. + * @arg SWPMI_FLAG_TXUNRF Transmit underrun error flag. + * @arg SWPMI_FLAG_TCF Transfer complete flag. + * @arg SWPMI_FLAG_SRF Slave resume flag. * @retval None */ #define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__)) /** @brief Enable the specified SWPMI interrupt. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __INTERRUPT__: specifies the SWPMI interrupt source to enable. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __INTERRUPT__ specifies the SWPMI interrupt source to enable. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBEIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval None */ #define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) /** @brief Disable the specified SWPMI interrupt. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __INTERRUPT__: specifies the SWPMI interrupt source to disable. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __INTERRUPT__ specifies the SWPMI interrupt source to disable. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBEIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval None */ #define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) /** @brief Check whether the specified SWPMI interrupt has occurred or not. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __IT__: specifies the SWPMI interrupt to check. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __IT__ specifies the SWPMI interrupt to check. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBERIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__)) /** @brief Check whether the specified SWPMI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SWPMI Handle. - * @param __IT__: specifies the SWPMI interrupt source to check. + * @param __HANDLE__ specifies the SWPMI Handle. + * @param __IT__ specifies the SWPMI interrupt source to check. * This parameter can be one of the following values: - * @arg SWPMI_IT_SRIE : Slave resume interrupt. - * @arg SWPMI_IT_TCIE : Transmit complete interrupt. - * @arg SWPMI_IT_TIE : Transmit interrupt. - * @arg SWPMI_IT_RIE : Receive interrupt. - * @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. - * @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. - * @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt. - * @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. - * @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. + * @arg SWPMI_IT_SRIE Slave resume interrupt. + * @arg SWPMI_IT_TCIE Transmit complete interrupt. + * @arg SWPMI_IT_TIE Transmit interrupt. + * @arg SWPMI_IT_RIE Receive interrupt. + * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt. + * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt. + * @arg SWPMI_IT_RXBERIE Receive CRC error interrupt. + * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt. + * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) @@ -366,6 +396,15 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi); +#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) +/* SWPMI callbacks register/unregister functions ********************************/ +HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID, + pSWPMI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, + HAL_SWPMI_CallbackIDTypeDef CallbackID); +#endif + /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); @@ -404,7 +443,7 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); /** @defgroup SWPMI_Private_Variables SWPMI Private Variables * @{ */ - + /** * @} */ @@ -427,7 +466,7 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); #define IS_SWPMI_VOLTAGE_CLASS(__CLASS__) (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \ ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B)) -#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63)) +#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63U)) #define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \ @@ -445,18 +484,16 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); * @} */ +#endif /* SWPMI1 */ + /** * @} */ -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_HAL_SWPMI_H */ +#endif /* STM32L4xx_HAL_SWPMI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c index 2aecea52dd..cea3a1a6e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c @@ -5,30 +5,30 @@ * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration + * + TIM OCRef clear configuration + * + TIM External Clock configuration @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -42,6 +42,9 @@ (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== @@ -76,8 +79,8 @@ PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: @@ -92,33 +95,90 @@ HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -142,6 +202,9 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); @@ -149,26 +212,31 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); + uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); + uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ */ -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @verbatim ============================================================================== ##### Time Base functions ##### @@ -190,17 +258,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -211,29 +279,41 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM Base peripheral + * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ @@ -247,8 +327,17 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -261,7 +350,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim TIM handle + * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -275,8 +364,8 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Base MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -292,22 +381,28 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -315,22 +410,22 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -338,19 +433,25 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -358,9 +459,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ @@ -377,23 +478,25 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM handle + * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if((pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -402,20 +505,33 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->State = HAL_TIM_STATE_BUSY; } } - /* Set the DMA Period elapsed callback */ + else + { + /* nothing to do */ + } + + /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -423,9 +539,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM handle + * @param htim TIM Base handle * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ @@ -434,6 +550,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); @@ -448,41 +566,41 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @verbatim ============================================================================== - ##### Time Output Compare functions ##### + ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -493,29 +611,41 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ @@ -524,13 +654,22 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - htim->State = HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -543,7 +682,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM handle + * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -557,8 +696,8 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Output Compare MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -583,23 +722,29 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -607,7 +752,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM handle + * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -617,7 +762,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -626,9 +771,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -641,19 +786,19 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM OC handle + * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -663,45 +808,49 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -716,10 +865,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -731,40 +878,40 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -784,24 +931,24 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -810,87 +957,110 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + switch (Channel) { case TIM_CHANNEL_1: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; - default: - break; + default: + break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -905,10 +1075,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -920,40 +1088,44 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; default: - break; + break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -971,41 +1143,41 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @verbatim ============================================================================== - ##### Time PWM functions ##### + ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. + (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM handle + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -1016,30 +1188,42 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM peripheral - * @param htim TIM handle + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1052,8 +1236,17 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1066,7 +1259,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim TIM handle + * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1080,8 +1273,8 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM PWM MSP. - * @param htim TIM handle + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1106,23 +1299,29 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1130,7 +1329,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1140,7 +1339,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1149,9 +1348,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -1167,7 +1366,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1175,9 +1374,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1187,45 +1387,49 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1233,7 +1437,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1241,8 +1445,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1253,40 +1457,40 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -1299,7 +1503,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1309,19 +1513,21 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -1330,87 +1536,109 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + switch (Channel) { case TIM_CHANNEL_1: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1418,7 +1646,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM handle + * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1426,7 +1654,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1438,40 +1666,44 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; default: - break; + break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -1489,41 +1721,41 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @verbatim ============================================================================== - ##### Time Input Capture functions ##### + ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -1534,29 +1766,41 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM peripheral + * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ @@ -1570,8 +1814,17 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1583,8 +1836,8 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) } /** - * @brief Initializes the TIM INput Capture MSP. - * @param htim TIM handle + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1598,7 +1851,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Input Capture MSP. + * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ @@ -1622,17 +1875,23 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1640,7 +1899,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim TIM handle + * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1648,7 +1907,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1674,9 +1933,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1686,38 +1947,42 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1725,7 +1990,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM handle + * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1733,7 +1998,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1745,32 +2010,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; } - break; default: - break; + break; } /* Disable the Input Capture channel */ @@ -1784,7 +2049,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /** - * @brief Starts the TIM Input Capture measurement on in DMA mode. + * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: @@ -1795,20 +2060,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if((pData == 0 ) && (Length > 0)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } @@ -1817,82 +2084,102 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } switch (Channel) { case TIM_CHANNEL_1: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; case TIM_CHANNEL_4: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; } - break; default: - break; + break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1908,7 +2195,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -1921,32 +2208,36 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; default: - break; + break; } /* Disable the Input Capture channel */ @@ -1965,35 +2256,35 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @verbatim ============================================================================== - ##### Time One Pulse functions ##### + ##### TIM One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @param htim TIM OnePulse handle + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. @@ -2003,7 +2294,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } @@ -2015,17 +2306,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); @@ -2037,13 +2340,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul htim->Instance->CR1 |= OnePulseMode; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM One Pulse + * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ @@ -2057,8 +2360,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2071,7 +2383,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM handle + * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2085,8 +2397,8 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM One Pulse MSP. - * @param htim TIM handle + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2107,7 +2419,7 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2125,7 +2437,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -2143,7 +2455,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2158,9 +2470,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } @@ -2179,7 +2491,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2203,7 +2515,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -2221,7 +2533,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ @@ -2241,14 +2553,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; @@ -2258,54 +2570,57 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @verbatim ============================================================================== - ##### Time Encoder functions ##### + ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2316,20 +2631,32 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); @@ -2348,18 +2675,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; @@ -2371,15 +2698,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini htim->Instance->CCER = tmpccer; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM Encoder interface - * @param htim TIM Encoder handle + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2392,8 +2719,17 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2406,7 +2742,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM handle + * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2420,8 +2756,8 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2443,7 +2779,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2455,21 +2791,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; } - break; case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - break; default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - break; } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); @@ -2487,7 +2823,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2500,21 +2836,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; } - break; case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; } - break; default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; } - break; } /* Disable the Peripheral */ @@ -2533,7 +2869,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2547,15 +2883,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; default : { @@ -2563,8 +2899,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; } /* Enable the Peripheral */ @@ -2583,7 +2919,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2591,19 +2927,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) + if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } - else if(Channel == TIM_CHANNEL_2) + else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { @@ -2637,19 +2973,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } @@ -2658,20 +2995,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } switch (Channel) { case TIM_CHANNEL_1: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); @@ -2680,19 +3024,22 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; } - break; case TIM_CHANNEL_2: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); @@ -2701,30 +3048,37 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - break; case TIM_CHANNEL_ALL: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } - /* Set the DMA Period elapsed callback */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ @@ -2735,11 +3089,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; default: - break; + break; } /* Return function status */ return HAL_OK; @@ -2754,7 +3108,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ @@ -2762,19 +3116,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) + if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } - else if(Channel == TIM_CHANNEL_2) + else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } else { @@ -2784,6 +3140,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } /* Disable the Peripheral */ @@ -2800,8 +3158,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * + * @brief TIM IRQ handler management + * @verbatim ============================================================================== ##### IRQ handler management ##### @@ -2820,126 +3178,191 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - HAL_TIMEx_CommutationCallback(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } @@ -2948,9 +3371,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @} */ -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -2983,7 +3406,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, + TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ @@ -3005,8 +3428,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_2: { @@ -3015,51 +3438,51 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_3: { /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; } - break; case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; } - break; default: - break; + break; } htim->State = HAL_TIM_STATE_READY; @@ -3074,7 +3497,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channels to be enabled + * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3082,7 +3505,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -3100,9 +3523,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; @@ -3124,7 +3547,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { @@ -3132,9 +3555,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; @@ -3148,15 +3571,15 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } htim->State = HAL_TIM_STATE_READY; @@ -3182,7 +3605,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, + TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ @@ -3212,8 +3635,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; } - break; case TIM_CHANNEL_2: { @@ -3228,9 +3651,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; } - break; case TIM_CHANNEL_3: { @@ -3243,11 +3666,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; } - break; case TIM_CHANNEL_4: { @@ -3260,48 +3683,48 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; } - break; case TIM_CHANNEL_5: { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - /* Configure the Channel 5 in PWM mode */ + /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; } - break; case TIM_CHANNEL_6: { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - /* Configure the Channel 5 in PWM mode */ + /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - /* Configure the Output Fast mode */ + /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; } - break; default: - break; + break; } htim->State = HAL_TIM_STATE_READY; @@ -3316,17 +3739,18 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM Channels to be enabled + * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM Channels to be enabled + * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; @@ -3334,14 +3758,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - if(OutputChannel != InputChannel) + if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; - /* Extract the Ouput compare configuration from sConfig structure */ + /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; @@ -3356,17 +3780,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); + break; } - break; case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); + break; } - break; default: - break; + break; } switch (InputChannel) @@ -3388,8 +3812,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; } - break; case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -3407,11 +3831,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; } - break; default: - break; + break; } htim->State = HAL_TIM_STATE_READY; @@ -3429,8 +3853,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write - * This parameters can be on of the following values: + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR @@ -3449,9 +3873,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_OR2 + * @arg TIM_DMABASE_OR3 * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: + * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source @@ -3461,11 +3890,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) + uint32_t *BurstBuffer, uint32_t BurstLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -3475,11 +3905,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3488,102 +3918,140 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->State = HAL_TIM_STATE_BUSY; } } - switch(BurstRequestSrc) + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC1: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC2: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC3: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC4: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_COM: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_TRIGGER: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; default: - break; + break; } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -3597,63 +4065,67 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; } - break; case TIM_DMA_CC1: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_DMA_CC2: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_DMA_CC3: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_DMA_CC4: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; case TIM_DMA_COM: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; } - break; case TIM_DMA_TRIGGER: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; } - break; default: - break; + break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read - * This parameters can be on of the following values: + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR @@ -3672,9 +4144,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_OR2 + * @arg TIM_DMABASE_OR3 * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: + * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source @@ -3684,11 +4161,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -3698,11 +4176,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3711,98 +4189,130 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->State = HAL_TIM_STATE_BUSY; } } - switch(BurstRequestSrc) + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC1: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC2: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA capture/compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC3: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_CC4: { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_COM: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; case TIM_DMA_TRIGGER: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; } - break; default: - break; + break; } /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; + htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); @@ -3821,56 +4331,60 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; } - break; case TIM_DMA_CC1: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_DMA_CC2: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_DMA_CC3: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; case TIM_DMA_CC4: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; } - break; case TIM_DMA_COM: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; } - break; case TIM_DMA_TRIGGER: { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; } - break; default: - break; + break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -3887,6 +4401,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). * @retval HAL status */ @@ -3921,20 +4439,18 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @retval None + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { - uint32_t tmpsmcr = 0; - /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -3942,28 +4458,20 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); + htim->State = HAL_TIM_STATE_BUSY; + switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } case TIM_CLEARINPUTSOURCE_OCREFCLR: { /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); } break; @@ -3974,110 +4482,120 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + break; } - break; - default: - break; + default: + break; } switch (Channel) { case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; + } case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; - } + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } - break; + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } default: - break; + break; } + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); return HAL_OK; @@ -4090,9 +4608,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); @@ -4110,15 +4628,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo switch (sClockSourceConfig->ClockSource) { - case TIM_CLOCKSOURCE_INTERNAL: + case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; + break; } - break; - case TIM_CLOCKSOURCE_ETRMODE1: + case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); @@ -4133,18 +4649,16 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; + break; } - break; - case TIM_CLOCKSOURCE_ETRMODE2: + case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); @@ -4161,10 +4675,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; + break; } - break; - case TIM_CLOCKSOURCE_TI1: + case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); @@ -4177,10 +4691,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; } - break; - case TIM_CLOCKSOURCE_TI2: + case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); @@ -4193,10 +4707,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; } - break; - case TIM_CLOCKSOURCE_TI1ED: + case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); @@ -4209,47 +4723,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; } - break; - case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; } - break; - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; + default: + break; } htim->State = HAL_TIM_STATE_READY; @@ -4272,7 +4762,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { - uint32_t tmpcr2 = 0; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); @@ -4298,11 +4788,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -4313,7 +4803,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI htim->State = HAL_TIM_STATE_BUSY; - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); @@ -4326,21 +4821,21 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI __HAL_UNLOCK(htim); return HAL_OK; - } +} /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { - /* Check the parameters */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); @@ -4349,7 +4844,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, htim->State = HAL_TIM_STATE_BUSY; - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); @@ -4362,7 +4862,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, __HAL_UNLOCK(htim); return HAL_OK; - } +} /** * @brief Read the captured value from Capture Compare unit @@ -4377,13 +4877,11 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpreg = 0; - - __HAL_LOCK(htim); + uint32_t tmpreg = 0U; switch (Channel) { - case TIM_CHANNEL_1: + case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -4393,7 +4891,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - case TIM_CHANNEL_2: + case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -4404,7 +4902,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - case TIM_CHANNEL_3: + case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); @@ -4415,7 +4913,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - case TIM_CHANNEL_4: + case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -4426,11 +4924,10 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - default: - break; + default: + break; } - __HAL_UNLOCK(htim); return tmpreg; } @@ -4439,19 +4936,19 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * + * @brief TIM Callbacks functions + * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback @endverbatim * @{ @@ -4468,10 +4965,25 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ - } + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + /** * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle @@ -4483,9 +4995,10 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } + /** * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle @@ -4497,7 +5010,22 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file */ } @@ -4512,7 +5040,22 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } @@ -4531,6 +5074,21 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) */ } +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + /** * @brief Timer error callback in non-blocking mode * @param htim TIM handle @@ -4546,13 +5104,506 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) */ } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -4577,7 +5628,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC handle state. - * @param htim TIM Ouput Compare handle + * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4617,7 +5668,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder handle + * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4629,6 +5680,14 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @} */ +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. @@ -4636,11 +5695,15 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -4650,9 +5713,9 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { @@ -4670,11 +5733,61 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } + else + { + /* nothing to do */ + } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief TIM DMA Capture complete callback. * @param hdma pointer to DMA handle. @@ -4682,9 +5795,9 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { @@ -4702,8 +5815,57 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } + else + { + /* nothing to do */ + } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -4715,11 +5877,33 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -4729,11 +5913,33 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** @@ -4744,7 +5950,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ @@ -4755,7 +5961,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= Structure->CounterMode; } - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; @@ -4763,8 +5969,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) } /* Set the auto-reload preload */ - tmpcr1 &= ~TIM_CR1_ARPE; - tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; @@ -4772,7 +5977,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) TIMx->ARR = (uint32_t)Structure->Period ; /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; + TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { @@ -4781,23 +5986,23 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) } /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediately */ + and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; } /** - * @brief Time Ouput Compare 1 configuration + * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ @@ -4819,7 +6024,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); @@ -4832,7 +6037,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer &= ~TIM_CCER_CC1NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -4846,6 +6051,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } + /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -4860,16 +6066,16 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Time Ouput Compare 2 configuration + * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4887,27 +6093,27 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); + tmpccer |= (OC_Config->OCPolarity << 4U); - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); + tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -4917,9 +6123,9 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpcr2 &= ~TIM_CR2_OIS2; tmpcr2 &= ~TIM_CR2_OIS2N; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2); + tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2); + tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ @@ -4936,16 +6142,16 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Time Ouput Compare 3 configuration + * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -4967,21 +6173,21 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); + tmpccer |= (OC_Config->OCPolarity << 8U); - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); + tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); @@ -4991,9 +6197,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); + tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); + tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ @@ -5010,16 +6216,16 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Time Ouput Compare 4 configuration + * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -5037,21 +6243,23 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); + tmpccer |= (OC_Config->OCPolarity << 12U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { + /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - /* Reset the Output Compare IDLE State */ + /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; + /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6); + tmpcr2 |= (OC_Config->OCIdleState << 6U); } /* Write to TIMx CR2 */ @@ -5068,7 +6276,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /** - * @brief Timer Ouput Compare 5 configuration + * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None @@ -5076,9 +6284,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; @@ -5098,14 +6306,14 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16); + tmpccer |= (OC_Config->OCPolarity << 16U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8); + tmpcr2 |= (OC_Config->OCIdleState << 8U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -5121,7 +6329,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, } /** - * @brief Timer Ouput Compare 6 configuration + * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None @@ -5129,9 +6337,9 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; @@ -5146,19 +6354,19 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20); + tmpccer |= (OC_Config->OCPolarity << 20U); - if(IS_TIM_BREAK_INSTANCE(TIMx)) + if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10); + tmpcr2 |= (OC_Config->OCIdleState << 10U); } /* Write to TIMx CR2 */ @@ -5174,12 +6382,18 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIMx->CCER = tmpccer; } -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -5200,7 +6414,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { - case TIM_TS_ETRF: + case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); @@ -5212,15 +6426,20 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; } - break; - case TIM_TS_TI1F_ED: + case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; @@ -5228,16 +6447,15 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; - + break; } - break; - case TIM_TS_TI1FP1: + case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); @@ -5248,10 +6466,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; } - break; - case TIM_TS_TI2FP2: + case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -5260,42 +6478,25 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; } - break; - case TIM_TS_ITR0: + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; } - break; - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; + default: + break; } + return HAL_OK; } /** @@ -5303,14 +6504,14 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5321,8 +6522,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -5330,7 +6531,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ tmpccer = TIMx->CCER; /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; @@ -5342,7 +6543,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5358,17 +6559,17 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; @@ -5377,7 +6578,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5393,14 +6594,14 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5409,10 +6610,10 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) + uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5421,15 +6622,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); + tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5441,17 +6642,17 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5460,11 +6661,11 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5476,14 +6677,14 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5492,10 +6693,10 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) + uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2; + uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -5508,11 +6709,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5524,14 +6725,14 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 @@ -5540,10 +6741,10 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) + uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2; + uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -5552,15 +6753,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); + tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5582,40 +6783,40 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr; - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; @@ -5623,7 +6824,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; @@ -5638,27 +6839,55 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { - uint32_t tmp = 0; + uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); - tmp = TIM_CCER_CC1E << Channel; + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h index bfc0194b00..2ef55fb52b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_H -#define __STM32L4xx_HAL_TIM_H +#ifndef STM32L4xx_HAL_TIM_H +#define STM32L4xx_HAL_TIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -81,8 +65,8 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -104,20 +88,20 @@ typedef struct uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ - uint32_t OCFastMode; /*!< Specifies the Fast mode state. + uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** @@ -136,15 +120,15 @@ typedef struct uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ + @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -156,14 +140,13 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; - /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -208,7 +191,6 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; - /** * @brief Clock Configuration Handle Structure definition */ @@ -220,12 +202,12 @@ typedef struct This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; /** - * @brief Clear Input Configuration Handle Structure definition + * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { @@ -236,41 +218,43 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition * @note Advanced timers provide TRGO2 internal line which is redirected * to the ADC */ -typedef struct { +typedef struct +{ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ + This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; + This parameter can be a value of @ref TIM_Master_Slave_Mode */ +} TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ + This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ + This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ + This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_SlaveConfigTypeDef; +} TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition @@ -279,28 +263,28 @@ typedef struct { */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2State; /*!< TIM Break2 State + This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + uint32_t Break2Polarity; /*!< TIM Break2 input polarity + This parameter can be a value of @ref TIM_Break2_Polarity */ + uint32_t Break2Filter; /*!< TIM break2 input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** @@ -308,40 +292,119 @@ typedef struct */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */ - HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} @@ -356,9 +419,9 @@ typedef struct /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ /** * @} */ @@ -366,37 +429,37 @@ typedef struct /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_DMAR (0x00000013) -#define TIM_DMABASE_OR1 (0x00000014) -#define TIM_DMABASE_CCMR3 (0x00000015) -#define TIM_DMABASE_CCR5 (0x00000016) -#define TIM_DMABASE_CCR6 (0x00000017) -#define TIM_DMABASE_OR2 (0x00000018) -#define TIM_DMABASE_OR3 (0x00000019) +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR1 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#define TIM_DMABASE_OR2 0x00000018U +#define TIM_DMABASE_OR3 0x00000019U /** * @} */ -/** @defgroup TIM_Event_Source TIM Extended Event Source +/** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ @@ -415,8 +478,8 @@ typedef struct /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} @@ -425,8 +488,8 @@ typedef struct /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ @@ -434,10 +497,10 @@ typedef struct /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ @@ -445,11 +508,11 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ @@ -457,18 +520,9 @@ typedef struct /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ @@ -476,17 +530,18 @@ typedef struct /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + /** * @} */ @@ -494,8 +549,17 @@ typedef struct /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ @@ -503,8 +567,8 @@ typedef struct /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ @@ -512,8 +576,8 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ @@ -521,8 +585,8 @@ typedef struct /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ @@ -530,8 +594,8 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ -#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ @@ -539,9 +603,9 @@ typedef struct /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ @@ -549,11 +613,11 @@ typedef struct /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ @@ -561,10 +625,10 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ @@ -572,8 +636,8 @@ typedef struct /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -581,9 +645,9 @@ typedef struct /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ /** * @} */ @@ -591,14 +655,14 @@ typedef struct /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_COM (TIM_DIER_COMIE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) -#define TIM_IT_BREAK (TIM_DIER_BIE) +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ /** * @} */ @@ -606,8 +670,8 @@ typedef struct /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ -#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ @@ -615,13 +679,13 @@ typedef struct /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_COM (TIM_DIER_COMDE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ @@ -629,22 +693,22 @@ typedef struct /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_CC5 (TIM_SR_CC5IF) -#define TIM_FLAG_CC6 (TIM_SR_CC6IF) -#define TIM_FLAG_COM (TIM_SR_COMIF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_BREAK (TIM_SR_BIF) -#define TIM_FLAG_BREAK2 (TIM_SR_B2IF) -#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ /** * @} */ @@ -652,13 +716,13 @@ typedef struct /** @defgroup TIM_Channel TIM Channel * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ @@ -666,16 +730,16 @@ typedef struct /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ @@ -683,9 +747,9 @@ typedef struct /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** @@ -695,10 +759,10 @@ typedef struct /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ @@ -706,8 +770,8 @@ typedef struct /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ @@ -715,10 +779,10 @@ typedef struct /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ @@ -726,8 +790,8 @@ typedef struct /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ @@ -735,18 +799,18 @@ typedef struct /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ @@ -754,8 +818,8 @@ typedef struct /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ -#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ @@ -763,8 +827,8 @@ typedef struct /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) -#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ @@ -772,8 +836,8 @@ typedef struct /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) -#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ /** * @} */ @@ -781,8 +845,8 @@ typedef struct /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity * @{ */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) -#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ /** * @} */ @@ -790,8 +854,9 @@ typedef struct /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ @@ -799,10 +864,10 @@ typedef struct /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ @@ -810,14 +875,14 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ /** * @} */ @@ -825,22 +890,22 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) -#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) -#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) -#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ /** * @} */ @@ -848,8 +913,8 @@ typedef struct /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ @@ -857,12 +922,12 @@ typedef struct /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) -#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ /** * @} */ @@ -870,21 +935,20 @@ typedef struct /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) -#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) - -#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) -#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ /** * @} */ @@ -892,15 +956,15 @@ typedef struct /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ @@ -908,8 +972,8 @@ typedef struct /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ @@ -920,10 +984,10 @@ typedef struct /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ @@ -931,8 +995,8 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ @@ -940,24 +1004,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -965,13 +1029,13 @@ typedef struct /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -979,10 +1043,10 @@ typedef struct /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ @@ -990,10 +1054,10 @@ typedef struct /** @defgroup TIM_Break_System TIM Break System * @{ */ -#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ -#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ /** * @} */ @@ -1012,13 +1076,33 @@ typedef struct * @param __HANDLE__ TIM handle. * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None - */ + */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** @@ -1034,15 +1118,15 @@ typedef struct * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) /** * @brief Disable the TIM main Output. @@ -1051,15 +1135,15 @@ typedef struct * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) /** * @brief Disable the TIM main Output. @@ -1085,7 +1169,6 @@ typedef struct */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. @@ -1195,7 +1278,8 @@ typedef struct * @arg TIM_IT_BREAK: Break interrupt * @retval The state of TIM_IT (SET or RESET). */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle @@ -1222,7 +1306,6 @@ mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. @@ -1244,8 +1327,7 @@ mode. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. @@ -1254,18 +1336,17 @@ mode. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. @@ -1278,11 +1359,11 @@ mode. * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) /** * @brief Get the TIM Clock Division value on runtime. @@ -1292,8 +1373,7 @@ mode. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. @@ -1313,10 +1393,10 @@ mode. * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) /** * @brief Get the TIM Input Capture prescaler on runtime. @@ -1335,9 +1415,9 @@ mode. */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. @@ -1354,12 +1434,12 @@ mode. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. @@ -1375,12 +1455,12 @@ mode. * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) /** * @brief Set the TIM Output compare preload. @@ -1396,12 +1476,12 @@ mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) /** * @brief Reset the TIM Output compare preload. @@ -1417,28 +1497,27 @@ mode. * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter + * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow @@ -1446,8 +1525,7 @@ mode. * _ Update generation through the slave mode controller * @retval None */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. @@ -1465,10 +1543,10 @@ mode. * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) /** * @} @@ -1492,7 +1570,6 @@ mode. /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ - #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) @@ -1515,17 +1592,15 @@ mode. ((__BASE__) == TIM_DMABASE_CCR3) || \ ((__BASE__) == TIM_DMABASE_CCR4) || \ ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR1) || \ ((__BASE__) == TIM_DMABASE_CCMR3) || \ ((__BASE__) == TIM_DMABASE_CCR5) || \ ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_OR1) || \ ((__BASE__) == TIM_DMABASE_OR2) || \ ((__BASE__) == TIM_DMABASE_OR3)) - #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ @@ -1613,7 +1688,7 @@ mode. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) @@ -1623,8 +1698,7 @@ mode. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ ((__STATE__) == TIM_OSSR_DISABLE)) @@ -1637,7 +1711,7 @@ mode. ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ ((__LEVEL__) == TIM_LOCKLEVEL_3)) -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF) +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ @@ -1655,7 +1729,7 @@ mode. #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) -#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000)) +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ @@ -1695,7 +1769,7 @@ mode. ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ @@ -1725,7 +1799,6 @@ mode. ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_NONE)) - #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ @@ -1737,7 +1810,7 @@ mode. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) @@ -1761,38 +1834,41 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12)))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) /** * @} @@ -1807,10 +1883,10 @@ mode. * @{ */ -/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); @@ -1829,10 +1905,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); @@ -1851,10 +1927,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); @@ -1873,10 +1949,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); @@ -1895,10 +1971,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); @@ -1914,30 +1990,31 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * @{ - */ +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ +/* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management + * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ @@ -1946,25 +2023,27 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @} */ -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -1973,24 +2052,36 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions + * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); @@ -2009,21 +2100,28 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions -* @{ -*/ + * @{ + */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** -* @} -*/ + * @} + */ /* End of private functions --------------------------------------------------*/ /** @@ -2038,6 +2136,6 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat } #endif -#endif /* __STM32L4xx_HAL_TIM_H */ +#endif /* STM32L4xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c index bf656a16fd..da5b0de84c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c @@ -49,11 +49,11 @@ (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() @@ -61,37 +61,20 @@ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -109,16 +92,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define BDTR_BKF_SHIFT (16) -#define BDTR_BK2F_SHIFT (20) -#define TIMx_ETRSEL_MASK ((uint32_t)0x0003C000) - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Private functions ---------------------------------------------------------*/ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions @@ -148,20 +125,21 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim TIM Encoder Interface handle + * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ - if(htim == NULL) + if (htim == NULL) { return HAL_ERROR; } + /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); @@ -170,13 +148,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - if(htim->State == HAL_TIM_STATE_RESET) + if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ @@ -221,14 +211,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the TIM Hall Sensor interface - * @param htim TIM Hall Sensor handle + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -241,8 +231,17 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -255,7 +254,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM handle + * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -269,8 +268,8 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim TIM handle + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -285,11 +284,13 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); @@ -297,8 +298,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -306,7 +311,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) @@ -327,11 +332,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); @@ -342,8 +349,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -351,7 +362,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) @@ -375,23 +386,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor handle + * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -400,23 +413,34 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - /* Set the DMA Input Capture 1 Callback */ + /* Set the DMA Input Capture 1 Callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -424,7 +448,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM handle + * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) @@ -440,6 +464,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); @@ -484,17 +509,23 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -519,7 +550,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -542,6 +573,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -551,32 +584,26 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Enable the TIM Break interrupt */ @@ -585,11 +612,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -608,8 +639,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; - + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -619,32 +649,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Disable the Capture compare channel N */ @@ -652,12 +675,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -682,16 +705,18 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -700,84 +725,86 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } + switch (Channel) { case TIM_CHANNEL_1: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: -{ - /* Set the DMA Period elapsed callback */ + { + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -805,38 +832,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -895,17 +918,23 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -929,7 +958,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -952,6 +981,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -961,32 +992,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Enable the TIM Break interrupt */ @@ -995,11 +1019,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1016,9 +1044,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1029,46 +1057,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; default: - break; + break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1093,16 +1113,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); if(htim->State == HAL_TIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } else if(htim->State == HAL_TIM_STATE_READY) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1111,84 +1133,85 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->State = HAL_TIM_STATE_BUSY; } } + else + { + /* nothing to do */ + } switch (Channel) { case TIM_CHANNEL_1: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; } - break; case TIM_CHANNEL_2: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; } - break; case TIM_CHANNEL_3: { - /* Set the DMA Period elapsed callback */ + /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } /* Return function status */ return HAL_OK; @@ -1216,38 +1239,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; } - break; case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; } - break; case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; default: - break; + break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1293,14 +1312,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { +{ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Enable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ @@ -1326,7 +1345,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1360,7 +1379,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /* Enable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - /* Enable the Main Ouput */ + /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ @@ -1391,7 +1410,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - /* Disable the Main Ouput */ + /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ @@ -1414,13 +1433,13 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t ============================================================================== [..] This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. - (+) Enable or disable channel grouping + (+) Enable or disable channel grouping. @endverbatim * @{ @@ -1448,7 +1467,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1470,6 +1490,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + __HAL_UNLOCK(htim); return HAL_OK; @@ -1497,7 +1523,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1519,7 +1546,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; - /* Enable the Commutation Interrupt Request */ + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); @@ -1550,7 +1580,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1575,9 +1606,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); @@ -1595,7 +1630,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef * sMasterConfig) + TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -1608,7 +1643,10 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Check input state */ __HAL_LOCK(htim); - /* Get the TIMx CR2 register value */ + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ @@ -1642,13 +1680,16 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); return HAL_OK; } /** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that @@ -1656,9 +1697,10 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { - uint32_t tmpbdtr = 0; + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -1685,8 +1727,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -1696,7 +1737,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); /* Set the BREAK2 input related BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } @@ -1724,142 +1765,116 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { - uint32_t tmporx = 0; - uint32_t bkin_enable_mask = 0; - uint32_t bkin_polarity_mask = 0; - uint32_t bkin_enable_bitpos = 0; - uint32_t bkin_polarity_bitpos = 0; + uint32_t tmporx; + uint32_t bkin_enable_mask = 0U; + uint32_t bkin_polarity_mask = 0U; + uint32_t bkin_enable_bitpos = 0U; + uint32_t bkin_polarity_bitpos = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined(DFSDM1_Channel0) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) { assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); } #else - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +#endif /* DFSDM1_Channel0 */ /* Check input state */ __HAL_LOCK(htim); - switch(sBreakInputConfig->Source) + switch (sBreakInputConfig->Source) { - case TIM_BREAKINPUTSOURCE_BKIN: + case TIM_BREAKINPUTSOURCE_BKIN: { bkin_enable_mask = TIM1_OR2_BKINE; - bkin_enable_bitpos = 0; + bkin_enable_bitpos = TIM1_OR2_BKINE_Pos; bkin_polarity_mask = TIM1_OR2_BKINP; - bkin_polarity_bitpos = 9; + bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos; + break; } - break; - case TIM_BREAKINPUTSOURCE_COMP1: + case TIM_BREAKINPUTSOURCE_COMP1: { bkin_enable_mask = TIM1_OR2_BKCMP1E; - bkin_enable_bitpos = 1; + bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos; bkin_polarity_mask = TIM1_OR2_BKCMP1P; - bkin_polarity_bitpos = 10; + bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos; + break; } - break; - case TIM_BREAKINPUTSOURCE_COMP2: + case TIM_BREAKINPUTSOURCE_COMP2: { bkin_enable_mask = TIM1_OR2_BKCMP2E; - bkin_enable_bitpos = 2; + bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos; bkin_polarity_mask = TIM1_OR2_BKCMP2P; - bkin_polarity_bitpos = 11; + bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos; + break; } - break; - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - case TIM_BREAKINPUTSOURCE_DFSDM1: +#if defined(DFSDM1_Channel0) + case TIM_BREAKINPUTSOURCE_DFSDM1: { bkin_enable_mask = TIM1_OR2_BKDF1BK0E; - bkin_enable_bitpos = 8; + bkin_enable_bitpos = 8U; + break; } - break; -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DFSDM1_Channel0 */ - default: - break; + default: + break; } - switch(BreakInput) + switch (BreakInput) { case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_OR2 register value */ + tmporx = htim->Instance->OR2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ { - /* Get the TIMx_OR2 register value */ - tmporx = htim->Instance->OR2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmporx; + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } - break; - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_OR3 register value */ - tmporx = htim->Instance->OR3; - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR3 */ - htim->Instance->OR3 = tmporx; - } + /* Set TIMx_OR2 */ + htim->Instance->OR2 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_OR3 register value */ + tmporx = htim->Instance->OR3; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_OR3 */ + htim->Instance->OR3 = tmporx; + break; + } + default: break; - default: - break; } __HAL_UNLOCK(htim); @@ -1870,9 +1885,22 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. - * @param Remap: specifies the TIM remapping source. + * @param Remap specifies the TIM remapping source. + @if STM32L422xx + * For TIM1, the parameter is a combination of 2 fields (field1 | field2): * - @if STM32L486xx + * field1 can have the following values: + * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * + * field2 can have the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * + @endif +@if STM32L486xx * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4): * * field1 can have the following values: @@ -1935,6 +1963,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output @endif + @if STM32L422xx + * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): + * + * field1 can have the following values: + * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 + * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF + * + * field2 can have the following values: + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * + * field3 can have the following values: + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * + @endif @if STM32L443xx * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): * @@ -1994,7 +2039,20 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant * @endif - * For TIM15, the parameter is a combination of 3 fields (field1 | field2): + @if STM32L422xx + * For TIM15, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE + * + * field2 can have the following values: + * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection + * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively + * + @endif + @if STM32L443xx + * For TIM15, the parameter is a combination of 2 fields (field1 | field2): * * field1 can have the following values: * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO @@ -2006,6 +2064,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * + @endif @if STM32L486xx * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI @@ -2013,6 +2072,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt * @endif + @if STM32L422xx + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt + * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) + * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source) + * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO + * + @endif @if STM32L443xx * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO @@ -2036,8 +2106,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - uint32_t tmpor1 = 0; - uint32_t tmpor2 = 0; + uint32_t tmpor1 = 0U; + uint32_t tmpor2 = 0U; __HAL_LOCK(htim); @@ -2049,8 +2119,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) { tmpor2 = htim->Instance->OR2; - tmpor2 &= ~TIMx_ETRSEL_MASK; - tmpor2 |= (Remap & TIMx_ETRSEL_MASK); + tmpor2 &= ~TIM1_OR2_ETRSEL_Msk; + tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk); /* Set TIMx_OR2 */ htim->Instance->OR2 = tmpor2; @@ -2058,13 +2128,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /* Set other remapping capabilities */ tmpor1 = Remap; - tmpor1 &= ~TIMx_ETRSEL_MASK; + tmpor1 &= ~TIM1_OR2_ETRSEL_Msk; /* Set TIMx_OR1 */ htim->Instance->OR1 = tmpor1; - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -2093,11 +2161,12 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan htim->State = HAL_TIM_STATE_BUSY; /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); /* Set GC5Cx bit fields */ htim->Instance->CCR5 |= Channels; + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); @@ -2130,13 +2199,27 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan * @param htim TIM handle * @retval None */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file */ } @@ -2155,6 +2238,20 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) */ } +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} /** * @} */ @@ -2188,6 +2285,15 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @} */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. @@ -2195,38 +2301,62 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State= HAL_TIM_STATE_READY; + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; - HAL_TIMEx_CommutationCallback(htim); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { - uint32_t tmp = 0; + uint32_t tmp; - tmp = TIM_CCER_CC1NE << Channel; + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h index eae1c9a328..74c41bc526 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_EX_H -#define __STM32L4xx_HAL_TIM_EX_H +#ifndef STM32L4xx_HAL_TIM_EX_H +#define STM32L4xx_HAL_TIM_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -63,7 +47,6 @@ typedef struct { - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -80,7 +63,8 @@ typedef struct /** * @brief TIM Break/Break2 input configuration */ -typedef struct { +typedef struct +{ uint32_t Source; /*!< Specifies the source of the timer break input. This parameter can be a value of @ref TIMEx_Break_Input_Source */ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. @@ -88,7 +72,8 @@ typedef struct { uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity Not relevant when analog watchdog output of the DFSDM1 used as break input source */ -} TIMEx_BreakInputConfigTypeDef; +} +TIMEx_BreakInputConfigTypeDef; /** * @} @@ -100,162 +85,129 @@ typedef struct { * @{ */ -/** @defgroup TIMEx_Remap TIM Extended Remapping +/** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */ +#if defined (ADC3) +#define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */ #define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ -#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ -#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ -#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ -#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ +#endif /* ADC3 */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ +#if defined(COMP2) +#define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP2 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ -#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ -#define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx */ -#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */ -#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */ -#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */ -#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */ -#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */ -#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */ -#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */ +#if defined (USB_OTG_FS) +#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ +#define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */ +#else +#if defined(STM32L471xx) +#define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ +#define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */ +#else +#define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ +#define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ +#endif /* STM32L471xx */ +#endif /* USB_OTG_FS */ +#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */ +#define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ +#if defined(COMP2) +#define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP2 */ +#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */ +#if defined(COMP2) +#define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */ #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ +#endif /* COMP2 */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ -#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ -#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ +#if defined (TIM3) +#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */ +#define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */ #define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ -#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */ -#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ +#endif /* TIM3 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */ +#if defined (TIM8) +#if defined(ADC2) && defined(ADC3) +#define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */ #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ -#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ -#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ -#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* ADC2 && ADC3 */ -#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ -#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */ -#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */ +#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */ +#define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */ +#endif /* TIM8 */ + +#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */ +#define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */ +#define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ +#if defined (TIM3) +#define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ +#endif /* TIM3 */ +#if defined (TIM4) #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* TIM4 */ -#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ -#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */ +#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */ +#define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */ #define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */ +#if defined (TIM16_OR1_TI1_RMP_2) +#define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */ #define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ #define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L496xx || STM32L4A6xx */ +#endif /* TIM16_OR1_TI1_RMP_2 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ -#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ +#if defined (TIM17) +#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */ +#define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* TIM17 */ /** * @} */ -/** @defgroup TIMEx_Break_Input TIM Extended Break input +/** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ -#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */ +#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ /** * @} */ -/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#if defined (DFSDM1_Channel0) +#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +#endif /* DFSDM1_Channel0 */ /** * @} */ @@ -263,17 +215,17 @@ typedef struct { /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ -#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ /** * @} */ -/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ /** * @} */ @@ -302,10 +254,7 @@ typedef struct { #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (DFSDM1_Channel0) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ @@ -314,15 +263,14 @@ typedef struct { #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* DFSDM1_Channel0 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + /** * @} */ @@ -334,17 +282,17 @@ typedef struct { */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ + * @brief Timer Hall Sensor functions + * @{ + */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ +/* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ @@ -358,9 +306,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ + * @brief Timer Complementary Output Compare functions + * @{ + */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -378,9 +326,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ + * @brief Timer Complementary PWM functions + * @{ + */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -397,9 +345,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ + * @brief Timer Complementary One Pulse functions + * @{ + */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); @@ -413,19 +361,24 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ + * @brief Peripheral Control functions + * @{ + */ /* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); - /** * @} */ @@ -435,8 +388,10 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @{ */ /* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); /** * @} */ @@ -457,13 +412,14 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** -* @} -*/ + * @} + */ /* End of private functions --------------------------------------------------*/ /** @@ -479,6 +435,6 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); #endif -#endif /* __STM32L4xx_HAL_TIM_EX_H */ +#endif /* STM32L4xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c index ffb54c8bb1..90311d2a2c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c @@ -2,46 +2,45 @@ ****************************************************************************** * @file stm32l4xx_hal_tsc.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and De-initialization * + Channel IOs, Shield IOs and Sampling IOs configuration * + Start and Stop an acquisition * + Read acquisition result * + Interrupts and flags management - * + * @verbatim ================================================================================ ##### TSC specific features ##### ================================================================================ [..] (#) Proven and robust surface charge transfer acquisition principle - + (#) Supports up to 3 capacitive sensing channels per group - + (#) Capacitive sensing channels can be acquired in parallel offering a very good response time - + (#) Spread spectrum feature to improve system robustness in noisy environments - + (#) Full hardware management of the charge transfer acquisition sequence - + (#) Programmable charge transfer frequency - + (#) Programmable sampling capacitor I/O pin - + (#) Programmable channel I/O pin - + (#) Programmable max count value to avoid long acquisition when a channel is faulty - + (#) Dedicated end of acquisition and max count error flags with interrupt capability - + (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components - + (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation - ##### How to use this driver ##### ================================================================================ [..] @@ -54,14 +53,14 @@ using HAL_GPIO_Init() function. (#) Interrupts configuration - (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority() + (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() and function. (#) TSC configuration (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function. [..] TSC peripheral alternate functions are mapped on AF9. - + *** Acquisition sequence *** =================================== [..] @@ -76,84 +75,122 @@ HAL_TSC_GetState() function or using WFI instruction for example. (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function. (+) Read the acquisition value using HAL_TSC_GroupGetValue() function. - + + *** Callback registration *** + ============================================= + + [..] + The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback. + + [..] + Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : callback for conversion complete process. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + This function allows to reset following callbacks: + (+) ConvCpltCallback : callback for conversion complete process. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + [..] + By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit() + or @ref HAL_TSC_Init() function. + + [..] + When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** Table 1. IOs for the STM32L4xx devices - +--------------------------------+ - | IOs | TSC functions | + +--------------------------------+ + | IOs | TSC functions | |--------------|-----------------| - | PB12 (AF) | TSC_G1_IO1 | - | PB13 (AF) | TSC_G1_IO2 | - | PB14 (AF) | TSC_G1_IO3 | - | PB15 (AF) | TSC_G1_IO4 | + | PB12 (AF) | TSC_G1_IO1 | + | PB13 (AF) | TSC_G1_IO2 | + | PB14 (AF) | TSC_G1_IO3 | + | PB15 (AF) | TSC_G1_IO4 | |--------------|-----------------| - | PB4 (AF) | TSC_G2_IO1 | - | PB5 (AF) | TSC_G2_IO2 | - | PB6 (AF) | TSC_G2_IO3 | - | PB7 (AF) | TSC_G2_IO4 | + | PB4 (AF) | TSC_G2_IO1 | + | PB5 (AF) | TSC_G2_IO2 | + | PB6 (AF) | TSC_G2_IO3 | + | PB7 (AF) | TSC_G2_IO4 | |--------------|-----------------| - | PA15 (AF) | TSC_G3_IO1 | - | PC10 (AF) | TSC_G3_IO2 | - | PC11 (AF) | TSC_G3_IO3 | - | PC12 (AF) | TSC_G3_IO4 | + | PA15 (AF) | TSC_G3_IO1 | + | PC10 (AF) | TSC_G3_IO2 | + | PC11 (AF) | TSC_G3_IO3 | + | PC12 (AF) | TSC_G3_IO4 | |--------------|-----------------| - | PC6 (AF) | TSC_G4_IO1 | - | PC7 (AF) | TSC_G4_IO2 | - | PC8 (AF) | TSC_G4_IO3 | - | PC9 (AF) | TSC_G4_IO4 | + | PC6 (AF) | TSC_G4_IO1 | + | PC7 (AF) | TSC_G4_IO2 | + | PC8 (AF) | TSC_G4_IO3 | + | PC9 (AF) | TSC_G4_IO4 | |--------------|-----------------| - | PE10 (AF) | TSC_G5_IO1 | - | PE11 (AF) | TSC_G5_IO2 | - | PE12 (AF) | TSC_G5_IO3 | - | PE13 (AF) | TSC_G5_IO4 | + | PE10 (AF) | TSC_G5_IO1 | + | PE11 (AF) | TSC_G5_IO2 | + | PE12 (AF) | TSC_G5_IO3 | + | PE13 (AF) | TSC_G5_IO4 | |--------------|-----------------| - | PD10 (AF) | TSC_G6_IO1 | - | PD11 (AF) | TSC_G6_IO2 | - | PD12 (AF) | TSC_G6_IO3 | - | PD13 (AF) | TSC_G6_IO4 | + | PD10 (AF) | TSC_G6_IO1 | + | PD11 (AF) | TSC_G6_IO2 | + | PD12 (AF) | TSC_G6_IO3 | + | PD13 (AF) | TSC_G6_IO4 | |--------------|-----------------| - | PE2 (AF) | TSC_G7_IO1 | - | PE3 (AF) | TSC_G7_IO2 | - | PE4 (AF) | TSC_G7_IO3 | - | PE5 (AF) | TSC_G7_IO4 | + | PE2 (AF) | TSC_G7_IO1 | + | PE3 (AF) | TSC_G7_IO2 | + | PE4 (AF) | TSC_G7_IO3 | + | PE5 (AF) | TSC_G7_IO4 | |--------------|-----------------| - | PF14 (AF) | TSC_G8_IO1 | - | PF15 (AF) | TSC_G8_IO2 | - | PG0 (AF) | TSC_G8_IO3 | - | PG1 (AF) | TSC_G8_IO4 | + | PF14 (AF) | TSC_G8_IO1 | + | PF15 (AF) | TSC_G8_IO2 | + | PG0 (AF) | TSC_G8_IO3 | + | PG1 (AF) | TSC_G8_IO4 | |--------------|-----------------| - | PB10 (AF) | TSC_SYNC | - | PD2 (AF) | | + | PB10 (AF) | TSC_SYNC | + | PD2 (AF) | | +--------------------------------+ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -171,7 +208,7 @@ */ #ifdef HAL_TSC_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -181,14 +218,14 @@ static uint32_t TSC_extract_groups(uint32_t iomask); /* Exported functions --------------------------------------------------------*/ -/** @defgroup TSC_Exported_Functions Exported Functions +/** @defgroup TSC_Exported_Functions TSC Exported Functions * @{ - */ + */ /** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -200,12 +237,12 @@ static uint32_t TSC_extract_groups(uint32_t iomask); */ /** - * @brief Initialize the TSC peripheral according to the specified parameters + * @brief Initialize the TSC peripheral according to the specified parameters * in the TSC_InitTypeDef structure and initialize the associated handle. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc) { /* Check TSC handle allocation */ if (htsc == NULL) @@ -226,29 +263,46 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode)); assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); + assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs)); + assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs)); + assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs)); - if(htsc->State == HAL_TSC_STATE_RESET) + if (htsc->State == HAL_TSC_STATE_RESET) { /* Allocate lock resource and initialize it */ htsc->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + /* Init the TSC Callback settings */ + htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */ + htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (htsc->MspInitCallback == NULL) + { + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + htsc->MspInitCallback(htsc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_TSC_MspInit(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_BUSY; - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_TSC_MspInit(htsc); - - /*--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------*/ /* Set TSC parameters */ /* Enable TSC */ htsc->Instance->CR = TSC_CR_TSCE; - + /* Set all functions */ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | htsc->Init.CTPulseLowLength | - (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) | + (htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) | htsc->Init.SpreadSpectrumPrescaler | htsc->Init.PulseGeneratorPrescaler | htsc->Init.MaxCountValue | @@ -260,40 +314,40 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) { htsc->Instance->CR |= TSC_CR_SSE; } - + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ - htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs)); + htsc->Instance->IOHCR = (~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs)); /* Set channel and shield IOs */ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs); - + /* Set sampling IOs */ htsc->Instance->IOSCR = htsc->Init.SamplingIOs; - + /* Set the groups to be acquired */ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs); - + /* Disable interrupts */ - htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE)); - + htsc->Instance->IER &= (~(TSC_IT_EOA | TSC_IT_MCE)); + /* Clear flags */ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE); /*--------------------------------------------------------------------------*/ - + /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief Deinitialize the TSC peripheral registers to their default reset values. - * @param htsc: TSC handle + * @param htsc TSC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc) { /* Check TSC handle allocation */ if (htsc == NULL) @@ -303,13 +357,23 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_BUSY; - + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + if (htsc->MspDeInitCallback == NULL) + { + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + htsc->MspDeInitCallback(htsc); +#else /* DeInit the low level hardware */ HAL_TSC_MspDeInit(htsc); - +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + /* Change TSC state */ htsc->State = HAL_TSC_STATE_RESET; @@ -322,47 +386,227 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) /** * @brief Initialize the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains - * the configuration information for the specified TSC. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TSC_MspInit could be implemented in the user file. - */ + */ } /** * @brief DeInitialize the TSC MSP. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains - * the configuration information for the specified TSC. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TSC_MspDeInit could be implemented in the user file. - */ + */ } +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TSC Callback + * To be used instead of the weak predefined callback + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID + * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID + * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htsc); + + if (HAL_TSC_STATE_READY == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_CONV_COMPLETE_CB_ID : + htsc->ConvCpltCallback = pCallback; + break; + + case HAL_TSC_ERROR_CB_ID : + htsc->ErrorCallback = pCallback; + break; + + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = pCallback; + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_TSC_STATE_RESET == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = pCallback; + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htsc); + return status; +} + +/** + * @brief Unregister an TSC Callback + * TSC callback is redirected to the weak predefined callback + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID + * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID + * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htsc); + + if (HAL_TSC_STATE_READY == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_CONV_COMPLETE_CB_ID : + htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */ + break; + + case HAL_TSC_ERROR_CB_ID : + htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_TSC_STATE_RESET == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htsc); + return status; +} + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions + * @brief Input and Output operation functions * -@verbatim +@verbatim =============================================================================== ##### IO Operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start acquisition in polling mode. (+) Start acquisition in interrupt mode. @@ -377,18 +621,18 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc) /** * @brief Start the acquisition. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + /* Process locked */ __HAL_LOCK(htsc); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_BUSY; @@ -407,24 +651,24 @@ HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc) { __HAL_TSC_SET_IODEF_INFLOAT(htsc); } - + /* Launch the acquisition */ __HAL_TSC_START_ACQ(htsc); - + /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Start the acquisition in interrupt mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -432,10 +676,10 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) /* Process locked */ __HAL_LOCK(htsc); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_BUSY; - + /* Enable end of acquisition interrupt */ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA); @@ -451,7 +695,7 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) /* Clear flags */ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); - + /* Set touch sensing IOs not acquired to the specified IODefaultMode */ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW) { @@ -461,82 +705,82 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc) { __HAL_TSC_SET_IODEF_INFLOAT(htsc); } - + /* Launch the acquisition */ __HAL_TSC_START_ACQ(htsc); /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Stop the acquisition previously launched in polling mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + /* Stop the acquisition */ __HAL_TSC_STOP_ACQ(htsc); /* Set touch sensing IOs in low power mode (output push-pull) */ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); - + /* Clear flags */ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Stop the acquisition previously launched in interrupt mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + /* Stop the acquisition */ __HAL_TSC_STOP_ACQ(htsc); - + /* Set touch sensing IOs in low power mode (output push-pull) */ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); - + /* Disable interrupts */ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE)); /* Clear flags */ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); - + /* Change TSC state */ htsc->State = HAL_TSC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } @@ -545,18 +789,18 @@ HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc) * @brief Start acquisition and wait until completion. * @note There is no need of a timeout parameter as the max count error is already * managed by the TSC peripheral. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ -HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + /* Check end of acquisition */ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY) { @@ -565,55 +809,55 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc) /* Process unlocked */ __HAL_UNLOCK(htsc); - + return HAL_OK; } /** * @brief Get the acquisition status for a group. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Group status */ -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index) +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); assert_param(IS_TSC_GROUP_INDEX(gx_index)); - /* Return the group status */ - return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index)); + /* Return the group status */ + return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index)); } /** * @brief Get the acquisition measure for a group. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param gx_index: Index of the group + * @param gx_index Index of the group * @retval Acquisition measure */ -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) -{ +uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index) +{ /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); assert_param(IS_TSC_GROUP_INDEX(gx_index)); - /* Return the group acquisition counter */ + /* Return the group acquisition counter */ return htsc->Instance->IOGXCR[gx_index]; } /** * @} */ - + /** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure TSC IOs (+) Discharge TSC IOs @@ -623,16 +867,19 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index) /** * @brief Configure TSC IOs. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param config: pointer to the configuration structure. + * @param config Pointer to the configuration structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config) +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + assert_param(IS_TSC_GROUP(config->ChannelIOs)); + assert_param(IS_TSC_GROUP(config->ShieldIOs)); + assert_param(IS_TSC_GROUP(config->SamplingIOs)); + /* Process locked */ __HAL_LOCK(htsc); @@ -640,39 +887,39 @@ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* __HAL_TSC_STOP_ACQ(htsc); /* Disable Schmitt trigger hysteresis on all used TSC IOs */ - htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs)); + htsc->Instance->IOHCR = (~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs)); /* Set channel and shield IOs */ htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs); - + /* Set sampling IOs */ htsc->Instance->IOSCR = config->SamplingIOs; - + /* Set groups to be acquired */ htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs); - + /* Process unlocked */ __HAL_UNLOCK(htsc); - + /* Return function status */ return HAL_OK; } /** * @brief Discharge TSC IOs. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. - * @param choice: enable or disable + * @param choice This parameter can be set to ENABLE or DISABLE. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) -{ +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice) +{ /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); /* Process locked */ __HAL_LOCK(htsc); - + if (choice == ENABLE) { __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); @@ -684,8 +931,8 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) /* Process unlocked */ __HAL_UNLOCK(htsc); - - /* Return the group acquisition counter */ + + /* Return the group acquisition counter */ return HAL_OK; } @@ -694,31 +941,31 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice) */ /** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Get TSC state. - + @endverbatim * @{ */ /** * @brief Return the TSC handle state. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval HAL state */ -HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - + if (htsc->State == HAL_TSC_STATE_BUSY) { /* Check end of acquisition flag */ @@ -737,7 +984,7 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) } } } - + /* Return TSC state */ return htsc->State; } @@ -748,15 +995,15 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc) /** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief Handle TSC interrupt request. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ -void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) +void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -767,7 +1014,7 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /* Clear EOA flag */ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); } - + /* Check if max count error occurred */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) { @@ -775,25 +1022,33 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE); /* Change TSC state */ htsc->State = HAL_TSC_STATE_ERROR; +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + htsc->ErrorCallback(htsc); +#else /* Conversion completed callback */ HAL_TSC_ErrorCallback(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } else { /* Change TSC state */ htsc->State = HAL_TSC_STATE_READY; +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + htsc->ConvCpltCallback(htsc); +#else /* Conversion completed callback */ HAL_TSC_ConvCpltCallback(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } } /** * @brief Acquisition completed callback in non-blocking mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); @@ -805,11 +1060,11 @@ __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc) /** * @brief Error callback in non-blocking mode. - * @param htsc: pointer to a TSC_HandleTypeDef structure that contains + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains * the configuration information for the specified TSC. * @retval None */ -__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) +__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(htsc); @@ -828,28 +1083,28 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TSC_Private_Functions Private Functions +/** @defgroup TSC_Private_Functions TSC Private Functions * @{ */ - + /** * @brief Utility function used to set the acquired groups mask. - * @param iomask: Channels IOs mask + * @param iomask Channels IOs mask * @retval Acquired groups mask */ static uint32_t TSC_extract_groups(uint32_t iomask) { - uint32_t groups = 0; + uint32_t groups = 0UL; uint32_t idx; - - for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++) + + for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++) { - if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET) + if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL ) { - groups |= ((uint32_t)1 << idx); + groups |= (1UL << idx); } } - + return groups; } @@ -861,10 +1116,10 @@ static uint32_t TSC_extract_groups(uint32_t iomask) /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h index 32f5bb622b..9215d73770 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TSC_H -#define __STM32L4xx_HAL_TSC_H +#ifndef STM32L4xx_HAL_TSC_H +#define STM32L4xx_HAL_TSC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -57,37 +41,37 @@ * @{ */ -/** - * @brief TSC state structure definition - */ +/** + * @brief TSC state structure definition + */ typedef enum { - HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ - HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ - HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ - HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ + HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ } HAL_TSC_StateTypeDef; -/** - * @brief TSC group status structure definition - */ +/** + * @brief TSC group status structure definition + */ typedef enum { - TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ - TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ + TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ } TSC_GroupStatusTypeDef; -/** - * @brief TSC init structure definition - */ +/** + * @brief TSC init structure definition + */ typedef struct { - uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length + uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length This parameter can be a value of @ref TSC_CTPulseHL_Config */ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length This parameter can be a value of @ref TSC_CTPulseLL_Config */ - uint32_t SpreadSpectrum; /*!< Spread spectrum activation - This parameter can be a value of @ref TSC_CTPulseLL_Config */ + FunctionalState SpreadSpectrum; /*!< Spread spectrum activation + This parameter can be set to ENABLE or DISABLE. */ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler @@ -102,16 +86,16 @@ typedef struct This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ uint32_t AcquisitionMode; /*!< Acquisition mode This parameter can be a value of @ref TSC_Acquisition_Mode */ - uint32_t MaxCountInterrupt; /*!< Max count interrupt activation + FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation This parameter can be set to ENABLE or DISABLE. */ uint32_t ChannelIOs; /*!< Channel IOs mask */ uint32_t ShieldIOs; /*!< Shield IOs mask */ uint32_t SamplingIOs; /*!< Sampling IOs mask */ } TSC_InitTypeDef; -/** - * @brief TSC IOs configuration structure definition - */ +/** + * @brief TSC IOs configuration structure definition + */ typedef struct { uint32_t ChannelIOs; /*!< Channel IOs mask */ @@ -119,17 +103,69 @@ typedef struct uint32_t SamplingIOs; /*!< Sampling IOs mask */ } TSC_IOConfigTypeDef; -/** - * @brief TSC handle Structure definition - */ -typedef struct +/** + * @brief TSC handle Structure definition + */ +typedef struct __TSC_HandleTypeDef { - TSC_TypeDef *Instance; /*!< Register base address */ - TSC_InitTypeDef Init; /*!< Initialization parameters */ - __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ - HAL_LockTypeDef Lock; /*!< Lock feature */ + TSC_TypeDef *Instance; /*!< Register base address */ + TSC_InitTypeDef Init; /*!< Initialization parameters */ + __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ + HAL_LockTypeDef Lock; /*!< Lock feature */ + __IO uint32_t ErrorCode; /*!< I2C Error code */ + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ + void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ + + void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ + void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ } TSC_HandleTypeDef; +enum +{ + TSC_GROUP1_IDX = 0x00UL, + TSC_GROUP2_IDX, + TSC_GROUP3_IDX, + TSC_GROUP4_IDX, +#if defined(TSC_IOCCR_G5_IO1) + TSC_GROUP5_IDX, +#endif +#if defined(TSC_IOCCR_G6_IO1) + TSC_GROUP6_IDX, +#endif +#if defined(TSC_IOCCR_G7_IO1) + TSC_GROUP7_IDX, +#endif +#if defined(TSC_IOCCR_G8_IO1) + TSC_GROUP8_IDX, +#endif + TSC_NB_OF_GROUPS +}; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TSC Callback ID enumeration definition + */ +typedef enum +{ + HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ + HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ + + HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ + HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ + +} HAL_TSC_CallbackIDTypeDef; + +/** + * @brief HAL TSC Callback pointer definition + */ +typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + /** * @} */ @@ -139,25 +175,37 @@ typedef struct * @{ */ +/** @defgroup TSC_Error_Code_definition TSC Error Code definition + * @brief TSC Error Code definition + * @{ + */ +#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup TSC_CTPulseHL_Config CTPulse High Length * @{ */ -#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) -#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) -#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) -#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) -#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) -#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) -#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) -#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) -#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) -#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) -#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) -#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) -#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) -#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) -#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) -#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) +#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ +#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ +#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ +#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ +#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ +#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ +#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ +#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ +#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ +#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ +#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ +#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ +#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ +#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ +#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ +#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ /** * @} */ @@ -165,22 +213,22 @@ typedef struct /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length * @{ */ -#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) -#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) -#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) -#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) -#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) -#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) -#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) -#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) -#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) -#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) -#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) -#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) -#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) -#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) -#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) -#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) +#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ +#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ +#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ +#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ +#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ +#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ +#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ +#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ +#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ +#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ +#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ +#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ +#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ +#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ +#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ +#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ /** * @} */ @@ -188,8 +236,8 @@ typedef struct /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler * @{ */ -#define TSC_SS_PRESC_DIV1 ((uint32_t)0) -#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) +#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ +#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ /** * @} */ @@ -197,14 +245,14 @@ typedef struct /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler * @{ */ -#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) -#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) -#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) -#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) -#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) -#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) -#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) -#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) +#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ +#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ +#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ +#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ +#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ +#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ +#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ +#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ /** * @} */ @@ -212,13 +260,13 @@ typedef struct /** @defgroup TSC_MaxCount_Value Max Count Value * @{ */ -#define TSC_MCV_255 ((uint32_t)(0 << 5)) -#define TSC_MCV_511 ((uint32_t)(1 << 5)) -#define TSC_MCV_1023 ((uint32_t)(2 << 5)) -#define TSC_MCV_2047 ((uint32_t)(3 << 5)) -#define TSC_MCV_4095 ((uint32_t)(4 << 5)) -#define TSC_MCV_8191 ((uint32_t)(5 << 5)) -#define TSC_MCV_16383 ((uint32_t)(6 << 5)) +#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ +#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ +#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ +#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ +#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ +#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ +#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ /** * @} */ @@ -226,8 +274,8 @@ typedef struct /** @defgroup TSC_IO_Default_Mode IO Default Mode * @{ */ -#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) -#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) +#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ +#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ /** * @} */ @@ -235,8 +283,8 @@ typedef struct /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity * @{ */ -#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) -#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) +#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ +#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ /** * @} */ @@ -244,19 +292,8 @@ typedef struct /** @defgroup TSC_Acquisition_Mode Acquisition Mode * @{ */ -#define TSC_ACQ_MODE_NORMAL ((uint32_t)0) -#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) -/** - * @} - */ - -/** @defgroup TSC_IO_Mode IO Mode - * @{ - */ -#define TSC_IOMODE_UNUSED ((uint32_t)0) -#define TSC_IOMODE_CHANNEL ((uint32_t)1) -#define TSC_IOMODE_SHIELD ((uint32_t)2) -#define TSC_IOMODE_SAMPLING ((uint32_t)3) +#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ +#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ /** * @} */ @@ -264,8 +301,8 @@ typedef struct /** @defgroup TSC_interrupts_definition Interrupts definition * @{ */ -#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE) -#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) +#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ +#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ /** * @} */ @@ -273,8 +310,8 @@ typedef struct /** @defgroup TSC_flags_definition Flags definition * @{ */ -#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF) -#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF) +#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ +#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ /** * @} */ @@ -282,76 +319,96 @@ typedef struct /** @defgroup TSC_Group_definition Group definition * @{ */ -#define TSC_NB_OF_GROUPS (8) +#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) +#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) +#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) +#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) +#if defined(TSC_IOCCR_G5_IO1) +#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) +#endif +#if defined(TSC_IOCCR_G6_IO1) +#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) +#endif +#if defined(TSC_IOCCR_G7_IO1) +#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) +#endif +#if defined(TSC_IOCCR_G8_IO1) +#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) +#endif -#define TSC_GROUP1 ((uint32_t)0x00000001) -#define TSC_GROUP2 ((uint32_t)0x00000002) -#define TSC_GROUP3 ((uint32_t)0x00000004) -#define TSC_GROUP4 ((uint32_t)0x00000008) -#define TSC_GROUP5 ((uint32_t)0x00000010) -#define TSC_GROUP6 ((uint32_t)0x00000020) -#define TSC_GROUP7 ((uint32_t)0x00000040) -#define TSC_GROUP8 ((uint32_t)0x00000080) -#define TSC_ALL_GROUPS ((uint32_t)0x000000FF) +#define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ -#define TSC_GROUP1_IDX ((uint32_t)0) -#define TSC_GROUP2_IDX ((uint32_t)1) -#define TSC_GROUP3_IDX ((uint32_t)2) -#define TSC_GROUP4_IDX ((uint32_t)3) -#define TSC_GROUP5_IDX ((uint32_t)4) -#define TSC_GROUP6_IDX ((uint32_t)5) -#define TSC_GROUP7_IDX ((uint32_t)6) -#define TSC_GROUP8_IDX ((uint32_t)7) +#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ +#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ +#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ +#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ -#define TSC_GROUP1_IO1 ((uint32_t)0x00000001) -#define TSC_GROUP1_IO2 ((uint32_t)0x00000002) -#define TSC_GROUP1_IO3 ((uint32_t)0x00000004) -#define TSC_GROUP1_IO4 ((uint32_t)0x00000008) -#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F) +#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ +#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ +#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ +#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ -#define TSC_GROUP2_IO1 ((uint32_t)0x00000010) -#define TSC_GROUP2_IO2 ((uint32_t)0x00000020) -#define TSC_GROUP2_IO3 ((uint32_t)0x00000040) -#define TSC_GROUP2_IO4 ((uint32_t)0x00000080) -#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0) +#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ +#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ +#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ +#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ -#define TSC_GROUP3_IO1 ((uint32_t)0x00000100) -#define TSC_GROUP3_IO2 ((uint32_t)0x00000200) -#define TSC_GROUP3_IO3 ((uint32_t)0x00000400) -#define TSC_GROUP3_IO4 ((uint32_t)0x00000800) -#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) +#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ +#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ +#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ +#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ +#if defined(TSC_IOCCR_G5_IO1) -#define TSC_GROUP4_IO1 ((uint32_t)0x00001000) -#define TSC_GROUP4_IO2 ((uint32_t)0x00002000) -#define TSC_GROUP4_IO3 ((uint32_t)0x00004000) -#define TSC_GROUP4_IO4 ((uint32_t)0x00008000) -#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) +#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ +#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ +#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ +#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ +#else -#define TSC_GROUP5_IO1 ((uint32_t)0x00010000) -#define TSC_GROUP5_IO2 ((uint32_t)0x00020000) -#define TSC_GROUP5_IO3 ((uint32_t)0x00040000) -#define TSC_GROUP5_IO4 ((uint32_t)0x00080000) -#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) +#define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ +#define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ +#define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ +#define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ +#endif +#if defined(TSC_IOCCR_G6_IO1) -#define TSC_GROUP6_IO1 ((uint32_t)0x00100000) -#define TSC_GROUP6_IO2 ((uint32_t)0x00200000) -#define TSC_GROUP6_IO3 ((uint32_t)0x00400000) -#define TSC_GROUP6_IO4 ((uint32_t)0x00800000) -#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) +#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ +#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ +#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ +#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ +#else -#define TSC_GROUP7_IO1 ((uint32_t)0x01000000) -#define TSC_GROUP7_IO2 ((uint32_t)0x02000000) -#define TSC_GROUP7_IO3 ((uint32_t)0x04000000) -#define TSC_GROUP7_IO4 ((uint32_t)0x08000000) -#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) +#define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ +#define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ +#define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ +#define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ +#endif +#if defined(TSC_IOCCR_G7_IO1) -#define TSC_GROUP8_IO1 ((uint32_t)0x10000000) -#define TSC_GROUP8_IO2 ((uint32_t)0x20000000) -#define TSC_GROUP8_IO3 ((uint32_t)0x40000000) -#define TSC_GROUP8_IO4 ((uint32_t)0x80000000) -#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) +#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ +#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ +#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ +#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ +#else -#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) +#define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ +#define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ +#define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ +#define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ +#endif +#if defined(TSC_IOCCR_G8_IO1) + +#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ +#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ +#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ +#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ +#else + +#define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ +#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ +#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ +#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ +#endif /** * @} */ @@ -367,193 +424,201 @@ typedef struct */ /** @brief Reset TSC handle state. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) +#endif /** * @brief Enable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) +#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) /** * @brief Disable the TSC peripheral. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) +#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) /** * @brief Start acquisition. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) +#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) /** * @brief Stop acquisition. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) +#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) /** * @brief Set IO default mode to output push-pull low. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) +#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) /** * @brief Set IO default mode to input floating. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) +#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) /** * @brief Set synchronization polarity to falling edge. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) +#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) /** * @brief Set synchronization polarity to rising edge and high level. - * @param __HANDLE__: TSC handle + * @param __HANDLE__ TSC handle * @retval None */ -#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) +#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) /** * @brief Enable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ -#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) +#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** * @brief Disable TSC interrupt. - * @param __HANDLE__: TSC handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt * @retval None */ -#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) +#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) /** @brief Check whether the specified TSC interrupt source is enabled or not. - * @param __HANDLE__: TSC Handle - * @param __INTERRUPT__: TSC interrupt + * @param __HANDLE__ TSC Handle + * @param __INTERRUPT__ TSC interrupt * @retval SET or RESET */ -#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Check whether the specified TSC flag is set or not. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval SET or RESET */ -#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @brief Clear the TSC's pending flag. - * @param __HANDLE__: TSC handle - * @param __FLAG__: TSC flag + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag * @retval None */ -#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable schmitt trigger hysteresis on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) +#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) /** * @brief Disable schmitt trigger hysteresis on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__))) /** * @brief Open analog switch on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__))) /** * @brief Close analog switch on a group of IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) /** * @brief Enable a group of IOs in channel mode. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) +#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of channel IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__))) /** * @brief Enable a group of IOs in sampling mode. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) +#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) /** * @brief Disable a group of sampling IOs. - * @param __HANDLE__: TSC handle - * @param __GX_IOY_MASK__: IOs mask + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask * @retval None */ -#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) +#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) /** * @brief Enable acquisition groups. - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) /** * @brief Disable acquisition groups. - * @param __HANDLE__: TSC handle - * @param __GX_MASK__: Groups mask + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask * @retval None */ -#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) +#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) /** @brief Gets acquisition group status. - * @param __HANDLE__: TSC Handle - * @param __GX_INDEX__: Group index + * @param __HANDLE__ TSC Handle + * @param __GX_INDEX__ Group index * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ -((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) +((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) /** * @} @@ -565,83 +630,113 @@ typedef struct * @{ */ -#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \ - ((VAL) == TSC_CTPH_2CYCLES) || \ - ((VAL) == TSC_CTPH_3CYCLES) || \ - ((VAL) == TSC_CTPH_4CYCLES) || \ - ((VAL) == TSC_CTPH_5CYCLES) || \ - ((VAL) == TSC_CTPH_6CYCLES) || \ - ((VAL) == TSC_CTPH_7CYCLES) || \ - ((VAL) == TSC_CTPH_8CYCLES) || \ - ((VAL) == TSC_CTPH_9CYCLES) || \ - ((VAL) == TSC_CTPH_10CYCLES) || \ - ((VAL) == TSC_CTPH_11CYCLES) || \ - ((VAL) == TSC_CTPH_12CYCLES) || \ - ((VAL) == TSC_CTPH_13CYCLES) || \ - ((VAL) == TSC_CTPH_14CYCLES) || \ - ((VAL) == TSC_CTPH_15CYCLES) || \ - ((VAL) == TSC_CTPH_16CYCLES)) +#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ + ((__VALUE__) == TSC_CTPH_2CYCLES) || \ + ((__VALUE__) == TSC_CTPH_3CYCLES) || \ + ((__VALUE__) == TSC_CTPH_4CYCLES) || \ + ((__VALUE__) == TSC_CTPH_5CYCLES) || \ + ((__VALUE__) == TSC_CTPH_6CYCLES) || \ + ((__VALUE__) == TSC_CTPH_7CYCLES) || \ + ((__VALUE__) == TSC_CTPH_8CYCLES) || \ + ((__VALUE__) == TSC_CTPH_9CYCLES) || \ + ((__VALUE__) == TSC_CTPH_10CYCLES) || \ + ((__VALUE__) == TSC_CTPH_11CYCLES) || \ + ((__VALUE__) == TSC_CTPH_12CYCLES) || \ + ((__VALUE__) == TSC_CTPH_13CYCLES) || \ + ((__VALUE__) == TSC_CTPH_14CYCLES) || \ + ((__VALUE__) == TSC_CTPH_15CYCLES) || \ + ((__VALUE__) == TSC_CTPH_16CYCLES)) -#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \ - ((VAL) == TSC_CTPL_2CYCLES) || \ - ((VAL) == TSC_CTPL_3CYCLES) || \ - ((VAL) == TSC_CTPL_4CYCLES) || \ - ((VAL) == TSC_CTPL_5CYCLES) || \ - ((VAL) == TSC_CTPL_6CYCLES) || \ - ((VAL) == TSC_CTPL_7CYCLES) || \ - ((VAL) == TSC_CTPL_8CYCLES) || \ - ((VAL) == TSC_CTPL_9CYCLES) || \ - ((VAL) == TSC_CTPL_10CYCLES) || \ - ((VAL) == TSC_CTPL_11CYCLES) || \ - ((VAL) == TSC_CTPL_12CYCLES) || \ - ((VAL) == TSC_CTPL_13CYCLES) || \ - ((VAL) == TSC_CTPL_14CYCLES) || \ - ((VAL) == TSC_CTPL_15CYCLES) || \ - ((VAL) == TSC_CTPL_16CYCLES)) +#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ + ((__VALUE__) == TSC_CTPL_2CYCLES) || \ + ((__VALUE__) == TSC_CTPL_3CYCLES) || \ + ((__VALUE__) == TSC_CTPL_4CYCLES) || \ + ((__VALUE__) == TSC_CTPL_5CYCLES) || \ + ((__VALUE__) == TSC_CTPL_6CYCLES) || \ + ((__VALUE__) == TSC_CTPL_7CYCLES) || \ + ((__VALUE__) == TSC_CTPL_8CYCLES) || \ + ((__VALUE__) == TSC_CTPL_9CYCLES) || \ + ((__VALUE__) == TSC_CTPL_10CYCLES) || \ + ((__VALUE__) == TSC_CTPL_11CYCLES) || \ + ((__VALUE__) == TSC_CTPL_12CYCLES) || \ + ((__VALUE__) == TSC_CTPL_13CYCLES) || \ + ((__VALUE__) == TSC_CTPL_14CYCLES) || \ + ((__VALUE__) == TSC_CTPL_15CYCLES) || \ + ((__VALUE__) == TSC_CTPL_16CYCLES)) -#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) +#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) -#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) +#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) -#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) +#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) -#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ - ((VAL) == TSC_PG_PRESC_DIV2) || \ - ((VAL) == TSC_PG_PRESC_DIV4) || \ - ((VAL) == TSC_PG_PRESC_DIV8) || \ - ((VAL) == TSC_PG_PRESC_DIV16) || \ - ((VAL) == TSC_PG_PRESC_DIV32) || \ - ((VAL) == TSC_PG_PRESC_DIV64) || \ - ((VAL) == TSC_PG_PRESC_DIV128)) +#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV128)) -#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \ - ((VAL) == TSC_MCV_511) || \ - ((VAL) == TSC_MCV_1023) || \ - ((VAL) == TSC_MCV_2047) || \ - ((VAL) == TSC_MCV_4095) || \ - ((VAL) == TSC_MCV_8191) || \ - ((VAL) == TSC_MCV_16383)) +#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ + ((__VALUE__) == TSC_MCV_511) || \ + ((__VALUE__) == TSC_MCV_1023) || \ + ((__VALUE__) == TSC_MCV_2047) || \ + ((__VALUE__) == TSC_MCV_4095) || \ + ((__VALUE__) == TSC_MCV_8191) || \ + ((__VALUE__) == TSC_MCV_16383)) -#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) +#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) -#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING)) +#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) -#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO)) +#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) -#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \ - ((VAL) == TSC_IOMODE_CHANNEL) || \ - ((VAL) == TSC_IOMODE_SHIELD) || \ - ((VAL) == TSC_IOMODE_SAMPLING)) +#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) -#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) +#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) -#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS))) + +#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ + ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ + (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ + (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ + (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ + (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ + (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ + (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ + (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ + (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ + (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ + (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ + (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ + (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ + (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ + (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ + (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ + (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ + (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ + (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ + (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ + (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ + (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ + (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ + (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ + (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ + (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ + (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ + (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ + (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ + (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ + (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ + (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup TSC_Exported_Functions * @{ */ @@ -650,10 +745,16 @@ typedef struct * @{ */ /* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc); +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); -void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc); -void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); +void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); +void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ /** * @} */ @@ -662,13 +763,13 @@ void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc); * @{ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc); -HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc); -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index); -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); +uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); /** * @} */ @@ -677,8 +778,8 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config); -HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); /** * @} */ @@ -687,18 +788,18 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc); +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); /** * @} */ /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /******* TSC IRQHandler and Callbacks used in Interrupt mode */ -void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc); -void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc); -void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); +void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); +void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); +void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); /** * @} */ @@ -719,6 +820,6 @@ void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); } #endif -#endif /* __STM32L4xx_HAL_TSC_H */ +#endif /* STM32L4xx_HAL_TSC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c index 8aa955c859..625980944b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c @@ -67,33 +67,88 @@ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_UART_MspInit() API. + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -124,14 +179,14 @@ #else #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_CR1_FIFOEN) #define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #else #define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ @@ -166,15 +221,14 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); #if defined(USART_CR1_FIFOEN) static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -#endif +#endif /* USART_CR1_FIFOEN */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); #if defined(USART_CR1_FIFOEN) static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -#endif - +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -221,10 +275,10 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the following table. - + Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | @@ -247,19 +301,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); /** * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. + * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* Check the parameters */ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); @@ -269,99 +323,119 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. + * parameters in the UART_InitTypeDef and creates the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -369,7 +443,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . + * parameters in the UART_InitTypeDef and creates the associated handle. * @param huart UART handle. * @param BreakDetectLength Specifies the LIN break detection length. * This parameter can be one of the following values: @@ -380,67 +454,77 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the LIN UART instance */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - + /* LIN mode limited to 16-bit oversampling only */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { return HAL_ERROR; } /* LIN mode limited to 8-bit data length */ - if(huart->Init.WordLength != UART_WORDLENGTH_8B) + if (huart->Init.WordLength != UART_WORDLENGTH_8B) { return HAL_ERROR; } - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - + /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -448,7 +532,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. + * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @param Address UART node address (4-, 6-, 7- or 8-bit long). * @param WakeUpMethod Specifies the UART wakeup method. @@ -467,57 +551,67 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { /* If address mark wake up method is chosen, set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); } - + /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -531,33 +625,40 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); - + huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); - +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - - /* Process Unlock */ + __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -570,7 +671,7 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file */ @@ -585,12 +686,269 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; +#endif /* USART_CR1_FIFOEN */ + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + +#endif /* USART_CR1_FIFOEN */ + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @} */ @@ -656,7 +1014,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. @@ -674,9 +1032,9 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * when TXFNF flag is set. From hardware perspective, TXFNF flag and * TXE are mapped on the same bit-field. * @param huart UART handle. * @param pData Pointer to data buffer. @@ -686,59 +1044,70 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - uint32_t tickstart = 0U; - + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) + if (huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + huart->TxXferSize = Size; huart->TxXferCount = Size; - - while(huart->TxXferCount > 0U) + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pData += 2U; + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; } huart->TxXferCount--; } - - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -749,9 +1118,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. * @param pData Pointer to data buffer. @@ -761,60 +1130,71 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; uint16_t uhMask; - uint32_t tickstart = 0; - + uint32_t tickstart; + /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; - - /* as long as data have to be received */ - while(huart->RxXferCount > 0U) + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2U; + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; } else { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; } huart->RxXferCount--; } - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -833,28 +1213,27 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) + if (huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; huart->TxISR = NULL; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + #if defined(USART_CR1_FIFOEN) /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { + { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { @@ -863,16 +1242,14 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; - } - - /* Process Unlocked */ + } + __HAL_UNLOCK(huart); - + /* Enable the TX FIFO threshold interrupt */ SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } else -#endif { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) @@ -882,19 +1259,30 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData else { huart->TxISR = UART_TxISR_8BIT; - } - - /* Process Unlocked */ + } + __HAL_UNLOCK(huart); - + /* Enable the Transmit Data Register Empty interrupt */ -#if defined(USART_CR1_FIFOEN) - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } - +#else + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +#endif /* USART_CR1_FIFOEN */ + return HAL_OK; } else @@ -913,30 +1301,29 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; huart->RxXferCount = Size; huart->RxISR = NULL; - + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + #if defined(USART_CR1_FIFOEN) /* Configure Rx interrupt processing*/ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) @@ -950,16 +1337,14 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, { huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else -#endif { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) @@ -970,18 +1355,29 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, { huart->RxISR = UART_RxISR_8BIT; } - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ -#if defined(USART_CR1_FIFOEN) + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); -#else - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); -#endif } - +#else + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif /* USART_CR1_FIFOEN */ + return HAL_OK; } else @@ -1000,48 +1396,59 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) + if (huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); - + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + return HAL_OK; } else @@ -1052,60 +1459,71 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). * @param huart UART handle. * @param pData Pointer to data buffer. * @param Size Amount of data to be received. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); - - /* Process Unlocked */ + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } __HAL_UNLOCK(huart); - + /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + return HAL_OK; } else @@ -1121,29 +1539,30 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { - /* Process Locked */ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + __HAL_LOCK(huart); - - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) { /* Disable the UART DMA Tx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the UART DMA Rx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1154,30 +1573,28 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); - - if(huart->gState == HAL_UART_STATE_BUSY_TX) + + if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the UART DMA Rx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -1189,49 +1606,70 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + /* Stop UART DMA Tx request if ongoing */ - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - HAL_DMA_Abort(huart->hdmatx); + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } - + UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - HAL_DMA_Abort(huart->hdmarx); + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } - + UART_EndRxTransfer(huart); } - + return HAL_OK; } /** * @brief Abort ongoing transfers (blocking mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1239,81 +1677,100 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); #else + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* USART_CR1_FIFOEN */ /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmatx); + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmarx); + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } - + /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - - /* Reset Handle ErrorCode to No Error */ + huart->ErrorCode = HAL_UART_ERROR_NONE; - + return HAL_OK; } /** * @brief Abort ongoing Transmit transfer (blocking mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1321,53 +1778,64 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { - /* Disable TXEIE and TCIE interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); #else + /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmatx); + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } - + /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - + huart->TxXferCount = 0U; + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + return HAL_OK; } /** * @brief Abort ongoing Receive transfer (blocking mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1375,52 +1843,63 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); #else + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* USART_CR1_FIFOEN */ /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback to Null. + /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmarx); + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } - + /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + return HAL_OK; } /** * @brief Abort ongoing transfers (Interrupt mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1430,27 +1909,28 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + + /* Disable interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* USART_CR1_FIFOEN */ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; } @@ -1460,11 +1940,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } /* DMA Rx Handle is valid */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; } @@ -1473,21 +1953,21 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) huart->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the UART DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* UART Tx DMA Abort callback has already been initialised : + /* UART Tx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) { huart->hdmatx->XferAbortCallback = NULL; } @@ -1497,20 +1977,20 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* UART Rx DMA Abort callback has already been initialised : + /* UART Rx DMA Abort callback has already been initialised : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { huart->hdmarx->XferAbortCallback = NULL; abortcplt = 1U; @@ -1521,50 +2001,56 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } } - + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0U; huart->RxXferCount = 0U; - + /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; - + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - + return HAL_OK; } /** * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Tx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1574,30 +2060,31 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { - /* Disable TXEIE and TCIE interrupts */ + /* Disable interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - /* Set the UART DMA Abort callback : + /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - + /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) { /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ huart->hdmatx->XferAbortCallback(huart->hdmatx); @@ -1606,23 +2093,29 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - + huart->TxXferCount = 0U; + /* Clear TxISR function pointers */ huart->TxISR = NULL; - + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - + huart->TxXferCount = 0U; + /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -1632,22 +2125,28 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - + return HAL_OK; } /** * @brief Abort ongoing Receive transfer (Interrupt mode). * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable UART Interrupts (Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1657,31 +2156,32 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* USART_CR1_FIFOEN */ /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback : + /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); @@ -1691,41 +2191,53 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Reset Rx transfer counter */ huart->RxXferCount = 0U; - + /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else { /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - + huart->RxXferCount = 0U; + /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - + return HAL_OK; } @@ -1739,118 +2251,127 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t isrflags = READ_REG(huart->Instance->ISR); uint32_t cr1its = READ_REG(huart->Instance->CR1); uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags; - + uint32_t errorcode; + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) + if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (huart->RxISR != NULL) {huart->RxISR(huart);} + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } return; } - } - + } + /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) #else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) -#endif + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) +#endif /* USART_CR1_FIFOEN */ { /* UART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - + huart->ErrorCode |= HAL_UART_ERROR_PE; } - + /* UART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - + huart->ErrorCode |= HAL_UART_ERROR_FE; } - + /* UART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - + huart->ErrorCode |= HAL_UART_ERROR_NE; } - + /* UART Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) #else - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || - ((cr3its & USART_CR3_EIE) != RESET))) -#endif + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) +#endif /* USART_CR1_FIFOEN */ { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - + huart->ErrorCode |= HAL_UART_ERROR_ORE; } - + /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) + if (huart->ErrorCode != HAL_UART_ERROR_NONE) { /* UART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (huart->RxISR != NULL) {huart->RxISR(huart);} + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + consider error as blocking */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & HAL_UART_ERROR_ORE) != 0U)) { /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); @@ -1859,74 +2380,115 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) else { /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } else { /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - /* Set the UART state ready to be able to start again the process */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } - + /* UART in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (huart->TxISR != NULL) {huart->TxISR(huart);} + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } return; } - + /* UART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) { UART_EndTransmit_IT(huart); return; } - + #if defined(USART_CR1_FIFOEN) /* UART TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } - + /* UART RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } -#endif +#endif /* USART_CR1_FIFOEN */ } /** @@ -1946,29 +2508,29 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callback. - * @param huart UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Transfer completed callback. - * @param huart UART handle. + * @brief Rx Transfer completed callback. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ @@ -1976,22 +2538,22 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callback. - * @param huart UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ } /** - * @brief UART error callback. - * @param huart UART handle. + * @brief UART error callback. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -2009,7 +2571,7 @@ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -2024,7 +2586,7 @@ __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -2039,7 +2601,7 @@ __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -2065,11 +2627,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) UART_SetConfig() API configures the UART peripheral (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver (+) HAL_LIN_SendBreak() API transmits the break characters @@ -2078,44 +2638,42 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) */ /** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Enable USART mute mode by setting the MME bit in the CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } @@ -2132,78 +2690,72 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - + huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. + * @param huart UART handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - + huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Transmit break characters. - * @param huart UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - /* Process Locked */ + __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Send break characters */ - SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); - + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -2212,8 +2764,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * + * @brief UART Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2230,24 +2782,25 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @brief Return the UART handle state. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. + * the configuration information for the specified UART. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1= 0x00U, temp2 = 0x00U; + uint32_t temp1; + uint32_t temp2; temp1 = huart->gState; temp2 = huart->RxState; - + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** -* @brief Return the UART handle error code. + * @brief Return the UART handle error code. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ + * the configuration information for the specified UART. + * @retval UART Error Code + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -2264,6 +2817,32 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) * @{ */ +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#if defined(USART_CR1_FIFOEN) + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif /* USART_CR1_FIFOEN */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @brief Configure the UART peripheral. * @param huart UART handle. @@ -2271,34 +2850,34 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000U; - UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000U; + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; uint32_t lpuart_ker_ck_pres = 0x00000000U; - + /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - if(UART_INSTANCE_LOWPOWER(huart)) + if (UART_INSTANCE_LOWPOWER(huart)) { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); } else { assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); } - + assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); -#endif - +#endif /* USART_PRESC_PRESCALER */ + /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure * the UART Word Length, Parity, Mode and oversampling: @@ -2307,85 +2886,86 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; +#if defined(USART_CR1_FIFOEN) + tmpreg |= (uint32_t)huart->FifoMode; +#endif /* USART_CR1_FIFOEN */ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - + /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - + /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) - * - set TXFTCFG bit according to huart->Init.TxFifoThreshold value - * - set RXFTCFG bit according to huart->Init.RxFifoThreshold value */ + * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - + if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - + #if defined(USART_PRESC_PRESCALER) /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); -#endif - +#endif /* USART_PRESC_PRESCALER */ + /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - + /* Check LPUART instance */ - if(UART_INSTANCE_LOWPOWER(huart)) + if (UART_INSTANCE_LOWPOWER(huart)) { /* Retrieve frequency clock */ switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq()/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); -#endif - break; - case UART_CLOCKSOURCE_HSI: + lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: + lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq()/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); -#endif - break; - case UART_CLOCKSOURCE_LSE: + lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); + lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); #else - lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* if proper clock source reported */ if (lpuart_ker_ck_pres != 0U) { /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || - (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) { ret = HAL_ERROR; } @@ -2393,40 +2973,40 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { @@ -2436,59 +3016,59 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { ret = HAL_ERROR; } - } /* if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */ - } /* if (tmpreg != 0) */ + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (lpuart_ker_ck_pres != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* USARTDIV must be greater than or equal to 0d16 */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { - brrtemp = usartdiv & 0xFFF0U; + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); huart->Instance->BRR = brrtemp; } @@ -2501,47 +3081,47 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { switch (clocksource) { - case UART_CLOCKSOURCE_PCLK1: + case UART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - + /* USARTDIV must be greater than or equal to 0d16 */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { @@ -2552,17 +3132,17 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) ret = HAL_ERROR; } } - + #if defined(USART_CR1_FIFOEN) /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; huart->NbRxDataToProcess = 1; -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; - + return ret; } @@ -2575,65 +3155,65 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - + /* if required, configure TX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); } - + /* if required, configure RX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); } - + /* if required, configure data inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - + /* if required, configure RX/TX pins swap */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); } - + /* if required, configure RX overrun detection disabling */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } - + /* if required, configure DMA disabling on reception error */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } - + /* if required, configure auto Baud rate detection scheme */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); /* set auto Baudrate detection parameters if detection is enabled */ - if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); } } - + /* if required, configure MSB first on communication line */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); @@ -2647,42 +3227,42 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Check if the Transmitter is enabled */ - if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } + /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } - + /* Initialize the UART State */ - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; - - /* Process Unlocked */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -2695,30 +3275,30 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ + __HAL_UNLOCK(huart); - + return HAL_TIMEOUT; } } @@ -2729,17 +3309,19 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { - /* Disable TXEIE and TCIE interrupts */ #if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, TXFT interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); #else + /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -2748,7 +3330,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) @@ -2756,14 +3338,15 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +#endif /* USART_CR1_FIFOEN */ /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Reset RxIsr function pointer */ huart->RxISR = NULL; } @@ -2776,24 +3359,30 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { huart->TxXferCount = 0U; - + /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ + in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } @@ -2804,9 +3393,15 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2816,26 +3411,32 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { huart->RxXferCount = 0U; - + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; } - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2845,9 +3446,15 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2857,41 +3464,57 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + /* Stop UART DMA Tx request if ongoing */ - if ( (huart->gState == HAL_UART_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) { huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ - if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) { huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } - + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** * @brief DMA UART communication abort callback, when initiated by HAL services on Error * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; huart->TxXferCount = 0U; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -2904,43 +3527,49 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->hdmatx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ - if(huart->hdmarx != NULL) + if (huart->hdmarx != NULL) { - if(huart->hdmarx->XferAbortCallback != NULL) + if (huart->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0U; huart->RxXferCount = 0U; - + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } -#endif +#endif /* USART_CR1_FIFOEN */ /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } @@ -2954,38 +3583,44 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->hdmarx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ - if(huart->hdmatx != NULL) + if (huart->hdmatx != NULL) { - if(huart->hdmatx->XferAbortCallback != NULL) + if (huart->hdmatx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ huart->TxXferCount = 0U; huart->RxXferCount = 0U; - + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } @@ -2999,23 +3634,29 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->TxXferCount = 0U; - + #if defined(USART_CR1_FIFOEN) /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -3028,21 +3669,27 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0U; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -3057,21 +3704,22 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; huart->TxXferCount--; } } @@ -3086,28 +3734,28 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; - + uint16_t *tmp; + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if(huart->TxXferCount == 0) + if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } @@ -3123,28 +3771,33 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint8_t nb_tx_data; - + uint16_t nb_tx_data; + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + break; /* force exit loop */ } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; huart->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } @@ -3158,39 +3811,43 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t* tmp; - uint8_t nb_tx_data; - + uint16_t *tmp; + uint16_t nb_tx_data; + /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + break; /* force exit loop */ } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; - huart->TxXferCount--; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ } } } } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -3198,14 +3855,20 @@ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Cleat TxISR function pointer */ huart->TxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } /** @@ -3217,32 +3880,40 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - - if(--huart->RxXferCount == 0) + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else @@ -3261,37 +3932,44 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; + tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - - if(--huart->RxXferCount == 0) + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } else @@ -3313,47 +3991,56 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint8_t nb_rx_data; - + uint16_t nb_rx_data; + uint16_t rxdatacount; + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; huart->RxXferCount--; - - if(huart->RxXferCount == 0U) + + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; - + /* Enable the UART Data Register Not Empty interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } @@ -3374,55 +4061,63 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t* tmp; + uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint8_t nb_rx_data; - + uint16_t nb_rx_data; + uint16_t rxdatacount; + /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; + tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; + huart->pRxBuffPtr += 2U; huart->RxXferCount--; - - if(huart->RxXferCount == 0U) + + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Clear RxISR function pointer */ huart->RxISR = NULL; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; - + /* Enable the UART Data Register Not Empty interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } + } } else { @@ -3430,7 +4125,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h index 34e100955f..02b5947fce 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_UART_H -#define __STM32L4xx_HAL_UART_H +#ifndef STM32L4xx_HAL_UART_H +#define STM32L4xx_HAL_UART_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -64,6 +48,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) UART: ===== - If oversampling is 16 or in LIN mode, @@ -72,11 +60,7 @@ typedef struct Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - - where (uart/lpuart)_ker_ck_pres is the UART input clock divided by a prescaler */ + where uart_ker_ck_pres is the UART input clock (divided by a prescaler if applicable) */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref UARTEx_Word_Length. */ @@ -104,16 +88,16 @@ typedef struct uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - + #if defined(USART_PRESC_PRESCALER) uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of @ref UART_ClockPrescaler. */ -#endif +#endif /* USART_PRESC_PRESCALER */ -}UART_InitTypeDef; +} UART_InitTypeDef; /** - * @brief UART Advanced Features initalization structure definition + * @brief UART Advanced Features initialization structure definition */ typedef struct { @@ -122,10 +106,10 @@ typedef struct This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ + This parameter can be a value of @ref UART_Tx_Inv. */ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ + This parameter can be a value of @ref UART_Rx_Inv. */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). @@ -141,7 +125,7 @@ typedef struct This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable */ + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate detection is carried out. @@ -154,24 +138,24 @@ typedef struct /** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : - * b7-b6 Error information + * b7-b6 Error information * 00 : No Error * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (Peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -181,9 +165,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -192,39 +176,7 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -}HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Error Code structure definition - */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00U, /*!< No error */ - HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04U, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; +typedef uint32_t HAL_UART_StateTypeDef; /** * @brief UART clock sources definition @@ -237,7 +189,7 @@ typedef enum UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}UART_ClockSourceTypeDef; +} UART_ClockSourceTypeDef; /** * @brief UART handle Structure definition @@ -265,18 +217,13 @@ typedef struct __UART_HandleTypeDef uint16_t Mask; /*!< UART Rx RDR register mask */ #if defined(USART_CR1_FIFOEN) + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. - This parameter can be a value of @ref UARTEx_FIFO_mode. */ -#endif - -#if defined(USART_CR2_SLVEN) - uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. - This parameter can be a value of @ref UARTEx_Slave_Mode. */ -#endif +#endif /*USART_CR1_FIFOEN */ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -288,7 +235,7 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of @ref HAL_UART_StateTypeDef */ @@ -297,7 +244,58 @@ typedef struct __UART_HandleTypeDef __IO uint32_t ErrorCode; /*!< UART Error code */ -}UART_HandleTypeDef; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ +#if defined(USART_CR1_FIFOEN) + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ +#endif /* USART_CR1_FIFOEN */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ +#if defined(USART_CR1_FIFOEN) + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ +#endif /* USART_CR1_FIFOEN */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -308,6 +306,46 @@ typedef struct __UART_HandleTypeDef * @{ */ +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ @@ -343,9 +381,9 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_Mode UART Transfer Mode * @{ */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ @@ -380,7 +418,7 @@ typedef struct __UART_HandleTypeDef #if defined(USART_PRESC_PRESCALER) /** @defgroup UART_ClockPrescaler UART Clock Prescaler * @{ - */ + */ #define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -396,14 +434,14 @@ typedef struct __UART_HandleTypeDef /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ /** * @} @@ -512,8 +550,8 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ @@ -539,8 +577,8 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ @@ -548,8 +586,8 @@ typedef struct __UART_HandleTypeDef /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ /** * @} */ @@ -654,10 +692,12 @@ typedef struct __UART_HandleTypeDef * - 0xXXXX : Flag mask in the ISR register * @{ */ +#if defined(USART_CR1_FIFOEN) #define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ #define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ #define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ #define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#endif /* USART_CR1_FIFOEN */ #define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ #define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ #define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ @@ -675,14 +715,14 @@ typedef struct __UART_HandleTypeDef #define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ #else #define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ -#endif +#endif /* USART_CR1_FIFOEN */ #define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ #if defined(USART_CR1_FIFOEN) #define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ #define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ #else #define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ -#endif +#endif /* USART_CR1_FIFOEN */ #define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ #define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ #define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ @@ -700,43 +740,43 @@ typedef struct __UART_HandleTypeDef * - 10: CR2 register * - 11: CR3 register * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#endif -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#endif /* USART_CR1_FIFOEN */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ #if defined(USART_CR1_FIFOEN) -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#endif -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#endif /* USART_CR1_FIFOEN */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ #if defined(USART_CR1_FIFOEN) #define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ #define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ #define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ #define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ -#endif +#endif /* USART_CR1_FIFOEN */ -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) - - XX : Interrupt source register (2bits) - - 01: CR1 register - - 10: CR2 register - - 11: CR3 register */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -746,12 +786,12 @@ typedef struct __UART_HandleTypeDef */ #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #if defined(USART_CR1_FIFOEN) #define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ @@ -775,35 +815,45 @@ typedef struct __UART_HandleTypeDef * @param __HANDLE__ UART handle. * @retval None */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0) + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + /** @brief Flush the UART Data registers. * @param __HANDLE__ specifies the UART Handle. - * @retval None + * @retval None */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0) + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -844,7 +894,7 @@ typedef struct __UART_HandleTypeDef * @retval None */ #define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) -#endif +#endif /* USART_CR1_FIFOEN */ /** @brief Check whether the specified UART flag is set or not. * @param __HANDLE__ specifies the UART Handle. @@ -898,7 +948,7 @@ typedef struct __UART_HandleTypeDef * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ @@ -954,7 +1004,8 @@ typedef struct __UART_HandleTypeDef * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. @@ -979,8 +1030,8 @@ typedef struct __UART_HandleTypeDef * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1013,18 +1064,18 @@ typedef struct __UART_HandleTypeDef * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None - */ + */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None - */ + */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable UART. @@ -1040,14 +1091,14 @@ typedef struct __UART_HandleTypeDef #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * @note This macro allows to enable CTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1055,17 +1106,17 @@ typedef struct __UART_HandleTypeDef do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) + } while(0U) /** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * @note This macro allows to disable CTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1073,17 +1124,17 @@ typedef struct __UART_HandleTypeDef do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) + } while(0U) /** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * @note This macro allows to enable RTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1091,17 +1142,17 @@ typedef struct __UART_HandleTypeDef do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) + } while(0U) /** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * @note This macro allows to disable RTS hardware flow control for a given UART instance, * without need to call HAL_UART_Init() function. * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1109,27 +1160,33 @@ typedef struct __UART_HandleTypeDef do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) + } while(0U) /** * @} */ -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup UART_Private_Variables UART Private Variables - * @{ - */ -static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - /* Private macros --------------------------------------------------------*/ /** @defgroup UART_Private_Macros UART Private Macros * @{ */ #if defined(USART_PRESC_PRESCALER) +/** @brief Get UART clok division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. @@ -1137,7 +1194,8 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ + + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1145,7 +1203,8 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1153,8 +1212,8 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) - +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ + + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register with LPUART. @@ -1162,37 +1221,41 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) - +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) #endif /* USART_PRESC_PRESCALER */ /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) /** @brief Check UART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) + * The maximum Baud Rate is derived from the maximum clock on L4 * divided by the smallest oversampling used on the USART (i.e. 8) + * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) +#else +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. @@ -1208,7 +1271,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. + * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ @@ -1218,58 +1281,58 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__ LPUART frame number of stop bits. + * @param __STOPBITS__ LPUART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ + */ #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ ((__STOPBITS__) == UART_STOPBITS_2)) /** * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. + * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ ((__PARITY__) == UART_PARITY_EVEN) || \ ((__PARITY__) == UART_PARITY_ODD)) /** * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. + * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ + */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. + * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. + * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ + */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ ((__STATE__) == UART_STATE_ENABLE)) /** * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. + * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ + */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ ((__SAMPLING__) == UART_OVERSAMPLING_8)) /** * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. + * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ @@ -1277,7 +1340,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. + * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ @@ -1287,7 +1350,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. + * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ @@ -1295,7 +1358,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. + * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ @@ -1303,7 +1366,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. + * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ @@ -1311,7 +1374,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. + * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ @@ -1319,7 +1382,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. + * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ @@ -1327,7 +1390,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. + * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ @@ -1335,7 +1398,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . + * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ @@ -1343,7 +1406,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. + * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ @@ -1354,7 +1417,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. + * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ @@ -1369,7 +1432,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. + * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ @@ -1377,7 +1440,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. + * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ @@ -1385,7 +1448,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. + * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ @@ -1393,7 +1456,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. + * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ @@ -1401,7 +1464,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. + * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -1409,7 +1472,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ @@ -1417,7 +1480,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. + * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -1425,7 +1488,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. + * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1433,7 +1496,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. + * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ @@ -1441,7 +1504,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. + * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ @@ -1449,7 +1512,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. + * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ @@ -1458,7 +1521,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /** * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. + * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ @@ -1467,7 +1530,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 #if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that UART Prescaler is valid. - * @param __CLOCKPRESCALER__ UART Prescaler value. + * @param __CLOCKPRESCALER__ UART Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ @@ -1482,33 +1545,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that UART RXFIFO threshold level is valid. - * @param __THRESHOLD__ UART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif +#endif /* USART_PRESC_PRESCALER */ /** * @} @@ -1517,6 +1554,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1 /* Include UART HAL Extended module */ #include "stm32l4xx_hal_uart_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1531,10 +1569,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + /** * @} */ @@ -1567,9 +1612,9 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); /** * @} @@ -1611,10 +1656,13 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); /** @addtogroup UART_Private_Functions UART Private Functions * @{ */ - +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** @@ -1633,6 +1681,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); } #endif -#endif /* __STM32L4xx_HAL_UART_H */ +#endif /* STM32L4xx_HAL_UART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c index 84f5600933..e8b9120b21 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c @@ -21,42 +21,21 @@ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - -@- When USART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be configured prior starting RX/TX transfers. - (#) Slave mode enabling/disabling and NSS pin configuration. - - -@- When USART operates in Slave mode, Slave mode must be enabled prior - starting RX/TX transfers. - @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -77,6 +56,20 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ +#endif /* USART_CR1_FIFOEN */ + /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -86,7 +79,7 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); #if defined(USART_CR1_FIFOEN) static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -131,10 +124,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the following table. - + Table 1. UART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | UART frame | @@ -174,71 +167,83 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) { - uint32_t temp = 0x0; - + uint32_t temp; + /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } /* Check the Driver Enable UART instance */ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - + /* Check the Driver Enable polarity */ assert_param(IS_UART_DE_POLARITY(Polarity)); - + /* Check the Driver Enable assertion time */ assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - + /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if(huart->gState == HAL_UART_STATE_RESET) + + if (huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - - if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - + /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - + /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } - /** * @} */ @@ -268,7 +273,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @param huart UART handle. * @retval None */ - __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -284,7 +289,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @param huart UART handle. * @retval None */ -__weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -299,7 +304,7 @@ __weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) * @param huart UART handle. * @retval None */ -__weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -308,7 +313,7 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -316,7 +321,7 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -330,10 +335,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) trigger: address match, Start Bit detection or RXNE bit status. (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode (+) HAL_UARTEx_DisableStopMode() API disables the above functionality - (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt - (+) HAL_UARTEx_EnableSPISlaveMode() API enables the SPI slave mode - (+) HAL_UARTEx_DisableSPISlaveMode() API disables the SPI slave mode - (+) HAL_UARTEx_ConfigNSS API configures the Slave Select input pin (NSS) (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold @@ -345,13 +346,56 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) +#if defined(USART_CR3_UCESM) +/** + * @brief Keep UART Clock enabled when in Stop Mode. + * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled + * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. + * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, + * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UCESM bit */ + SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Clock when in Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UCESM bit */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} +#endif /* USART_CR3_UCESM */ /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; * this API allows to enable longer addresses detection (6-, 7- or 8-bit * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. * @param huart UART handle. * @param AddressLength This parameter can be one of the following values: @@ -362,30 +406,29 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) { /* Check the UART handle allocation */ - if(huart == NULL) + if (huart == NULL) { return HAL_ERROR; } - + /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState to Ready */ return (UART_CheckIdleState(huart)); } - /** * @brief Set Wakeup from Stop mode interrupt flag selection. * @note It is the application responsibility to enable the interrupt used as @@ -401,37 +444,37 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = 0; - + uint32_t tickstart; + /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); } - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } @@ -440,14 +483,13 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return status; } - /** * @brief Enable UART Stop Mode. * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. @@ -458,45 +500,15 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - + /* Set UESM bit */ SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/* MBED */ -/** - * @brief Enable UART Clock in Stop Mode - * The UART keeps the Clock ON during Stop mode - * @param huart: uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Set the USART UESM bit */ - huart->Instance->CR3 |= USART_CR3_UCESM; - - huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } -/* MBED */ /** * @brief Disable UART Stop Mode. @@ -507,192 +519,15 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - + /* Clear UESM bit */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/* MBED */ -/** - * @brief Disable UART Clock in Stop Mode - * @param huart: uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear USART UESM bit */ - huart->Instance->CR3 &= ~(USART_CR3_UCESM); - - huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } -/* MBED */ - - -#if defined(USART_CR2_SLVEN) -/** - * @brief Enable the SPI slave mode. - * @note When the UART operates in SPI slave mode, it handles data flow using - * the serial interface clock derived from the external SCLK signal - * provided by the external master SPI device. - * @note In SPI slave mode, the UART must be enabled before starting the master - * communications (or between frames while the clock is stable). Otherwise, - * if the UART slave is enabled while the master is in the middle of a - * frame, it will become desynchronized with the master. - * @note The data register of the slave needs to be ready before the first edge - * of the communication clock or before the end of the ongoing communication, - * otherwise the SPI slave will transmit zeros. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* In SPI slave mode mode, the following bits must be kept cleared: - - LINEN and CLKEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable SPI slave mode */ - SET_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Enable UART */ - __HAL_UART_ENABLE(huart); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the SPI slave mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Disable SPI slave mode */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Configure the Slave Select input pin (NSS). - * @note Software NSS management: SPI slave will always be selected and NSS - * input pin will be ignored. - * @note Hardware NSS management: the SPI slave selection depends on NSS - * input pin. The slave is selected when NSS is low and deselected when - * NSS is high. - * @param huart UART handle. - * @param NSSConfig NSS configuration. - * This parameter can be one of the following values: - * @arg @ref UART_NSS_HARD - * @arg @ref UART_NSS_SOFT - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - assert_param(IS_UART_NSS(NSSConfig)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Program DIS_NSS bit in the USART_CR2 register */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} -#endif #if defined(USART_CR1_FIFOEN) /** @@ -702,37 +537,37 @@ HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSCo */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_ENABLE; - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -743,34 +578,34 @@ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -789,37 +624,37 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } @@ -838,40 +673,40 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint3 */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - + /* Disable UART */ __HAL_UART_DISABLE(huart); - + /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - + /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -894,10 +729,10 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - + /* Set the USART address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - + /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } @@ -910,32 +745,31 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy * @param huart UART handle. * @retval None */ -void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { uint8_t rx_fifo_depth; uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + if (huart->FifoMode == UART_FIFOMODE_DISABLE) { - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; } else { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } -#endif - +#endif /* USART_CR1_FIFOEN */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h index 3b4c4b01ad..b6e9e5e577 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_UART_EX_H -#define __STM32L4xx_HAL_UART_EX_H +#ifndef STM32L4xx_HAL_UART_EX_H +#define STM32L4xx_HAL_UART_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -62,7 +46,7 @@ */ typedef struct { - uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up. */ @@ -85,36 +69,35 @@ typedef struct /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ - + /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management - * @{ - */ -#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ -#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ -/** - * @} - */ -#endif - #if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level - * @brief UART TXFIFO level + * @brief UART TXFIFO threshold level * @{ */ #define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ @@ -126,9 +109,9 @@ typedef struct /** * @} */ - + /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level - * @brief UART RXFIFO level + * @brief UART RXFIFO threshold level * @{ */ #define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ @@ -140,7 +123,7 @@ typedef struct /** * @} */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -157,7 +140,8 @@ typedef struct */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); /** * @} @@ -167,13 +151,12 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -/* IO operation functions *****************************************************/ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); #if defined(USART_CR1_FIFOEN) void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -186,28 +169,18 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); /* Peripheral Control functions **********************************************/ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); -/* MBED */ -HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); -/* MBED */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); -/* MBED */ +#if defined(USART_CR3_UCESM) +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); -/* MBED */ +#endif /* USART_CR3_UCESM */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - -#if defined(USART_CR2_SLVEN) -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig); -#endif - #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -#endif - +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -217,35 +190,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * @} */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Constants UARTEx Private Constants - * @{ - */ -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode - * @{ - */ -#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ -#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode - * @{ - */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ -#endif -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup UARTEx_Private_Macros UARTEx Private Macros * @{ @@ -256,15 +200,15 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \ + || defined (STM32L496xx) || defined (STM32L4A6xx) \ + || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -280,12 +224,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -301,12 +245,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -322,12 +266,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -343,12 +287,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART5) \ { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ case RCC_UART5CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -364,12 +308,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -385,16 +329,21 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ - } while(0) -#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined (STM32L412xx) || defined (STM32L422xx) \ + || defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -410,12 +359,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -431,12 +380,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -452,12 +401,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -473,16 +422,20 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ - } while(0) + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #elif defined (STM32L432xx) || defined (STM32L442xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -498,12 +451,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -519,12 +472,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -540,16 +493,20 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ - } while(0) + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -565,12 +522,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -586,12 +543,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -607,12 +564,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -628,12 +585,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ case RCC_LPUART1CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -649,10 +606,17 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ - } while(0) -#endif + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || + * STM32L496xx || STM32L4A6xx || + * STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx + */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -660,50 +624,53 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ -} while(0) - + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. + * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ @@ -712,47 +679,37 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 /** * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. + * @param __ADDRESS__ UART wake-up address length. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) -#if defined(USART_CR2_SLVEN) -/** - * @brief Ensure that UART Negative Slave Select (NSS) pin management is valid. - * @param __NSS__ UART Negative Slave Select pin management. - * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) - */ -#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \ - ((__NSS__) == UART_NSS_SOFT)) -#endif - #if defined(USART_CR1_FIFOEN) /** * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. + * @param __THRESHOLD__ UART TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) /** - * @brief Ensure that USART RXFIFO threshold level is valid. - * @param __THRESHOLD__ USART RXFIFO threshold level. + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -772,6 +729,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 } #endif -#endif /* __STM32L4xx_HAL_UART_EX_H */ +#endif /* STM32L4xx_HAL_UART_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c index af1c56627f..142c155063 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c @@ -50,36 +50,87 @@ [..] (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's - HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and - HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_USART_RegisterCallback() to register a user callback. + Function @ref HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init() + and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit() + or @ref HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -104,8 +155,7 @@ * @{ */ #define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ -#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */ - +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ #if defined(USART_CR1_FIFOEN) #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ @@ -121,9 +171,10 @@ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ -#endif +#endif /* USART_CR1_FIFOEN */ #define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ /** * @} */ @@ -134,6 +185,9 @@ /** @addtogroup USART_Private_Functions * @{ */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ static void USART_EndTransfer(USART_HandleTypeDef *husart); static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); @@ -143,7 +197,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma); static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); @@ -151,14 +206,14 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); #if defined(USART_CR1_FIFOEN) static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); -#endif +#endif /* USART_CR1_FIFOEN */ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); #if defined(USART_CR1_FIFOEN) static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); -#endif +#endif /* USART_CR1_FIFOEN */ /** @@ -172,7 +227,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); */ /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -198,10 +253,10 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); @endverbatim - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible USART formats are listed in the + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the following table. - + Table 1. USART frame format. +-----------------------------------------------------------------------+ | M1 bit | M0 bit | PCE bit | USART frame | @@ -231,7 +286,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { /* Check the USART handle allocation */ - if(husart == NULL) + if (husart == NULL) { return HAL_ERROR; } @@ -239,13 +294,25 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* Check the parameters */ assert_param(IS_USART_INSTANCE(husart->Instance)); - if(husart->State == HAL_USART_STATE_RESET) + if (husart->State == HAL_USART_STATE_RESET) { /* Allocate lock resource and initialize it */ husart->Lock = HAL_UNLOCKED; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else /* Init the low level hardware : GPIO, CLOCK */ HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } husart->State = HAL_USART_STATE_BUSY; @@ -279,8 +346,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { - /* Check the USART handle allocation */ - if(husart == NULL) + /* Check the USART handle allocation */ + if (husart == NULL) { return HAL_ERROR; } @@ -290,12 +357,21 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_BUSY; - husart->Instance->CR1 = 0x0; - husart->Instance->CR2 = 0x0; - husart->Instance->CR3 = 0x0; + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_RESET; @@ -311,11 +387,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ - __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspInit can be implemented in the user file */ @@ -326,22 +402,276 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ - __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspDeInit can be implemented in the user file */ } +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used instead of the weak predefined callback + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(husart); + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = pCallback; + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = pCallback; + break; +#endif /* USART_CR1_FIFOEN */ + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(husart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param husart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(husart); + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + +#if defined(USART_CR1_FIFOEN) + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; +#endif /* USART_CR1_FIFOEN */ + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(husart); + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + /** * @} */ /** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions + * @brief USART Transmit and Receive functions * @verbatim =============================================================================== @@ -353,32 +683,34 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) [..] The USART supports master mode only: it cannot receive or send data related to an input clock (SCLK is always an output). + [..] + (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (++) HAL_USART_Transmit()in simplex mode + (++) HAL_USART_Transmit() in simplex mode (++) HAL_USART_Receive() in full duplex receive only (++) HAL_USART_TransmitReceive() in full duplex mode (#) Non-Blocking mode API's with Interrupt are : - (++) HAL_USART_Transmit_IT()in simplex mode + (++) HAL_USART_Transmit_IT() in simplex mode (++) HAL_USART_Receive_IT() in full duplex receive only - (++) HAL_USART_TransmitReceive_IT()in full duplex mode + (++) HAL_USART_TransmitReceive_IT() in full duplex mode (++) HAL_USART_IRQHandler() (#) No-Blocking mode API's with DMA are : - (++) HAL_USART_Transmit_DMA()in simplex mode + (++) HAL_USART_Transmit_DMA() in simplex mode (++) HAL_USART_Receive_DMA() in full duplex receive only (++) HAL_USART_TransmitReceive_DMA() in full duplex mode (++) HAL_USART_DMAPause() @@ -394,22 +726,22 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) (++) HAL_USART_TxRxCpltCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_USART_Abort() - (+) HAL_USART_Abort_IT() + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: - (+) HAL_USART_AbortCpltCallback() + (++) HAL_USART_AbortCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -425,68 +757,81 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - uint32_t tickstart = 0; + uint8_t *ptxdata8bits; + uint16_t *ptxdata16bits; + uint32_t tickstart; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->TxXferSize = Size; husart->TxXferCount = Size; - - /* Check the remaining data to be sent */ - while(husart->TxXferCount > 0) + + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + ptxdata8bits = NULL; + ptxdata16bits = (uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + + /* Check the remaining data to be sent */ + while (husart->TxXferCount > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (ptxdata8bits == NULL) { - tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pTxData += 2; + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; } - + husart->TxXferCount--; } - - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear Transmission Complete Flag */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - + /* Clear overrun flag and discard the received data */ __HAL_USART_CLEAR_OREFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); - + /* At end of Tx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -506,72 +851,85 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; uint16_t uhMask; - uint32_t tickstart = 0; - - if(husart->State == HAL_USART_STATE_READY) + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if ((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->RxXferSize = Size; husart->RxXferCount = Size; - + /* Computation of USART mask to apply to RDR register */ USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + /* as long as data have to be received */ - while(husart->RxXferCount > 0) + while (husart->RxXferCount > 0U) { #if defined(USART_CR2_SLVEN) if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) -#endif +#endif /* USART_CR2_SLVEN */ { /* Wait until TXE flag is set to send dummy byte in order to generate the * clock for the slave to send data. * Whatever the frame length (7, 8 or 9-bit long), the same dummy value * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); } - + /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + + if (prxdata8bits == NULL) { - tmp = (uint16_t*) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; } else { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; } - + husart->RxXferCount--; - + } - + #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) @@ -579,14 +937,14 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat __HAL_USART_CLEAR_UDRFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR2_SLVEN */ + /* At end of Rx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -604,19 +962,24 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint8_t *ptxdata8bits; + uint16_t *ptxdata16bits; uint16_t uhMask; - uint32_t tickstart = 0; + uint16_t rxdatacount; + uint32_t tickstart; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); @@ -635,76 +998,95 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + #if defined(USART_CR2_SLVEN) - if ((husart->SlaveMode == USART_SLAVEMODE_ENABLE) || (husart->TxXferCount == 0x01U)) + if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE)) #else if (husart->TxXferCount == 0x01U) -#endif +#endif /* USART_CR2_SLVEN */ { /* Wait until TXE flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (ptxdata8bits == NULL) { - tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2U; + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; } else - { - husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; } husart->TxXferCount--; } - + /* Check the remain data to be sent */ - while ((husart->TxXferCount > 0) || (husart->RxXferCount > 0)) + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) { - if (husart->TxXferCount > 0) + if (husart->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if (ptxdata8bits == NULL) { - tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; } - + husart->TxXferCount--; } - - if (husart->RxXferCount > 0) + + if (husart->RxXferCount > 0U) { /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + + if (prxdata8bits == NULL) { - tmp = (uint16_t*) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; } else { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; } - + husart->RxXferCount--; } + rxdatacount = husart->RxXferCount; } /* At end of TxRx process, restore husart->State to Ready */ @@ -730,9 +1112,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if ((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -757,7 +1139,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT #if defined(USART_CR1_FIFOEN) /* Configure Tx interrupt processing */ if (husart->FifoMode == USART_FIFOMODE_ENABLE) - { + { /* Set the Tx ISR function pointer according to the data word length */ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { @@ -766,16 +1148,16 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT else { husart->TxISR = USART_TxISR_8BIT_FIFOEN; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the TX FIFO threshold interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); } else -#endif +#endif /* USART_CR1_FIFOEN */ { /* Set the Tx ISR function pointer according to the data word length */ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) @@ -785,11 +1167,11 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT else { husart->TxISR = USART_TxISR_8BIT; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Transmit Data Register Empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); } @@ -803,7 +1185,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT } /** - * @brief Receive an amount of data in blocking mode. + * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. * @param husart USART handle. * @param pRxData pointer to data buffer. @@ -813,12 +1195,12 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { #if defined(USART_CR1_FIFOEN) - uint8_t nb_dummy_data; -#endif - - if(husart->State == HAL_USART_STATE_READY) + uint16_t nb_dummy_data; +#endif /* USART_CR1_FIFOEN */ + + if (husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if ((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -852,16 +1234,16 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { husart->RxISR = USART_RxISR_8BIT_FIFOEN; } - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else -#endif +#endif /* USART_CR1_FIFOEN */ { /* Set the Rx ISR function pointer according to the data word length */ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) @@ -872,21 +1254,21 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { husart->RxISR = USART_RxISR_8BIT; } - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Parity Error and Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); -#endif +#endif /* USART_CR1_FIFOEN */ } #if defined(USART_CR2_SLVEN) if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) -#endif +#endif /* USART_CR2_SLVEN */ { /* Send dummy data in order to generate the clock for the Slave to send the next data. When FIFO mode is disabled only one data must be transferred. @@ -895,18 +1277,18 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx #if defined(USART_CR1_FIFOEN) if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) { - for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0 ; nb_dummy_data--) + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--) { husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } } else -#endif +#endif /* USART_CR1_FIFOEN */ { husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } } - + return HAL_OK; } else @@ -919,19 +1301,21 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. + * @param pRxData pointer to RX data buffer. * @param Size amount of data to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -947,7 +1331,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - + #if defined(USART_CR1_FIFOEN) /* Configure TxRx interrupt processing */ if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) @@ -963,13 +1347,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->TxISR = USART_TxISR_8BIT_FIFOEN; husart->RxISR = USART_RxISR_8BIT_FIFOEN; } - + /* Process Locked */ __HAL_UNLOCK(husart); - + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Enable the USART Parity Error interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -977,7 +1361,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); } else -#endif +#endif /* USART_CR1_FIFOEN */ { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { @@ -992,23 +1376,23 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Process Locked */ __HAL_UNLOCK(husart); - + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ #if defined(USART_CR1_FIFOEN) SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); #else - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); -#endif - + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif /* USART_CR1_FIFOEN */ + /* Enable the USART Transmit Data Register Empty Interrupt */ #if defined(USART_CR1_FIFOEN) SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); #else SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); -#endif +#endif /* USART_CR1_FIFOEN */ } return HAL_OK; @@ -1028,14 +1412,16 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { + HAL_StatusTypeDef status = HAL_OK; uint32_t *tmp; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL ) || (Size == 0)) + if ((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -1046,30 +1432,49 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - /* Set the USART DMA transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - /* Set the DMA error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Enable the USART transmit DMA channel */ + tmp = (uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } - /* Clear the TC flag in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Process Unlocked */ + __HAL_UNLOCK(husart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - return HAL_OK; + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1079,22 +1484,23 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @param husart USART handle. * @param pRxData pointer to data buffer. * @param Size amount of data to be received. - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp; + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; /* Check that a Rx process is not already ongoing */ - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL ) || (Size == 0)) + if ((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1110,52 +1516,82 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; - /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + } #if defined(USART_CR2_SLVEN) - if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + if ((status == HAL_OK) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#endif /* USART_CR2_SLVEN */ { /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive mode */ - tmp = (uint32_t*)&pRxData; + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + /* Set the USART DMA Tx Complete and Error callback to Null */ - husart->hdmatx->XferErrorCallback = NULL; - husart->hdmatx->XferHalfCpltCallback = NULL; - husart->hdmatx->XferCpltCallback = NULL; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } } -#endif - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - return HAL_OK; + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if (husart->hdmarx != NULL) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1165,23 +1601,26 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. * @param Size amount of data to be received/sent. - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { + HAL_StatusTypeDef status; uint32_t *tmp; - if(husart->State == HAL_USART_STATE_READY) + if (husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -1193,53 +1632,87 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - /* Set the USART DMA Tx transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - /* Set the USART DMA Tx transfer error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; - /* Enable the USART receive DMA channel */ - tmp = (uint32_t*)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); + /* Enable the USART receive DMA channel */ + tmp = (uint32_t *)&pRxData; + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); - /* Enable the USART transmit DMA channel */ - tmp = (uint32_t*)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Enable the USART transmit DMA channel */ + if (status == HAL_OK) + { + tmp = (uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } + } + else + { + status = HAL_ERROR; + } - /* Process Unlocked */ - __HAL_UNLOCK(husart); + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Clear the TC flag in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - return HAL_OK; + return HAL_OK; + } + else + { + if (husart->hdmarx != NULL) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } } else { @@ -1254,33 +1727,39 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin */ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + /* Process Locked */ __HAL_LOCK(husart); - if( (husart->State == HAL_USART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if( (husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } + } if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { + { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Disable the USART DMA Rx request */ + /* Disable the USART DMA Rx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1295,19 +1774,21 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + /* Process Locked */ __HAL_LOCK(husart); - if(husart->State == HAL_USART_STATE_BUSY_TX) + if (state == HAL_USART_STATE_BUSY_TX) { /* Enable the USART DMA Tx request */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if( (husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -1319,6 +1800,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /* Enable the USART DMA Tx request */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } + else + { + /* Nothing to do */ + } /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1335,24 +1820,42 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) { /* The Lock is not implemented on this API to allow the user application to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / - HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ /* Disable the USART Tx/Rx DMA requests */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA tx channel */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - HAL_DMA_Abort(husart->hdmatx); + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } /* Abort the USART DMA rx channel */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - HAL_DMA_Abort(husart->hdmarx); + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } USART_EndTransfer(husart); @@ -1364,7 +1867,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) /** * @brief Abort ongoing transfers (blocking mode). * @param husart USART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable USART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1372,17 +1875,18 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { #if defined(USART_CR1_FIFOEN) /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) @@ -1390,13 +1894,22 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - /* Set the USART DMA Abort callback to Null. + /* Set the USART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(husart->hdmatx); + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } @@ -1406,19 +1919,28 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - /* Set the USART DMA Abort callback to Null. + /* Set the USART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(husart->hdmarx); + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } } /* Reset Tx and Rx transfer counters */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); @@ -1429,8 +1951,8 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Discard the received data */ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); @@ -1446,7 +1968,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) /** * @brief Abort ongoing transfers (Interrupt mode). * @param husart USART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable USART Interrupts (Tx and Rx) * - Disable the DMA transfer in the peripheral register (if enabled) @@ -1456,28 +1978,29 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { - uint32_t abortcplt = 1; - + uint32_t abortcplt = 1U; + #if defined(USART_CR1_FIFOEN) /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; } @@ -1487,11 +2010,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } /* DMA Rx Handle is valid */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; } @@ -1500,27 +2023,27 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) husart->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the USART DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at USART level */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - /* USART Tx DMA Abort callback has already been initialised : + /* USART Tx DMA Abort callback has already been initialised : will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) { husart->hdmatx->XferAbortCallback = NULL; } else { - abortcplt = 0; + abortcplt = 0U; } } } @@ -1531,30 +2054,30 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - /* USART Rx DMA Abort callback has already been initialised : + /* USART Rx DMA Abort callback has already been initialised : will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) { husart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Reset errorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -1568,16 +2091,22 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } - -#endif +#endif /* USART_CR1_FIFOEN */ + /* Discard the received data */ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - + /* Restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } return HAL_OK; @@ -1595,84 +2124,88 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t cr3its = READ_REG(husart->Instance->CR3); uint32_t errorflags; - + uint32_t errorcode; + /* If no error occurs */ #if defined(USART_CR2_SLVEN) errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); #else errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); -#endif - if (errorflags == RESET) +#endif /* USART_CR2_SLVEN */ + if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (husart->RxISR != NULL) {husart->RxISR(husart);} + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } return; } } - + /* If some errors occur */ #if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != 0U) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) #else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) -#endif + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) +#endif /* USART_CR1_FIFOEN */ { /* USART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - + husart->ErrorCode |= HAL_USART_ERROR_PE; } - + /* USART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - + husart->ErrorCode |= HAL_USART_ERROR_FE; } - + /* USART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - + husart->ErrorCode |= HAL_USART_ERROR_NE; } - + /* USART Over-Run interrupt occurred -----------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) #else - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || - ((cr3its & USART_CR3_EIE) != RESET))) -#endif + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) +#endif /* USART_CR1_FIFOEN */ { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - + husart->ErrorCode |= HAL_USART_ERROR_ORE; } - + #if defined(USART_CR2_SLVEN) /* USART SPI slave underrun error interrupt occurred -------------------------*/ - if(((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { /* Ignore SPI slave underrun errors when reception is going on */ if (husart->State == HAL_USART_STATE_BUSY_RX) @@ -1686,59 +2219,63 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->ErrorCode |= HAL_USART_ERROR_UDR; } } -#endif - +#endif /* USART_CR2_SLVEN */ + /* Call USART Error Call back function if need be --------------------------*/ - if(husart->ErrorCode != HAL_USART_ERROR_NONE) + if (husart->ErrorCode != HAL_USART_ERROR_NONE) { /* USART in mode Receiver ---------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (husart->RxISR != NULL) {husart->RxISR(husart);} + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) - { + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) + { /* Blocking error : transfer is aborted - Set the USART state ready to be able to start again the process, - Disable Interrupts, and disable DMA requests, if ongoing */ + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - + /* Disable the USART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); - + /* Abort the USART DMA Tx channel */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { /* Set the USART Tx DMA Abort callback to NULL : no callback - executed at end of DMA abort procedure */ + executed at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; - + /* Abort DMA TX */ - HAL_DMA_Abort_IT(husart->hdmatx); + (void)HAL_DMA_Abort_IT(husart->hdmatx); } - + /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - /* Set the USART Rx DMA Abort callback : - will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; - + /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) { /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ husart->hdmarx->XferAbortCallback(husart->hdmarx); @@ -1747,64 +2284,97 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) else { /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } else { /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } else { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ husart->ErrorCode = HAL_USART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - - + + /* USART in mode Transmitter ------------------------------------------------*/ #if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET))) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) #else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) -#endif + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) +#endif /* USART_CR1_FIFOEN */ { - if (husart->TxISR != NULL) {husart->TxISR(husart);} + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } return; } - + /* USART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) { USART_EndTransmit_IT(husart); return; } - + #if defined(USART_CR1_FIFOEN) /* USART TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->TxFifoEmptyCallback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ HAL_USARTEx_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ return; } - + /* USART RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->RxFifoFullCallback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ HAL_USARTEx_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ return; } -#endif +#endif /* USART_CR1_FIFOEN */ } /** @@ -1816,7 +2386,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxCpltCallback can be implemented in the user file. */ @@ -1827,11 +2397,11 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ - __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1846,7 +2416,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_RxCpltCallback can be implemented in the user file. */ @@ -1861,7 +2431,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_RxHalfCpltCallback can be implemented in the user file */ @@ -1876,7 +2446,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxRxCpltCallback can be implemented in the user file */ @@ -1891,7 +2461,7 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_ErrorCallback can be implemented in the user file. */ @@ -1902,7 +2472,7 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ -__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -1917,8 +2487,8 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief USART Peripheral State and Error functions - * + * @brief USART Peripheral State and Error functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -1964,8 +2534,31 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ /** @defgroup USART_Private_Functions USART Private Functions - * @{ - */ + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ +#if defined(USART_CR1_FIFOEN) + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +#endif /* USART_CR1_FIFOEN */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ /** * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). @@ -1976,13 +2569,14 @@ static void USART_EndTransfer(USART_HandleTypeDef *husart) { #if defined(USART_CR1_FIFOEN) /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); #else /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); -#endif +#endif /* USART_CR1_FIFOEN */ /* At end of process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -1995,14 +2589,14 @@ static void USART_EndTransfer(USART_HandleTypeDef *husart) */ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - husart->TxXferCount = 0; + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + husart->TxXferCount = 0U; - if(husart->State == HAL_USART_STATE_BUSY_TX) + if (husart->State == HAL_USART_STATE_BUSY_TX) { /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the USART CR3 register */ @@ -2015,11 +2609,17 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Circular mode */ else { - if(husart->State == HAL_USART_STATE_BUSY_TX) + if (husart->State == HAL_USART_STATE_BUSY_TX) { - HAL_USART_TxCpltCallback(husart); - } - } +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } } /** @@ -2029,9 +2629,15 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2041,46 +2647,70 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); - + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - husart->RxXferCount = 0; - + husart->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ + in USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ + clock to the slave device */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if (husart->State == HAL_USART_STATE_BUSY_RX) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - husart->State= HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; } /* DMA circular mode */ else { - if(husart->State == HAL_USART_STATE_BUSY_RX) + if (husart->State == HAL_USART_STATE_BUSY_RX) { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } } } @@ -2092,9 +2722,15 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2104,16 +2740,22 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMAError(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - husart->RxXferCount = 0; - husart->TxXferCount = 0; + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; USART_EndTransfer(husart); husart->ErrorCode |= HAL_USART_ERROR_DMA; - husart->State= HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2124,11 +2766,17 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) */ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); - husart->RxXferCount = 0; - husart->TxXferCount = 0; + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } /** @@ -2141,22 +2789,22 @@ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent); - + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->hdmatx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(husart->hdmarx != NULL) + if (husart->hdmarx != NULL) { - if(husart->hdmarx->XferAbortCallback != NULL) + if (husart->hdmarx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Reset errorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2168,7 +2816,14 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) husart->State = HAL_USART_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } @@ -2182,22 +2837,22 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent); - + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ - if(husart->hdmatx != NULL) + if (husart->hdmatx != NULL) { - if(husart->hdmatx->XferAbortCallback != NULL) + if (husart->hdmatx->XferAbortCallback != NULL) { return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - husart->TxXferCount = 0; - husart->RxXferCount = 0; + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; /* Reset errorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2209,7 +2864,13 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) husart->State = HAL_USART_STATE_READY; /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } @@ -2222,21 +2883,22 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ - while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - husart->State= HAL_USART_STATE_READY; - + husart->State = HAL_USART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_TIMEOUT; } } @@ -2251,11 +2913,11 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { - uint32_t tmpreg = 0x0; - USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp; + uint32_t usartdiv = 0x00000000; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -2268,15 +2930,15 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) assert_param(IS_USART_MODE(husart->Init.Mode)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); -#endif - +#endif /* USART_PRESC_PRESCALER */ + /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits and configure - * the USART Word Length, Parity and Mode: - * set the M bits according to husart->Init.WordLength value - * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); @@ -2286,7 +2948,6 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) * set CPHA bit according to husart->Init.CLKPhase value * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = 0; tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); @@ -2298,59 +2959,58 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Configure * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); -#endif +#endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART BRR Configuration -----------------------*/ - /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ USART_GETCLOCKSOURCE(husart, clocksource); - + switch (clocksource) { - case USART_CLOCKSOURCE_PCLK1: + case USART_CLOCKSOURCE_PCLK1: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); -#endif - break; - case USART_CLOCKSOURCE_PCLK2: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case USART_CLOCKSOURCE_PCLK2: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); -#endif - break; - case USART_CLOCKSOURCE_HSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case USART_CLOCKSOURCE_HSI: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); -#endif - break; - case USART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case USART_CLOCKSOURCE_SYSCLK: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); -#endif - break; - case USART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + case USART_CLOCKSOURCE_LSE: #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); #else - usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); -#endif - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); +#endif /* USART_PRESC_PRESCALER */ + break; + default: + ret = HAL_ERROR; + break; } - - /* USARTDIV must be greater than or equal to 0d16 */ - if (usartdiv >= USART_BRR_MIN) + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) { - brrtemp = usartdiv & 0xFFF0U; + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); husart->Instance->BRR = brrtemp; } @@ -2358,28 +3018,28 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { ret = HAL_ERROR; } - + #if defined(USART_CR1_FIFOEN) /* Initialize the number of data to process during RX/TX ISR execution */ - husart->NbTxDataToProcess = 1; - husart->NbRxDataToProcess = 1; -#endif - + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; +#endif /* USART_CR1_FIFOEN */ + /* Clear ISR function pointers */ husart->RxISR = NULL; husart->TxISR = NULL; - + return ret; } /** * @brief Check the USART Idle State. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) { - uint32_t tickstart = 0; + uint32_t tickstart; /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; @@ -2388,20 +3048,20 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ - if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; } } /* Check if the Receiver is enabled */ - if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2409,7 +3069,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) } /* Initialize the USART state*/ - husart->State= HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -2429,21 +3089,24 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) */ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - if(husart->TxXferCount == 0) + if (husart->TxXferCount == 0U) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } else { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; husart->TxXferCount--; } } @@ -2461,24 +3124,25 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) */ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; - - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + const HAL_USART_StateTypeDef state = husart->State; + uint16_t *tmp; + + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - if(husart->TxXferCount == 0) + if (husart->TxXferCount == 0U) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } else { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + tmp = (uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; husart->TxXferCount--; } } @@ -2497,29 +3161,36 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) */ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint8_t nb_tx_data; + const HAL_USART_StateTypeDef state = husart->State; + uint16_t nb_tx_data; + /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) { - if(husart->TxXferCount == 0) + if (husart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - + break; /* force exit loop */ } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; husart->TxXferCount--; } - } + else + { + /* Nothing to do */ + } + } } } @@ -2535,37 +3206,41 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) */ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint16_t* tmp; - uint8_t nb_tx_data; - + const HAL_USART_StateTypeDef state = husart->State; + uint16_t *tmp; + uint16_t nb_tx_data; + /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_TX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(husart->TxXferCount == 0) + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - + break; /* force exit loop */ } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + tmp = (uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; husart->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } -#endif - +#endif /* USART_CR1_FIFOEN */ /** * @brief Wraps up transmission in non-blocking mode. @@ -2583,24 +3258,40 @@ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) /* Clear TxISR function pointer */ husart->TxISR = NULL; - + if (husart->State == HAL_USART_STATE_BUSY_TX) { /* Clear overrun flag and discard the received data */ __HAL_USART_CLEAR_OREFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - + /* Tx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if (husart->RxXferCount == 0) + else if (husart->RxXferCount == 0U) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } @@ -2616,29 +3307,44 @@ static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) */ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) { + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; uint16_t uhMask = husart->Mask; - - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) +#if defined(USART_CR1_FIFOEN) + uint32_t txftie; +#endif /* USART_CR1_FIFOEN */ + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - - if(--husart->RxXferCount == 0) + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - +#endif /* USART_CR1_FIFOEN */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + +#if defined(USART_CR1_FIFOEN) + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); +#else + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ +#endif /* USART_CR1_FIFOEN */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2647,32 +3353,58 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_UDRFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR2_SLVEN */ + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) +#if defined(USART_CR1_FIFOEN) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) +#else + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) +#endif /* USART_CR1_FIFOEN */ { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } #if defined(USART_CR2_SLVEN) - else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) -#endif + else if (state == HAL_USART_STATE_BUSY_RX) +#endif /* USART_CR2_SLVEN */ { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); - } + } + else + { + /* Nothing to do */ + } } } @@ -2687,32 +3419,46 @@ static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) */ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t *tmp; uint16_t uhMask = husart->Mask; +#if defined(USART_CR1_FIFOEN) + uint32_t txftie; +#endif /* USART_CR1_FIFOEN */ - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - tmp = (uint16_t*) husart->pRxBuffPtr; + tmp = (uint16_t *) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; - - if(--husart->RxXferCount == 0) + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ #if defined(USART_CR1_FIFOEN) CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif +#endif /* USART_CR1_FIFOEN */ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + +#if defined(USART_CR1_FIFOEN) + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); +#else + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ +#endif /* USART_CR1_FIFOEN */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2721,32 +3467,58 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_UDRFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR2_SLVEN */ + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) +#if defined(USART_CR1_FIFOEN) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) +#else + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) +#endif /* USART_CR1_FIFOEN */ { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } #if defined(USART_CR2_SLVEN) - else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) -#endif + else if (state == HAL_USART_STATE_BUSY_RX) +#endif /* USART_CR2_SLVEN */ { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } @@ -2757,36 +3529,46 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) * interruptions have been enabled by HAL_USART_Receive_IT(). * @note ISR function executed when FIFO mode is enabled and when the * data word length is less than 9 bits long. + * @param husart USART handle * @retval None - * @retval HAL status */ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) { + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; uint16_t uhMask = husart->Mask; - uint8_t nb_rx_data; - + uint16_t nb_rx_data; + uint32_t txftie; + /* Check that a Rx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - - if(--husart->RxXferCount == 0) + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if (husart->State == HAL_USART_STATE_BUSY_RX) + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2795,58 +3577,82 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_UDRFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR2_SLVEN */ + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } - else if ((husart->TxXferCount == 0) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); - } +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } } #if defined(USART_CR2_SLVEN) - else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + else if ((state == HAL_USART_STATE_BUSY_RX) && (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) -#endif + else if (state == HAL_USART_STATE_BUSY_RX) +#endif /* USART_CR2_SLVEN */ { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) { /* Disable the USART RXFT interrupt*/ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ husart->RxISR = USART_RxISR_8BIT; - + /* Enable the USART Data Register Not Empty interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - + #if defined(USART_CR2_SLVEN) - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && - (husart->TxXferCount == 0U)) + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->TxXferCount == 0U)) -#endif + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX)) +#endif /* USART_CR2_SLVEN */ { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); @@ -2871,34 +3677,43 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) */ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { - uint16_t* tmp; + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t *tmp; uint16_t uhMask = husart->Mask; - uint8_t nb_rx_data; - + uint16_t nb_rx_data; + uint32_t txftie; + /* Check that a Tx process is ongoing */ - if ((husart->State == HAL_USART_STATE_BUSY_RX) || - (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) { - for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) { - tmp = (uint16_t*) husart->pRxBuffPtr; + tmp = (uint16_t *) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; - - if(--husart->RxXferCount == 0) + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) { /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - + /* Clear RxISR function pointer */ husart->RxISR = NULL; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) { #if defined(USART_CR2_SLVEN) /* Clear SPI slave underrun flag and discard transmit data */ @@ -2907,58 +3722,82 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_UDRFLAG(husart); __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); } -#endif - +#endif /* USART_CR2_SLVEN */ + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ HAL_USART_RxCpltCallback(husart); - } - else if ((husart->TxXferCount == 0) && - (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) { /* TxRx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ } } #if defined(USART_CR2_SLVEN) - else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + else if ((state == HAL_USART_STATE_BUSY_RX) && (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - else if (husart->State == HAL_USART_STATE_BUSY_RX) -#endif + else if (state == HAL_USART_STATE_BUSY_RX) +#endif /* USART_CR2_SLVEN */ { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } + else + { + /* Nothing to do */ + } } } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) { /* Disable the USART RXFT interrupt*/ CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); - + /* Update the RxISR function pointer */ husart->RxISR = USART_RxISR_16BIT; - + /* Enable the USART Data Register Not Empty interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - + #if defined(USART_CR2_SLVEN) - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && - (husart->TxXferCount == 0U)) + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) #else - if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && - (husart->TxXferCount == 0U)) -#endif + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX)) +#endif /* USART_CR2_SLVEN */ { /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); @@ -2971,7 +3810,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); } } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h index baea5261ee..c5d821d81d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_USART_H -#define __STM32L4xx_HAL_USART_H +#ifndef STM32L4xx_HAL_USART_H +#define STM32L4xx_HAL_USART_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -67,7 +51,7 @@ typedef struct Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. + where fclk_pres is the USART input clock frequency (fclk) (divided by a prescaler if applicable) @note Oversampling by 8 is systematically applied to achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. @@ -99,9 +83,8 @@ typedef struct #if defined(USART_PRESC_PRESCALER) uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. This parameter can be a value of @ref USART_ClockPrescaler. */ -#endif - -}USART_InitTypeDef; +#endif /* USART_PRESC_PRESCALER */ +} USART_InitTypeDef; /** * @brief HAL USART State structures definition @@ -116,21 +99,7 @@ typedef enum HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_USART_STATE_ERROR = 0x04U /*!< Error */ -}HAL_USART_StateTypeDef; - -/** - * @brief HAL USART Error Code structure definition - */ -typedef enum -{ - HAL_USART_ERROR_NONE = 0x00U, /*!< No error */ - HAL_USART_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04U, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10U, /*!< DMA transfer error */ - HAL_USART_ERROR_UDR = 0x20U /*!< SPI slave underrun error */ -}HAL_USART_ErrorTypeDef; +} HAL_USART_StateTypeDef; /** * @brief USART clock sources definitions @@ -143,15 +112,14 @@ typedef enum USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}USART_ClockSourceTypeDef; - +} USART_ClockSourceTypeDef; /** * @brief USART handle Structure definition */ typedef struct __USART_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ USART_InitTypeDef Init; /*!< USART communication parameters */ @@ -174,30 +142,79 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. - This parameter can be a value of @ref USARTEx_FIFO_mode. */ -#endif - +#endif /* USART_CR1_FIFOEN */ #if defined(USART_CR2_SLVEN) - uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. - This parameter can be a value of @ref USARTEx_Slave_Mode. */ -#endif + uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + of @ref USARTEx_Slave_Mode */ - void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ +#endif /* USART_CR2_SLVEN */ +#if defined(USART_CR1_FIFOEN) + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref USARTEx_FIFO_mode. */ - void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ +#endif /* USART_CR1_FIFOEN */ + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ __IO uint32_t ErrorCode; /*!< USART Error code */ -}USART_HandleTypeDef; +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ +#if defined(USART_CR1_FIFOEN) + void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */ +#endif /* USART_CR1_FIFOEN */ + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ +#if defined(USART_CR1_FIFOEN) + HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */ + HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */ +#endif /* USART_CR1_FIFOEN */ + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; + +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ /** * @} @@ -208,13 +225,32 @@ typedef struct __USART_HandleTypeDef * @{ */ +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#if defined(USART_CR2_SLVEN) +#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */ +#endif /* USART_CR2_SLVEN */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +/** + * @} + */ + /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ #define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ -#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ -#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ /** * @} */ @@ -231,9 +267,9 @@ typedef struct __USART_HandleTypeDef /** @defgroup USART_Mode USART Mode * @{ - */ -#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ #define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} @@ -287,7 +323,7 @@ typedef struct __USART_HandleTypeDef #if defined(USART_PRESC_PRESCALER) /** @defgroup USART_ClockPrescaler USART Clock Prescaler * @{ - */ + */ #define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ #define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ #define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ @@ -300,10 +336,11 @@ typedef struct __USART_HandleTypeDef #define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /** @defgroup USART_Request_Parameters USART Request Parameters * @{ @@ -324,26 +361,31 @@ typedef struct __USART_HandleTypeDef #define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ #define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ #define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ -#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ -#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ -#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#endif /* USART_CR1_FIFOEN */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#if defined(USART_CR2_SLVEN) +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#endif /* USART_CR2_SLVEN */ +#if defined(USART_CR1_FIFOEN) +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#else +#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#endif /* USART_CR1_FIFOEN */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#if defined(USART_CR1_FIFOEN) +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ #define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ #else -#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ -#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ -#endif -#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ -#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ -#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ -#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ -#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ -#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ -#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ -#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ -#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ -#if defined(USART_CR2_SLVEN) -#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ -#endif +#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ +#endif /* USART_CR1_FIFOEN */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ /** * @} */ @@ -360,22 +402,26 @@ typedef struct __USART_HandleTypeDef */ #define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ #if defined(USART_CR1_FIFOEN) #define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ -#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ -#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ -#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ -#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ -#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ -#endif -#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#endif /* USART_CR1_FIFOEN */ #define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ #define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#endif /* USART_CR1_FIFOEN */ #define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ #define USART_IT_ERR 0x0060U /*!< USART error interruption */ #define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ #define USART_IT_NE 0x0200U /*!< USART noise error interruption */ #define USART_IT_FE 0x0100U /*!< USART frame error interruption */ +#if defined(USART_CR1_FIFOEN) +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -386,24 +432,28 @@ typedef struct __USART_HandleTypeDef */ #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ #define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#if defined(USART_CR1_FIFOEN) -#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ -#endif #if defined(USART_CR2_SLVEN) #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ -#endif +#endif /* USART_CR2_SLVEN */ +#if defined(USART_CR1_FIFOEN) +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#endif /* USART_CR1_FIFOEN */ /** * @} */ /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask * @{ - */ + */ #define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ /** * @} */ @@ -421,7 +471,15 @@ typedef struct __USART_HandleTypeDef * @param __HANDLE__ USART handle. * @retval None */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ /** @brief Check whether the specified USART flag is set or not. * @param __HANDLE__ specifies the USART Handle @@ -453,13 +511,13 @@ typedef struct __USART_HandleTypeDef * @param __HANDLE__ specifies the USART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -501,7 +559,7 @@ typedef struct __USART_HandleTypeDef * @retval None */ #define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_CR2_SLVEN) /** @brief Clear SPI slave underrun error flag. @@ -509,7 +567,7 @@ typedef struct __USART_HandleTypeDef * @retval None */ #define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) -#endif +#endif /* USART_CR2_SLVEN */ /** @brief Enable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -529,9 +587,9 @@ typedef struct __USART_HandleTypeDef * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -551,9 +609,9 @@ typedef struct __USART_HandleTypeDef * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. @@ -576,7 +634,8 @@ typedef struct __USART_HandleTypeDef * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -599,8 +658,8 @@ typedef struct __USART_HandleTypeDef * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. @@ -608,13 +667,13 @@ typedef struct __USART_HandleTypeDef * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None */ #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) @@ -628,18 +687,18 @@ typedef struct __USART_HandleTypeDef * * @retval None */ -#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the USART one bit sample method. - * @param __HANDLE__ specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ + */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the USART one bit sample method. - * @param __HANDLE__ specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ + */ #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable USART. @@ -658,54 +717,63 @@ typedef struct __USART_HandleTypeDef * @} */ -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup USART_Private_Variables USART Private Variables - * @{ - */ -static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - /* Private macros --------------------------------------------------------*/ /** @defgroup USART_Private_Macros USART Private Macros * @{ */ #if defined(USART_PRESC_PRESCALER) +/** @brief Get USART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval USART clock division factor + */ +#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) #else /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) -#endif +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#endif /* USART_PRESC_PRESCALER */ /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on L4 * divided by the smallest oversampling used on the USART (i.e. 8) * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U) #else -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) -#endif +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__ USART frame number of stop bits. + * @param __STOPBITS__ USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ @@ -715,53 +783,53 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, /** * @brief Ensure that USART frame parity is valid. - * @param __PARITY__ USART frame parity. + * @param __PARITY__ USART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ + */ #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ ((__PARITY__) == USART_PARITY_EVEN) || \ - ((__PARITY__) == USART_PARITY_ODD)) + ((__PARITY__) == USART_PARITY_ODD)) /** * @brief Ensure that USART communication mode is valid. - * @param __MODE__ USART communication mode. + * @param __MODE__ USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. + * @param __SAMPLING__ USART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ + */ #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ ((__SAMPLING__) == USART_OVERSAMPLING_8)) /** * @brief Ensure that USART clock state is valid. - * @param __CLOCK__ USART clock state. + * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) - */ + */ #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ ((__CLOCK__) == USART_CLOCK_ENABLE)) /** * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__ USART frame polarity. + * @param __CPOL__ USART frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) - */ + */ #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) /** * @brief Ensure that USART frame phase is valid. - * @param __CPHA__ USART frame phase. + * @param __CPHA__ USART frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) /** * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @param __LASTBIT__ USART frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ @@ -769,7 +837,7 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, /** * @brief Ensure that USART request parameter is valid. - * @param __PARAM__ USART request parameter. + * @param __PARAM__ USART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ @@ -778,7 +846,7 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, #if defined(USART_PRESC_PRESCALER) /** * @brief Ensure that USART Prescaler is valid. - * @param __CLOCKPRESCALER__ USART Prescaler value. + * @param __CLOCKPRESCALER__ USART Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ @@ -794,7 +862,7 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) -#endif +#endif /* USART_PRESC_PRESCALER */ /** * @} */ @@ -817,6 +885,13 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); void HAL_USART_MspInit(USART_HandleTypeDef *husart); void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + /** * @} */ @@ -828,13 +903,16 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); @@ -883,6 +961,6 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); } #endif -#endif /* __STM32L4xx_HAL_USART_H */ +#endif /* STM32L4xx_HAL_USART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c index d2b1b3d70f..8fa822bd60 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c @@ -15,42 +15,26 @@ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - -@- When USART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be configured prior starting RX/TX transfers. (#) Slave mode enabling/disabling and NSS pin configuration. - -@- When USART operates in Slave mode, Slave mode must be enabled prior + -@- When USART operates in Slave mode, Slave mode must be enabled prior starting RX/TX transfers. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -70,6 +54,14 @@ #ifdef HAL_USART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U + +#endif /* USART_CR1_FIFOEN */ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -82,7 +74,7 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); /** * @} */ -#endif +#endif /* USART_CR1_FIFOEN */ /* Exported functions --------------------------------------------------------*/ @@ -90,8 +82,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); * @{ */ -/** @defgroup USARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended USART Transmit/Receive functions +/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions + * @brief Extended USART Transmit/Receive functions * @verbatim =============================================================================== @@ -113,7 +105,7 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); * @param husart USART handle. * @retval None */ -__weak void HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart) +__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -128,7 +120,7 @@ __weak void HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart) * @param husart USART handle. * @retval None */ -__weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) +__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -137,15 +129,15 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ -/** @defgroup USARTEx_Exported_Functions_Group3 Peripheral Control functions +/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -173,7 +165,7 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) * @note In SPI slave mode, the USART must be enabled before starting the master * communications (or between frames while the clock is stable). Otherwise, * if the USART slave is enabled while the master is in the middle of a - * frame, it will become desynchronized with the master. + * frame, it will become desynchronized with the master. * @note The data register of the slave needs to be ready before the first edge * of the communication clock or before the end of the ongoing communication, * otherwise the SPI slave will transmit zeros. @@ -182,45 +174,45 @@ __weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); - + /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* In SPI slave mode mode, the following bits must be kept cleared: - LINEN and CLKEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + /* Enable SPI slave mode */ SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->SlaveMode = USART_SLAVEMODE_ENABLE; - + husart->State = HAL_USART_STATE_READY; - + /* Enable USART */ __HAL_USART_ENABLE(husart); - + /* Process Unlocked */ __HAL_UNLOCK(husart); - - return HAL_OK; + + return HAL_OK; } /** @@ -230,36 +222,36 @@ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); - + /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); /* Disable SPI slave mode */ CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); husart->SlaveMode = USART_SLAVEMODE_ENABLE; - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - - return HAL_OK; + + return HAL_OK; } /** @@ -278,37 +270,37 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); assert_param(IS_USART_NSS(NSSConfig)); - + /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); /* Program DIS_NSS bit in the USART_CR2 register */ MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); return HAL_OK; } -#endif +#endif /* USART_CR2_SLVEN */ #if defined(USART_CR1_FIFOEN) /** @@ -318,37 +310,37 @@ HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NS */ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Enable FIFO mode */ SET_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_ENABLE; - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } @@ -359,34 +351,34 @@ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } @@ -405,37 +397,37 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Update TX threshold configuration */ MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } @@ -454,40 +446,40 @@ HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, ui */ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) { - uint32_t tmpcr1 = 0; - + uint32_t tmpcr1; + /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(husart); - + husart->State = HAL_USART_STATE_BUSY; - + /* Save actual USART configuration */ tmpcr1 = READ_REG(husart->Instance->CR1); - + /* Disable USART */ __HAL_USART_DISABLE(husart); - + /* Update RX threshold configuration */ MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - + /* Determine the number of data to process during RX/TX ISR execution */ USARTEx_SetNbDataToProcess(husart); - + /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -509,31 +501,32 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui * @param husart USART handle. * @retval None */ -void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { uint8_t rx_fifo_depth; uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + if (husart->FifoMode == USART_FIFOMODE_DISABLE) { - husart->NbTxDataToProcess = 1; - husart->NbRxDataToProcess = 1; + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; } else { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ - rx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - husart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - husart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h index bea5add84f..c59cf4be2d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h @@ -6,39 +6,23 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_USART_EX_H -#define __STM32L4xx_HAL_USART_EX_H +#ifndef STM32L4xx_HAL_USART_EX_H +#define STM32L4xx_HAL_USART_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -57,13 +41,13 @@ /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants * @{ */ - + /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ @@ -72,30 +56,51 @@ /** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management * @{ */ -#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ -#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ /** * @} */ -#endif -#if defined(USART_CR1_FIFOEN) -/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level - * @brief USART TXFIFO level + +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable + * @brief USART SLAVE mode * @{ */ -#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ +#endif /* USART_CR2_SLVEN */ + +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @brief USART FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ /** * @} */ /** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level - * @brief USART RXFIFO level + * @brief USART RXFIFO level * @{ */ #define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ @@ -107,37 +112,8 @@ /** * @} */ -#endif +#endif /* USART_CR1_FIFOEN */ -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USARTEx_Private_Constants USARTEx Private Constants - * @{ - */ -#if defined(USART_CR2_SLVEN) -/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode - * @{ - */ -#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ -#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode - * @{ - */ -#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ -#endif /** * @} */ @@ -148,8 +124,8 @@ */ /** @brief Report the USART clock source. - * @param __HANDLE__: specifies the USART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #if defined (STM32L432xx) || defined (STM32L442xx) @@ -157,8 +133,8 @@ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ break; \ @@ -174,12 +150,12 @@ default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -195,7 +171,11 @@ default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) #else @@ -203,8 +183,8 @@ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ break; \ @@ -220,12 +200,12 @@ default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -241,12 +221,12 @@ default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -262,7 +242,11 @@ default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) #endif /* STM32L432xx || STM32L442xx */ @@ -278,64 +262,85 @@ */ #define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ -} while(0) + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that USART frame length is valid. - * @param __LENGTH__ USART frame length. + * @param __LENGTH__ USART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ ((__LENGTH__) == USART_WORDLENGTH_8B) || \ ((__LENGTH__) == USART_WORDLENGTH_9B)) + #if defined(USART_CR2_SLVEN) /** * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. - * @param __NSS__ USART Negative Slave Select pin management. + * @param __NSS__ USART Negative Slave Select pin management. * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) */ #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ ((__NSS__) == USART_NSS_SOFT)) -#endif + +/** + * @brief Ensure that USART Slave Mode is valid. + * @param __STATE__ USART Slave Mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ + ((__STATE__) == USART_SLAVEMODE_ENABLE)) +#endif /* USART_CR2_SLVEN */ #if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that USART FIFO mode is valid. + * @param __STATE__ USART FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ + ((__STATE__) == USART_FIFOMODE_ENABLE)) + /** * @brief Ensure that USART TXFIFO threshold level is valid. - * @param __THRESHOLD__ USART TXFIFO threshold level. + * @param __THRESHOLD__ USART TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ @@ -343,11 +348,11 @@ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) /** * @brief Ensure that USART RXFIFO threshold level is valid. - * @param __THRESHOLD__ USART RXFIFO threshold level. + * @param __THRESHOLD__ USART RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ @@ -356,8 +361,7 @@ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) -#endif - +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -367,7 +371,7 @@ * @{ */ -/** @addtogroup USARTEx_Exported_Functions_Group2 +/** @addtogroup USARTEx_Exported_Functions_Group1 * @{ */ @@ -375,13 +379,13 @@ #if defined(USART_CR1_FIFOEN) void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ -/** @addtogroup USARTEx_Exported_Functions_Group3 +/** @addtogroup USARTEx_Exported_Functions_Group2 * @{ */ @@ -390,14 +394,13 @@ void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); -#endif - +#endif /* USART_CR2_SLVEN */ #if defined(USART_CR1_FIFOEN) HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -419,6 +422,6 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui } #endif -#endif /* __STM32L4xx_HAL_USART_EX_H */ +#endif /* STM32L4xx_HAL_USART_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c index ce4a280195..7fa0776857 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c @@ -3,120 +3,112 @@ * @file stm32l4xx_hal_wwdg.c * @author MCD Application Team * @brief WWDG HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and Configuration function + * + Initialization and Configuration functions * + IO operation functions @verbatim ============================================================================== - ##### WWDG specific features ##### + ##### WWDG Specific features ##### ============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). + value rolls down from 0x40 to 0x3F). (+) An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. - (+) Once enabled the WWDG cannot be disabled except by a system reset. - - (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has - occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). - - (+) The WWDG downcounter input clock is derived from the APB clock divided + (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG + reset occurs. + (+) The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. - - (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler) - - (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock) - where T[5;0] are the lowest 6 bits of downcounter. - + (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz) + where T[5;0] are the lowest 6 bits of Counter. (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock) - (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock) - - (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms - - (+) The Early Wakeup Interrupt (EWI) can be used if specific safety - operations or data logging must be performed before the actual reset is - generated. When the downcounter reaches the value 0x40, an EWI interrupt - is generated and the corresponding interrupt service routine (ISR) can - be used to trigger specific actions (such as communications or data - logging), before resetting the device. - In some applications, the EWI interrupt can be used to manage a software - system check and/or system recovery/graceful degradation, without - generating a WWDG reset. In this case, the corresponding interrupt - service routine (ISR) should reload the WWDG counter to avoid the WWDG - reset, then trigger the required actions. - Note:When the EWI interrupt cannot be served, e.g. due to a system lock - in a higher priority task, the WWDG reset will eventually be generated. - - (+) Debug mode : When the microcontroller enters debug mode (core halted), - the WWDG counter either continues to work normally or stops, depending - on DBG_WWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros + (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (+) Typical values: + (++) Counter min (T[5;0] = 0x00) @80 MHz(PCLK1) with zero prescaler: + max timeout before reset: ~51.2 µs + (++) Counter max (T[5;0] = 0x3F) @80 MHz(PCLK1) with prescaler dividing by 128: + max timeout before reset: ~26.22 ms + ============================================================================== ##### How to use this driver ##### ============================================================================== [..] + *** Common driver usage *** + =========================== (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - - (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup - Interrupt mode using using HAL_WWDG_Init() function. - This enables WWDG peripheral and the downcounter starts downcounting - from given counter value. - Init function can be called again to modify all watchdog parameters, - however if EWI mode has been set once, it can't be clear until next - reset. - - (+) The application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset using + (+) Set the WWDG prescaler, refresh window and counter value + using HAL_WWDG_Init() function. + (+) Start the WWDG using HAL_WWDG_Start() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is + generated when the counter reaches 0x40, and then start the WWDG using + HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can + add his own code by customization of callback HAL_WWDG_WakeupCallback. + Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the window value already programmed. + the counter is lower than the refresh window value already programmed. - (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when - the counter reaches 0x40. User can add his own code in weak function - HAL_WWDG_EarlyWakeupCallback(). + [..] + *** Callback registration *** + ============================= + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + the user to configure dynamically the driver callbacks. Use Functions + @ref HAL_WWDG_RegisterCallback() to register a user callback. - *** WWDG HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in WWDG HAL driver. + (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. - (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. + (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + takes as parameters the HAL peripheral handle and the Callback ID. + This function allows to reset following callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + + When calling @ref HAL_WWDG_Init function, callbacks are reset to the + corresponding legacy weak (surcharged) functions: + @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + not been registered before. + + When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** WWDG HAL driver macros list *** + =================================== + [..] + Below the list of most used macros in WWDG HAL driver. + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -152,7 +144,7 @@ ============================================================================== ##### Initialization and Configuration functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and start the WWDG according to the specified parameters in the WWDG_InitTypeDef of associated handle. @@ -172,7 +164,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) { /* Check the WWDG handle allocation */ - if(hwwdg == NULL) + if (hwwdg == NULL) { return HAL_ERROR; } @@ -184,8 +176,24 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers */ + if(hwwdg->EwiCallback == NULL) + { + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + } + + if(hwwdg->MspInitCallback == NULL) + { + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + } + + /* Init the low level hardware */ + hwwdg->MspInitCallback(hwwdg); +#else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); +#endif /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -217,17 +225,93 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) */ } + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User WWDG Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + status = HAL_ERROR; + } + else + { + switch(CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = pCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + + return status; +} + + +/** + * @brief Unregister a WWDG Callback + * WWDG Callback is redirected to the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch(CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif + /** * @} */ /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * @verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Refresh the WWDG. @@ -256,7 +340,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) * @brief Handle WWDG interrupt request. * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with * EWIMode set to WWDG_EWI_ENABLE. * When the downcounter reaches the value 0x40, and EWI interrupt is * generated and the corresponding Interrupt Service Routine (ISR) can @@ -269,16 +353,21 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) { /* Check if Early Wakeup Interrupt is enable */ - if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) + if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { /* Check if WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) { /* Clear the WWDG Early Wakeup flag */ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - /* Early Wakeup callback */ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Early Wakeup registered callback */ + hwwdg->EwiCallback(hwwdg); +#else + /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); +#endif } } } @@ -290,7 +379,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) * the configuration information for the specified WWDG module. * @retval None */ -__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h index 75759788f5..0e3caec5f7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_WWDG_H -#define __STM32L4xx_HAL_WWDG_H +#ifndef STM32L4xx_HAL_WWDG_H +#define STM32L4xx_HAL_WWDG_H #ifdef __cplusplus extern "C" { @@ -58,7 +42,7 @@ * @{ */ -/** +/** * @brief WWDG Init structure definition */ typedef struct @@ -75,18 +59,40 @@ typedef struct uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ -}WWDG_InitTypeDef; +} WWDG_InitTypeDef; /** * @brief WWDG handle Structure definition */ -typedef struct +typedef struct __WWDG_HandleTypeDef { - WWDG_TypeDef *Instance; /*!< Register base address */ + WWDG_TypeDef *Instance; /*!< Register base address */ - WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ -}WWDG_HandleTypeDef; +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif +} WWDG_HandleTypeDef; + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL WWDG common Callback ID enumeration definition + */ +typedef enum +{ + HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ +}HAL_WWDG_CallbackIDTypeDef; + +/** + * @brief HAL WWDG Callback pointer definition + */ +typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */ + +#endif /** * @} */ @@ -117,10 +123,10 @@ typedef struct /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ /** * @} */ @@ -143,9 +149,9 @@ typedef struct /** @defgroup WWDG_Private_Macros WWDG Private Macros * @{ */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ ((__PRESCALER__) == WWDG_PRESCALER_8)) #define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) @@ -247,6 +253,12 @@ typedef struct /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); +#endif + /** * @} */ @@ -257,7 +269,7 @@ void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* I/O operation functions ******************************************************/ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); /** * @} */ @@ -278,6 +290,6 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg); } #endif -#endif /* __STM32L4xx_HAL_WWDG_H */ +#endif /* STM32L4xx_HAL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c index ead41c287d..4944c57dfa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -39,9 +23,9 @@ #include "stm32l4xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32L4xx_LL_Driver @@ -62,7 +46,7 @@ */ /* Definitions of ADC hardware constraints delays */ -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values: */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ @@ -80,9 +64,9 @@ /* with highest ratio CPU clock frequency vs HSI clock frequency: */ /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */ /* Unit: CPU cycles. */ -#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) -#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) -#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) +#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL) +#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) /** * @} @@ -327,7 +311,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - + /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC); @@ -355,14 +339,14 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); - + #if defined(ADC_MULTIMODE_SUPPORT) assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); @@ -374,7 +358,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* On this STM32 serie, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ @@ -386,16 +370,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE + ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay @@ -404,13 +388,13 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni else { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE + ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } @@ -424,7 +408,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* the same ADC common instance are not disabled. */ status = ERROR; } - + return status; } @@ -440,7 +424,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - + #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; @@ -470,86 +454,90 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; - - __IO uint32_t timeout_cpu_cycles = 0U; - + + __IO uint32_t timeout_cpu_cycles = 0UL; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1U) + if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - + /* Stop potential ADC conversion on going on ADC group regular. */ - if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) + if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) + if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_REG_StopConversion(ADCx); } } - + /* Set ADC group injected trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - + /* Stop potential ADC conversion on going on ADC group injected. */ - if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U) + if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U) + if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_INJ_StopConversion(ADCx); } } - + /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; - while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) - | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U) + while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) + | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) { - if(timeout_cpu_cycles-- == 0U) + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; + break; } } - + /* Flush group injected contexts queue (register JSQR): */ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ /* contexts queue is maintained with the last active context). */ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); - + /* Disable the ADC instance */ LL_ADC_Disable(ADCx); - + /* Wait for ADC instance is effectively disabled */ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; - while (LL_ADC_IsDisableOngoing(ADCx) == 1U) + while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) { - if(timeout_cpu_cycles-- == 0U) + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; + break; } } } - + /* Check whether ADC state is compliant with expected state */ - if(READ_BIT(ADCx->CR, - ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - | ADC_CR_ADDIS | ADC_CR_ADEN ) - ) - == 0U) + if (READ_BIT(ADCx->CR, + (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN) + ) + == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ CLEAR_BIT(ADCx->IER, - ( LL_ADC_IT_ADRDY + (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR @@ -559,12 +547,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_IT_JQOVF | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 - | LL_ADC_IT_AWD3 ) + | LL_ADC_IT_AWD3 + ) ); - + /* Reset register ISR */ SET_BIT(ADCx->ISR, - ( LL_ADC_FLAG_ADRDY + (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR @@ -574,9 +563,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 - | LL_ADC_FLAG_AWD3 ) + | LL_ADC_FLAG_AWD3 + ) ); - + /* Reset register CR */ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ @@ -589,79 +579,79 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* already done above. */ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); - + /* Reset register CFGR */ MODIFY_REG(ADCx->CFGR, - ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN + (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN - | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ), - ADC_CFGR_JQDIS + | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN), + ADC_CFGR_JQDIS ); - + /* Reset register CFGR2 */ CLEAR_BIT(ADCx->CFGR2, - ( ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS + (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) ); - + /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 + (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) ); - + /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 + (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) ); - + /* Reset register TR1 */ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); - + /* Reset register TR2 */ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); - + /* Reset register TR3 */ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); - + /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 + (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L) ); - + /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 + (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) ); - + /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, - ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 + (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) ); - + /* Reset register SQR4 */ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - + /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL + (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); - + /* Reset register DR */ /* Note: bits in access mode read only, no direct reset applicable */ - + /* Reset register OFR1 */ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ @@ -673,16 +663,16 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ - + /* Reset register AWD2CR */ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); - + /* Reset register AWD3CR */ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); - + /* Reset register DIFSEL */ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); - + /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); } @@ -699,7 +689,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* all ADC instances belonging to the common ADC instance. */ status = ERROR; } - + return status; } @@ -739,17 +729,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ @@ -757,15 +747,15 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ MODIFY_REG(ADCx->CFGR, - ADC_CFGR_RES + ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY - , - ADC_InitStruct->Resolution + , + ADC_InitStruct->Resolution | ADC_InitStruct->DataAlignment | ADC_InitStruct->LowPowerMode ); - + } else { @@ -788,7 +778,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; - + } /** @@ -826,22 +816,22 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -854,10 +844,10 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL + ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM @@ -865,8 +855,8 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource + , + ADC_REG_InitStruct->TriggerSource | ADC_REG_InitStruct->SequencerDiscont | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer @@ -876,7 +866,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I else { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL + ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM @@ -884,15 +874,15 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource + , + ADC_REG_InitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer | ADC_REG_InitStruct->Overrun ); } - + /* Set ADC group regular sequencer length and scan direction */ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); } @@ -959,20 +949,20 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ @@ -983,33 +973,33 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* from ADC group regular */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN + ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont + , + ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN + ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } - + MODIFY_REG(ADCx->JSQR, - ADC_JSQR_JEXTSEL + ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL - , - ADC_INJ_InitStruct->TriggerSource + , + ADC_INJ_InitStruct->TriggerSource | ADC_INJ_InitStruct->SequencerLength ); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h index f859f8783a..1894796fcf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_ADC_H -#define __STM32L4xx_LL_ADC_H +#ifndef STM32L4xx_LL_ADC_H +#define STM32L4xx_LL_ADC_H #ifdef __cplusplus extern "C" { @@ -69,35 +53,33 @@ extern "C" { /* Internal register offset for ADC group regular sequencer configuration */ /* (offset placed into a spare area of literal definition) */ -#define ADC_SQR1_REGOFFSET (0x00000000U) -#define ADC_SQR2_REGOFFSET (0x00000100U) -#define ADC_SQR3_REGOFFSET (0x00000200U) -#define ADC_SQR4_REGOFFSET (0x00000300U) +#define ADC_SQR1_REGOFFSET (0x00000000UL) +#define ADC_SQR2_REGOFFSET (0x00000100UL) +#define ADC_SQR3_REGOFFSET (0x00000200UL) +#define ADC_SQR4_REGOFFSET (0x00000300UL) #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) -#if defined(CORE_CM0PLUS) -#define ADC_SQRX_REGOFFSET_POS (8U) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ -#endif +#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ -#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ -#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */ -#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */ -#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */ -#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */ -#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */ -#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */ -#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */ @@ -108,23 +90,21 @@ extern "C" { /* Internal register offset for ADC group injected data register */ /* (offset placed into a spare area of literal definition) */ -#define ADC_JDR1_REGOFFSET (0x00000000U) -#define ADC_JDR2_REGOFFSET (0x00000100U) -#define ADC_JDR3_REGOFFSET (0x00000200U) -#define ADC_JDR4_REGOFFSET (0x00000300U) +#define ADC_JDR1_REGOFFSET (0x00000000UL) +#define ADC_JDR2_REGOFFSET (0x00000100UL) +#define ADC_JDR3_REGOFFSET (0x00000200UL) +#define ADC_JDR4_REGOFFSET (0x00000300UL) #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) -#if defined(CORE_CM0PLUS) -#define ADC_JDRX_REGOFFSET_POS (8U) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ -#endif +#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ -#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */ -#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */ -#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */ -#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */ +#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */ +#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */ +#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */ +#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */ @@ -137,22 +117,22 @@ extern "C" { /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \ - ((ADC_CFGR_EXTSEL) << (4U * 3U)) ) +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */ @@ -165,22 +145,22 @@ extern "C" { /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 3U)) ) +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group injected trigger bits information. */ -#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */ -#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */ +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */ @@ -197,31 +177,29 @@ extern "C" { /* and SMPx bits positions into SMPRx register */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /* Internal register offset for ADC channel sampling time configuration */ /* (offset placed into a spare area of literal definition) */ -#define ADC_SMPR1_REGOFFSET (0x00000000U) -#define ADC_SMPR2_REGOFFSET (0x02000000U) +#define ADC_SMPR1_REGOFFSET (0x00000000UL) +#define ADC_SMPR2_REGOFFSET (0x02000000UL) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) -#if defined(CORE_CM0PLUS) -#define ADC_SMPRX_REGOFFSET_POS (25U) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ -#endif +#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ -#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U) -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER (0x00000000U) +#define ADC_CHANNEL_0_NUMBER (0x00000000UL) #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) @@ -265,25 +243,25 @@ extern "C" { /* Definition of channels sampling time information to be inserted into */ /* channels literals definition. */ -#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */ -#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */ -#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */ -#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */ -#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */ -#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */ -#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */ -#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */ -#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */ -#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */ -#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */ -#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */ -#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */ -#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */ -#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */ -#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */ -#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */ -#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */ -#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */ +#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */ /* Internal mask for ADC mode single or differential ended: */ @@ -295,12 +273,10 @@ extern "C" { #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ -#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ -#if defined(CORE_CM0PLUS) -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000U) /* Selection of 1 bit to discriminate differential mode: mask of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16U) /* Selection of 1 bit to discriminate differential mode: position of bit */ -#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4U) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ -#endif +#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ @@ -312,14 +288,14 @@ extern "C" { /* selection on groups. */ /* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET (0x00000000U) -#define ADC_AWD_CR2_REGOFFSET (0x00100000U) -#define ADC_AWD_CR3_REGOFFSET (0x00200000U) +#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) +#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) -#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024U) +#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) @@ -327,35 +303,33 @@ extern "C" { #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) -#define ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) -#if defined(CORE_CM0PLUS) #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ -#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000U) /* Selection of 1 bit to discriminate threshold high: mask of bit */ -#define ADC_AWD_TRX_BIT_HIGH_POS (16U) /* Selection of 1 bit to discriminate threshold high: position of bit */ -#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4U) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ -#endif +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ /* Internal mask for ADC offset: */ /* Internal register offset for ADC offset number configuration */ -#define ADC_OFR1_REGOFFSET (0x00000000U) -#define ADC_OFR2_REGOFFSET (0x00000001U) -#define ADC_OFR3_REGOFFSET (0x00000002U) -#define ADC_OFR4_REGOFFSET (0x00000003U) +#define ADC_OFR1_REGOFFSET (0x00000000UL) +#define ADC_OFR2_REGOFFSET (0x00000001UL) +#define ADC_OFR3_REGOFFSET (0x00000002UL) +#define ADC_OFR4_REGOFFSET (0x00000003UL) #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ -#define ADC_CFGR_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */ -#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */ -#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */ -#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */ -#define ADC_TR1_HT1_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */ +#define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */ +#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */ +#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */ +#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ /* ADC registers bits groups */ @@ -364,14 +338,18 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) +#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#else +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#endif +#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ /** @@ -384,17 +362,6 @@ extern "C" { * @{ */ -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits - */ -#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset @@ -404,7 +371,7 @@ extern "C" { * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -434,23 +401,23 @@ typedef struct @note On this STM32 serie, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ #if defined(ADC_MULTIMODE_SUPPORT) uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ #endif /* ADC_MULTIMODE_SUPPORT */ @@ -480,17 +447,17 @@ typedef struct { uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ uint32_t LowPowerMode; /*!< Set ADC low power mode. This parameter can be a value of @ref ADC_LL_EC_LP_MODE - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ } LL_ADC_InitTypeDef; @@ -516,41 +483,41 @@ typedef struct */ typedef struct { - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE @note This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ } LL_ADC_REG_InitTypeDef; @@ -576,30 +543,30 @@ typedef struct */ typedef struct { - uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE @note This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; @@ -682,9 +649,9 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) -#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ #endif /** * @} @@ -696,7 +663,7 @@ typedef struct #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock without prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ @@ -720,7 +687,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ @@ -731,7 +698,7 @@ typedef struct /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ @@ -742,7 +709,7 @@ typedef struct /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ /** * @} @@ -751,7 +718,7 @@ typedef struct /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} @@ -771,7 +738,7 @@ typedef struct /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state * @{ */ -#define LL_ADC_OFFSET_DISABLE (0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ /** * @} @@ -780,9 +747,9 @@ typedef struct /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ -#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ -#define LL_ADC_GROUP_INJECTED (0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/ -#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U) /*!< ADC both groups regular and injected */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ /** * @} */ @@ -830,23 +797,23 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -862,9 +829,9 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ -#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ + * @{ + */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} @@ -873,9 +840,9 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ @@ -884,7 +851,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} @@ -895,7 +862,7 @@ typedef struct /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration * @{ */ -#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000U) /*!< ADC sampling time let to default settings. */ +#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ /** * @} @@ -903,9 +870,9 @@ typedef struct #endif /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data -* @{ -*/ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ + * @{ + */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} @@ -914,7 +881,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ @@ -937,7 +904,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ @@ -976,23 +943,23 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source * @{ */ -#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -1008,9 +975,9 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ -#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ + * @{ + */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** * @} @@ -1019,7 +986,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ /** @@ -1029,7 +996,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ @@ -1040,7 +1007,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} @@ -1060,7 +1027,7 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U) /*!< Sampling time 2.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ @@ -1095,7 +1062,7 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ @@ -1169,23 +1136,23 @@ typedef struct #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */ #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */ #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */ -#define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */ -#define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by group regular only */ +#define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by group injected only */ +#define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by either group regular or injected */ #elif defined(ADC2) #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */ #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */ #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */ -#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */ -#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by group regular only */ +#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by group injected only */ +#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by either group regular or injected */ #if defined(ADC3) #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */ #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */ #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */ -#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */ -#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by group regular only */ +#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by group injected only */ +#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by either group regular or injected */ #endif #endif /** @@ -1205,7 +1172,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ -#define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ @@ -1217,7 +1184,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define LL_ADC_OVS_REG_CONT (0x00000000U) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} @@ -1226,7 +1193,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ @@ -1241,7 +1208,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ @@ -1258,7 +1225,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ @@ -1273,7 +1240,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ @@ -1285,7 +1252,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ @@ -1348,14 +1315,14 @@ typedef struct /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. * @{ */ - -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ + +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values. */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ @@ -1377,19 +1344,19 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12U) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 120U) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ @@ -1398,7 +1365,7 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} @@ -1480,7 +1447,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -1492,14 +1459,14 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \ - ? ( \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ + ? ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ - : \ - ( \ - POSITION_VAL((__CHANNEL__)) \ - ) \ + ) \ + : \ + ( \ + (uint32_t)POSITION_VAL((__CHANNEL__)) \ + ) \ ) /** @@ -1538,7 +1505,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -1551,19 +1518,19 @@ typedef struct * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9U) \ - ? ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ - (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ - (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9UL) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ ) /** @@ -1612,7 +1579,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -1625,7 +1592,7 @@ typedef struct * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) /** * @brief Helper macro to convert a channel defined from parameter @@ -1669,7 +1636,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -1726,7 +1693,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -1761,7 +1728,7 @@ typedef struct ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \ ) \ : \ - (0U) \ + (0UL) \ ) #elif defined (ADC1) && defined (ADC2) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ @@ -1779,7 +1746,7 @@ typedef struct ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \ ) \ : \ - (0U) \ + (0UL) \ ) #elif defined (ADC1) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ @@ -1830,7 +1797,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -1935,7 +1902,7 @@ typedef struct * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6) - * + * * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n @@ -1946,12 +1913,12 @@ typedef struct */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ ) /** @@ -1979,7 +1946,7 @@ typedef struct /** * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is + * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to get the value of @@ -2011,13 +1978,8 @@ typedef struct * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -#if defined(CORE_CM0PLUS) #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) -#else -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW) -#endif /** * @brief Helper macro to set the ADC calibration value with both single ended @@ -2032,13 +1994,8 @@ typedef struct * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -#if defined(CORE_CM0PLUS) #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) -#else -#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ - (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__)) -#endif #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -2054,8 +2011,35 @@ typedef struct * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) +#endif + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to select, from a ADC instance, to which ADC instance + * it has a dependence in multimode (ADC master of the corresponding + * ADC common instance). + * @note In case of device with multimode available and a mix of + * ADC instances compliant and not compliant with multimode feature, + * ADC instances not compliant with multimode feature are + * considered as master instances (do not depend to + * any other ADC instance). + * @param __ADCx__ ADC instance + * @retval __ADCx__ ADC instance master of the corresponding ADC common instance + */ +#if defined(ADC2) +#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ + ( ( ((__ADCx__) == ADC2) \ + )? \ + (ADC1) \ + : \ + (__ADCx__) \ + ) +#else +#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ + (__ADCx__) +#endif #endif /** @@ -2121,16 +2105,16 @@ typedef struct * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) */ #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) + (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B @@ -2148,8 +2132,8 @@ typedef struct __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ ) /** @@ -2206,10 +2190,9 @@ typedef struct #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - ) + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2296,7 +2279,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12bits + * @note ADC measurement data must correspond to a resolution of 12 bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). @@ -2323,13 +2306,13 @@ typedef struct ((( ( \ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000) \ + * 1000UL) \ - \ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000) \ + * 1000UL) \ ) \ - ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ ) /** @@ -2379,33 +2362,36 @@ typedef struct * @param Register This parameter can be one of the following values: * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) - * + * * (1) Available on devices with several ADC instances. * @retval ADC register address */ #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr = 0U; - + register uint32_t data_reg_addr; + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); + data_reg_addr = (uint32_t) &(ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } - + return data_reg_addr; } #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { + /* Prevent unused argument(s) compilation warning */ + (void)(Register); + /* Retrieve address of register DR */ - return (uint32_t)&(ADCx->DR); + return (uint32_t) &(ADCx->DR); } #endif @@ -2501,12 +2487,6 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n * CCR TSEN LL_ADC_SetCommonPathInternalCh\n * CCR VBATEN LL_ADC_SetCommonPathInternalCh @@ -2587,15 +2567,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx */ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { -#if defined(CORE_CM0PLUS) MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); -#else - MODIFY_REG(ADCx->CALFACT, - SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, - CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); -#endif } /** @@ -2620,11 +2594,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); -#else - return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); -#endif } /** @@ -2727,7 +2697,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * retrieve ADC conversion data. This will trig another * ADC conversion start. * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): * the ADC automatically powers-off after a conversion and * automatically wakes up when a new conversion is triggered * (with startup time between trigger and start of sampling). @@ -2780,7 +2750,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * retrieve ADC conversion data. This will trig another * ADC conversion start. * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): * the ADC automatically powers-off after a conversion and * automatically wakes up when a new conversion is triggered * (with startup time between trigger and start of sampling). @@ -2870,7 +2840,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -2884,8 +2854,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); @@ -2948,7 +2918,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -2963,8 +2933,8 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -2989,8 +2959,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3022,9 +2992,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register uint32_t *preg = (uint32_t *)((uint32_t) - ((uint32_t)(&ADCx->OFR1) + (Offsety*4U))); - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, OffsetState); @@ -3049,8 +3018,8 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -3099,15 +3068,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) /** * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, + * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 serie, setting trigger source to external trigger - * also set trigger polarity to rising edge + * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3143,15 +3112,15 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri /** * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, + * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group regular trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, - * (equivalent to + * (equivalent to * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n * CFGR EXTEN LL_ADC_REG_GetTriggerSource @@ -3177,12 +3146,12 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); - + register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); - + register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource @@ -3193,7 +3162,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) /** * @brief Get ADC group regular conversion trigger source internal (SW start) - or external. + * or external. * @note In case of group regular trigger source set to external trigger, * to determine which peripheral is selected as external trigger, * use function @ref LL_ADC_REG_GetTriggerSource(). @@ -3204,7 +3173,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); + return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } /** @@ -3359,7 +3328,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * @brief Set ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. - * @note It is not possible to enable both ADC group regular + * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. @@ -3493,7 +3462,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -3510,12 +3479,8 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); -#endif - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); @@ -3604,7 +3569,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -3619,16 +3584,12 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); -#endif - - return (uint32_t) ((READ_BIT(*preg, + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + + return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - ); + ); } /** @@ -3637,7 +3598,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular + * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3833,15 +3794,15 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) /** * @brief Set ADC group injected conversion trigger source: - * internal (SW start) or from external IP (timer event, + * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 serie, setting trigger source to external trigger - * also set trigger polarity to rising edge + * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_INJ_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -3877,15 +3838,15 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri /** * @brief Get ADC group injected conversion trigger source: - * internal (SW start) or from external IP (timer event, + * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group injected trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, - * (equivalent to + * (equivalent to * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource @@ -3911,12 +3872,12 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); - + register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); - + register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource @@ -3938,7 +3899,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); + return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } /** @@ -4110,7 +4071,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4187,7 +4148,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4203,8 +4164,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) - >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4212,18 +4173,18 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * @brief Set ADC group injected conversion trigger: * independent or from ADC group regular. * @note This mode can be used to extend number of data registers - * updated after one ADC conversion trigger and with data + * updated after one ADC conversion trigger and with data * permanently kept (not erased by successive conversions of scan of * ADC sequencer ranks), up to 5 data registers: * 1 data register on ADC group regular, 4 data registers - * on ADC group injected. + * on ADC group injected. * @note If ADC group injected injected trigger source is set to an * external trigger, this feature must be must be set to * independent trigger. - * ADC group injected automatic trigger is compliant only with - * group injected trigger source set to SW start, without any - * further action on ADC group injected conversion start or stop: - * in this case, ADC group injected is controlled only + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. @@ -4412,7 +4373,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4450,7 +4411,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4488,7 +4449,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4526,7 +4487,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4552,16 +4513,17 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ - MODIFY_REG(ADCx->JSQR , + register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | - ADC_JSQR_JL , - TriggerSource | - (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) | + ADC_JSQR_JL, + (TriggerSource & ADC_JSQR_JEXTSEL) | + (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | @@ -4653,7 +4615,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4683,19 +4645,11 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), - SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); -#endif } /** @@ -4758,7 +4712,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) - * + * * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n @@ -4783,21 +4737,12 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) ); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) - >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) - ); -#endif } /** @@ -4855,7 +4800,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK, - (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); + (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } /** @@ -5045,7 +4990,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6) - * + * * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n @@ -5061,21 +5006,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - - MODIFY_REG(*preg, - (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), - AWDChannelGroup & AWDy); -#endif } /** @@ -5129,7 +5065,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 (1) * @arg @ref LL_ADC_AWD3 (1) - * + * * (1) On this AWD number, monitored channel can be retrieved * if only 1 channel is programmed (or none or all channels). * This function cannot retrieve monitored channel if @@ -5197,28 +5133,28 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * + * * (0) On STM32L4, parameter available only on analog watchdog number: AWD1. */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if(AnalogWDMonitChannels != 0) + if (AnalogWDMonitChannels != 0UL) { - if(AWDy == LL_ADC_AWD1) + if (AWDy == LL_ADC_AWD1) { - if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0) + if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (( AnalogWDMonitChannels + AnalogWDMonitChannels = ((AnalogWDMonitChannels | (ADC_AWD_CR23_CHANNEL_MASK) ) & (~(ADC_CFGR_AWD1CH)) @@ -5234,10 +5170,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint } else { - if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK + AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) ); } @@ -5245,16 +5181,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ( AnalogWDMonitChannels + AnalogWDMonitChannels = (AnalogWDMonitChannels | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) ); } } } - - return AnalogWDMonitChannels; + return AnalogWDMonitChannels; } /** @@ -5286,6 +5221,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going @@ -5305,19 +5244,16 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, + uint32_t AWDThresholdLowValue) { /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ /* position in register and register position depending on parameter */ /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); -#endif - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); @@ -5352,6 +5288,10 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going @@ -5373,26 +5313,19 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - + register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - AWDThresholdsHighLow, - AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow)); -#endif } /** @@ -5422,24 +5355,15 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) ); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - (AWDThresholdsHighLow | ADC_TR1_LT1)) - >> POSITION_VAL(AWDThresholdsHighLow) - ); -#endif } /** @@ -5517,8 +5441,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @note On this STM32 serie, oversampling discontinuous mode - * (triggered mode) can be used only when oversampling is + * @note On this STM32 serie, oversampling discontinuous mode + * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont * @param ADCx ADC instance @@ -5604,7 +5528,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_64 * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); @@ -5625,7 +5549,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); @@ -5821,7 +5745,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_CO * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) - * + * * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. @@ -5850,7 +5774,7 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) - * + * * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. @@ -5938,7 +5862,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); + return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } /** @@ -5987,12 +5911,12 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 serie, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. @@ -6047,7 +5971,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } /** @@ -6058,7 +5982,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } /** @@ -6102,7 +6026,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleD */ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } /** @@ -6115,7 +6039,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 serie, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. @@ -6169,7 +6093,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } /** @@ -6180,7 +6104,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } /** @@ -6283,7 +6207,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) - >> POSITION_VAL(ConversionData) + >> (POSITION_VAL(ConversionData) & 0x1FUL) ); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -6298,7 +6222,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 serie, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. @@ -6352,7 +6276,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); + return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } /** @@ -6363,7 +6287,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); + return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } /** @@ -6385,12 +6309,8 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -6416,12 +6336,8 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -6447,12 +6363,8 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -6478,12 +6390,8 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -6509,12 +6417,8 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { -#if defined(CORE_CM0PLUS) - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); -#else - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); -#endif - + register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -6539,7 +6443,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } /** @@ -6550,7 +6454,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); + return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } /** @@ -6561,7 +6465,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } /** @@ -6572,7 +6476,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } /** @@ -6583,7 +6487,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } /** @@ -6594,7 +6498,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } /** @@ -6605,7 +6509,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } /** @@ -6616,7 +6520,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } /** @@ -6627,7 +6531,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } /** @@ -6638,7 +6542,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } /** @@ -6649,7 +6553,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } /** @@ -6786,7 +6690,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } /** @@ -6798,7 +6702,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } /** @@ -6810,7 +6714,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** @@ -6822,7 +6726,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** @@ -6834,7 +6738,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } /** @@ -6846,7 +6750,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } /** @@ -6858,7 +6762,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } /** @@ -6870,7 +6774,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } /** @@ -6882,7 +6786,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } /** @@ -6894,7 +6798,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } /** @@ -6906,7 +6810,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } /** @@ -6918,7 +6822,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } /** @@ -6930,7 +6834,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } /** @@ -6942,7 +6846,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } /** @@ -6954,7 +6858,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } /** @@ -6966,7 +6870,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } /** @@ -6978,7 +6882,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } /** @@ -6990,7 +6894,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } /** @@ -7002,7 +6906,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } /** @@ -7014,7 +6918,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } /** @@ -7026,7 +6930,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } /** @@ -7038,7 +6942,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -7301,7 +7205,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } /** @@ -7313,7 +7217,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } /** @@ -7325,7 +7229,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } /** @@ -7337,7 +7241,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } /** @@ -7349,7 +7253,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } /** @@ -7361,7 +7265,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } /** @@ -7373,7 +7277,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } /** @@ -7385,7 +7289,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } /** @@ -7397,7 +7301,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } /** @@ -7409,7 +7313,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } /** @@ -7421,7 +7325,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) { - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } /** @@ -7477,6 +7381,6 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); } #endif -#endif /* __STM32L4xx_LL_ADC_H */ +#endif /* STM32L4xx_LL_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h index a547514fcb..8340ad3cb5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h @@ -4,17 +4,17 @@ * @author MCD Application Team * @brief Header file of BUS LL module. - @verbatim + @verbatim ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary - [..] + [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each LL_{BUS}_GRP{x}_EnableClock() function. @@ -23,36 +23,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_BUS_H -#define __STM32L4xx_LL_BUS_H +#ifndef STM32L4xx_LL_BUS_H +#define STM32L4xx_LL_BUS_H #ifdef __cplusplus extern "C" { @@ -325,7 +309,7 @@ extern "C" { * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 @@ -357,7 +341,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 @@ -373,7 +357,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -385,7 +369,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 @@ -412,8 +396,8 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 @@ -441,8 +425,8 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 @@ -627,7 +611,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -923,7 +907,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1193,7 +1177,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs); + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1213,7 +1197,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs); + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1733,7 +1717,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); } /** @@ -1965,6 +1949,6 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) } #endif -#endif /* __STM32L4xx_LL_BUS_H */ +#endif /* STM32L4xx_LL_BUS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c index 9f902eb443..bcd23b47d0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -38,9 +22,9 @@ #include "stm32l4xx_ll_comp.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32L4xx_LL_Driver @@ -131,10 +115,11 @@ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) +#if defined(COMP2) #define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ ? ( \ - (1U) \ + (1UL) \ ) \ : \ (((__COMP_INSTANCE__) == COMP1) \ @@ -151,7 +136,34 @@ ) \ ) \ ) - +#else +#if defined(TIM3) +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + ? ( \ + (1UL) \ + ) \ + : \ + ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + ) \ + ) +#else +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + ? ( \ + (1UL) \ + ) \ + : \ + ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + ) \ + ) +#endif /* TIM3 */ +#endif /* COMP2 */ /** * @} */ @@ -182,15 +194,15 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); - + /* Note: Hardware constraint (refer to description of this function): */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if (LL_COMP_IsLocked(COMPx) == 0UL) { - LL_COMP_WriteReg(COMPx, CSR, 0x00000000U); + LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL); } else @@ -200,7 +212,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) /* The only way to unlock the comparator is a device hardware reset. */ status = ERROR; } - + return status; } @@ -219,7 +231,7 @@ ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(COMPx)); assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode)); @@ -228,10 +240,10 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis)); assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource)); - + /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ - if(LL_COMP_IsLocked(COMPx) == 0U) + if (LL_COMP_IsLocked(COMPx) == 0UL) { /* Configuration of comparator instance : */ /* - PowerMode */ @@ -242,7 +254,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* - OutputBlankingSource */ #if defined(COMP_CSR_INMESEL_1) MODIFY_REG(COMPx->CSR, - COMP_CSR_PWRMODE + COMP_CSR_PWRMODE | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN @@ -251,8 +263,8 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru | COMP_CSR_HYST | COMP_CSR_POLARITY | COMP_CSR_BLANKING - , - COMP_InitStruct->PowerMode + , + COMP_InitStruct->PowerMode | COMP_InitStruct->InputPlus | COMP_InitStruct->InputMinus | COMP_InitStruct->InputHysteresis @@ -261,7 +273,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru ); #else MODIFY_REG(COMPx->CSR, - COMP_CSR_PWRMODE + COMP_CSR_PWRMODE | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN @@ -269,8 +281,8 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru | COMP_CSR_HYST | COMP_CSR_POLARITY | COMP_CSR_BLANKING - , - COMP_InitStruct->PowerMode + , + COMP_InitStruct->PowerMode | COMP_InitStruct->InputPlus | COMP_InitStruct->InputMinus | COMP_InitStruct->InputHysteresis @@ -285,7 +297,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /* Initialization error: COMP instance is locked. */ status = ERROR; } - + return status; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h index 8b02ddb71e..bed801aab5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_COMP_H -#define __STM32L4xx_LL_COMP_H +#ifndef STM32L4xx_LL_COMP_H +#define STM32L4xx_LL_COMP_H #ifdef __cplusplus extern "C" { @@ -62,7 +46,7 @@ extern "C" { */ /* COMP registers bits positions */ -#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ +#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ /** * @} @@ -82,32 +66,32 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - + This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -125,8 +109,10 @@ typedef struct /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ -#define LL_COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */ +#if defined(COMP2) +#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */ #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#endif /* COMP2 */ /** * @} */ @@ -134,7 +120,7 @@ typedef struct /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ -#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< COMP power mode to high speed */ +#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */ #define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ /** @@ -144,7 +130,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection * @{ */ -#define LL_COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -204,7 +190,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis * @{ */ -#define LL_COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ #define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ @@ -215,7 +201,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity * @{ */ -#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ +#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ #define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */ /** * @} @@ -224,7 +210,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source * @{ */ -#define LL_COMP_BLANKINGSRC_NONE (0x00000000U) /*!__REG__, (__VALUE__)) +#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in COMP register @@ -312,7 +298,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -346,6 +332,7 @@ typedef struct * @{ */ +#if defined(COMP2) /** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances * @{ */ @@ -387,6 +374,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy * @} */ +#endif /* COMP2 */ /** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes * @{ */ @@ -438,7 +426,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or * subdivision of VrefInt). - * - For scaler bridge power consumption values, + * - For scaler bridge power consumption values, * refer to device datasheet, parameter "IDDA(SCALER)". * - Voltage scaler requires a delay for voltage stabilization. * Refer to device datasheet, parameter "tSTART_SCALER". @@ -462,13 +450,13 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_IO3 (*) * @arg @ref LL_COMP_INPUT_MINUS_IO4 (*) * @arg @ref LL_COMP_INPUT_MINUS_IO5 (*) - * + * * (*) Parameter not available on all devices. * @param InputPlus This parameter can be one of the following values: * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 (*) - * + * * (*) Parameter not available on all devices. * @retval None */ @@ -496,7 +484,7 @@ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMin * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 (*) - * + * * (*) Parameter not available on all devices. * @retval None */ @@ -516,7 +504,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_IO3 (*) - * + * * (*) Parameter not available on all devices. */ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) @@ -534,7 +522,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or * subdivision of VrefInt). - * - For scaler bridge power consumption values, + * - For scaler bridge power consumption values, * refer to device datasheet, parameter "IDDA(SCALER)". * - Voltage scaler requires a delay for voltage stabilization. * Refer to device datasheet, parameter "tSTART_SCALER". @@ -557,7 +545,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_IO3 (*) * @arg @ref LL_COMP_INPUT_MINUS_IO4 (*) * @arg @ref LL_COMP_INPUT_MINUS_IO5 (*) - * + * * (*) Parameter not available on all devices. * @retval None */ @@ -591,7 +579,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_IO3 (*) * @arg @ref LL_COMP_INPUT_MINUS_IO4 (*) * @arg @ref LL_COMP_INPUT_MINUS_IO5 (*) - * + * * (*) Parameter not available on all devices. */ __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) @@ -685,7 +673,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (1)(3) * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (1)(3) * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3) - * + * * (1) Parameter availability depending on timer availability * on the selected device. * (2) On STM32L4, parameter available only on comparator instance: COMP1. @@ -713,7 +701,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (1)(3) * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (1)(3) * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2 (1)(3) - * + * * (1) Parameter availability depending on timer availability * on the selected device. * (2) On STM32L4, parameter available only on comparator instance: COMP1. @@ -793,7 +781,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) */ __STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) { - return (READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)); + return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); } /** @@ -820,7 +808,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) */ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) { - return (READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)); + return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); } /** @@ -875,6 +863,10 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); * @} */ +/** + * @} + */ + #endif /* COMP1 || COMP2 */ /** @@ -885,6 +877,6 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); } #endif -#endif /* __STM32L4xx_LL_COMP_H */ +#endif /* STM32L4xx_LL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h index 692f320a58..7268c2c62c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h @@ -21,29 +21,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c index 3edbbd5bf0..cc55e023e5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h index de2b5b3613..6ca1a28512 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crc.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_CRC_H -#define __STM32L4xx_LL_CRC_H +#ifndef STM32L4xx_LL_CRC_H +#define STM32L4xx_LL_CRC_H #ifdef __cplusplus extern "C" { @@ -354,7 +338,7 @@ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) { __IO uint16_t *pReg; - pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = InData; } @@ -444,7 +428,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) #if (CRC_IDR_IDR == 0x0FFU) *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; #else - WRITE_REG(CRCx->IDR, InData); + WRITE_REG(CRCx->IDR, InData); #endif } /** @@ -481,6 +465,6 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); } #endif -#endif /* __STM32L4xx_LL_CRC_H */ +#endif /* STM32L4xx_LL_CRC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c index 83b775ad36..557ec9a694 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h index 4eb39e0989..74b865aae3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -143,24 +127,29 @@ extern "C" { * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz * and a synchronization signal frequency of 1 kHz (SOF signal from USB) */ -#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) +#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) /** * @brief Reset value of Frequency error limit. */ -#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) +#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) /** * @brief Reset value of the HSI48 Calibration field - * @note The default value is 32, which corresponds to the middle of the trimming interval. - * The trimming step is around 67 kHz between two consecutive TRIM steps. + * @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds + * to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. * A higher TRIM value corresponds to a higher output frequency */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) +#if defined (STM32L412xx) || defined (STM32L422xx) +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U) +#else +#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U) +#endif /** * @} - */ - + */ + /** * @} */ @@ -200,7 +189,7 @@ extern "C" { /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between + * @note The RELOAD value should be selected according to the ratio between * the target frequency and the frequency of the synchronization source after * prescaling. It is then decreased by one in order to reach the expected * synchronization on the zero value. The formula is the following: @@ -293,8 +282,8 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) * @brief Set HSI48 oscillator smooth trimming * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming - * @param Value a number between Min_Data = 0 and Max_Data = 63 - * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT * @retval None */ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) @@ -305,7 +294,7 @@ __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) /** * @brief Get HSI48 oscillator smooth trimming * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming - * @retval a number between Min_Data = 0 and Max_Data = 63 + * @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise */ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) { @@ -316,7 +305,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) * @brief Set counter reload value * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF - * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) * @retval None */ @@ -339,7 +328,7 @@ __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) * @brief Set frequency error limit * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit * @param Value a number between Min_Data = 0 and Max_Data = 255 - * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT * @retval None */ __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) @@ -467,8 +456,8 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) { MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); - MODIFY_REG(CRS->CFGR, - CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); } @@ -491,7 +480,7 @@ __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) } /** - * @brief Get the frequency error direction latched in the time of the last + * @brief Get the frequency error direction latched in the time of the last * SYNC event * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection * @retval Returned value can be one of the following values: @@ -612,7 +601,7 @@ __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) } /** - * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also * the ERR flag * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR * @retval None @@ -768,7 +757,7 @@ __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions * @{ */ - + ErrorStatus LL_CRS_DeInit(void); /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c index 30a154f970..c0d5a15750 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -64,13 +48,13 @@ */ #if defined(DAC_CHANNEL2_SUPPORT) -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ +#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #else -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ +#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ ) @@ -86,8 +70,8 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) @@ -110,31 +94,35 @@ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) -#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ - ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ +#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ + ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ @@ -180,26 +168,37 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); - + /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); - + /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); - + return SUCCESS; } /** - * @brief Initialize some features of DAC instance. + * @brief Initialize some features of DAC channel. + * @note @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel. + * Leaving it ready to be enabled and output: + * a level by calling one of + * @ref LL_DAC_ConvertData12RightAligned + * @ref LL_DAC_ConvertData12LeftAligned + * @ref LL_DAC_ConvertData8RightAligned + * or one of the supported autogenerated wave. + * @note This function allows configuration of: + * - Output mode + * - Trigger + * - Wave generation * @note The setting of these parameters by function @ref LL_DAC_Init() * is conditioned to DAC state: - * DAC instance must be disabled. + * DAC channel must be disabled. * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure @@ -210,10 +209,10 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); - assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); + assert_param(IS_LL_DAC_CHANNEL(DAC_Channel)); assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection)); @@ -221,12 +220,13 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { - assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration, + DAC_InitStruct->WaveAutoGenerationConfig)); } - + /* Note: Hardware constraint (refer to description of this function) */ /* DAC instance must be disabled. */ - if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) + if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) { /* Configuration of DAC channel: */ /* - TriggerSource */ @@ -237,12 +237,12 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { MODIFY_REG(DACx->CR, - ( DAC_CR_TSEL1 + (DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) , - ( DAC_InitStruct->TriggerSource + (DAC_InitStruct->TriggerSource | DAC_InitStruct->WaveAutoGeneration | DAC_InitStruct->WaveAutoGenerationConfig ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) @@ -251,23 +251,22 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType else { MODIFY_REG(DACx->CR, - ( DAC_CR_TSEL1 + (DAC_CR_TSEL1 | DAC_CR_WAVE1 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) , - ( DAC_InitStruct->TriggerSource + (DAC_InitStruct->TriggerSource | LL_DAC_WAVE_AUTO_GENERATION_NONE ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } - MODIFY_REG(DACx->MCR, - ( DAC_MCR_MODE1_1 + (DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0 | DAC_MCR_MODE1_2 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) , - ( DAC_InitStruct->OutputBuffer + (DAC_InitStruct->OutputBuffer | DAC_InitStruct->OutputConnection | DAC_InitStruct->OutputMode ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h index e312a599c3..88b2a45e07 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DAC_H -#define __STM32L4xx_LL_DAC_H +#ifndef STM32L4xx_LL_DAC_H +#define STM32L4xx_LL_DAC_H #ifdef __cplusplus extern "C" { @@ -69,14 +53,13 @@ extern "C" { /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ /* - channel register offset of sample-and-hold sample time register SHSRx */ - #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) -#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) #else #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) @@ -86,18 +69,18 @@ extern "C" { #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #else #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) @@ -105,17 +88,27 @@ extern "C" { #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_SHSR2_REGOFFSET 0x00001000U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */ +#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) #else #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) #endif /* DAC_CHANNEL2_SUPPORT */ +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ + +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ + /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos #endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ @@ -131,17 +124,6 @@ extern "C" { * @{ */ -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits -*/ -#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset @@ -169,38 +151,38 @@ extern "C" { */ typedef struct { - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE @note If waveform automatic generation mode is disabled, this parameter is discarded. - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() + depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION - + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ } LL_DAC_InitTypeDef; /** @@ -254,6 +236,18 @@ typedef struct /** * @} */ +#if defined (DAC_CR_HFSEL) /* High frequency interface mode */ + +/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode + * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode + * @{ + */ +#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ +#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ +/** + * @} + */ +#endif /* High frequency interface mode */ /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode * @{ @@ -271,13 +265,13 @@ typedef struct #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ #else @@ -298,9 +292,9 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ -#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ -#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ /** * @} */ @@ -370,28 +364,6 @@ typedef struct * @} */ -/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming - * @{ - */ -#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE) -#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO) -#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO) -#define LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) -#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO) -#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO) -#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO) -#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9) - -#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE) -#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE) -#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) - -#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO) -#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL) -/** - * @} - */ - /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ @@ -407,15 +379,15 @@ typedef struct /* List of DAC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ -#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ -#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ -#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ /** * @} */ /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays - * @note Only DAC IP HW delays are defined in DAC LL driver driver, + * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. @@ -448,7 +420,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 2U /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */ /** * @} @@ -502,11 +474,8 @@ typedef struct * number is returned. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. - * @retval 1...2 (value "2" depending on DAC channel 2 availability) + * @arg @ref LL_DAC_CHANNEL_2 + * @retval 1...2 */ #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((__CHANNEL__) & DAC_SWTR_CHX_MASK) @@ -519,40 +488,37 @@ typedef struct * will return a data equivalent to "LL_DAC_CHANNEL_1". * @note If the input parameter does not correspond to a DAC channel, * this macro returns value '0'. - * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) + * @param __DECIMAL_NB__ 1...2 * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 */ #if defined(DAC_CHANNEL2_SUPPORT) #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1U) \ + (((__DECIMAL_NB__) == 1U) \ ? ( \ LL_DAC_CHANNEL_1 \ ) \ : \ - (((__DECIMAL_NB__) == 2U) \ + (((__DECIMAL_NB__) == 2U) \ ? ( \ LL_DAC_CHANNEL_2 \ ) \ : \ ( \ - 0 \ + 0U \ ) \ ) \ ) #else #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1U) \ + (((__DECIMAL_NB__) == 1U) \ ? ( \ LL_DAC_CHANNEL_1 \ ) \ : \ ( \ - 0 \ + 0U \ ) \ ) #endif /* DAC_CHANNEL2_SUPPORT */ @@ -609,6 +575,44 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ + +#if defined (DAC_CR_HFSEL) /* High frequency interface mode */ + +/** @defgroup DAC_LL_EF_Configuration Configuration of DAC instance + * @{ + */ +/** + * @brief Set the high frequency interface mode for the selected DAC instance + * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode + * @param DACx DAC instance + * @param HighFreqMode This parameter can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode) +{ + MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode); +} + +/** + * @brief Get the high frequency interface mode for the selected DAC instance + * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode + * @param DACx DAC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE + * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ + */ +__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL)); +} +/** + * @} + */ + +#endif /* High frequency interface mode */ + /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ @@ -621,10 +625,7 @@ typedef struct * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * - * @arg @ref LL_DAC_CHANNEL_2 (1) - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @param ChannelMode This parameter can be one of the following values: * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION @@ -645,10 +646,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_MODE_NORMAL_OPERATION * @arg @ref LL_DAC_MODE_CALIBRATION @@ -669,10 +667,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F * @retval None */ @@ -692,10 +687,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) @@ -718,18 +710,19 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 (1) - * - * (1) On this STM32 serie, parameter not available on all devices. - * Refer to device datasheet for channels availability. + * @arg @ref LL_DAC_CHANNEL_2 * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 * @retval None */ @@ -752,18 +745,22 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_DAC_TRIGGER_EXT_IT9 + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) { @@ -781,7 +778,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param WaveAutoGeneration This parameter can be one of the following values: @@ -806,7 +803,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -835,7 +832,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param NoiseLFSRMask This parameter can be one of the following values: @@ -861,7 +858,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha } /** - * @brief Set the noise waveform generation for the selected DAC channel: + * @brief Get the noise waveform generation for the selected DAC channel: * Noise mode and parameters LFSR (linear feedback shift register). * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n * CR MAMP2 LL_DAC_GetWaveNoiseLFSR @@ -869,7 +866,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -907,7 +904,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriangleAmplitude This parameter can be one of the following values: @@ -925,7 +922,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 * @retval None */ -__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, + uint32_t TriangleAmplitude) { MODIFY_REG(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), @@ -933,7 +931,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t } /** - * @brief Set the triangle waveform generation for the selected DAC channel: + * @brief Get the triangle waveform generation for the selected DAC channel: * triangle mode and amplitude. * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude @@ -941,7 +939,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -988,7 +986,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * (both connections to GPIO pin and internal path). * @note Mode sample-and-hold requires an external capacitor * to be connected between DAC channel output and ground. - * Capacitor value depends on load on DAC channel output and + * Capacitor value depends on load on DAC channel output and * sample-and-hold timings configured. * As indication, capacitor typical value is 100nF * (refer to device datasheet, parameter "CSH"). @@ -998,7 +996,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputMode This parameter can be one of the following values: @@ -1012,7 +1010,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL * @retval None */ -__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection) +__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, + uint32_t OutputBuffer, uint32_t OutputConnection) { MODIFY_REG(DACx->MCR, (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), @@ -1024,7 +1023,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel * for the selected DAC channel. * @note Mode sample-and-hold requires an external capacitor * to be connected between DAC channel output and ground. - * Capacitor value depends on load on DAC channel output and + * Capacitor value depends on load on DAC channel output and * sample-and-hold timings configured. * As indication, capacitor typical value is 100nF * (refer to device datasheet, parameter "CSH"). @@ -1034,7 +1033,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputMode This parameter can be one of the following values: @@ -1045,7 +1044,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) { MODIFY_REG(DACx->MCR, - DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } @@ -1057,7 +1056,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -1066,7 +1065,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe */ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } @@ -1083,7 +1082,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputBuffer This parameter can be one of the following values: @@ -1094,7 +1093,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) { MODIFY_REG(DACx->MCR, - DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } @@ -1106,7 +1105,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -1115,7 +1114,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan */ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } @@ -1138,7 +1137,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputConnection This parameter can be one of the following values: @@ -1149,7 +1148,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) { MODIFY_REG(DACx->MCR, - DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } @@ -1171,7 +1170,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: @@ -1180,7 +1179,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ */ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } @@ -1198,7 +1197,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF @@ -1206,8 +1205,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK)); - + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); @@ -1222,15 +1221,15 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK)); - + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); } @@ -1243,7 +1242,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, ui * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF @@ -1265,7 +1264,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF @@ -1286,7 +1285,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF @@ -1308,7 +1307,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x00 and Max_Data=0xFF @@ -1320,24 +1319,6 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, u ); } -/** - * @} - */ - -/** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name - * @{ - */ -/* Old functions name kept for legacy purpose, to be replaced by the */ -/* current functions name. */ -__STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode) -{ - LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode); -} -__STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel); -} - /** * @} */ @@ -1356,7 +1337,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Chan * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1377,7 +1358,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1397,16 +1378,16 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, + return ((READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** @@ -1434,7 +1415,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Register This parameter can be one of the following values: @@ -1447,7 +1428,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, + ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -1468,7 +1450,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1487,7 +1469,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1507,16 +1489,16 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, + return ((READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** @@ -1535,7 +1517,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1554,7 +1536,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1574,22 +1556,24 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, + return ((READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** * @brief Trig DAC conversion by software for the selected DAC channel. * @note Preliminarily, DAC trigger must be set to software trigger - * using function @ref LL_DAC_SetTriggerSource() + * using function + * @ref LL_DAC_Init() + * @ref LL_DAC_SetTriggerSource() * with parameter "LL_DAC_TRIGGER_SOFTWARE". * and DAC trigger must be enabled using * function @ref LL_DAC_EnableTrigger(). @@ -1603,7 +1587,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC * @param DAC_Channel This parameter can a combination of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None @@ -1624,7 +1608,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF @@ -1632,8 +1616,8 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); - + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); @@ -1649,7 +1633,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF @@ -1657,8 +1641,8 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); - + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); @@ -1674,7 +1658,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF @@ -1682,8 +1666,8 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); - + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); @@ -1701,7 +1685,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { MODIFY_REG(DACx->DHR12RD, (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), @@ -1760,15 +1745,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) - * + * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); - + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } @@ -1787,7 +1772,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1799,7 +1784,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1811,7 +1796,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1823,7 +1808,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1835,7 +1820,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1847,7 +1832,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1939,7 +1924,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } #if defined(DAC_CHANNEL2_SUPPORT) @@ -1951,7 +1936,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } #endif /* DAC_CHANNEL2_SUPPORT */ @@ -1964,9 +1949,9 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); -void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); +ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** * @} @@ -1991,6 +1976,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); } #endif -#endif /* __STM32L4xx_LL_DAC_H */ +#endif /* STM32L4xx_LL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c index c60a79c7e2..2d80835987 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -176,10 +160,10 @@ * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) { - DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; ErrorStatus status = SUCCESS; + DMA_Channel_TypeDef *tmp; /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); @@ -217,20 +201,20 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) CLEAR_BIT(tmp->CCR, DMA_CCR_EN); /* Reset DMAx_Channely control register */ - LL_DMA_WriteReg(tmp, CCR, 0U); + WRITE_REG(tmp->CCR, 0U); /* Reset DMAx_Channely remaining bytes register */ - LL_DMA_WriteReg(tmp, CNDTR, 0U); + WRITE_REG(tmp->CNDTR, 0U); /* Reset DMAx_Channely peripheral address register */ - LL_DMA_WriteReg(tmp, CPAR, 0U); + WRITE_REG(tmp->CPAR, 0U); - /* Reset DMAx_Channely memory address register */ - LL_DMA_WriteReg(tmp, CMAR, 0U); + /* Reset DMAx_Channely memory 0 address register */ + WRITE_REG(tmp->CMAR, 0U); #if defined(DMAMUX1) /* Reset Request register field for DMAx Channel */ - LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQUEST_MEM2MEM); + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM); #else /* Reset Request register field for DMAx Channel */ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); @@ -300,7 +284,7 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) * - SUCCESS: DMA registers are initialized * - ERROR: Not applicable */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) { /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); @@ -389,7 +373,7 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; DMA_InitStruct->NbData = 0x00000000U; #if defined(DMAMUX1) - DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQUEST_MEM2MEM; + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM; #else DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; #endif /* DMAMUX1 */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h index f6c75b0416..fea188e80d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DMA_H -#define __STM32L4xx_LL_DMA_H +#ifndef STM32L4xx_LL_DMA_H +#define STM32L4xx_LL_DMA_H #ifdef __cplusplus extern "C" { @@ -87,12 +71,13 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) /* Defines used for the bit position in the register and perform offsets */ -#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U)) +#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U)) /** * @} */ #endif /* DMAMUX1 */ +/* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ #if defined(DMAMUX1) /** @defgroup DMA_LL_Private_Macros DMA Private Macros @@ -106,7 +91,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). */ #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ -(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) +(((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7) /** * @} @@ -297,13 +282,13 @@ typedef struct /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ -#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ -#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ #if defined(USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ @@ -379,108 +364,7 @@ typedef struct * @} */ -#if defined(DMAMUX1) -/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request - * @{ - */ -#define LL_DMAMUX_REQUEST_MEM2MEM 0U /*!< Memory to memory transfer */ -#define LL_DMAMUX_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ -#define LL_DMAMUX_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ -#define LL_DMAMUX_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ -#define LL_DMAMUX_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ -#define LL_DMAMUX_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ -#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ -#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ -#define LL_DMAMUX_REQUEST_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ -#define LL_DMAMUX_REQUEST_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ -#define LL_DMAMUX_REQUEST_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ -#define LL_DMAMUX_REQUEST_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ -#define LL_DMAMUX_REQUEST_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ -#define LL_DMAMUX_REQUEST_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ -#define LL_DMAMUX_REQUEST_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ -#define LL_DMAMUX_REQUEST_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ -#define LL_DMAMUX_REQUEST_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ -#define LL_DMAMUX_REQUEST_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ -#define LL_DMAMUX_REQUEST_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ -#define LL_DMAMUX_REQUEST_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ -#define LL_DMAMUX_REQUEST_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ -#define LL_DMAMUX_REQUEST_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ -#define LL_DMAMUX_REQUEST_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ -#define LL_DMAMUX_REQUEST_USART1_RX 24U /*!< DMAMUX USART1 RX request */ -#define LL_DMAMUX_REQUEST_USART1_TX 25U /*!< DMAMUX USART1 TX request */ -#define LL_DMAMUX_REQUEST_USART2_RX 26U /*!< DMAMUX USART2 RX request */ -#define LL_DMAMUX_REQUEST_USART2_TX 27U /*!< DMAMUX USART2 TX request */ -#define LL_DMAMUX_REQUEST_USART3_RX 28U /*!< DMAMUX USART3 RX request */ -#define LL_DMAMUX_REQUEST_USART3_TX 29U /*!< DMAMUX USART3 TX request */ -#define LL_DMAMUX_REQUEST_UART4_RX 30U /*!< DMAMUX UART4 RX request */ -#define LL_DMAMUX_REQUEST_UART4_TX 31U /*!< DMAMUX UART4 TX request */ -#define LL_DMAMUX_REQUEST_UART5_RX 32U /*!< DMAMUX UART5 RX request */ -#define LL_DMAMUX_REQUEST_UART5_TX 33U /*!< DMAMUX UART5 TX request */ -#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ -#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ -#define LL_DMAMUX_REQUEST_SAI1_A 36U /*!< DMAMUX SAI1 A request */ -#define LL_DMAMUX_REQUEST_SAI1_B 37U /*!< DMAMUX SAI1 B request */ -#define LL_DMAMUX_REQUEST_SAI2_A 38U /*!< DMAMUX SAI2 A request */ -#define LL_DMAMUX_REQUEST_SAI2_B 39U /*!< DMAMUX SAI2 B request */ -#define LL_DMAMUX_REQUEST_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ -#define LL_DMAMUX_REQUEST_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ -#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ -#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ -#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ -#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ -#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ -#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ -#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ -#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ -#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ -#define LL_DMAMUX_REQUEST_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ -#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ -#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ -#define LL_DMAMUX_REQUEST_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ -#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ -#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ -#define LL_DMAMUX_REQUEST_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ -#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ -#define LL_DMAMUX_REQUEST_DCMI 90U /*!< DMAMUX DCMI request */ -#define LL_DMAMUX_REQUEST_AES_IN 91U /*!< DMAMUX AES_IN request */ -#define LL_DMAMUX_REQUEST_AES_OUT 92U /*!< DMAMUX AES_OUT request */ -#define LL_DMAMUX_REQUEST_HASH_IN 93U /*!< DMAMUX HASH_IN request */ -/** - * @} - */ -#else +#if !defined (DMAMUX1) /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request * @{ */ @@ -495,7 +379,7 @@ typedef struct /** * @} */ -#endif /* DMAMUX1 */ +#endif /* !defined DMAMUX1 */ /** * @} @@ -672,7 +556,8 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); } /** @@ -691,7 +576,8 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); } /** @@ -710,8 +596,9 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } /** @@ -745,7 +632,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); } @@ -771,7 +659,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -795,7 +684,8 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -820,7 +710,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, Mode); } @@ -842,7 +733,8 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC)); } @@ -865,7 +757,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -887,7 +780,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC)); } @@ -910,7 +804,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -932,7 +827,8 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC)); } @@ -956,7 +852,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -979,7 +876,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE)); } @@ -1003,7 +901,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -1026,7 +925,8 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE)); } @@ -1051,7 +951,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, Priority); } @@ -1075,7 +976,8 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL)); } @@ -1098,7 +1000,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -1120,7 +1023,8 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, DMA_CNDTR_NDT)); } @@ -1150,17 +1054,18 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { + uint32_t dma_base_addr = (uint32_t)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress); } } @@ -1183,7 +1088,8 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); } /** @@ -1205,7 +1111,8 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); } /** @@ -1225,7 +1132,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); } /** @@ -1245,7 +1153,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); } /** @@ -1267,7 +1176,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); } /** @@ -1289,7 +1199,8 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); } /** @@ -1309,7 +1220,8 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); } /** @@ -1329,7 +1241,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); } #if defined(DMAMUX1) @@ -1348,105 +1261,106 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param Request This parameter can be one of the following values: - * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 - * @arg @ref LL_DMAMUX_REQUEST_ADC1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP - * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX - * @arg @ref LL_DMAMUX_REQUEST_USART1_RX - * @arg @ref LL_DMAMUX_REQUEST_USART1_TX - * @arg @ref LL_DMAMUX_REQUEST_USART2_RX - * @arg @ref LL_DMAMUX_REQUEST_USART2_TX - * @arg @ref LL_DMAMUX_REQUEST_USART3_RX - * @arg @ref LL_DMAMUX_REQUEST_USART3_TX - * @arg @ref LL_DMAMUX_REQUEST_UART4_RX - * @arg @ref LL_DMAMUX_REQUEST_UART4_TX - * @arg @ref LL_DMAMUX_REQUEST_UART5_RX - * @arg @ref LL_DMAMUX_REQUEST_UART5_TX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX - * @arg @ref LL_DMAMUX_REQUEST_SAI1_A - * @arg @ref LL_DMAMUX_REQUEST_SAI1_B - * @arg @ref LL_DMAMUX_REQUEST_SAI2_A - * @arg @ref LL_DMAMUX_REQUEST_SAI2_B - * @arg @ref LL_DMAMUX_REQUEST_OSPI1 - * @arg @ref LL_DMAMUX_REQUEST_OSPI2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 - * @arg @ref LL_DMAMUX_REQUEST_DCMI - * @arg @ref LL_DMAMUX_REQUEST_AES_IN - * @arg @ref LL_DMAMUX_REQUEST_AES_OUT - * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN * @retval None */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } /** @@ -1464,104 +1378,105 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: - * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 - * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 - * @arg @ref LL_DMAMUX_REQUEST_ADC1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP - * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX - * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX - * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX - * @arg @ref LL_DMAMUX_REQUEST_USART1_RX - * @arg @ref LL_DMAMUX_REQUEST_USART1_TX - * @arg @ref LL_DMAMUX_REQUEST_USART2_RX - * @arg @ref LL_DMAMUX_REQUEST_USART2_TX - * @arg @ref LL_DMAMUX_REQUEST_USART3_RX - * @arg @ref LL_DMAMUX_REQUEST_USART3_TX - * @arg @ref LL_DMAMUX_REQUEST_UART4_RX - * @arg @ref LL_DMAMUX_REQUEST_UART4_TX - * @arg @ref LL_DMAMUX_REQUEST_UART5_RX - * @arg @ref LL_DMAMUX_REQUEST_UART5_TX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX - * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX - * @arg @ref LL_DMAMUX_REQUEST_SAI1_A - * @arg @ref LL_DMAMUX_REQUEST_SAI1_B - * @arg @ref LL_DMAMUX_REQUEST_SAI2_A - * @arg @ref LL_DMAMUX_REQUEST_SAI2_B - * @arg @ref LL_DMAMUX_REQUEST_OSPI1 - * @arg @ref LL_DMAMUX_REQUEST_OSPI2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 - * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG - * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM - * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP - * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 - * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 - * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 - * @arg @ref LL_DMAMUX_REQUEST_DCMI - * @arg @ref LL_DMAMUX_REQUEST_AES_IN - * @arg @ref LL_DMAMUX_REQUEST_AES_OUT - * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); } #else /** @@ -1597,7 +1512,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) { MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, - DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); + DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); } /** @@ -1631,7 +1546,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, - DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); + DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS); } #endif /* DMAMUX1 */ @@ -1651,7 +1566,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } /** @@ -1662,7 +1577,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } /** @@ -1673,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } /** @@ -1684,7 +1599,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } /** @@ -1695,7 +1610,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } /** @@ -1706,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } /** @@ -1717,7 +1632,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } /** @@ -1728,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } /** @@ -1739,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } /** @@ -1750,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } /** @@ -1761,7 +1676,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } /** @@ -1772,7 +1687,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } /** @@ -1783,7 +1698,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } /** @@ -1794,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } /** @@ -1805,7 +1720,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } /** @@ -1816,7 +1731,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } /** @@ -1827,7 +1742,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } /** @@ -1838,7 +1753,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } /** @@ -1849,7 +1764,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } /** @@ -1860,7 +1775,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } /** @@ -1871,7 +1786,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } /** @@ -1882,7 +1797,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } /** @@ -1893,7 +1808,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } /** @@ -1904,7 +1819,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } /** @@ -1915,7 +1830,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } /** @@ -1926,7 +1841,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } /** @@ -1937,7 +1852,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } /** @@ -1948,7 +1863,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } /** @@ -2282,7 +2197,8 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); } /** @@ -2301,7 +2217,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); } /** @@ -2320,7 +2237,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); } /** @@ -2339,7 +2257,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); } /** @@ -2358,7 +2277,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); } /** @@ -2377,7 +2297,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); } /** @@ -2396,8 +2317,9 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } /** @@ -2416,8 +2338,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } /** @@ -2436,8 +2359,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)); + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } /** @@ -2448,9 +2372,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Chann /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions * @{ */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); /** @@ -2476,6 +2399,6 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); } #endif -#endif /* __STM32L4xx_LL_DMA_H */ +#endif /* STM32L4xx_LL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c index 3f1012ea3e..d7aebdddad 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -83,7 +67,7 @@ ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ ((MODE) == LL_DMA2D_MODE_R2M)) -#endif +#endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/ #define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ @@ -99,8 +83,8 @@ #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) #define IS_LL_DMA2D_OFFSET_MODE(MODE) (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \ ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES)) - #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + #define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX) #define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES) @@ -109,8 +93,8 @@ #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) #define IS_LL_DMA2D_SWAP_MODE(MODE) (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \ ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO)) - #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + #define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \ ((ALPHA) == LL_DMA2D_ALPHA_INVERTED)) @@ -137,6 +121,8 @@ #define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \ ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \ ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE)) + + /** * @} */ @@ -187,7 +173,7 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, * otherwise ERROR result is returned. * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure * that contains the configuration information for the specified DMA2D peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content @@ -197,7 +183,8 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini { ErrorStatus status = ERROR; LL_DMA2D_ColorTypeDef DMA2D_ColorStruct; - uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U; + uint32_t tmp, tmp1, tmp2; + uint32_t regMask, regValue; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -234,14 +221,20 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ + regMask = DMA2D_OPFCCR_CM; + regValue = DMA2D_InitStruct->ColorMode; + #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) - MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB | DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), \ - (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->OutputSwapMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); -#else - MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \ - (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); + regMask |= DMA2D_OPFCCR_SB; + regValue |= DMA2D_InitStruct->OutputSwapMode; #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI); + regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode); + + + MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue); + /* DMA2D OOR register configuration ------------------------------------------*/ LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); @@ -268,7 +261,7 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini /** * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -299,9 +292,9 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) * @brief Configure the foreground or background according to the specified parameters * in the LL_DMA2D_LayerCfgTypeDef structure. * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains * the configuration information for the specified layer. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval None @@ -321,6 +314,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode)); assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode)); + if (LayerIdx == 0U) { /* Configure the background memory address */ @@ -373,7 +367,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D /** * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -399,15 +393,15 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) * @brief Initialize DMA2D output color register according to the specified parameters * in DMA2D_ColorStruct. * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains * the color configuration information for the specified DMA2D peripheral. * @retval None */ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct) { - uint32_t outgreen = 0U; - uint32_t outred = 0U; - uint32_t outalpha = 0U; + uint32_t outgreen; + uint32_t outred; + uint32_t outalpha; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -464,7 +458,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM */ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -491,7 +485,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU)); } - + return color; } @@ -508,7 +502,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) */ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -535,7 +529,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U); } - + return color; } @@ -552,7 +546,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) */ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -579,7 +573,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U); } - + return color; } @@ -596,7 +590,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) */ uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { - uint32_t color = 0U; + uint32_t color; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -619,7 +613,7 @@ uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U); } - + return color; } @@ -657,3 +651,4 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h index 3cf689e711..b3a6b4580e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DMA2D_H -#define __STM32L4xx_LL_DMA2D_H +#ifndef STM32L4xx_LL_DMA2D_H +#define STM32L4xx_LL_DMA2D_H #ifdef __cplusplus extern "C" { @@ -148,7 +132,8 @@ typedef struct #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ uint32_t LineOffset; /*!< Specifies the output line offset value. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on STM32L496xx/STM32L4A6xx + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on devices + where the Line Offset Mode feature is available. else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices. This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ @@ -271,6 +256,7 @@ typedef struct - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ + } LL_DMA2D_LayerCfgTypeDef; /** @@ -422,7 +408,7 @@ typedef struct /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode * @{ */ -#define LL_DMA2D_SWAP_MODE_REGULAR ((uint32_t)0x00000000) /*!< Regular order */ +#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */ #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ /** * @} @@ -447,11 +433,12 @@ typedef struct * @} */ + #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode * @{ */ -#define LL_DMA2D_LINE_OFFSET_PIXELS ((uint32_t)0x00000000) /*!< Line offsets are expressed in pixels */ +#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */ #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ /** * @} @@ -467,6 +454,7 @@ typedef struct * @} */ + /** * @} */ @@ -487,7 +475,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in DMA2D register. @@ -495,7 +483,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -532,7 +520,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } /** @@ -569,7 +557,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } /** @@ -594,7 +582,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } /** @@ -723,6 +711,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } + #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) /** * @brief Set DMA2D output swap mode. @@ -995,7 +984,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)); + return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions @@ -1044,7 +1033,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)); + return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } /** @@ -1430,7 +1419,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)); + return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } /** @@ -1787,7 +1776,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)); + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } /** @@ -1798,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)); + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } /** @@ -1809,7 +1798,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)); + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } /** @@ -1820,7 +1809,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)); + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } /** @@ -1831,7 +1820,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)); + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } /** @@ -1842,7 +1831,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)); + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } /** @@ -2059,7 +2048,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } /** @@ -2070,7 +2059,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } /** @@ -2081,7 +2070,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } /** @@ -2092,7 +2081,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } /** @@ -2103,7 +2092,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } /** @@ -2114,7 +2103,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) { - return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)); + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2163,6 +2152,6 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb } #endif -#endif /* __STM32L4xx_LL_DMA2D_H */ +#endif /* STM32L4xx_LL_DMA2D_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h index 66a10c9d19..82aead0c41 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_DMAMUX_H -#define __STM32L4xx_LL_DMAMUX_H +#ifndef STM32L4xx_LL_DMAMUX_H +#define STM32L4xx_LL_DMAMUX_H #ifdef __cplusplus extern "C" { @@ -61,10 +45,10 @@ extern "C" { * @{ */ /* Define used to get DMAMUX CCR register size */ -#define DMAMUX_CCR_SIZE 0x00000004U +#define DMAMUX_CCR_SIZE 0x00000004UL /* Define used to get DMAMUX RGCR register size */ -#define DMAMUX_RGCR_SIZE 0x00000004U +#define DMAMUX_RGCR_SIZE 0x00000004UL /** * @} */ @@ -141,21 +125,27 @@ extern "C" { * @{ */ #define LL_DMAMUX_REQ_MEM2MEM 0U /*!< Memory to memory transfer */ + #define LL_DMAMUX_REQ_GENERATOR0 1U /*!< DMAMUX request generator 0 */ #define LL_DMAMUX_REQ_GENERATOR1 2U /*!< DMAMUX request generator 1 */ #define LL_DMAMUX_REQ_GENERATOR2 3U /*!< DMAMUX request generator 2 */ #define LL_DMAMUX_REQ_GENERATOR3 4U /*!< DMAMUX request generator 3 */ + #define LL_DMAMUX_REQ_ADC1 5U /*!< DMAMUX ADC1 request */ + #define LL_DMAMUX_REQ_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ #define LL_DMAMUX_REQ_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ + #define LL_DMAMUX_REQ_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ #define LL_DMAMUX_REQ_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ + #define LL_DMAMUX_REQ_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ #define LL_DMAMUX_REQ_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ #define LL_DMAMUX_REQ_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ #define LL_DMAMUX_REQ_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ #define LL_DMAMUX_REQ_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ #define LL_DMAMUX_REQ_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ + #define LL_DMAMUX_REQ_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ #define LL_DMAMUX_REQ_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ #define LL_DMAMUX_REQ_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ @@ -164,24 +154,30 @@ extern "C" { #define LL_DMAMUX_REQ_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ #define LL_DMAMUX_REQ_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ #define LL_DMAMUX_REQ_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ + #define LL_DMAMUX_REQ_USART1_RX 24U /*!< DMAMUX USART1 RX request */ #define LL_DMAMUX_REQ_USART1_TX 25U /*!< DMAMUX USART1 TX request */ #define LL_DMAMUX_REQ_USART2_RX 26U /*!< DMAMUX USART2 RX request */ #define LL_DMAMUX_REQ_USART2_TX 27U /*!< DMAMUX USART2 TX request */ #define LL_DMAMUX_REQ_USART3_RX 28U /*!< DMAMUX USART3 RX request */ #define LL_DMAMUX_REQ_USART3_TX 29U /*!< DMAMUX USART3 TX request */ + #define LL_DMAMUX_REQ_UART4_RX 30U /*!< DMAMUX UART4 RX request */ #define LL_DMAMUX_REQ_UART4_TX 31U /*!< DMAMUX UART4 TX request */ #define LL_DMAMUX_REQ_UART5_RX 32U /*!< DMAMUX UART5 RX request */ #define LL_DMAMUX_REQ_UART5_TX 33U /*!< DMAMUX UART5 TX request */ + #define LL_DMAMUX_REQ_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ #define LL_DMAMUX_REQ_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ + #define LL_DMAMUX_REQ_SAI1_A 36U /*!< DMAMUX SAI1 A request */ #define LL_DMAMUX_REQ_SAI1_B 37U /*!< DMAMUX SAI1 B request */ #define LL_DMAMUX_REQ_SAI2_A 38U /*!< DMAMUX SAI2 A request */ #define LL_DMAMUX_REQ_SAI2_B 39U /*!< DMAMUX SAI2 B request */ + #define LL_DMAMUX_REQ_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ #define LL_DMAMUX_REQ_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ + #define LL_DMAMUX_REQ_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ #define LL_DMAMUX_REQ_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ #define LL_DMAMUX_REQ_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ @@ -189,6 +185,7 @@ extern "C" { #define LL_DMAMUX_REQ_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ #define LL_DMAMUX_REQ_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ #define LL_DMAMUX_REQ_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ + #define LL_DMAMUX_REQ_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ #define LL_DMAMUX_REQ_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ #define LL_DMAMUX_REQ_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ @@ -196,22 +193,26 @@ extern "C" { #define LL_DMAMUX_REQ_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ #define LL_DMAMUX_REQ_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ #define LL_DMAMUX_REQ_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ + #define LL_DMAMUX_REQ_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ #define LL_DMAMUX_REQ_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ #define LL_DMAMUX_REQ_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ #define LL_DMAMUX_REQ_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ #define LL_DMAMUX_REQ_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ + #define LL_DMAMUX_REQ_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ #define LL_DMAMUX_REQ_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ #define LL_DMAMUX_REQ_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ #define LL_DMAMUX_REQ_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ #define LL_DMAMUX_REQ_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ #define LL_DMAMUX_REQ_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ + #define LL_DMAMUX_REQ_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ #define LL_DMAMUX_REQ_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ #define LL_DMAMUX_REQ_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ #define LL_DMAMUX_REQ_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ #define LL_DMAMUX_REQ_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ + #define LL_DMAMUX_REQ_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ #define LL_DMAMUX_REQ_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ #define LL_DMAMUX_REQ_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ @@ -222,18 +223,24 @@ extern "C" { #define LL_DMAMUX_REQ_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ #define LL_DMAMUX_REQ_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ #define LL_DMAMUX_REQ_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ + #define LL_DMAMUX_REQ_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ #define LL_DMAMUX_REQ_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ #define LL_DMAMUX_REQ_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ #define LL_DMAMUX_REQ_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ + #define LL_DMAMUX_REQ_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ #define LL_DMAMUX_REQ_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ #define LL_DMAMUX_REQ_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ #define LL_DMAMUX_REQ_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ + #define LL_DMAMUX_REQ_DCMI 90U /*!< DMAMUX DCMI request */ -#define LL_DMAMUX_REQ_AES_IN 91U /*!< DMAMUX AES_IN request */ + +#define LL_DMAMUX_REQ_AES_IN 91U /*!< DMAMUX AES_IN request */ #define LL_DMAMUX_REQ_AES_OUT 92U /*!< DMAMUX AES_OUT request */ + #define LL_DMAMUX_REQ_HASH_IN 93U /*!< DMAMUX HASH_IN request */ + /** * @} */ @@ -241,16 +248,16 @@ extern "C" { /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel * @{ */ -#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ -#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ -#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ -#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ -#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ -#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ -#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ -#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ -#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ -#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ @@ -273,32 +280,32 @@ extern "C" { /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event * @{ */ -#define LL_DMAMUX_SYNC_EXTI_LINE0 0U /*!< Synchronization signal from EXTI Line0 */ -#define LL_DMAMUX_SYNC_EXTI_LINE1 1U /*!< Synchronization signal from EXTI Line1 */ -#define LL_DMAMUX_SYNC_EXTI_LINE2 2U /*!< Synchronization signal from EXTI Line2 */ -#define LL_DMAMUX_SYNC_EXTI_LINE3 3U /*!< Synchronization signal from EXTI Line3 */ -#define LL_DMAMUX_SYNC_EXTI_LINE4 4U /*!< Synchronization signal from EXTI Line4 */ -#define LL_DMAMUX_SYNC_EXTI_LINE5 5U /*!< Synchronization signal from EXTI Line5 */ -#define LL_DMAMUX_SYNC_EXTI_LINE6 6U /*!< Synchronization signal from EXTI Line6 */ -#define LL_DMAMUX_SYNC_EXTI_LINE7 7U /*!< Synchronization signal from EXTI Line7 */ -#define LL_DMAMUX_SYNC_EXTI_LINE8 8U /*!< Synchronization signal from EXTI Line8 */ -#define LL_DMAMUX_SYNC_EXTI_LINE9 9U /*!< Synchronization signal from EXTI Line9 */ -#define LL_DMAMUX_SYNC_EXTI_LINE10 10U /*!< Synchronization signal from EXTI Line10 */ -#define LL_DMAMUX_SYNC_EXTI_LINE11 11U /*!< Synchronization signal from EXTI Line11 */ -#define LL_DMAMUX_SYNC_EXTI_LINE12 12U /*!< Synchronization signal from EXTI Line12 */ -#define LL_DMAMUX_SYNC_EXTI_LINE13 13U /*!< Synchronization signal from EXTI Line13 */ -#define LL_DMAMUX_SYNC_EXTI_LINE14 14U /*!< Synchronization signal from EXTI Line14 */ -#define LL_DMAMUX_SYNC_EXTI_LINE15 15U /*!< Synchronization signal from EXTI Line15 */ -#define LL_DMAMUX_SYNC_DMAMUX_CH0 16U /*!< Synchronization signal from DMAMUX channel0 Event */ -#define LL_DMAMUX_SYNC_DMAMUX_CH1 17U /*!< Synchronization signal from DMAMUX channel1 Event */ -#define LL_DMAMUX_SYNC_DMAMUX_CH2 18U /*!< Synchronization signal from DMAMUX channel2 Event */ -#define LL_DMAMUX_SYNC_DMAMUX_CH3 19U /*!< Synchronization signal from DMAMUX channel3 Event */ -#define LL_DMAMUX_SYNC_LPTIM1_OUT 20U /*!< Synchronization signal from LPTIM1 Ouput */ -#define LL_DMAMUX_SYNC_LPTIM2_OUT 21U /*!< Synchronization signal from LPTIM2 Ouput */ -#define LL_DMAMUX_SYNC_DSI_TE 22U /*!< Synchronization signal from DSI Tearing Effect */ -#define LL_DMAMUX_SYNC_DSI_REFRESH_END 23U /*!< Synchronization signal from DSI End of Refresh */ -#define LL_DMAMUX_SYNC_DMA2D_TX_END 24U /*!< Synchronization signal from DMA2D End of Transfer */ -#define LL_DMAMUX_SYNC_LTDC_LINE_IT 25U /*!< Synchronization signal from LTDC Line Interrupt */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Ouput */ +#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Ouput */ +#define LL_DMAMUX_SYNC_DSI_TE (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DSI Tearing Effect */ +#define LL_DMAMUX_SYNC_DSI_REFRESH_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DSI End of Refresh */ +#define LL_DMAMUX_SYNC_DMA2D_TX_END (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3) /*!< Synchronization signal from DMA2D End of Transfer */ +#define LL_DMAMUX_SYNC_LTDC_LINE_IT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LTDC Line Interrupt */ /** * @} */ @@ -306,10 +313,10 @@ extern "C" { /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel * @{ */ -#define LL_DMAMUX_REQ_GEN_0 0x00000000U -#define LL_DMAMUX_REQ_GEN_1 0x00000001U -#define LL_DMAMUX_REQ_GEN_2 0x00000002U -#define LL_DMAMUX_REQ_GEN_3 0x00000003U +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U /** * @} */ @@ -328,32 +335,32 @@ extern "C" { /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation * @{ */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0U /*!< Request signal generation from EXTI Line0 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 1U /*!< Request signal generation from EXTI Line1 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 2U /*!< Request signal generation from EXTI Line2 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 3U /*!< Request signal generation from EXTI Line3 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 4U /*!< Request signal generation from EXTI Line4 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 5U /*!< Request signal generation from EXTI Line5 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 6U /*!< Request signal generation from EXTI Line6 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 7U /*!< Request signal generation from EXTI Line7 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 8U /*!< Request signal generation from EXTI Line8 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 9U /*!< Request signal generation from EXTI Line9 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 10U /*!< Request signal generation from EXTI Line10 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 11U /*!< Request signal generation from EXTI Line11 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 12U /*!< Request signal generation from EXTI Line12 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 13U /*!< Request signal generation from EXTI Line13 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 14U /*!< Request signal generation from EXTI Line14 */ -#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 15U /*!< Request signal generation from EXTI Line15 */ -#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 16U /*!< Request signal generation from DMAMUX channel0 Event */ -#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 17U /*!< Request signal generation from DMAMUX channel1 Event */ -#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 18U /*!< Request signal generation from DMAMUX channel2 Event */ -#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 19U /*!< Request signal generation from DMAMUX channel3 Event */ -#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT 20U /*!< Request signal generation from LPTIM1 Ouput */ -#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT 21U /*!< Request signal generation from LPTIM2 Ouput */ -#define LL_DMAMUX_REQ_GEN_DSI_TE 22U /*!< Request signal generation from DSI Tearing Effect */ -#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END 23U /*!< Request signal generation from DSI End of Refresh */ -#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END 24U /*!< Request signal generation from DMA2D End of Transfer */ -#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT 25U /*!< Request signal generation from LTDC Line Interrupt */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Ouput */ +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Ouput */ +#define LL_DMAMUX_REQ_GEN_DSI_TE (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DSI Tearing Effect */ +#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DSI End of Refresh */ +#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3) /*!< Request signal generation from DMA2D End of Transfer */ +#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LTDC Line Interrupt */ /** * @} */ @@ -522,7 +529,8 @@ extern "C" { */ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); } /** @@ -644,7 +652,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel-1)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); } /** @@ -671,7 +680,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ, RequestNb - 1); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); } /** @@ -697,7 +707,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ) + 1); + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); } /** @@ -728,7 +739,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL, Polarity); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); } /** @@ -758,7 +770,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); } /** @@ -784,7 +797,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); } /** @@ -810,7 +824,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); } /** @@ -836,7 +851,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); } /** @@ -862,7 +878,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD */ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); } /** @@ -888,7 +905,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 */ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); } /** @@ -914,7 +932,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); } /** @@ -967,7 +986,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { - MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); } /** @@ -1019,7 +1039,8 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 */ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); } /** @@ -1035,7 +1056,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -1051,7 +1073,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -1067,7 +1090,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)); + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); } /** @@ -1088,7 +1112,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D */ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); } /** @@ -1108,7 +1133,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); } /** @@ -1126,7 +1152,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef */ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1) << DMAMUX_RGxCR_GNBREQ_Pos); + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); } /** @@ -1142,7 +1169,8 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, */ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1); + (void)(DMAMUXx); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); } /** @@ -1185,7 +1213,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU */ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { - MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); } /** @@ -1227,7 +1256,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX */ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); } /** @@ -1246,7 +1276,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); } /** @@ -1257,7 +1288,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); } /** @@ -1268,7 +1300,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); } /** @@ -1279,7 +1312,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); } /** @@ -1290,7 +1324,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); } /** @@ -1301,7 +1336,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); } /** @@ -1312,7 +1348,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); } /** @@ -1323,7 +1360,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); } /** @@ -1334,7 +1372,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); } /** @@ -1345,7 +1384,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); } /** @@ -1356,7 +1396,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); } /** @@ -1367,7 +1408,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); } /** @@ -1378,7 +1420,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); } /** @@ -1389,7 +1432,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); } /** @@ -1400,7 +1444,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); } /** @@ -1411,7 +1456,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); } /** @@ -1422,7 +1468,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); } /** @@ -1433,7 +1480,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { - return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)); + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); } /** @@ -1444,6 +1492,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); } @@ -1455,6 +1504,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); } @@ -1466,6 +1516,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); } @@ -1477,6 +1528,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); } @@ -1488,6 +1540,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); } @@ -1499,6 +1552,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); } @@ -1510,6 +1564,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); } @@ -1521,6 +1576,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); } @@ -1532,6 +1588,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); } @@ -1543,6 +1600,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); } @@ -1554,6 +1612,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); } @@ -1565,6 +1624,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); } @@ -1576,6 +1636,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); } @@ -1587,6 +1648,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); } @@ -1598,6 +1660,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); } @@ -1609,6 +1672,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); } @@ -1620,6 +1684,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); } @@ -1631,6 +1696,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) { + (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); } @@ -1665,7 +1731,8 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) */ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1691,7 +1758,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint */ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); } /** @@ -1717,7 +1785,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { - return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE)); + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); } /** @@ -1733,7 +1802,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX */ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); } /** @@ -1749,7 +1819,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin */ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); } /** @@ -1765,7 +1836,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui */ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { - return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)); + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); } /** @@ -1790,6 +1862,6 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMU } #endif -#endif /* __STM32L4xx_LL_DMAMUX_H */ +#endif /* STM32L4xx_LL_DMAMUX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c index c97b41c126..5c52247842 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -91,8 +75,7 @@ /** * @brief De-initialize the EXTI registers to their default reset values. * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are de-initialized - * - ERROR: not applicable + * - 0x00: EXTI registers are de-initialized */ uint32_t LL_EXTI_DeInit(void) { @@ -126,19 +109,20 @@ uint32_t LL_EXTI_DeInit(void) /* Pending register 2 clear */ LL_EXTI_WriteReg(PR2, 0x00000078U); - return SUCCESS; + return 0x00u; } /** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are initialized - * - ERROR: not applicable + * - 0x00: EXTI registers are initialized + * - any other calue : wrong configuration */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) { - ErrorStatus status = SUCCESS; + uint32_t status = 0x00u; + /* Check the parameters */ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); @@ -173,7 +157,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); break; default: - status = ERROR; + status = 0x01u; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) @@ -197,7 +181,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); break; default: - status = ERROR; + status |= 0x02u; break; } } @@ -225,7 +209,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); break; default: - status = ERROR; + status |= 0x04u; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) @@ -265,6 +249,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); } + return status; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h index 9127ab2f91..245f7fdbd5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -200,6 +184,8 @@ typedef struct /** * @} */ + + #if defined(USE_FULL_LL_DRIVER) /** @defgroup EXTI_LL_EC_MODE Mode @@ -464,7 +450,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -489,7 +475,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -677,7 +663,7 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } @@ -700,7 +686,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -878,7 +864,7 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -893,7 +879,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1068,7 +1054,7 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1083,7 +1069,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1200,7 +1186,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) { - return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1217,7 +1203,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) { - return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)); + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } /** @@ -1259,7 +1245,6 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); } - /** * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 * @note This bit is set when the selected edge event arrives on the interrupt @@ -1333,6 +1318,7 @@ __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) WRITE_REG(EXTI->PR2, ExtiLine); } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c index c052ded246..349104f896 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c @@ -11,27 +11,28 @@ * + Peripheral State functions * @verbatim - ============================================================================= + ============================================================================== ##### FMC peripheral features ##### - ============================================================================= + ============================================================================== [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller (+) The NAND memory controller [..] The FMC functional block makes the interface with synchronous and asynchronous static memories. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol. - (+) to meet the access time requirements of the external memory devices. + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices [..] All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device. The main features of the FMC controller are the following: (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM). - (++) NOR Flash memory. - (++) PSRAM (4 memory banks). - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of data (+) Independent Chip Select control for each memory bank (+) Independent configuration for each memory bank @@ -40,29 +41,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -74,8 +59,6 @@ * @{ */ -#if defined(FMC_BANK1) - #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer @@ -85,31 +68,18 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants * @{ */ /* ----------------------- FMC registers bit mask --------------------------- */ -/* --- PCR Register ---*/ -/* PCR register clear mask */ -#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ - FMC_PCR_PTYP | FMC_PCR_PWID | \ - FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)) - -/* --- PMEM Register ---*/ -/* PMEM register clear mask */ -#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ - FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) - -/* --- PATT Register ---*/ -/* PATT register clear mask */ -#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ - FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) +#if defined(FMC_BANK1) /* --- BCR Register ---*/ /* BCR register clear mask */ #if defined(FMC_BCRx_NBLSET) +#if defined(FMC_BCR1_WFDIS) #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ FMC_BCRx_MTYP | FMC_BCRx_MWID |\ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ @@ -119,7 +89,18 @@ FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS |\ FMC_BCRx_NBLSET)) -#elif defined(FMC_BCR1_WFDIS) +#else +#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ + FMC_BCRx_MTYP | FMC_BCRx_MWID |\ + FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ + FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ + FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ + FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ + FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ + FMC_BCR1_CCLKEN | FMC_BCRx_NBLSET)) +#endif /* FMC_BCR1_WFDIS */ +#else +#if defined(FMC_BCR1_WFDIS) #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ FMC_BCRx_MTYP | FMC_BCRx_MWID |\ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ @@ -138,6 +119,7 @@ FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ FMC_BCR1_CCLKEN)) #endif /* FMC_BCR1_WFDIS */ +#endif /* FMC_BCRx_NBLSET */ /* --- BTR Register ---*/ /* BTR register clear mask */ @@ -164,20 +146,33 @@ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ FMC_BWTRx_ACCMOD)) #endif /* FMC_BWTRx_DATAHLD */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) + +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PTYP | FMC_PCR_PWID | \ + FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)) + +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ + FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ + FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) + +#endif /* FMC_BANK3 */ /** * @} */ /* Private macro -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros - * @{ - */ - -/** - * @} - */ - /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -186,7 +181,9 @@ * @{ */ -/** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions +#if defined(FMC_BANK1) + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions * @brief NORSRAM Controller functions * @verbatim @@ -206,12 +203,11 @@ (+) FMC NORSRAM bank enable/disable write operation using the functions FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - @endverbatim * @{ */ -/** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -237,6 +233,8 @@ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) { + uint32_t flashaccess; + /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); @@ -255,10 +253,10 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); #endif /* FMC_BCR1_WFDIS */ -#if defined(FMC_BCRx_NBLSET) - assert_param(IS_FMC_NBLSETUP_TIME(Init->NBLSetupTime)); -#endif /* FMC_BCRx_NBLSET */ assert_param(IS_FMC_PAGESIZE(Init->PageSize)); +#if defined(FMC_BCRx_NBLSET) + assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); +#endif /* FMC_BCRx_NBLSET */ /* Disable NORSRAM Device */ __FMC_NORSRAM_DISABLE(Device, Init->NSBank); @@ -266,54 +264,33 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /* Set NORSRAM device control parameters */ if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) { - MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE - | Init->DataAddressMux - | Init->MemoryType - | Init->MemoryDataWidth - | Init->BurstAccessMode - | Init->WaitSignalPolarity - | Init->WaitSignalActive - | Init->WriteOperation - | Init->WaitSignal - | Init->ExtendedMode - | Init->AsynchronousWait - | Init->WriteBurst - | Init->ContinuousClock -#if defined(FMC_BCR1_WFDIS) - | Init->WriteFifo -#endif /* FMC_BCR1_WFDIS */ -#if defined(FMC_BCRx_NBLSET) - | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) -#endif /* FMC_BCRx_NBLSET */ - | Init->PageSize - ) - ); + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; } else { - MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE - | Init->DataAddressMux - | Init->MemoryType - | Init->MemoryDataWidth - | Init->BurstAccessMode - | Init->WaitSignalPolarity - | Init->WaitSignalActive - | Init->WriteOperation - | Init->WaitSignal - | Init->ExtendedMode - | Init->AsynchronousWait - | Init->WriteBurst - | Init->ContinuousClock + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (flashaccess | + Init->DataAddressMux | + Init->MemoryType | + Init->MemoryDataWidth | + Init->BurstAccessMode | + Init->WaitSignalPolarity | + Init->WaitSignalActive | + Init->WriteOperation | + Init->WaitSignal | + Init->ExtendedMode | + Init->AsynchronousWait | + Init->WriteBurst | + Init->ContinuousClock | #if defined(FMC_BCR1_WFDIS) - | Init->WriteFifo + Init->WriteFifo | #endif /* FMC_BCR1_WFDIS */ #if defined(FMC_BCRx_NBLSET) - | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) + Init->NBLSetupTime | #endif /* FMC_BCRx_NBLSET */ - | Init->PageSize - ) - ); - } + Init->PageSize)); /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) @@ -354,16 +331,16 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX /* FMC_NORSRAM_BANK1 */ if (Bank == FMC_NORSRAM_BANK1) { - Device->BTCR[Bank] = 0x000030DB; + Device->BTCR[Bank] = 0x000030DBU; } /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ else { - Device->BTCR[Bank] = 0x000030D2; + Device->BTCR[Bank] = 0x000030D2U; } - Device->BTCR[Bank + 1] = 0x0FFFFFFF; - ExDevice->BWTR[Bank] = 0x0FFFFFFF; + Device->BTCR[Bank + 1] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; return HAL_OK; } @@ -385,10 +362,10 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); #if defined(FMC_BTRx_DATAHLD) - assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); + assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); #endif /* FMC_BTRx_DATAHLD */ + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); @@ -396,24 +373,22 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1], - BTR_CLEAR_MASK, - (uint32_t)(Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | + MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | #if defined(FMC_BTRx_DATAHLD) - ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | + ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | #endif /* FMC_BTRx_DATAHLD */ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | - (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | - (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | + ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2) << FMC_BTRx_DATLAT_Pos) | (Timing->AccessMode))); /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV))); - tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr); } @@ -444,41 +419,36 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); -#if defined(FMC_BTRx_DATAHLD) - assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); -#endif /* FMC_BTRx_DATAHLD */ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); +#if defined(FMC_BTRx_DATAHLD) + assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); +#endif /* FMC_BTRx_DATAHLD */ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - MODIFY_REG(Device->BWTR[Bank], - BWTR_CLEAR_MASK, - (uint32_t)(Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | #if defined(FMC_BTRx_DATAHLD) - ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | + ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | #endif /* FMC_BTRx_DATAHLD */ - Timing->AccessMode | - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BWTRx_BUSTURN)))); + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); } else { - Device->BWTR[Bank] = 0x0FFFFFFF; + Device->BWTR[Bank] = 0x0FFFFFFFU; } return HAL_OK; } - - /** * @} */ - -/** @defgroup FMC_NORSRAM_Group2 Control functions +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 * @brief management functions * @verbatim @@ -536,7 +506,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @} */ -/** @defgroup FMC_NAND FMC NAND Controller functions +#endif /* FMC_BANK1 */ + +#if defined(FMC_BANK3) + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions * @brief NAND Controller functions * @verbatim @@ -561,7 +535,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @{ */ -/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -597,17 +571,16 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | - FMC_PCR_MEMORY_TYPE_NAND | - Init->MemoryDataWidth | - Init->EccComputation | - Init->ECCPageSize | - ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCR_TCLR)) | - ((Init->TARSetupTime) << POSITION_VAL(FMC_PCR_TAR)))); + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); return HAL_OK; - } /** @@ -626,13 +599,15 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) | - ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) | - ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); return HAL_OK; } @@ -653,20 +628,21 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATT_ATTWAIT)) | - ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATT_ATTHOLD)) | - ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATT_ATTHIZ)))); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); return HAL_OK; } - /** - * @brief DeInitialize the FMC_NAND device + * @brief DeInitializes the FMC_NAND device * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status @@ -675,17 +651,19 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device, Bank); + __FMC_NAND_DISABLE(Device); /* De-initialize the NAND Bank */ - /* Set the FMC_NAND_BANK3 registers to their reset values */ - WRITE_REG(Device->PCR, 0x00000018); - WRITE_REG(Device->SR, 0x00000040); - WRITE_REG(Device->PMEM, 0xFCFCFCFC); - WRITE_REG(Device->PATT, 0xFCFCFCFC); + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018); + WRITE_REG(Device->SR, 0x00000040); + WRITE_REG(Device->PMEM, 0xFCFCFCFC); + WRITE_REG(Device->PATT, 0xFCFCFCFC); return HAL_OK; } @@ -694,8 +672,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) * @} */ - -/** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions * @brief management functions * @verbatim @@ -721,10 +698,12 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Enable ECC feature */ - SET_BIT(Device->PCR, FMC_PCR_ECCEN); + SET_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; } @@ -740,10 +719,12 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Disable ECC feature */ - CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; } @@ -762,7 +743,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); /* Get tick */ tickstart = HAL_GetTick(); @@ -780,8 +763,8 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui } } - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; return HAL_OK; } @@ -789,10 +772,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @} */ +#endif /* FMC_BANK3 */ + -/** - * @} - */ /** * @} @@ -803,9 +785,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */ - -#endif /* FMC_BANK1 */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h index e22ecd214d..17d4c66e4a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -48,8 +32,6 @@ extern "C" { * @{ */ -#if defined(FMC_BANK1) - /** @addtogroup FMC_LL * @{ */ @@ -57,215 +39,94 @@ extern "C" { /** @addtogroup FMC_LL_Private_Macros * @{ */ +#if defined(FMC_BANK1) -#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ - ((__BANK__) == FMC_NORSRAM_BANK2) || \ - ((__BANK__) == FMC_NORSRAM_BANK3) || \ - ((__BANK__) == FMC_NORSRAM_BANK4)) - -#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) - -#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ - ((__SIZE__) == FMC_PAGE_SIZE_128) || \ - ((__SIZE__) == FMC_PAGE_SIZE_256) || \ - ((__SIZE__) == FMC_PAGE_SIZE_512) || \ - ((__SIZE__) == FMC_PAGE_SIZE_1024)) - -#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) #if defined(FMC_BCR1_WFDIS) -#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ - ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) #endif /* FMC_BCR1_WFDIS */ - +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) #if defined(FMC_BCRx_NBLSET) -#define IS_FMC_NBLSETUP_TIME(__TIME__) ((__TIME__) <= 3) +#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_3)) #endif /* FMC_BCRx_NBLSET */ - -#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) - -#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) - -#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) - -#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) - -#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ - ((__STATE__) == FMC_NAND_ECC_ENABLE)) - -#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time - * @{ - */ -#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time - * @{ - */ -#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Setup_Time FMC_Setup_Time - * @{ - */ -#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time - * @{ - */ -#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time - * @{ - */ -#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time - * @{ - */ -#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance - * @{ - */ - -#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) - -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance - * @{ - */ - +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) +#if defined(FMC_BTRx_DATAHLD) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3) +#endif /* FMC_BTRx_DATAHLD */ +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) -/** - * @} - */ +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) -/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance - * @{ - */ -#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) -/** - * @} - */ +#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) +#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) -#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) - -#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) - -#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) - -#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) - -/** @defgroup FMC_Data_Latency FMC Data Latency - * @{ - */ -#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) -/** - * @} - */ - -/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time - * @{ - */ -#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time - * @{ - */ -#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) -/** - * @} - */ - -/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time - * @{ - */ -#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) -/** - * @} - */ - -#if defined(FMC_BTRx_DATAHLD) -/** @defgroup FMC_Data_Hold_Time - * @{ - */ -#define IS_FMC_DATAHOLD_TIME(__TIME__) ((__TIME__) <= 3) -/** - * @} - */ -#endif /* FMC_BTRx_DATAHLD */ - -/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration - * @{ - */ -#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ +#endif /* FMC_BANK3 */ /** * @} @@ -273,20 +134,29 @@ extern "C" { /* Exported typedef ----------------------------------------------------------*/ -/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types * @{ */ -#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef -#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef -#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#if defined(FMC_BANK1) +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#endif /* FMC_BANK3 */ -#define FMC_NORSRAM_DEVICE FMC_Bank1_R -#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R -#define FMC_NAND_DEVICE FMC_Bank3_R +#if defined(FMC_BANK1) +#define FMC_NORSRAM_DEVICE FMC_Bank1_R +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) +#define FMC_NAND_DEVICE FMC_Bank3_R +#endif /* FMC_BANK3 */ +#if defined(FMC_BANK1) /** - * @brief FMC_NORSRAM Configuration Structure definition + * @brief FMC NORSRAM Configuration Structure definition */ typedef struct { @@ -345,19 +215,18 @@ typedef struct This parameter can be a value of @ref FMC_Write_FIFO. @note This Parameter is not available for STM32L47x/L48x devices. */ -#if defined(FMC_BCRx_NBLSET) - uint32_t NBLSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the byte lane (NBL) setup time from NBLx low to Chip select NEx low. - This parameter can be a value between Min_Data = 0 and Max_Data = 3. - @note This parameter is used for SRAMs, ROMs and NOR Flash memories. */ -#endif /* FMC_BCRx_NBLSET */ - uint32_t PageSize; /*!< Specifies the memory page size. This parameter can be a value of @ref FMC_Page_Size */ + +#if defined(FMC_BCRx_NBLSET) + uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number + This parameter can be a value of @ref FMC_Byte_Lane */ +#endif /* FMC_BCRx_NBLSET */ + }FMC_NORSRAM_InitTypeDef; /** - * @brief FMC_NORSRAM Timing parameters structure definition + * @brief FMC NORSRAM Timing parameters structure definition */ typedef struct { @@ -381,10 +250,7 @@ typedef struct uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the data hold time. This parameter can be a value between Min_Data = 0 and Max_Data = 3. - @note This parameter value corresponds to x HCLK cycles for read and - x+1 HCLK cycles for write. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + @note This parameter is used for used in asynchronous accesses. */ #endif /* FMC_BTRx_DATAHLD */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure @@ -407,11 +273,12 @@ typedef struct uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FMC_Access_Mode */ - }FMC_NORSRAM_TimingTypeDef; +#endif /* FMC_BANK1 */ +#if defined(FMC_BANK3) /** - * @brief FMC_NAND Configuration Structure definition + * @brief FMC NAND Configuration Structure definition */ typedef struct { @@ -437,11 +304,10 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - }FMC_NAND_InitTypeDef; /** - * @brief FMC_NAND Timing parameters structure definition + * @brief FMC NAND Timing parameters structure definition */ typedef struct { @@ -449,51 +315,50 @@ typedef struct the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ }FMC_NAND_PCC_TimingTypeDef; +#endif /* FMC_BANK3 */ /** * @} */ /* Exported constants --------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants * @{ */ +#if defined(FMC_BANK1) -/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller * @{ */ /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) - +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) /** * @} */ @@ -501,10 +366,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ - -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) - /** * @} */ @@ -512,11 +375,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ - -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) - /** * @} */ @@ -524,11 +385,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width * @{ */ - -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) - /** * @} */ @@ -536,9 +395,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ - #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) /** * @} */ @@ -546,26 +404,17 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ - -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) - /** * @} */ - /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ - -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) - -/** - * @} - */ - /** * @} */ @@ -573,10 +422,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ - -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) - /** * @} */ @@ -584,10 +431,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ - -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) - /** * @} */ @@ -595,10 +440,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ - -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) - /** * @} */ @@ -606,10 +449,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ - -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) - /** * @} */ @@ -617,10 +458,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ - -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) - /** * @} */ @@ -628,7 +467,7 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) @@ -640,18 +479,16 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ - -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) - /** * @} */ -/** @defgroup FMC_Continous_Clock FMC Continous Clock +/** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) /** * @} @@ -662,17 +499,16 @@ typedef struct * @{ */ #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) +#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) /** * @} */ - #endif /* FMC_BCR1_WFDIS */ + /** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ - -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) @@ -680,20 +516,33 @@ typedef struct /** * @} */ +#if defined(FMC_BCRx_NBLSET) +/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup + * @{ + */ +#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) +#define FMC_NBL_SETUPTIME_1 ((uint32_t)FMC_BCRx_NBLSET_0) +#define FMC_NBL_SETUPTIME_2 ((uint32_t)FMC_BCRx_NBLSET_1) +#define FMC_NBL_SETUPTIME_3 ((uint32_t)(FMC_BCRx_NBLSET_0 | FMC_BCRx_NBLSET_1)) +/** + * @} + */ +#endif /* FMC_BCRx_NBLSET */ /** * @} */ +#endif /* FMC_BANK1 */ -/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller +#if defined(FMC_BANK3) + +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller * @{ */ - /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100) - +#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) /** * @} */ @@ -701,9 +550,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) - /** * @} */ @@ -711,7 +559,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) +#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) /** * @} */ @@ -719,19 +567,17 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) - /** * @} */ -/** @defgroup FMC_ECC FMC NAND ECC +/** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) - /** * @} */ @@ -739,38 +585,46 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) - /** * @} */ -/** @defgroup FMC_Interrupt_definition FMC Interrupt definition - * @brief FMC Interrupt definition +/** + * @} + */ +#endif /* FMC_BANK3 */ + + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ +#if defined(FMC_BANK3) #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) - +#endif /* FMC_BANK3 */ /** * @} */ -/** @defgroup FMC_Flag_definition FMC Flag definition - * @brief FMC Flag definition +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ +#if defined(FMC_BANK3) #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) - +#endif /* FMC_BANK3 */ +/** + * @} + */ /** * @} */ @@ -779,17 +633,13 @@ typedef struct * @} */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros * @{ */ -/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros +#if defined(FMC_BANK1) +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros * @brief macros to handle NOR device enable/disable and read/write operations * @{ */ @@ -798,23 +648,25 @@ typedef struct * @brief Enable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance * @param __BANK__ FMC_NORSRAM Bank - * @retval none + * @retval None */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance * @param __BANK__ FMC_NORSRAM Bank - * @retval none + * @retval None */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) /** * @} */ +#endif /* FMC_BANK1 */ -/** @defgroup FMC_NAND_Macros FMC NAND Macros +#if defined(FMC_BANK3) +/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros * @brief macros to handle NAND device enable/disable * @{ */ @@ -822,32 +674,29 @@ typedef struct /** * @brief Enable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) /** * @brief Disable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) /** * @} */ -/** @defgroup FMC_Interrupt FMC Interrupt - * @brief macros to handle FMC interrupts +/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @brief macros to handle NAND interrupts * @{ */ /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __INSTANCE__ FMC_NAND instance * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE Interrupt rising edge. @@ -855,12 +704,11 @@ typedef struct * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. * @retval None */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) /** * @brief Disable the NAND device interrupt. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE Interrupt rising edge. @@ -868,7 +716,7 @@ typedef struct * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. * @retval None */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) /** * @brief Get flag status of the NAND device. @@ -887,7 +735,6 @@ typedef struct /** * @brief Clear flag status of the NAND device. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. @@ -896,85 +743,84 @@ typedef struct * @arg FMC_FLAG_FEMPT FIFO empty flag. * @retval None */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) + +/** + * @} + */ +#endif /* FMC_BANK3 */ /** * @} */ - /** * @} */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup FMC_LL_Exported_Functions +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions * @{ */ -/** @addtogroup FMC_NORSRAM +#if defined(FMC_BANK1) +/** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ - -/** @addtogroup FMC_NORSRAM_Group1 +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ - -/* FMC_NORSRAM Controller functions ******************************************/ -/* Initialization/de-initialization functions */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); - /** * @} */ -/** @addtogroup FMC_NORSRAM_Group2 +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions * @{ */ - -/* FMC_NORSRAM Control functions */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); - /** * @} */ - /** * @} */ +#endif /* FMC_BANK1 */ -/** @addtogroup FMC_NAND +#if defined(FMC_BANK3) +/** @defgroup FMC_LL_NAND NAND * @{ */ - -/* FMC_NAND Controller functions **********************************************/ -/* Initialization/de-initialization functions */ -/** @addtogroup FMC_NAND_Exported_Functions_Group1 +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ - HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); - /** * @} */ -/* FMC_NAND Control functions */ -/** @addtogroup FMC_NAND_Exported_Functions_Group2 +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions * @{ */ - HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +/** + * @} + */ +/** + * @} + */ +#endif /* FMC_BANK3 */ + + /** * @} @@ -984,16 +830,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @} */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* FMC_BANK1 */ - /** * @} */ @@ -1005,4 +841,3 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u #endif /* __STM32L4xx_LL_FMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c index 0bd742a8d2..b1aef8dedf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -52,6 +36,11 @@ /** @addtogroup GPIO_LL * @{ */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -60,7 +49,7 @@ /** @addtogroup GPIO_LL_Private_Macros * @{ */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ @@ -193,7 +182,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -201,8 +190,8 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) */ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) { - uint32_t pinpos = 0x00000000U; - uint32_t currentpin = 0x00000000U; + uint32_t pinpos; + uint32_t currentpin; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -215,12 +204,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru pinpos = POSITION_VAL(GPIO_InitStruct->Pin); /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) { /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); - if (currentpin) + if (currentpin != 0x00u) { /* Pin Mode configuration */ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); @@ -243,7 +232,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); /* Speed mode configuration */ - if (POSITION_VAL(currentpin) < 0x00000008U) + if (currentpin < LL_GPIO_PIN_8) { LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); } @@ -270,7 +259,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h index ae61d32827..f1fc7fd796 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -53,6 +37,14 @@ extern "C" { /** @defgroup GPIO_LL GPIO * @{ */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -793,6 +785,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); WRITE_REG(GPIOx->LCKR, PinMask); WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ temp = READ_REG(GPIOx->LCKR); (void) temp; } @@ -823,7 +816,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) */ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } /** @@ -834,7 +827,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa */ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) { - return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } /** @@ -882,7 +875,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) */ __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } /** @@ -934,7 +927,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) */ __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c index 8d8105b0de..2dbdc97778 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -100,7 +84,7 @@ * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ -uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; @@ -160,7 +144,7 @@ uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) * - SUCCESS: I2C registers are initialized * - ERROR: Not applicable */ -uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) { /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h index 564210d489..f5f2350f48 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_I2C_H -#define __STM32L4xx_LL_I2C_H +#ifndef STM32L4xx_LL_I2C_H +#define STM32L4xx_LL_I2C_H #ifdef __cplusplus extern "C" { @@ -431,7 +415,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } /** @@ -513,7 +497,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } /** @@ -546,7 +530,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } /** @@ -579,7 +563,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } /** @@ -594,7 +578,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) { - register uint32_t data_reg_addr = 0U; + register uint32_t data_reg_addr; if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { @@ -642,7 +626,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } /** @@ -675,7 +659,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } /** @@ -715,7 +699,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } /** @@ -750,7 +734,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } /** @@ -827,7 +811,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)); + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } /** @@ -883,7 +867,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)); + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } /** @@ -1038,7 +1022,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } /** @@ -1077,7 +1061,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } /** @@ -1097,7 +1081,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) + uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); @@ -1242,7 +1226,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { - return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)); + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1283,7 +1267,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } /** @@ -1316,7 +1300,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } /** @@ -1349,7 +1333,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } /** @@ -1382,7 +1366,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } /** @@ -1415,7 +1399,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } /** @@ -1454,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } /** @@ -1505,7 +1489,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)); + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } /** @@ -1526,7 +1510,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } /** @@ -1539,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } /** @@ -1552,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } /** @@ -1565,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } /** @@ -1578,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } /** @@ -1591,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } /** @@ -1604,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } /** @@ -1617,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } /** @@ -1630,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } /** @@ -1643,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } /** @@ -1656,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } /** @@ -1671,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } /** @@ -1686,7 +1670,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } /** @@ -1702,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } /** @@ -1715,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)); + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } /** @@ -1876,7 +1860,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } /** @@ -1911,7 +1895,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } /** @@ -2010,7 +1994,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } /** @@ -2104,11 +2088,11 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); + SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } /** @@ -2163,7 +2147,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) { - return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)); + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } /** @@ -2211,8 +2195,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) * @{ */ -uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); @@ -2239,6 +2223,6 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); } #endif -#endif /* __STM32L4xx_LL_I2C_H */ +#endif /* STM32L4xx_LL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h index 0ab5630db2..bac7d56506 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_IWDG_H -#define __STM32L4xx_LL_IWDG_H +#ifndef STM32L4xx_LL_IWDG_H +#define STM32L4xx_LL_IWDG_H #ifdef __cplusplus extern "C" { @@ -61,12 +45,10 @@ extern "C" { /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants * @{ */ - #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ - /** * @} */ @@ -86,7 +68,6 @@ extern "C" { #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ #define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ - /** * @} */ @@ -160,7 +141,7 @@ extern "C" { */ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); } /** @@ -171,7 +152,7 @@ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); } /** @@ -182,7 +163,7 @@ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); } /** @@ -193,7 +174,7 @@ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); } /** @@ -230,7 +211,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale */ __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->PR)); + return (READ_REG(IWDGx->PR)); } /** @@ -253,7 +234,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun */ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->RLR)); + return (READ_REG(IWDGx->RLR)); } /** @@ -276,7 +257,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) */ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->WINR)); + return (READ_REG(IWDGx->WINR)); } /** @@ -295,7 +276,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } /** @@ -306,7 +287,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); + return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } /** @@ -317,7 +298,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)); + return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } /** @@ -330,7 +311,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U); + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } /** @@ -346,7 +327,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ -#endif /* IWDG) */ +#endif /* IWDG */ /** * @} @@ -356,6 +337,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) } #endif -#endif /* __STM32L4xx_LL_IWDG_H */ +#endif /* STM32L4xx_LL_IWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c index c776c5c67c..f25942f013 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -37,11 +21,13 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_lptim.h" #include "stm32l4xx_ll_bus.h" +#include "stm32l4xx_ll_rcc.h" + #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32L4xx_LL_Driver @@ -84,6 +70,13 @@ /* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup LPTIM_LL_Exported_Functions * @{ @@ -100,30 +93,30 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) +ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + if (LPTIMx == LPTIM1) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); - } + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); + } #if defined(LPTIM2) else if (LPTIMx == LPTIM2) - { + { LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); } -#endif +#endif /* LPTIM2 */ else { result = ERROR; } - + return result; } @@ -133,7 +126,7 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure * @retval None */ -void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { /* Set the default configuration */ LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; @@ -152,36 +145,35 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; - - /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + + /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit is reset to 0). */ - if (LL_LPTIM_IsEnabled(LPTIMx)) + if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL) { result = ERROR; } else { - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); - assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); - assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); - assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); - - /* Set CKSEL bitfield according to ClockSource value */ - /* Set PRESC bitfield according to Prescaler value */ - /* Set WAVE bitfield according to Waveform value */ - /* Set WAVEPOL bitfield according to Polarity value */ - MODIFY_REG(LPTIMx->CFGR, - (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), - LPTIM_InitStruct->ClockSource | \ - LPTIM_InitStruct->Prescaler | \ - LPTIM_InitStruct->Waveform | \ - LPTIM_InitStruct->Polarity); + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFGR, + (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); } return result; @@ -196,15 +188,155 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In */ /** - * @} + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LL_LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None */ +void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) +{ + LL_RCC_ClocksTypeDef rcc_clock; + uint32_t tmpclksource = 0; + uint32_t tmpIER; + uint32_t tmpCFGR; + uint32_t tmpCMP; + uint32_t tmpARR; + uint32_t tmpOR; +#if defined(LPTIM_RCR_REP) + uint32_t tmpRCR; +#endif -#endif /* defined (LPTIM1) || defined (LPTIM2) */ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + + __disable_irq(); + + /********** Save LPTIM Config *********/ + /* Save LPTIM source clock */ + switch ((uint32_t)LPTIMx) + { + case LPTIM1_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + break; +#if defined(LPTIM2) + case LPTIM2_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); + break; +#endif /* LPTIM2 */ + default: + break; + } + + /* Save LPTIM configuration registers */ + tmpIER = LPTIMx->IER; + tmpCFGR = LPTIMx->CFGR; + tmpCMP = LPTIMx->CMP; + tmpARR = LPTIMx->ARR; + tmpOR = LPTIMx->OR; +#if defined(LPTIM_RCR_REP) + tmpRCR = LPTIMx->RCR; +#endif + + /************* Reset LPTIM ************/ + (void)LL_LPTIM_DeInit(LPTIMx); + + /********* Restore LPTIM Config *******/ + LL_RCC_GetSystemClocksFreq(&rcc_clock); + +#if defined(LPTIM_RCR_REP) + if ((tmpCMP != 0UL) || (tmpARR != 0UL) || (tmpRCR != 0UL)) +#else + if ((tmpCMP != 0UL) || (tmpARR != 0UL)) +#endif + { + /* Force LPTIM source kernel clock from APB */ + switch ((uint32_t)LPTIMx) + { + case LPTIM1_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); + break; +#if defined(LPTIM2) + case LPTIM2_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1); + break; +#endif /* LPTIM2 */ + default: + break; + } + + if (tmpCMP != 0UL) + { + /* Restore CMP and ARR registers (LPTIM should be enabled first) */ + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->CMP = tmpCMP; + + /* Polling on CMP write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_CMPOK(LPTIMx); + } + + if (tmpARR != 0UL) + { + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->ARR = tmpARR; + + LL_RCC_GetSystemClocksFreq(&rcc_clock); + /* Polling on ARR write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_ARROK(LPTIMx); + } + +#if defined(LPTIM_RCR_REP) + if (tmpRCR != 0UL) + { + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->RCR = tmpRCR; + + LL_RCC_GetSystemClocksFreq(&rcc_clock); + /* Polling on RCR write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_REPOK(LPTIMx); + } +#endif + + /* Restore LPTIM source kernel clock */ + LL_RCC_SetLPTIMClockSource(tmpclksource); + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + LPTIMx->CR &= ~(LPTIM_CR_ENABLE); + LPTIMx->IER = tmpIER; + LPTIMx->CFGR = tmpCFGR; + LPTIMx->OR = tmpOR; + + __enable_irq(); +} /** * @} */ - + +#endif /* LPTIM1 || LPTIM2 */ + +/** + * @} + */ + #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h index fc04402a39..7f0984451c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_LPTIM_H -#define __STM32L4xx_LL_LPTIM_H +#ifndef STM32L4xx_LL_LPTIM_H +#define STM32L4xx_LL_LPTIM_H #ifdef __cplusplus extern "C" { @@ -47,8 +31,9 @@ extern "C" { /** @addtogroup STM32L4xx_LL_Driver * @{ */ + #if defined (LPTIM1) || defined (LPTIM2) - + /** @defgroup LPTIM_LL LPTIM * @{ */ @@ -121,6 +106,10 @@ typedef struct #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ +#if defined(LPTIM_RCR_REP) +#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */ +#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */ +#endif /** * @} */ @@ -136,6 +125,10 @@ typedef struct #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#if defined(LPTIM_RCR_REP) +#define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event Interrupt Enable */ +#define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK Interrupt Enable */ +#endif /** * @} */ @@ -143,8 +136,8 @@ typedef struct /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode * @{ */ -#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!CR, LPTIM_CR_ENABLE); } -/** - * @brief Disable the LPTIM instance - * @rmtoll CR ENABLE LL_LPTIM_Disable - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); -} - /** * @brief Indicates whether the LPTIM instance is enabled. * @rmtoll CR ENABLE LL_LPTIM_IsEnabled @@ -375,7 +375,7 @@ __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE)); + return ((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL); } /** @@ -396,6 +396,59 @@ __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t Opera MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); } +#if defined(LPTIM_CR_RSTARE) +/** + * @brief Enable reset after read. + * @note After calling this function any read access to LPTIM_CNT + * register will asynchronously reset the LPTIM_CNT register content. + * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Disable reset after read. + * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Indicate whether the reset after read feature is enabled. + * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL); +} +#endif + +#if defined(LPTIM_CR_COUNTRST) +/** + * @brief Reset of the LPTIM_CNT counter register (synchronous). + * @note Due to the synchronous nature of this reset, it only takes + * place after a synchronization delay of 3 LPTIM core clock cycles + * (LPTIM core clock may be different from APB clock). + * @note COUNTRST is automatically cleared by hardware + * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST); +} +#endif /** * @brief Set the LPTIM registers update mode (enable/disable register preload) @@ -454,6 +507,32 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } +#if defined(LPTIM_RCR_REP) +/** + * @brief Set the repetition value + * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled + * @rmtoll RCR REP LL_LPTIM_SetRepetition + * @param LPTIMx Low-Power Timer instance + * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition) +{ + MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition); +} + +/** + * @brief Get the repetition value + * @rmtoll RCR REP LL_LPTIM_GetRepetition + * @param LPTIMx Low-Power Timer instance + * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP)); +} +#endif + /** * @brief Set the compare value * @note After a write to the LPTIMx_CMP register a new write operation to the @@ -722,7 +801,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL)); } /** @@ -750,9 +829,9 @@ __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*) * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*) * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 * @param Filter This parameter can be one of the following values: @@ -779,9 +858,9 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (*) * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (*) * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 */ @@ -985,7 +1064,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL)); } /** @@ -1015,7 +1094,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL)); } /** @@ -1037,7 +1116,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL)); } /** @@ -1059,7 +1138,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL)); } /** @@ -1074,14 +1153,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL)); } /** @@ -1096,14 +1175,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL)); } /** @@ -1125,7 +1204,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL)); } /** @@ -1147,9 +1226,55 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL)); } +#if defined(LPTIM_RCR_REP) +/** + * @brief Clear the repetition register update interrupt flag (REPOKCF). + * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully completed; If so, a new one can be initiated. + * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == LPTIM_ISR_REPOK) ? 1UL : 0UL); +} + +/** + * @brief Clear the update event flag (UECF). + * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF); +} + +/** + * @brief Informs application whether the LPTIMx update event has occurred. + * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == LPTIM_ISR_UE) ? 1UL : 0UL); +} +#endif + /** * @} */ @@ -1188,7 +1313,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL)); } /** @@ -1221,7 +1346,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL)); } /** @@ -1254,7 +1379,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL)); } /** @@ -1287,7 +1412,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL)); } /** @@ -1320,7 +1445,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL)); } /** @@ -1353,7 +1478,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL)); } /** @@ -1386,25 +1511,80 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE)); + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); +} + +#if defined(LPTIM_RCR_REP) +/** + * @brief Enable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE); } /** - * @} + * @brief Disable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None */ +__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE); +} -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions - * @{ +/** + * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled. + * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == LPTIM_IER_REPOKIE) ? 1UL : 0UL); +} + +/** + * @brief Enable update event interrupt (UEIE). + * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->IER, LPTIM_IER_UEIE); +} + +/** + * @brief Disable update event interrupt (UEIE). + * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UEIE); +} + +/** + * @brief Indicates whether the update event interrupt (UEIE) is enabled. + * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == LPTIM_IER_UEIE) ? 1UL : 0UL); +} +#endif -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); -void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); /** * @} */ -#endif /* USE_FULL_LL_DRIVER */ /** * @} @@ -1424,6 +1604,6 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_Ini } #endif -#endif /* __STM32L4xx_LL_LPTIM_H */ +#endif /* STM32L4xx_LL_LPTIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c index dc74d16025..c732d4dd77 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -38,11 +22,11 @@ #include "stm32l4xx_ll_lpuart.h" #include "stm32l4xx_ll_rcc.h" #include "stm32l4xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32L4xx_LL_Driver * @{ @@ -75,50 +59,53 @@ #if defined(USART_PRESC_PRESCALER) #define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) -#endif +#endif /* USART_PRESC_PRESCALER */ /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ /* value : */ /* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ /* - LPUART_BRR register value should be >= 0x300 */ /* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ -/* Baudrate specified by the user should belong to [8, 26000000].*/ -#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U)) +/* Baudrate specified by the user should belong to [8, 40000000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 40000000U) && ((__BAUDRATE__) >= 8U)) /* __VALUE__ BRR content must be greater than or equal to 0x300. */ -#define IS_LL_LPUART_BRR(__VALUE__) ((__VALUE__) >= 0x300U) +#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */ +#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ - || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ - || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ - || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) /** * @} @@ -169,7 +156,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) * @brief Initialize LPUART registers according to the specified * parameters in LPUART_InitStruct. * @note As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), - * LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). * @param LPUARTx LPUART Instance * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure @@ -181,13 +168,13 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) { ErrorStatus status = ERROR; - uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t periphclk; /* Check the parameters */ assert_param(IS_LPUART_INSTANCE(LPUARTx)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); -#endif +#endif /* USART_PRESC_PRESCALER */ assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); @@ -227,9 +214,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); /* Configure the LPUART Baud Rate : -#if defined(USART_PRESC_PRESCALER) + #if defined(USART_PRESC_PRESCALER) - prescaler value is required -#endif + #endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -241,20 +228,23 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART periphclk, #if defined(USART_PRESC_PRESCALER) LPUART_InitStruct->PrescalerValue, -#endif +#endif /* USART_PRESC_PRESCALER */ LPUART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 0x300 */ - assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR)); - } -#if defined(USART_PRESC_PRESCALER) + assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR)); + /* Check BRR is lower than or equal to 0xFFFFF */ + assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR)); + } + +#if defined(USART_PRESC_PRESCALER) /*---------------------------- LPUART PRESC Configuration ----------------------- * Configure LPUARTx PRESC (Prescaler) with parameters: * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. */ LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); -#endif +#endif /* USART_PRESC_PRESCALER */ } return (status); @@ -272,7 +262,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) /* Set LPUART_InitStruct fields to default values */ #if defined(USART_PRESC_PRESCALER) LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; -#endif +#endif /* USART_PRESC_PRESCALER */ LPUART_InitStruct->BaudRate = 9600U; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h index d91b729458..07272e8f9d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_LPUART_H -#define __STM32L4xx_LL_LPUART_H +#ifndef STM32L4xx_LL_LPUART_H +#define STM32L4xx_LL_LPUART_H #ifdef __cplusplus extern "C" { @@ -79,7 +63,7 @@ static const uint16_t LPUART_PRESCALER_TAB[] = /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /* Private constants ---------------------------------------------------------*/ /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants @@ -121,7 +105,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ -#endif +#endif /* USART_PRESC_PRESCALER */ uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ @@ -169,12 +153,12 @@ typedef struct */ #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ @@ -196,13 +180,13 @@ typedef struct #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ #else #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ #else #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ @@ -217,7 +201,7 @@ typedef struct #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -231,26 +215,26 @@ typedef struct #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ #else #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ #else #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -268,7 +252,7 @@ typedef struct /** * @} */ -#endif +#endif /* USART_CR1_FIFOEN */ /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ @@ -329,7 +313,7 @@ typedef struct /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ @@ -488,16 +472,17 @@ typedef struct * @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 - * @param __PRESCALER__ Prescaler value @endif * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ #if defined(USART_PRESC_PRESCALER) -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\ + + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) #else -#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) -#endif +#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\ + & LPUART_BRR_MASK) +#endif /* USART_PRESC_PRESCALER */ /** * @} @@ -554,7 +539,7 @@ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) @@ -588,7 +573,7 @@ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } /** @@ -684,9 +669,9 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief LPUART enabled in STOP Mode @@ -722,9 +707,46 @@ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } +#if defined(USART_CR3_UCESM) +/** + * @brief LPUART Clock enabled in STOP Mode + * @note When this function is called, LPUART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief LPUART clock disabled in STOP Mode + * @note When this function is called, LPUART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if LPUART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL); +} + +#endif /* USART_CR3_UCESM */ /** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx @@ -923,7 +945,7 @@ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } #if defined(USART_PRESC_PRESCALER) @@ -948,7 +970,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) { - MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); } /** @@ -973,7 +995,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); } -#endif +#endif /* USART_PRESC_PRESCALER */ /** * @brief Set the length of the stop bits @@ -1339,7 +1361,7 @@ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } /** @@ -1403,16 +1425,17 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) * @retval None */ #if defined(USART_PRESC_PRESCALER) -__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) #else __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate) -#endif +#endif /* USART_PRESC_PRESCALER */ { #if defined(USART_PRESC_PRESCALER) LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); #else LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); -#endif +#endif /* USART_PRESC_PRESCALER */ } /** @@ -1443,13 +1466,13 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) #else __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk) -#endif +#endif /* USART_PRESC_PRESCALER */ { - register uint32_t lpuartdiv = 0x0U; - register uint32_t brrresult = 0x0U; + register uint32_t lpuartdiv; + register uint32_t brrresult; #if defined(USART_PRESC_PRESCALER) - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue])); -#endif + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); +#endif /* USART_PRESC_PRESCALER */ lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; @@ -1459,7 +1482,11 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); #else brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); -#endif +#endif /* USART_PRESC_PRESCALER */ + } + else + { + brrresult = 0x0UL; } return (brrresult); @@ -1503,7 +1530,7 @@ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } /** @@ -1590,7 +1617,7 @@ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } /** @@ -1636,7 +1663,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } /** @@ -1647,7 +1674,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } /** @@ -1658,7 +1685,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } /** @@ -1669,7 +1696,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } /** @@ -1680,11 +1707,10 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE @@ -1696,10 +1722,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } #else - /** * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE @@ -1708,9 +1733,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUART */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Transmission Complete Flag is set or not @@ -1720,11 +1745,10 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF @@ -1736,10 +1760,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } #else - /** * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE @@ -1748,9 +1771,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART CTS interrupt Flag is set or not @@ -1760,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } /** @@ -1771,7 +1794,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } /** @@ -1782,7 +1805,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } /** @@ -1793,7 +1816,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } /** @@ -1804,7 +1827,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } /** @@ -1815,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } /** @@ -1826,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } /** @@ -1837,7 +1860,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } /** @@ -1848,11 +1871,10 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the LPUART TX FIFO Empty Flag is set or not * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE @@ -1861,7 +1883,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } /** @@ -1872,7 +1894,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } /** @@ -1883,7 +1905,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } /** @@ -1894,9 +1916,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Clear Parity Error Flag @@ -1922,13 +1944,13 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) /** * @brief Clear Noise detected Flag - * @rmtoll ICR NCF LL_LPUART_ClearFlag_NE + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE * @param LPUARTx LPUART Instance * @retval None */ __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) { - WRITE_REG(LPUARTx->ICR, USART_ICR_NCF); + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); } /** @@ -1954,7 +1976,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Clear TX FIFO Empty Flag * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE @@ -1965,7 +1986,7 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) { WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Clear Transmission Complete Flag @@ -2031,7 +2052,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE @@ -2057,7 +2077,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Enable Transmission Complete Interrupt @@ -2071,7 +2091,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF @@ -2097,7 +2116,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Enable Parity Error Interrupt @@ -2122,7 +2141,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Empty Interrupt * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE @@ -2144,7 +2162,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Enable Error Interrupt @@ -2184,7 +2202,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Threshold Interrupt * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT @@ -2206,7 +2223,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable IDLE Interrupt @@ -2220,7 +2237,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE @@ -2246,7 +2262,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable Transmission Complete Interrupt @@ -2260,7 +2276,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF @@ -2286,7 +2301,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable Parity Error Interrupt @@ -2311,7 +2326,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Empty Interrupt * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE @@ -2333,7 +2347,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable Error Interrupt @@ -2373,7 +2387,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Threshold Interrupt * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT @@ -2395,7 +2408,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. @@ -2405,11 +2418,10 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE @@ -2421,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } #else @@ -2433,9 +2445,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. @@ -2445,11 +2457,10 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF @@ -2461,7 +2472,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } #else @@ -2473,9 +2484,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. @@ -2485,7 +2496,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } /** @@ -2496,10 +2507,10 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } -#if defined(USART_CR1_FIFOEN) +#if defined(USART_CR1_FIFOEN) /** * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE @@ -2508,7 +2519,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } /** @@ -2519,9 +2530,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the LPUART Error Interrupt is enabled or disabled. @@ -2531,7 +2542,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } /** @@ -2542,7 +2553,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } /** @@ -2553,11 +2564,10 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT @@ -2566,7 +2576,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } /** @@ -2577,9 +2587,9 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} @@ -2619,7 +2629,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } /** @@ -2652,7 +2662,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } /** @@ -2685,7 +2695,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) */ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) { - return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } /** @@ -2700,7 +2710,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR */ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) { - register uint32_t data_reg_addr = 0U; + register uint32_t data_reg_addr; if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { @@ -2732,7 +2742,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 */ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) { - return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** @@ -2767,7 +2777,7 @@ __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Val */ __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) { - LPUARTx->TDR = Value & 0x1FFU; + LPUARTx->TDR = Value & 0x1FFUL; } /** @@ -2786,7 +2796,7 @@ __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Va */ __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ); + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); } /** @@ -2797,7 +2807,7 @@ __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ); + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); } /** @@ -2814,7 +2824,7 @@ __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ); + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } /** @@ -2851,6 +2861,6 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); } #endif -#endif /* __STM32L4xx_LL_LPUART_H */ +#endif /* STM32L4xx_LL_LPUART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c index 6e0653a383..685a080130 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -121,10 +105,10 @@ ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx)); - + LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U); return status; @@ -153,7 +137,7 @@ ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_Ini assert_param(IS_LL_OPAMP_POWER_MODE(OPAMP_InitStruct->PowerMode)); assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode)); assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting)); - + /* Note: OPAMP inverting input can be used with OPAMP in mode standalone */ /* or PGA with external capacitors for filtering circuit. */ /* Otherwise (OPAMP in mode follower), OPAMP inverting input is */ @@ -162,7 +146,7 @@ ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_Ini { assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting)); } - + /* Configuration of OPAMP instance : */ /* - PowerMode */ /* - Functional mode */ @@ -199,7 +183,7 @@ ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_Ini | LL_OPAMP_INPUT_INVERT_CONNECT_NO ); } - + return SUCCESS; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h index a77c0044e4..c49f227bb7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_OPAMP_H -#define __STM32L4xx_LL_OPAMP_H +#ifndef STM32L4xx_LL_OPAMP_H +#define STM32L4xx_LL_OPAMP_H #ifdef __cplusplus extern "C" { @@ -68,8 +52,8 @@ extern "C" { /* - OPAMP trimming register offset */ /* Internal register offset for OPAMP trimming configuration */ -#define OPAMP_POWERMODE_OTR_REGOFFSET ((uint32_t)0x00000000U) -#define OPAMP_POWERMODE_LPOTR_REGOFFSET ((uint32_t)0x00000001U) +#define OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U +#define OPAMP_POWERMODE_LPOTR_REGOFFSET 0x00000001U #define OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET) /* Mask for OPAMP power mode into control register */ @@ -125,24 +109,24 @@ typedef struct { uint32_t PowerMode; /*!< Set OPAMP power mode. This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */ uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ... This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain(). - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */ uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection. This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */ uint32_t InputInverting; /*!< Set OPAMP inverting input connection. This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded. - + This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */ } LL_OPAMP_InitTypeDef; @@ -160,7 +144,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range * @{ */ -#define LL_OPAMP_POWERSUPPLY_RANGE_LOW ((uint32_t)0x00000000U) /*!< Power supply range low. On STM32L4 serie: Vdda lower than 2.4V. */ +#define LL_OPAMP_POWERSUPPLY_RANGE_LOW 0x00000000U /*!< Power supply range low. On STM32L4 serie: Vdda lower than 2.4V. */ #define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE) /*!< Power supply range high. On STM32L4 serie: Vdda higher than 2.4V. */ /** * @} @@ -178,7 +162,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional. * @{ */ -#define LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U) /*!< OPAMP functional mode */ +#define LL_OPAMP_MODE_FUNCTIONAL 0x00000000U /*!< OPAMP functional mode */ #define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */ /** * @} @@ -187,7 +171,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode * @{ */ -#define LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone */ +#define LL_OPAMP_MODE_STANDALONE 0x00000000U /*!< OPAMP functional mode, OPAMP operation in standalone */ #define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0) /*!< OPAMP functional mode, OPAMP operation in follower */ #define LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1) /*!< OPAMP functional mode, OPAMP operation in PGA */ /** @@ -197,7 +181,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA) * @{ */ -#define LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U) /*!< OPAMP PGA gain 2 */ +#define LL_OPAMP_PGA_GAIN_2 0x00000000U /*!< OPAMP PGA gain 2 */ #define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 */ #define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1) /*!< OPAMP PGA gain 8 */ #define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */ @@ -208,7 +192,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting * @{ */ -#define LL_OPAMP_INPUT_NONINVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ #define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP1_CSR_VPSEL) /*!< OPAMP non inverting input connected to DAC1 channel1 output */ /** * @} @@ -217,7 +201,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting * @{ */ -#define LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */ +#define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */ #define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */ #define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering) */ /** @@ -242,7 +226,7 @@ typedef struct /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode * @{ */ -#define LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */ +#define LL_OPAMP_TRIMMING_FACTORY 0x00000000U /*!< OPAMP trimming factors set to factory values */ #define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */ /** * @} @@ -299,7 +283,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in OPAMP register @@ -307,7 +291,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -391,6 +375,9 @@ typedef struct */ __STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) { + /* Prevent unused parameter warning */ + (void)(*OPAMPxy_COMMON); + MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, PowerRange); } @@ -407,6 +394,9 @@ __STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_ */ __STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON) { + /* Prevent unused parameter warning */ + (void)(*OPAMPxy_COMMON); + return (uint32_t)(READ_BIT(OPAMP1->CSR, OPAMP1_CSR_OPARANGE)); } @@ -444,8 +434,8 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power __STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) { register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM)); - - return (uint32_t)(power_mode | (power_mode >> (POSITION_VAL(OPAMP_CSR_OPALPM)))); + + return (uint32_t)(power_mode | (power_mode >> (OPAMP_CSR_OPALPM_Pos))); } /** @@ -718,9 +708,9 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) { register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); - + return (CalibrationSelection | - ((OPAMP_OTR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_OTR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL)))); + (((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP)); } /** @@ -734,7 +724,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) */ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) { - return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT); + return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 1UL : 0UL); } /** @@ -758,14 +748,14 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue) { register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); - + /* Set bits with position in register depending on parameter */ /* "TransistorsDiffPair". */ /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ /* containing other bits reserved for other purpose. */ MODIFY_REG(*preg, - (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK), - TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))); + (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK), + TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos)); } /** @@ -787,15 +777,14 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P */ __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { - register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); - + register const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); + /* Retrieve bits with position in register depending on parameter */ /* "TransistorsDiffPair". */ /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */ /* containing other bits reserved for other purpose. */ return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)) - >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)) - ); + >> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos)); } /** @@ -839,7 +828,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) */ __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) { - return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)); + return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)) ? 1UL : 0UL); } /** @@ -878,6 +867,6 @@ void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct); } #endif -#endif /* __STM32L4xx_LL_OPAMP_H */ +#endif /* STM32L4xx_LL_OPAMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c index b934799fda..7b12da7533 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h index 1d1f4624c3..b3939f886a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -87,6 +71,9 @@ extern "C" { * @{ */ #define LL_PWR_SR1_WUFI PWR_SR1_WUFI +#if defined(PWR_SR1_EXT_SMPS_RDY) +#define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY +#endif /* PWR_SR1_EXT_SMPS_RDY */ #define LL_PWR_SR1_SBF PWR_SR1_SBF #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 @@ -152,7 +139,7 @@ extern "C" { /** * @} */ - + /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL * @{ */ @@ -328,7 +315,7 @@ __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) { - return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); + return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); } /** @@ -359,7 +346,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) #if defined(PWR_CR5_R1MODE) /** - * @brief Enable main regulator voltage range 1 boost mode + * @brief Enable main regulator voltage range 1 boost mode * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode * @retval None */ @@ -369,7 +356,7 @@ __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) } /** - * @brief Disable main regulator voltage range 1 boost mode + * @brief Disable main regulator voltage range 1 boost mode * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode * @retval None */ @@ -385,7 +372,7 @@ __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) { - return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET); + return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL); } #endif /* PWR_CR5_R1MODE */ @@ -416,7 +403,7 @@ __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) { - return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); } /** @@ -478,7 +465,7 @@ __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) { - return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)); + return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL); } #endif /* PWR_CR1_RRSTP */ @@ -510,11 +497,11 @@ __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); + return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); } #endif /* PWR_CR3_DSIPDEN */ -#if defined(PWR_CR2_PVME1) +#if defined(PWR_CR2_USV) /** * @brief Enable VDDUSB supply * @rmtoll CR2 USV LL_PWR_EnableVddUSB @@ -542,7 +529,7 @@ __STATIC_INLINE void LL_PWR_DisableVddUSB(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { - return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); + return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); } #endif @@ -574,7 +561,7 @@ __STATIC_INLINE void LL_PWR_DisableVddIO2(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) { - return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); + return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); } #endif @@ -635,7 +622,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) { - return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); + return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); } /** @@ -702,7 +689,7 @@ __STATIC_INLINE void LL_PWR_DisablePVD(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { - return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); + return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); } /** @@ -732,7 +719,7 @@ __STATIC_INLINE void LL_PWR_DisableInternWU(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); + return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL); } /** @@ -762,7 +749,7 @@ __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); + return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); } #if defined(PWR_CR3_DSIPDEN) @@ -793,10 +780,42 @@ __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); + return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL); } #endif /* PWR_CR3_DSIPDEN */ +#if defined(PWR_CR3_ENULP) +/** + * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes + * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_ENULP); +} + +/** + * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes + * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP); +} + +/** + * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled + * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL); +} +#endif /* PWR_CR3_ENULP */ + /** * @brief Enable SRAM2 content retention in Standby mode * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention @@ -824,7 +843,7 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) { - return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); + return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); } /** @@ -884,9 +903,47 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) { - return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); + return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); } +#if defined(PWR_CR4_EXT_SMPS_ON) +/** + * @brief Enable the CFLDO working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void) +{ + SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Disable the CFLDO working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON); +} + +/** + * @brief Check if CFLDO is working @ 0.95V + * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the + * internal CFLDO can be reduced to 0.95V. + * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void) +{ + return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL); +} +#endif /* PWR_CR4_EXT_SMPS_ON */ + /** * @brief Set the resistor impedance * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor @@ -939,7 +996,7 @@ __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) { - return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); + return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); } /** @@ -999,7 +1056,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) */ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) { - return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); + return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); } /** @@ -1046,7 +1103,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) */ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - SET_BIT(*((uint32_t *)GPIO), GPIONumber); + SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** @@ -1093,7 +1150,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) */ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); + CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber); } /** @@ -1140,7 +1197,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { - return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)); + return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1187,8 +1244,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIO */ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4; - SET_BIT(*((uint32_t *)(temp)), GPIONumber); + SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** @@ -1235,8 +1291,7 @@ __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe */ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4; - CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); + CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber); } /** @@ -1283,8 +1338,7 @@ __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { - register uint32_t temp = (uint32_t)(GPIO) + 4; - return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)); + return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL); } /** @@ -1302,9 +1356,21 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GP */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); } +#if defined(PWR_SR1_EXT_SMPS_RDY) +/** + * @brief Get Ready Flag for switching to external SMPS + * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL); +} +#endif /* PWR_SR1_EXT_SMPS_RDY */ + /** * @brief Get Stand-By Flag * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB @@ -1312,7 +1378,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); + return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); } /** @@ -1322,7 +1388,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); } /** @@ -1332,7 +1398,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); } /** @@ -1342,7 +1408,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); } /** @@ -1352,7 +1418,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); } /** @@ -1362,7 +1428,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) { - return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); + return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); } /** @@ -1442,7 +1508,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL); } /** @@ -1452,7 +1518,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); } #if defined(PWR_SR2_PVMO2) @@ -1463,7 +1529,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL); } #endif /* PWR_SR2_PVMO2 */ @@ -1475,7 +1541,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); } #endif /* PWR_SR2_PVMO1 */ @@ -1486,7 +1552,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); + return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); } /** @@ -1496,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)); + return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); } /** @@ -1507,7 +1573,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); } /** @@ -1517,7 +1583,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) { - return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); + return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c index d3c5a0f053..1a1406aecd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -99,19 +83,20 @@ #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) -#if defined(RCC_CCIPR_SAI2SEL) +#if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) -#else +#elif defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) -#endif /* RCC_CCIPR_SAI2SEL */ +#endif /* RCC_CCIPR_SAI2SEL RCC_CCIPR2_SAI2SEL ||*/ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE)) #endif /* RCC_CCIPR2_SDMMCSEL */ #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) - +#endif /* SDMMC1 */ #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) @@ -159,9 +144,11 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); uint32_t RCC_PLL_GetFreqDomain_SYS(void); uint32_t RCC_PLL_GetFreqDomain_SAI(void); uint32_t RCC_PLL_GetFreqDomain_48M(void); +#if defined(RCC_PLLSAI1_SUPPORT) uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void); uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); #if defined(LTDC) @@ -204,7 +191,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void); */ ErrorStatus LL_RCC_DeInit(void) { - uint32_t vl_mask = 0U; + __IO uint32_t vl_mask; /* Set MSION bit */ LL_RCC_MSI_Enable(); @@ -226,21 +213,24 @@ ErrorStatus LL_RCC_DeInit(void) /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); - vl_mask = 0xFFFFFFFFU; + /* Read CR register */ + vl_mask = LL_RCC_ReadReg(CR); /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */ - CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | - RCC_CR_PLLON)); + CLEAR_BIT(vl_mask, + (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON)); +#if defined(RCC_PLLSAI1_SUPPORT) /* Reset PLLSAI1ON bit */ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON); +#endif /*RCC_PLLSAI1_SUPPORT*/ #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2ON bit */ CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON); #endif /*RCC_PLLSAI2_SUPPORT*/ - /* Write new mask in CR register */ + /* Write new value in CR register */ LL_RCC_WriteReg(CR, vl_mask); #if defined(RCC_PLLSAI2_SUPPORT) @@ -248,18 +238,25 @@ ErrorStatus LL_RCC_DeInit(void) while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) { } -#else - /* Wait for PLLRDY, PLLSAI1RDY bits to be reset */ +#elif defined(RCC_PLLSAI1_SUPPORT) + /* Wait for PLLRDY and PLLSAI1RDY to be reset */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) { } +#else + /* Wait for PLLRDY bit to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + } #endif /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); +#if defined(RCC_PLLSAI1_SUPPORT) /* Reset PLLSAI1CFGR register */ LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos); +#endif /*RCC_PLLSAI1_SUPPORT*/ #if defined(RCC_PLLSAI2_SUPPORT) /* Reset PLLSAI2CFGR register */ @@ -274,14 +271,16 @@ ErrorStatus LL_RCC_DeInit(void) /* Clear all interrupt flags */ vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ - RCC_CICR_PLLSAI1RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC; + RCC_CICR_CSSC | RCC_CICR_LSECSSC; #if defined(RCC_HSI48_SUPPORT) vl_mask |= RCC_CICR_HSI48RDYC; #endif +#if defined(RCC_PLLSAI1_SUPPORT) + vl_mask |= RCC_CICR_PLLSAI1RDYC; +#endif #if defined(RCC_PLLSAI2_SUPPORT) vl_mask |= RCC_CICR_PLLSAI2RDYC; #endif - LL_RCC_WriteReg(CICR, vl_mask); /* Clear reset flags */ @@ -370,23 +369,25 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ - default: usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) @@ -399,23 +400,25 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ - default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } else @@ -431,23 +434,25 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) break; case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ - default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /* RCC_CCIPR_USART3SEL */ @@ -482,23 +487,25 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ - default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /* RCC_CCIPR_UART4SEL */ @@ -514,23 +521,25 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) break; case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ - default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /* RCC_CCIPR_UART5SEL */ @@ -568,16 +577,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #if defined(RCC_CCIPR_I2C2SEL) @@ -591,16 +602,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #endif /*RCC_CCIPR_I2C2SEL*/ @@ -616,16 +629,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } #if defined(RCC_CCIPR2_I2C4SEL) @@ -641,16 +656,18 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) break; case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { i2c_frequency = HSI_VALUE; } break; case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */ - default: i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } } @@ -683,23 +700,25 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) break; case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { lpuart_frequency = HSI_VALUE; } break; case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { lpuart_frequency = LSE_VALUE; } break; case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ - default: lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } return lpuart_frequency; @@ -726,30 +745,41 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ - if (LL_RCC_LSI_IsReady()) + if (LL_RCC_LSI_IsReady() != 0U) { - lptim_frequency = LSI_VALUE; +#if defined(RCC_CSR_LSIPREDIV) + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + lptim_frequency = LSI_VALUE / 128U; + } + else +#endif /* RCC_CSR_LSIPREDIV */ + { + lptim_frequency = LSI_VALUE; + } } break; case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { lptim_frequency = HSI_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { lptim_frequency = LSE_VALUE; } break; case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ - default: lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } else @@ -760,30 +790,41 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ - if (LL_RCC_LSI_IsReady()) + if (LL_RCC_LSI_IsReady() != 0U) { - lptim_frequency = LSI_VALUE; +#if defined(RCC_CSR_LSIPREDIV) + if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128) + { + lptim_frequency = LSI_VALUE / 128U; + } + else +#endif /* RCC_CSR_LSIPREDIV */ + { + lptim_frequency = LSI_VALUE; + } } break; case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { lptim_frequency = HSI_VALUE; } break; case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) + if (LL_RCC_LSE_IsReady() != 0U) { lptim_frequency = LSE_VALUE; } break; case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ - default: lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } } } @@ -791,6 +832,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) return lptim_frequency; } +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL) /** * @brief Return SAIx clock frequency * @param SAIxSource This parameter can be one of the following values: @@ -800,7 +842,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) * (*) value not defined in all devices. * @retval SAI clock frequency (in Hz) * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready - * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) { @@ -815,7 +857,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) switch (LL_RCC_GetSAIClockSource(SAIxSource)) { case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); } @@ -823,7 +865,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) #if defined(RCC_PLLSAI2_SUPPORT) case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI(); } @@ -831,61 +873,67 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) #endif /* RCC_PLLSAI2_SUPPORT */ case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sai_frequency = RCC_PLL_GetFreqDomain_SAI(); } break; case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ + sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + default: - sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; break; } } else { -#if defined(RCC_CCIPR_SAI2SEL) +#if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL) if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) { /* SAI2CLK clock frequency */ switch (LL_RCC_GetSAIClockSource(SAIxSource)) { case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); } break; - #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2_SUPPORT) case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI(); } break; - #endif /* RCC_PLLSAI2_SUPPORT */ +#endif /* RCC_PLLSAI2_SUPPORT */ case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sai_frequency = RCC_PLL_GetFreqDomain_SAI(); } break; - case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ - default: - sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; + case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ + sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE; + break; + + default: + break; } } -#endif /* RCC_CCIPR_SAI2SEL */ +#endif /* RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI2SEL */ } return sai_frequency; } +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI1SEL || RCC_CCIPR2_SAI2SEL*/ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) /** * @brief Return SDMMCx kernel clock frequency @@ -910,7 +958,7 @@ uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource) break; case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI(); } @@ -945,7 +993,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) { #if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1) case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } @@ -953,7 +1001,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) #endif case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); } @@ -961,10 +1009,10 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) #if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI) case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -973,7 +1021,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) #if defined(RCC_HSI48_SUPPORT) case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ - if (LL_RCC_HSI48_IsReady()) + if (LL_RCC_HSI48_IsReady() != 0U) { sdmmc_frequency = HSI48_VALUE; } @@ -988,6 +1036,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) return sdmmc_frequency; } +#endif /* SDMMC1 */ /** * @brief Return RNGx clock frequency @@ -1007,25 +1056,27 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) /* RNGCLK clock frequency */ switch (LL_RCC_GetRNGClockSource(RNGxSource)) { +#if defined(RCC_PLLSAI1_SUPPORT) case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif /* RCC_PLLSAI1_SUPPORT */ case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { rng_frequency = RCC_PLL_GetFreqDomain_48M(); } break; case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -1033,14 +1084,14 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) #if defined(RCC_HSI48_SUPPORT) - case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ - if (LL_RCC_HSI48_IsReady()) + case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */ + if (LL_RCC_HSI48_IsReady() != 0U) { rng_frequency = HSI48_VALUE; } break; #else - case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */ + case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */ #endif default: rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA; @@ -1071,25 +1122,27 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) /* USBCLK clock frequency */ switch (LL_RCC_GetUSBClockSource(USBxSource)) { +#if defined(RCC_PLLSAI1_SUPPORT) case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif /* RCC_PLLSAI1_SUPPORT */ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { usb_frequency = RCC_PLL_GetFreqDomain_48M(); } break; case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -1097,7 +1150,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) #if defined(RCC_HSI48_SUPPORT) case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */ - if (LL_RCC_HSI48_IsReady()) + if (LL_RCC_HSI48_IsReady() != 0U) { usb_frequency = HSI48_VALUE; } @@ -1132,16 +1185,18 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) /* ADCCLK clock frequency */ switch (LL_RCC_GetADCClockSource(ADCxSource)) { +#if defined(RCC_PLLSAI1_SUPPORT) case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ - if (LL_RCC_PLLSAI1_IsReady()) + if (LL_RCC_PLLSAI1_IsReady() != 0U) { adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC(); } break; +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2) case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC(); } @@ -1151,6 +1206,7 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ adc_frequency = RCC_GetSystemClockFreq(); break; + case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */ default: adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; @@ -1186,9 +1242,11 @@ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource) break; case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */ - default: swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } return swpmi_frequency; @@ -1217,9 +1275,11 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) break; case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ - default: dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; + + default: + break; } return dfsdm_frequency; @@ -1248,10 +1308,10 @@ uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) break; case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } @@ -1259,7 +1319,7 @@ uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */ default: - if (LL_RCC_HSI_IsReady()) + if (LL_RCC_HSI_IsReady() != 0U) { dfsdm_frequency = HSI_VALUE; } @@ -1291,7 +1351,7 @@ uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) switch (LL_RCC_GetDSIClockSource(DSIxSource)) { case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */ - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI(); } @@ -1322,7 +1382,7 @@ uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) /* Check parameter */ assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); - if (LL_RCC_PLLSAI2_IsReady()) + if (LL_RCC_PLLSAI2_IsReady() != 0U) { ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC(); } @@ -1354,17 +1414,17 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) break; case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */ - if (LL_RCC_MSI_IsReady()) + if (LL_RCC_MSI_IsReady() != 0U) { octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); } break; case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */ - if (LL_RCC_PLL_IsReady()) + if (LL_RCC_PLL_IsReady() != 0U) { octospi_frequency = RCC_PLL_GetFreqDomain_48M(); } @@ -1397,14 +1457,14 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) */ uint32_t RCC_GetSystemClockFreq(void) { - uint32_t frequency = 0U; + uint32_t frequency; /* Get SYSCLK source -------------------------------------------------------*/ switch (LL_RCC_GetSysClkSource()) { case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1423,7 +1483,7 @@ uint32_t RCC_GetSystemClockFreq(void) default: frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1471,7 +1531,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) */ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR @@ -1482,7 +1542,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1497,7 +1557,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1505,13 +1565,15 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); } + +#if defined(SAI1) /** * @brief Return PLL clock frequency used for SAI domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SAI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN SAI Domain clock = PLL_VCO / PLLP @@ -1522,7 +1584,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1537,7 +1599,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1545,6 +1607,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); } +#endif /* SAI1 */ /** * @brief Return PLL clock frequency used for 48 MHz domain @@ -1552,7 +1615,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) */ uint32_t RCC_PLL_GetFreqDomain_48M(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN 48M Domain clock = PLL_VCO / PLLQ @@ -1563,7 +1626,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1578,7 +1641,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1593,7 +1656,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) */ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ /* DSICLK = PLLSAI2_VCO / PLLSAI2R */ @@ -1603,7 +1666,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1618,7 +1681,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1629,13 +1692,14 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) } #endif /* DSI */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Return PLLSAI1 clock frequency used for SAI domain * @retval PLLSAI1 clock frequency (in Hz) */ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ @@ -1649,7 +1713,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1664,7 +1728,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1679,7 +1743,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) */ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ @@ -1693,7 +1757,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1708,7 +1772,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1723,7 +1787,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) */ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ @@ -1737,7 +1801,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1752,7 +1816,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1760,6 +1824,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR()); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -1768,7 +1833,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) */ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ @@ -1782,7 +1847,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1797,7 +1862,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1818,7 +1883,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) */ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) { - uint32_t pllinputfreq = 0U, pllsource = 0U; + uint32_t pllinputfreq, pllsource; /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */ @@ -1828,7 +1893,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1843,7 +1908,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1871,7 +1936,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) { case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; @@ -1886,7 +1951,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) default: pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - (LL_RCC_MSI_IsEnabledRangeSelect() ? + ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); break; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h index e1d4b8667b..a61d290393 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_RCC_H -#define __STM32L4xx_LL_RCC_H +#ifndef STM32L4xx_LL_RCC_H +#define STM32L4xx_LL_RCC_H #ifdef __cplusplus extern "C" { @@ -56,18 +40,6 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -#if defined(RCC_CCIPR2_PLLSAI2DIVR) -static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16}; -#endif /* RCC_CCIPR2_PLLSAI2DIVR */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_LL_Private_Constants RCC Private Constants * @{ @@ -153,6 +125,14 @@ typedef struct #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ #endif /* RCC_HSI48_SUPPORT */ + +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) +#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /** * @} */ @@ -170,7 +150,9 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -193,7 +175,9 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -224,7 +208,9 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -495,7 +481,7 @@ typedef struct #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ -#else +#elif defined(RCC_CCIPR_SAI1SEL) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ @@ -533,6 +519,7 @@ typedef struct */ #endif /* RCC_CCIPR2_SDMMCSEL */ +#if defined(SDMMC1) /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection * @{ */ @@ -541,12 +528,15 @@ typedef struct #else #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */ #endif +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */ #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */ /** * @} */ +#endif /* SDMMC1 */ /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection * @{ @@ -556,7 +546,9 @@ typedef struct #else #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */ #endif +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */ #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */ /** @@ -572,7 +564,9 @@ typedef struct #else #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */ #endif +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */ #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */ /** @@ -585,11 +579,17 @@ typedef struct * @{ */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ +#if defined(RCC_PLLSAI1_SUPPORT) #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(RCC_CCIPR_ADCSEL) #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ +#else +#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */ +#endif /** * @} */ @@ -728,6 +728,7 @@ typedef struct * @} */ +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source * @{ */ @@ -744,7 +745,9 @@ typedef struct /** * @} */ +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) /** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source * @{ @@ -762,6 +765,7 @@ typedef struct /** * @} */ +#endif /* SDMMC1 */ /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source * @{ @@ -784,7 +788,11 @@ typedef struct /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source * @{ */ +#if defined(RCC_CCIPR_ADCSEL) #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ +#else +#define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */ +#endif /** * @} */ @@ -913,6 +921,7 @@ typedef struct * @} */ +#if defined(RCC_PLLP_SUPPORT) /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) * @{ */ @@ -954,6 +963,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLP_SUPPORT */ /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) * @{ @@ -991,6 +1001,7 @@ typedef struct */ #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) * @{ */ @@ -1054,6 +1065,7 @@ typedef struct /** * @} */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) @@ -1170,6 +1182,17 @@ typedef struct * @} */ +#if defined(RCC_CSR_LSIPREDIV) +/** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor + * @{ + */ +#define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */ +#define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */ +/** + * @} + */ +#endif /* RCC_CSR_LSIPREDIV */ + /** Legacy definitions for compatibility purpose @cond 0 */ @@ -1256,6 +1279,7 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) +#if defined(RCC_PLLSAI1_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain @@ -1343,6 +1367,7 @@ typedef struct (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLSAI1_SUPPORT */ /** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain @@ -1379,6 +1404,7 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) +#if defined(RCC_PLLSAI1_SUPPORT) #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain @@ -1647,6 +1673,7 @@ typedef struct ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) /** @@ -1827,8 +1854,8 @@ typedef struct */ #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ - (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos]))) -#else + (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos)))) +#elif defined(RCC_PLLSAI2_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -2048,7 +2075,7 @@ __STATIC_INLINE void LL_RCC_HSE_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); } /** @@ -2087,7 +2114,7 @@ __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) { - return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)); + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); } /** @@ -2117,7 +2144,7 @@ __STATIC_INLINE void LL_RCC_HSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); } /** @@ -2211,7 +2238,7 @@ __STATIC_INLINE void LL_RCC_HSI48_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) { - return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL); } /** @@ -2332,7 +2359,7 @@ __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) { - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); } /** @@ -2342,9 +2369,43 @@ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) { - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); } +#if defined(RCC_BDCR_LSESYSDIS) +/** + * @brief Disable LSE oscillator propagation + * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked + * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +} + +/** + * @brief Enable LSE oscillator propagation + * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +} + +/** + * @brief Check if LSE oscillator propagation is enabled + * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL); +} +#endif /* RCC_BDCR_LSESYSDIS */ /** * @} */ @@ -2380,9 +2441,36 @@ __STATIC_INLINE void LL_RCC_LSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); } +#if defined(RCC_CSR_LSIPREDIV) +/** + * @brief Set LSI division factor + * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv + * @param LSI_PREDIV This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV); +} + +/** + * @brief Get LSI division factor + * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI_PREDIV_1 + * @arg @ref LL_RCC_LSI_PREDIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV)); +} +#endif /* RCC_CSR_LSIPREDIV */ + /** * @} */ @@ -2418,7 +2506,7 @@ __STATIC_INLINE void LL_RCC_MSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); } /** @@ -2467,7 +2555,7 @@ __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) { - return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)); + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL); } /** @@ -2861,7 +2949,7 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale */ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) { - MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF)); + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); } #if defined(UART4) || defined(UART5) @@ -2881,7 +2969,7 @@ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) */ __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) { - MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF)); + MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); } #endif /* UART4 || UART5 */ @@ -2923,7 +3011,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); - MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U))); + MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U))); } /** @@ -2945,6 +3033,7 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); } +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) /** * @brief Configure SAIx clock source @if STM32L4S9xx @@ -2973,6 +3062,7 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); #endif /* RCC_CCIPR2_SAI1SEL */ } +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ #if defined(RCC_CCIPR2_SDMMCSEL) /** @@ -3015,7 +3105,7 @@ __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) * @param RNGxSource This parameter can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI * @@ -3034,7 +3124,7 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_MSI * @@ -3047,12 +3137,13 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) } #endif /* USB_OTG_FS || USB */ +#if defined(RCC_CCIPR_ADCSEL) /** * @brief Configure ADC clock source * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK * @@ -3063,6 +3154,7 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); } +#endif /* RCC_CCIPR_ADCSEL */ #if defined(SWPMI1) /** @@ -3263,8 +3355,8 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); - return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); } /** @@ -3285,9 +3377,10 @@ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) */ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) { - return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U | LPTIMx); + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); } +#if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL) /** * @brief Get SAIx clock source @if STM32L4S9xx @@ -3320,7 +3413,9 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); #endif /* RCC_CCIPR2_SAI1SEL */ } +#endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) /** * @brief Get SDMMCx kernel clock source @@ -3357,6 +3452,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) { return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx)); } +#endif /* SDMMC1 */ /** * @brief Get RNGx clock source @@ -3366,7 +3462,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI * @@ -3386,7 +3482,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_MSI * @@ -3405,7 +3501,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) * @arg @ref LL_RCC_ADC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE - * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK * @@ -3413,7 +3509,12 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { +#if defined(RCC_CCIPR_ADCSEL) return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +#else + (void)ADCx; /* unused */ + return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE); +#endif /* RCC_CCIPR_ADCSEL */ } #if defined(SWPMI1) @@ -3590,7 +3691,7 @@ __STATIC_INLINE void LL_RCC_DisableRTC(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) { - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); } /** @@ -3650,7 +3751,7 @@ __STATIC_INLINE void LL_RCC_PLL_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); } /** @@ -3697,9 +3798,10 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); } +#if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Configure PLL used for SAI domain clock @@ -3805,12 +3907,13 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, { #if defined(RCC_PLLP_DIV_2_31_SUPPORT) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); #else MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ } +#endif /* RCC_PLLP_SUPPORT */ /** * @brief Configure PLL used for 48Mhz domain clock @@ -3857,7 +3960,7 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); } /** @@ -3899,6 +4002,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); } +#if defined(RCC_PLLP_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Get Main PLL division factor for PLLP @@ -3954,6 +4058,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); } #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLP_SUPPORT */ /** * @brief Get Main PLL division factor for PLLQ @@ -4013,6 +4118,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); } +#if defined(RCC_PLLP_SUPPORT) /** * @brief Enable PLL output mapped on SAI domain clock * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI @@ -4036,6 +4142,7 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) { CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); } +#endif /* RCC_PLLP_SUPPORT */ /** * @brief Enable PLL output mapped on 48MHz domain clock @@ -4089,6 +4196,7 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) * @} */ +#if defined(RCC_PLLSAI1_SUPPORT) /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 * @{ */ @@ -4120,7 +4228,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)); + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL); } #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) @@ -4167,7 +4275,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ); } #else /** @@ -4279,7 +4387,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP); } #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** @@ -4428,7 +4536,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); + PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR); } #else /** @@ -4663,6 +4771,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void) /** * @} */ +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2 @@ -4696,7 +4805,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) { - return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)); + return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL); } #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) @@ -4769,7 +4878,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t P { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, - PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); + PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP); } #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) /** @@ -4916,7 +5025,8 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t P __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, + (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM); } #endif /* DSI */ @@ -4969,7 +5079,8 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t P __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, + (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM); MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); } #else @@ -5330,6 +5441,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Clear PLLSAI1 ready interrupt flag * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY @@ -5339,6 +5451,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) { SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5379,7 +5492,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); } /** @@ -5389,7 +5502,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); } /** @@ -5399,7 +5512,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL); } /** @@ -5409,7 +5522,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); } /** @@ -5419,7 +5532,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); } /** @@ -5429,7 +5542,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL); } #if defined(RCC_HSI48_SUPPORT) @@ -5440,10 +5553,11 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Check if PLLSAI1 ready interrupt occurred or not * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY @@ -5451,8 +5565,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5462,7 +5577,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL); } #endif /* RCC_PLLSAI2_SUPPORT */ @@ -5473,7 +5588,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); } /** @@ -5483,7 +5598,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) { - return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); } /** @@ -5493,7 +5608,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL); } /** @@ -5503,7 +5618,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); } /** @@ -5513,7 +5628,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); } /** @@ -5523,7 +5638,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); } /** @@ -5533,7 +5648,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); } /** @@ -5543,7 +5658,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); } /** @@ -5553,7 +5668,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); } /** @@ -5563,7 +5678,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) { - return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); + return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); } /** @@ -5656,6 +5771,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Enable PLLSAI1 ready interrupt * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY @@ -5665,6 +5781,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) { SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5760,6 +5877,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Disable PLLSAI1 ready interrupt * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY @@ -5769,6 +5887,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) { CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5799,7 +5918,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); } /** @@ -5809,7 +5928,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); } /** @@ -5819,7 +5938,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL); } /** @@ -5829,7 +5948,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); } /** @@ -5839,7 +5958,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); } /** @@ -5849,7 +5968,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL); } #if defined(RCC_HSI48_SUPPORT) @@ -5860,10 +5979,11 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); } #endif /* RCC_HSI48_SUPPORT */ +#if defined(RCC_PLLSAI1_SUPPORT) /** * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY @@ -5871,8 +5991,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL); } +#endif /* RCC_PLLSAI1_SUPPORT */ #if defined(RCC_PLLSAI2_SUPPORT) /** @@ -5882,7 +6003,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL); } #endif /* RCC_PLLSAI2_SUPPORT */ @@ -5893,7 +6014,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) { - return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); } /** @@ -5920,11 +6041,15 @@ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#if defined(SAI1) uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif /* SAI1 */ +#if defined(SDMMC1) #if defined(RCC_CCIPR2_SDMMCSEL) uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); #endif uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +#endif /* SDMMC1 */ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); #if defined(USB_OTG_FS) || defined(USB) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); @@ -5971,6 +6096,6 @@ uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); } #endif -#endif /* __STM32L4xx_LL_RCC_H */ +#endif /* STM32L4xx_LL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c index 5ded9ba331..62bc8dee48 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h index 2c49eac9a1..dc13996f0d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c index 1fff8e3f76..33146c2648 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -103,18 +87,7 @@ #define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) -#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ - || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ - || ((__VALUE__) == LL_RTC_MONTH_MAY) \ - || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ - || ((__VALUE__) == LL_RTC_MONTH_JULY) \ - || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ - || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ - || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) @@ -176,18 +149,14 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) if (LL_RTC_EnterInitMode(RTCx) != ERROR) { /* Reset TR, DR and CR registers */ - LL_RTC_WriteReg(RTCx, TR, 0x00000000U); -#if defined(RTC_WAKEUP_SUPPORT) - LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + LL_RTC_WriteReg(RTCx, TR, 0x00000000U); + + LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); + LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); /* Reset All CR bits except CR[2:0] */ -#if defined(RTC_WAKEUP_SUPPORT) LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); -#else - LL_RTC_WriteReg(RTCx, CR, 0x00000000U); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + + LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); @@ -195,6 +164,8 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); +#if defined(STM32L412xx) || defined(STM32L422xx) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Reset ISR register and exit initialization mode */ LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); @@ -203,6 +174,7 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) /* Reset Option register */ LL_RTC_WriteReg(RTCx, OR, 0x00000000U); +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /* Wait till the RTC RSF flag is set */ status = LL_RTC_WaitForSynchro(RTCx); @@ -398,8 +370,9 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) { - RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + RTC_DateStruct->Month = (uint8_t)((RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU); } + if (RTC_Format == LL_RTC_FORMAT_BIN) { assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); @@ -757,7 +730,7 @@ ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) { __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; + uint32_t tmp; /* Check the parameter */ assert_param(IS_RTC_ALL_INSTANCE(RTCx)); @@ -828,7 +801,7 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) { __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; + uint32_t tmp; /* Check the parameter */ assert_param(IS_RTC_ALL_INSTANCE(RTCx)); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h index 41ace5a83e..0c89177b7a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_RTC_H -#define __STM32L4xx_LL_RTC_H +#ifndef STM32L4xx_LL_RTC_H +#define STM32L4xx_LL_RTC_H #ifdef __cplusplus extern "C" { @@ -61,13 +45,13 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU /* Write protection defines */ -#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) -#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) -#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) +#define RTC_WRITE_PROTECTION_DISABLE 0xFFU +#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU +#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U /* Defines used to combine date & time */ #define RTC_OFFSET_WEEKDAY 24U @@ -103,19 +87,19 @@ typedef struct { uint32_t HourFormat; /*!< Specifies the RTC Hours Format. This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetHourFormat(). */ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetAsynchPrescaler(). */ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetSynchPrescaler(). */ } LL_RTC_InitTypeDef; @@ -183,7 +167,7 @@ typedef struct uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A or @ref LL_RTC_ALMB_SetMask() for ALARM B */ @@ -221,8 +205,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ /** * @} */ @@ -251,6 +235,21 @@ typedef struct * @brief Flags defines which can be used with LL_RTC_ReadReg function * @{ */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define LL_RTC_SCR_ITSF RTC_SCR_CITSF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_CSR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ #define LL_RTC_ISR_ITSF RTC_ISR_ITSF #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F @@ -268,6 +267,7 @@ typedef struct #define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF #define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF #define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ @@ -280,10 +280,13 @@ typedef struct #define LL_RTC_CR_WUTIE RTC_CR_WUTIE #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +#if defined(STM32L412xx) || defined(STM32L422xx) +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ @@ -291,13 +294,13 @@ typedef struct /** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY * @{ */ -#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */ -#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ -#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */ -#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */ -#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */ -#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ -#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ /** * @} */ @@ -305,18 +308,18 @@ typedef struct /** @defgroup RTC_LL_EC_MONTH MONTH * @{ */ -#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */ -#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */ -#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */ -#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */ -#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */ -#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */ -#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */ -#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */ -#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */ -#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */ -#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */ -#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ /** * @} */ @@ -344,8 +347,13 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ -#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ +#if defined(STM32L412xx) || defined(STM32L422xx) +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} */ @@ -439,6 +447,82 @@ typedef struct * @} */ +#if defined(STM32L412xx) || defined(STM32L422xx) +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +/** + * @} + */ + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** @defgroup RTC_LL_EC_TAMPER TAMPER * @{ */ @@ -546,14 +630,16 @@ typedef struct * @} */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV * @{ */ #define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ #define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ #define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ /** * @} @@ -613,12 +699,12 @@ typedef struct */ #define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ #define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ /** * @} */ -/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion * @{ */ #define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ @@ -793,7 +879,7 @@ typedef struct * @brief Set Hours format (24 hour/day or AM/PM hour format) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR FMT LL_RTC_SetHourFormat + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat * @param RTCx RTC Instance * @param HourFormat This parameter can be one of the following values: * @arg @ref LL_RTC_HOURFORMAT_24HOUR @@ -807,7 +893,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat /** * @brief Get Hours format (24 hour/day or AM/PM hour format) - * @rmtoll CR FMT LL_RTC_GetHourFormat + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_HOURFORMAT_24HOUR @@ -821,7 +907,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) /** * @brief Select the flag to be routed to RTC_ALARM output * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent * @param RTCx RTC Instance * @param AlarmOutput This parameter can be one of the following values: * @arg @ref LL_RTC_ALARMOUT_DISABLE @@ -837,7 +923,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu /** * @brief Get the flag to be routed to RTC_ALARM output - * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_ALARMOUT_DISABLE @@ -850,6 +936,63 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT); +} + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note Used only when RTC_ALARM is mapped on PC13 @@ -891,7 +1034,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) { /* Set the Initialization mode */ - WRITE_REG(RTCx->ISR, RTC_INIT_MASK); + WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK); } /** @@ -905,11 +1048,12 @@ __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) /* Exit Initialization mode */ WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR POL LL_RTC_SetOutputPolarity + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity * @param RTCx RTC Instance * @param Polarity This parameter can be one of the following values: * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH @@ -923,7 +1067,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari /** * @brief Get Output polarity - * @rmtoll CR POL LL_RTC_GetOutputPolarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH @@ -937,7 +1081,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) /** * @brief Enable Bypass the shadow registers * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass * @param RTCx RTC Instance * @retval None */ @@ -948,7 +1092,7 @@ __STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) /** * @brief Disable Bypass the shadow registers - * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass * @param RTCx RTC Instance * @retval None */ @@ -959,7 +1103,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) /** * @brief Check if Shadow registers bypass is enabled or not. - * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ @@ -972,7 +1116,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR REFCKON LL_RTC_EnableRefClock + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock * @param RTCx RTC Instance * @retval None */ @@ -985,7 +1129,7 @@ __STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR REFCKON LL_RTC_DisableRefClock + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock * @param RTCx RTC Instance * @retval None */ @@ -996,7 +1140,7 @@ __STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) /** * @brief Set Asynchronous prescaler factor - * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler * @param RTCx RTC Instance * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F * @retval None @@ -1008,7 +1152,7 @@ __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t Async /** * @brief Set Synchronous prescaler factor - * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler * @param RTCx RTC Instance * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF * @retval None @@ -1020,7 +1164,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP /** * @brief Get Asynchronous prescaler factor - * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ @@ -1031,7 +1175,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) /** * @brief Get Synchronous prescaler factor - * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ @@ -1042,7 +1186,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) /** * @brief Enable the write protection for RTC registers. - * @rmtoll WPR KEY LL_RTC_EnableWriteProtection + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection * @param RTCx RTC Instance * @retval None */ @@ -1053,7 +1197,7 @@ __STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) /** * @brief Disable the write protection for RTC registers. - * @rmtoll WPR KEY LL_RTC_DisableWriteProtection + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection * @param RTCx RTC Instance * @retval None */ @@ -1063,6 +1207,113 @@ __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); } +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)); +} + +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 isn't available ins VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)); +} + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + /** * @brief Enable RTC_OUT remap * @rmtoll OR OUT_RMP LL_RTC_EnableOutRemap @@ -1084,6 +1335,7 @@ __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP); } +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ /** * @} @@ -1097,7 +1349,7 @@ __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) * @brief Set time format (AM/24-hour or PM notation) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll TR PM LL_RTC_TIME_SetFormat + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat * @param RTCx RTC Instance * @param TimeFormat This parameter can be one of the following values: * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 @@ -1115,7 +1367,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @rmtoll TR PM LL_RTC_TIME_GetFormat + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 @@ -1131,8 +1383,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format - * @rmtoll TR HT LL_RTC_TIME_SetHour\n - * TR HU LL_RTC_TIME_SetHour + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n + * RTC_TR HU LL_RTC_TIME_SetHour * @param RTCx RTC Instance * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 * @retval None @@ -1151,17 +1403,14 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to * Binary format - * @rmtoll TR HT LL_RTC_TIME_GetHour\n - * TR HU LL_RTC_TIME_GetHour + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n + * RTC_TR HU LL_RTC_TIME_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU)); - return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)); + return ((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } /** @@ -1169,8 +1418,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n - * TR MNU LL_RTC_TIME_SetMinute + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n + * RTC_TR MNU LL_RTC_TIME_SetMinute * @param RTCx RTC Instance * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1189,17 +1438,14 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD * to Binary format - * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n - * TR MNU LL_RTC_TIME_GetMinute + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n + * RTC_TR MNU LL_RTC_TIME_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)); - return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)); + return ((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))) >> RTC_TR_MNU_Pos); } /** @@ -1207,8 +1453,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll TR ST LL_RTC_TIME_SetSecond\n - * TR SU LL_RTC_TIME_SetSecond + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n + * RTC_TR SU LL_RTC_TIME_SetSecond * @param RTCx RTC Instance * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1227,17 +1473,14 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD * to Binary format - * @rmtoll TR ST LL_RTC_TIME_GetSecond\n - * TR SU LL_RTC_TIME_GetSecond + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n + * RTC_TR SU LL_RTC_TIME_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)); + return ((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos); } /** @@ -1245,13 +1488,13 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) * @note TimeFormat and Hours should follow the same format - * @rmtoll TR PM LL_RTC_TIME_Config\n - * TR HT LL_RTC_TIME_Config\n - * TR HU LL_RTC_TIME_Config\n - * TR MNT LL_RTC_TIME_Config\n - * TR MNU LL_RTC_TIME_Config\n - * TR ST LL_RTC_TIME_Config\n - * TR SU LL_RTC_TIME_Config + * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n + * RTC_TR HT LL_RTC_TIME_Config\n + * RTC_TR HU LL_RTC_TIME_Config\n + * RTC_TR MNT LL_RTC_TIME_Config\n + * RTC_TR MNU LL_RTC_TIME_Config\n + * RTC_TR ST LL_RTC_TIME_Config\n + * RTC_TR SU LL_RTC_TIME_Config * @param RTCx RTC Instance * @param Format12_24 This parameter can be one of the following values: * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 @@ -1280,19 +1523,19 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll TR HT LL_RTC_TIME_Get\n - * TR HU LL_RTC_TIME_Get\n - * TR MNT LL_RTC_TIME_Get\n - * TR MNU LL_RTC_TIME_Get\n - * TR ST LL_RTC_TIME_Get\n - * TR SU LL_RTC_TIME_Get + * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n + * RTC_TR HU LL_RTC_TIME_Get\n + * RTC_TR MNT LL_RTC_TIME_Get\n + * RTC_TR MNU LL_RTC_TIME_Get\n + * RTC_TR ST LL_RTC_TIME_Get\n + * RTC_TR SU LL_RTC_TIME_Get * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { register uint32_t temp = 0U; - + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ @@ -1302,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) /** * @brief Memorize whether the daylight saving time change has been performed * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore * @param RTCx RTC Instance * @retval None */ @@ -1314,7 +1557,7 @@ __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) /** * @brief Disable memorization whether the daylight saving time change has been performed. * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore * @param RTCx RTC Instance * @retval None */ @@ -1325,7 +1568,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) /** * @brief Check if RTC Day Light Saving stored operation has been enabled or not - * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ @@ -1337,7 +1580,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) /** * @brief Subtract 1 hour (winter time change) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR SUB1H LL_RTC_TIME_DecHour + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour * @param RTCx RTC Instance * @retval None */ @@ -1349,7 +1592,7 @@ __STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) /** * @brief Add 1 hour (summer time change) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ADD1H LL_RTC_TIME_IncHour + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour * @param RTCx RTC Instance * @retval None */ @@ -1367,7 +1610,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit * This conversion can be performed only if no shift operation is pending * (ie. SHFP=0) when PREDIV_S >= SS. - * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ @@ -1381,8 +1624,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note When REFCKON is set, firmware must not write to Shift control register. - * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n - * SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize * @param RTCx RTC Instance * @param ShiftSecond This parameter can be one of the following values: * @arg @ref LL_RTC_SHIFT_SECOND_DELAY @@ -1406,8 +1649,8 @@ __STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSe /** * @brief Set Year in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format - * @rmtoll DR YT LL_RTC_DATE_SetYear\n - * DR YU LL_RTC_DATE_SetYear + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n + * RTC_DR YU LL_RTC_DATE_SetYear * @param RTCx RTC Instance * @param Year Value between Min_Data=0x00 and Max_Data=0x99 * @retval None @@ -1423,22 +1666,19 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format - * @rmtoll DR YT LL_RTC_DATE_GetYear\n - * DR YU LL_RTC_DATE_GetYear + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n + * RTC_DR YU LL_RTC_DATE_GetYear * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)); + return ((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } /** * @brief Set Week day - * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1459,7 +1699,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @brief Get Week day * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit - * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1478,8 +1718,8 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Set Month in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format - * @rmtoll DR MT LL_RTC_DATE_SetMonth\n - * DR MU LL_RTC_DATE_SetMonth + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n + * RTC_DR MU LL_RTC_DATE_SetMonth * @param RTCx RTC Instance * @param Month This parameter can be one of the following values: * @arg @ref LL_RTC_MONTH_JANUARY @@ -1507,8 +1747,8 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format - * @rmtoll DR MT LL_RTC_DATE_GetMonth\n - * DR MU LL_RTC_DATE_GetMonth + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n + * RTC_DR MU LL_RTC_DATE_GetMonth * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_MONTH_JANUARY @@ -1526,17 +1766,14 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)); - return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)); + return ((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } /** * @brief Set Day in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll DR DT LL_RTC_DATE_SetDay\n - * DR DU LL_RTC_DATE_SetDay + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n + * RTC_DR DU LL_RTC_DATE_SetDay * @param RTCx RTC Instance * @param Day Value between Min_Data=0x01 and Max_Data=0x31 * @retval None @@ -1552,28 +1789,25 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll DR DT LL_RTC_DATE_GetDay\n - * DR DU LL_RTC_DATE_GetDay + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n + * RTC_DR DU LL_RTC_DATE_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU)); - return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)); + return ((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } /** * @brief Set date (WeekDay, Day, Month and Year) in BCD format - * @rmtoll DR WDU LL_RTC_DATE_Config\n - * DR MT LL_RTC_DATE_Config\n - * DR MU LL_RTC_DATE_Config\n - * DR DT LL_RTC_DATE_Config\n - * DR DU LL_RTC_DATE_Config\n - * DR YT LL_RTC_DATE_Config\n - * DR YU LL_RTC_DATE_Config + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n + * RTC_DR MT LL_RTC_DATE_Config\n + * RTC_DR MU LL_RTC_DATE_Config\n + * RTC_DR DT LL_RTC_DATE_Config\n + * RTC_DR DU LL_RTC_DATE_Config\n + * RTC_DR YT LL_RTC_DATE_Config\n + * RTC_DR YU LL_RTC_DATE_Config * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1618,20 +1852,20 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. - * @rmtoll DR WDU LL_RTC_DATE_Get\n - * DR MT LL_RTC_DATE_Get\n - * DR MU LL_RTC_DATE_Get\n - * DR DT LL_RTC_DATE_Get\n - * DR DU LL_RTC_DATE_Get\n - * DR YT LL_RTC_DATE_Get\n - * DR YU LL_RTC_DATE_Get + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n + * RTC_DR MT LL_RTC_DATE_Get\n + * RTC_DR MU LL_RTC_DATE_Get\n + * RTC_DR DT LL_RTC_DATE_Get\n + * RTC_DR DU LL_RTC_DATE_Get\n + * RTC_DR YT LL_RTC_DATE_Get\n + * RTC_DR YU LL_RTC_DATE_Get * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { register uint32_t temp = 0U; - + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ @@ -1650,7 +1884,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) /** * @brief Enable Alarm A * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAE LL_RTC_ALMA_Enable + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable * @param RTCx RTC Instance * @retval None */ @@ -1662,7 +1896,7 @@ __STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) /** * @brief Disable Alarm A * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAE LL_RTC_ALMA_Disable + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable * @param RTCx RTC Instance * @retval None */ @@ -1673,10 +1907,10 @@ __STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) /** * @brief Specify the Alarm A masks. - * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: * @arg @ref LL_RTC_ALMA_MASK_NONE @@ -1694,10 +1928,10 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Get the Alarm A masks. - * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask * @param RTCx RTC Instance * @retval Returned value can be can be a combination of the following values: * @arg @ref LL_RTC_ALMA_MASK_NONE @@ -1714,7 +1948,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) /** * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) - * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday * @param RTCx RTC Instance * @retval None */ @@ -1725,7 +1959,7 @@ __STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) /** * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) - * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday * @param RTCx RTC Instance * @retval None */ @@ -1737,8 +1971,8 @@ __STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Day in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n - * ALRMAR DU LL_RTC_ALMA_SetDay + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay * @param RTCx RTC Instance * @param Day Value between Min_Data=0x01 and Max_Data=0x31 * @retval None @@ -1752,22 +1986,19 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get ALARM A Day in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n - * ALRMAR DU LL_RTC_ALMA_GetDay + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU)); - return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } /** * @brief Set ALARM A Weekday - * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1786,7 +2017,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get ALARM A Weekday - * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -1804,7 +2035,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Set Alarm A time format (AM/24-hour or PM notation) - * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat * @param RTCx RTC Instance * @param TimeFormat This parameter can be one of the following values: * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM @@ -1818,7 +2049,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF /** * @brief Get Alarm A time format (AM or PM notation) - * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM @@ -1832,8 +2063,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) /** * @brief Set ALARM A Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format - * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n - * ALRMAR HU LL_RTC_ALMA_SetHour + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour * @param RTCx RTC Instance * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 * @retval None @@ -1847,24 +2078,21 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get ALARM A Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n - * ALRMAR HU LL_RTC_ALMA_GetHour + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU)); - return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } /** * @brief Set ALARM A Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n - * ALRMAR MNU LL_RTC_ALMA_SetMinute + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute * @param RTCx RTC Instance * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1878,24 +2106,21 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get ALARM A Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n - * ALRMAR MNU LL_RTC_ALMA_GetMinute + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)); - return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } /** * @brief Set ALARM A Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n - * ALRMAR SU LL_RTC_ALMA_SetSecond + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond * @param RTCx RTC Instance * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -1909,28 +2134,25 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get ALARM A Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n - * ALRMAR SU LL_RTC_ALMA_GetSecond + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos)); + return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } /** * @brief Set Alarm A Time (hour, minute and second) in BCD format - * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n - * ALRMAR HT LL_RTC_ALMA_ConfigTime\n - * ALRMAR HU LL_RTC_ALMA_ConfigTime\n - * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n - * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n - * ALRMAR ST LL_RTC_ALMA_ConfigTime\n - * ALRMAR SU LL_RTC_ALMA_ConfigTime + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime * @param RTCx RTC Instance * @param Format12_24 This parameter can be one of the following values: * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM @@ -1955,12 +2177,12 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 * @brief Get Alarm B Time (hour, minute and second) in BCD format * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n - * ALRMAR HU LL_RTC_ALMA_GetTime\n - * ALRMAR MNT LL_RTC_ALMA_GetTime\n - * ALRMAR MNU LL_RTC_ALMA_GetTime\n - * ALRMAR ST LL_RTC_ALMA_GetTime\n - * ALRMAR SU LL_RTC_ALMA_GetTime + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ @@ -1973,7 +2195,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) * @brief Set Alarm A Mask the most-significant bits starting at this bit * @note This register can be written only when ALRAE is reset in RTC_CR register, * or in initialization mode. - * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask * @param RTCx RTC Instance * @param Mask Value between Min_Data=0x00 and Max_Data=0xF * @retval None @@ -1985,7 +2207,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma /** * @brief Get Alarm A Mask the most-significant bits starting at this bit - * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ @@ -1996,7 +2218,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) /** * @brief Set Alarm A Sub seconds value - * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF * @retval None @@ -2008,7 +2230,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec /** * @brief Get Alarm A Sub seconds value - * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ @@ -2028,7 +2250,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) /** * @brief Enable Alarm B * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBE LL_RTC_ALMB_Enable + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable * @param RTCx RTC Instance * @retval None */ @@ -2040,7 +2262,7 @@ __STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) /** * @brief Disable Alarm B * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBE LL_RTC_ALMB_Disable + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable * @param RTCx RTC Instance * @retval None */ @@ -2051,10 +2273,10 @@ __STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) /** * @brief Specify the Alarm B masks. - * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: * @arg @ref LL_RTC_ALMB_MASK_NONE @@ -2072,10 +2294,10 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) /** * @brief Get the Alarm B masks. - * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask * @param RTCx RTC Instance * @retval Returned value can be can be a combination of the following values: * @arg @ref LL_RTC_ALMB_MASK_NONE @@ -2092,7 +2314,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) /** * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) - * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday * @param RTCx RTC Instance * @retval None */ @@ -2103,7 +2325,7 @@ __STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) /** * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) - * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday * @param RTCx RTC Instance * @retval None */ @@ -2115,8 +2337,8 @@ __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Day in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n - * ALRMBR DU LL_RTC_ALMB_SetDay + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay * @param RTCx RTC Instance * @param Day Value between Min_Data=0x01 and Max_Data=0x31 * @retval None @@ -2130,22 +2352,19 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get ALARM B Day in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n - * ALRMBR DU LL_RTC_ALMB_GetDay + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU)); - return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } /** * @brief Set ALARM B Weekday - * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay * @param RTCx RTC Instance * @param WeekDay This parameter can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -2164,7 +2383,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get ALARM B Weekday - * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -2182,7 +2401,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Set ALARM B time format (AM/24-hour or PM notation) - * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat * @param RTCx RTC Instance * @param TimeFormat This parameter can be one of the following values: * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM @@ -2196,7 +2415,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF /** * @brief Get ALARM B time format (AM or PM notation) - * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM @@ -2210,8 +2429,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) /** * @brief Set ALARM B Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format - * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n - * ALRMBR HU LL_RTC_ALMB_SetHour + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour * @param RTCx RTC Instance * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 * @retval None @@ -2225,24 +2444,21 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get ALARM B Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n - * ALRMBR HU LL_RTC_ALMB_GetHour + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU)); - return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } /** * @brief Set ALARM B Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n - * ALRMBR MNU LL_RTC_ALMB_SetMinute + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute * @param RTCx RTC Instance * @param Minutes between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -2256,24 +2472,21 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get ALARM B Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n - * ALRMBR MNU LL_RTC_ALMB_GetMinute + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)); - return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } /** * @brief Set ALARM B Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n - * ALRMBR SU LL_RTC_ALMB_SetSecond + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond * @param RTCx RTC Instance * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None @@ -2287,28 +2500,25 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get ALARM B Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n - * ALRMBR SU LL_RTC_ALMB_GetSecond + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); + return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } /** * @brief Set Alarm B Time (hour, minute and second) in BCD format - * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n - * ALRMBR HT LL_RTC_ALMB_ConfigTime\n - * ALRMBR HU LL_RTC_ALMB_ConfigTime\n - * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n - * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n - * ALRMBR ST LL_RTC_ALMB_ConfigTime\n - * ALRMBR SU LL_RTC_ALMB_ConfigTime + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime * @param RTCx RTC Instance * @param Format12_24 This parameter can be one of the following values: * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM @@ -2326,19 +2536,19 @@ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); } /** * @brief Get Alarm B Time (hour, minute and second) in BCD format * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n - * ALRMBR HU LL_RTC_ALMB_GetTime\n - * ALRMBR MNT LL_RTC_ALMB_GetTime\n - * ALRMBR MNU LL_RTC_ALMB_GetTime\n - * ALRMBR ST LL_RTC_ALMB_GetTime\n - * ALRMBR SU LL_RTC_ALMB_GetTime + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ @@ -2351,7 +2561,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) * @brief Set Alarm B Mask the most-significant bits starting at this bit * @note This register can be written only when ALRBE is reset in RTC_CR register, * or in initialization mode. - * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask * @param RTCx RTC Instance * @param Mask Value between Min_Data=0x00 and Max_Data=0xF * @retval None @@ -2363,7 +2573,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma /** * @brief Get Alarm B Mask the most-significant bits starting at this bit - * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ @@ -2374,7 +2584,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) /** * @brief Set Alarm B Sub seconds value - * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF * @retval None @@ -2386,7 +2596,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec /** * @brief Get Alarm B Sub seconds value - * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ @@ -2406,7 +2616,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) /** * @brief Enable internal event timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ITSE LL_RTC_TS_EnableInternalEvent + * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent * @param RTCx RTC Instance * @retval None */ @@ -2418,7 +2628,7 @@ __STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) /** * @brief Disable internal event timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ITSE LL_RTC_TS_DisableInternalEvent + * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent * @param RTCx RTC Instance * @retval None */ @@ -2430,7 +2640,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) /** * @brief Enable Timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSE LL_RTC_TS_Enable + * @rmtoll RTC_CR ITSE LL_RTC_TS_Enable * @param RTCx RTC Instance * @retval None */ @@ -2442,7 +2652,7 @@ __STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) /** * @brief Disable Timestamp * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSE LL_RTC_TS_Disable + * @rmtoll RTC_CR ITSE LL_RTC_TS_Disable * @param RTCx RTC Instance * @retval None */ @@ -2455,7 +2665,7 @@ __STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) * @brief Set Time-stamp event active edge * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting - * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge + * @rmtoll RTC_CR ITSEDGE LL_RTC_TS_SetActiveEdge * @param RTCx RTC Instance * @param Edge This parameter can be one of the following values: * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING @@ -2470,7 +2680,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) /** * @brief Get Time-stamp event active edge * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge + * @rmtoll RTC_CR ITSEDGE LL_RTC_TS_GetActiveEdge * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING @@ -2483,7 +2693,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) /** * @brief Get Timestamp AM/PM notation (AM or 24-hour format) - * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_TS_TIME_FORMAT_AM @@ -2497,8 +2707,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Hours in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll TSTR HT LL_RTC_TS_GetHour\n - * TSTR HU LL_RTC_TS_GetHour + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n + * RTC_TSTR HU LL_RTC_TS_GetHour * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ @@ -2510,8 +2720,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Minutes in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n - * TSTR MNU LL_RTC_TS_GetMinute + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n + * RTC_TSTR HU LL_RTC_TS_GetMinute * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2523,8 +2733,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Seconds in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n - * TSTR SU LL_RTC_TS_GetSecond + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n + * RTC_TSTR HU LL_RTC_TS_GetSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ @@ -2537,12 +2747,12 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @brief Get Timestamp time (hour, minute and second) in BCD format * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND * are available to get independently each parameter. - * @rmtoll TSTR HT LL_RTC_TS_GetTime\n - * TSTR HU LL_RTC_TS_GetTime\n - * TSTR MNT LL_RTC_TS_GetTime\n - * TSTR MNU LL_RTC_TS_GetTime\n - * TSTR ST LL_RTC_TS_GetTime\n - * TSTR SU LL_RTC_TS_GetTime + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n + * RTC_TSTR HU LL_RTC_TS_GetTime\n + * RTC_TSTR MNT LL_RTC_TS_GetTime\n + * RTC_TSTR MNU LL_RTC_TS_GetTime\n + * RTC_TSTR ST LL_RTC_TS_GetTime\n + * RTC_TSTR SU LL_RTC_TS_GetTime * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ @@ -2554,7 +2764,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Week day - * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_WEEKDAY_MONDAY @@ -2573,8 +2783,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Month in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format - * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n - * TSDR MU LL_RTC_TS_GetMonth + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n + * RTC_TSDR MU LL_RTC_TS_GetMonth * @param RTCx RTC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_RTC_MONTH_JANUARY @@ -2598,8 +2808,8 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) /** * @brief Get Timestamp Day in BCD format * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll TSDR DT LL_RTC_TS_GetDay\n - * TSDR DU LL_RTC_TS_GetDay + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n + * RTC_TSDR DU LL_RTC_TS_GetDay * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ @@ -2612,11 +2822,11 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. - * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n - * TSDR MT LL_RTC_TS_GetDate\n - * TSDR MU LL_RTC_TS_GetDate\n - * TSDR DT LL_RTC_TS_GetDate\n - * TSDR DU LL_RTC_TS_GetDate + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n + * RTC_TSDR MT LL_RTC_TS_GetDate\n + * RTC_TSDR MU LL_RTC_TS_GetDate\n + * RTC_TSDR DT LL_RTC_TS_GetDate\n + * RTC_TSDR DU LL_RTC_TS_GetDate * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ @@ -2627,7 +2837,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) /** * @brief Get time-stamp sub second value - * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond + * @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ @@ -2636,10 +2846,1216 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } +/** + * @} + */ + +#if defined(RTC_WAKEUP_SUPPORT) +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Set Wakeup auto-clear value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @rmtoll RTC_WUTR WUTOCLR LL_RTC_WAKEUP_SetAutoClr + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoClr(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUTOCLR, (Value << RTC_WUTR_WUTOCLR_Pos)); +} + +/** + * @brief Get Wakeup auto-clear value + * @rmtoll RTC_WUTR WUTOCLR LL_RTC_WAKEUP_GetAutoClr + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoClr(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->WUTR, RTC_WUTR_WUTOCLR)) >> RTC_WUTR_WUTOCLR_Pos); +} +#endif /* defined(STM32L412xx) || defined(STM32L422xx) */ + +/** + * @} + */ +#endif /* RTC_WAKEUP_SUPPORT */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Enable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Disable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Check if Calibration Low Power is enabled or not + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)); +} +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ +/** + * @} + */ + + +#if defined(STM32L412xx) || defined(STM32L422xx) +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Enable + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Disable + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP2MF LL_RTC_TAMPER_EnableMask + * @param TAMPx TAMP Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask) +{ + SET_BIT(TAMPx->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMP_CR2 TAMP2MF LL_RTC_TAMPER_DisableMask + * @param TAMPx TAMP Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask) +{ + CLEAR_BIT(TAMPx->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param TAMPx TAMP Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param TAMPx TAMP Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param TAMPx TAMP Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR2, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param TAMPx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)(&(TAMPx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param TAMPx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)(&(TAMPx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CITSF); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)); +} + +/** + * @brief Get Internal Time-stamp masked flag. + * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)); +} + + + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)); +} + +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); +} + + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + return (READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)); +} + +/** + * @} + */ + +#else /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + #if defined(RTC_TAMPCR_TAMPTS) /** * @brief Activate timestamp on tamper detection event - * @rmtoll TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper * @param RTCx RTC Instance * @retval None */ @@ -2650,7 +4066,7 @@ __STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) /** * @brief Disable timestamp on tamper detection event - * @rmtoll TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper * @param RTCx RTC Instance * @retval None */ @@ -2660,10 +4076,6 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) } #endif /* RTC_TAMPCR_TAMPTS */ -/** - * @} - */ - /** @defgroup RTC_LL_EF_Tamper Tamper * @{ */ @@ -2675,10 +4087,10 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * TAMPCR TAMP3E LL_RTC_TAMPER_Enable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2693,10 +4105,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) * TAMPCR TAMP3E LL_RTC_TAMPER_Disable * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2712,10 +4124,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) @@ -2730,10 +4142,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask * @param RTCx RTC Instance * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) @@ -2748,10 +4160,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2766,10 +4178,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2915,10 +4327,10 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 - * + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2933,10 +4345,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 - * + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2948,112 +4360,6 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * @} */ -#if defined(RTC_WAKEUP_SUPPORT) -/** @defgroup RTC_LL_EF_Wakeup Wakeup - * @{ - */ - -/** - * @brief Enable Wakeup timer - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_WUTE); -} - -/** - * @brief Disable Wakeup timer - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); -} - -/** - * @brief Check if Wakeup timer is enabled or not - * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); -} - -/** - * @brief Select Wakeup clock - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 - * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock - * @param RTCx RTC Instance - * @param WakeupClock This parameter can be one of the following values: - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) -{ - MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); -} - -/** - * @brief Get Wakeup clock - * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); -} - -/** - * @brief Set Wakeup auto-reload value - * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR - * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload - * @param RTCx RTC Instance - * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) -{ - MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); -} - -/** - * @brief Get Wakeup auto-reload value - * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); -} - -/** - * @} - */ -#endif /* RTC_WAKEUP_SUPPORT */ - #if defined(RTC_BACKUP_SUPPORT) /** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers * @{ @@ -3165,138 +4471,13 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back */ #endif /* RTC_BACKUP_SUPPORT */ -/** @defgroup RTC_LL_EF_Calibration Calibration - * @{ - */ - -/** - * @brief Set Calibration output frequency (1 Hz or 512 Hz) - * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n - * CR COSEL LL_RTC_CAL_SetOutputFreq - * @param RTCx RTC Instance - * @param Frequency This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ - * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) -{ - MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); -} - -/** - * @brief Get Calibration output frequency (1 Hz or 512 Hz) - * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n - * CR COSEL LL_RTC_CAL_GetOutputFreq - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ - * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); -} - -/** - * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALP LL_RTC_CAL_SetPulse - * @param RTCx RTC Instance - * @param Pulse This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE - * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); -} - -/** - * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) - * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); -} - -/** - * @brief Set the calibration cycle period - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n - * CALR CALW16 LL_RTC_CAL_SetPeriod - * @param RTCx RTC Instance - * @param Period This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_PERIOD_32SEC - * @arg @ref LL_RTC_CALIB_PERIOD_16SEC - * @arg @ref LL_RTC_CALIB_PERIOD_8SEC - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); -} - -/** - * @brief Get the calibration cycle period - * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n - * CALR CALW16 LL_RTC_CAL_GetPeriod - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_PERIOD_32SEC - * @arg @ref LL_RTC_CALIB_PERIOD_16SEC - * @arg @ref LL_RTC_CALIB_PERIOD_8SEC - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); -} - -/** - * @brief Set Calibration minus - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALM LL_RTC_CAL_SetMinus - * @param RTCx RTC Instance - * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); -} - -/** - * @brief Get Calibration minus - * @rmtoll CALR CALM LL_RTC_CAL_GetMinus - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); -} - -/** - * @} - */ - /** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management * @{ */ /** * @brief Get Internal Time-stamp flag - * @rmtoll ISR ITSF LL_RTC_IsActiveFlag_ITS + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ @@ -3620,7 +4801,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) /** * @brief Enable Time-stamp interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSIE LL_RTC_EnableIT_TS + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS * @param RTCx RTC Instance * @retval None */ @@ -3632,7 +4813,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) /** * @brief Disable Time-stamp interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSIE LL_RTC_DisableIT_TS + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS * @param RTCx RTC Instance * @retval None */ @@ -3645,7 +4826,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) /** * @brief Enable Wakeup timer interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT * @param RTCx RTC Instance * @retval None */ @@ -3657,7 +4838,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) /** * @brief Disable Wakeup timer interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT * @param RTCx RTC Instance * @retval None */ @@ -3670,7 +4851,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) /** * @brief Enable Alarm B interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB * @param RTCx RTC Instance * @retval None */ @@ -3682,7 +4863,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) /** * @brief Disable Alarm B interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB * @param RTCx RTC Instance * @retval None */ @@ -3694,7 +4875,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) /** * @brief Enable Alarm A interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA * @param RTCx RTC Instance * @retval None */ @@ -3706,7 +4887,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) /** * @brief Disable Alarm A interrupt * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA * @param RTCx RTC Instance * @retval None */ @@ -3914,6 +5095,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) * @} */ +#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -3957,6 +5140,6 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); } #endif -#endif /* __STM32L4xx_LL_RTC_H */ +#endif /* STM32L4xx_LL_RTC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c index c245cca9cb..26e08b769b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c @@ -2,47 +2,48 @@ ****************************************************************************** * @file stm32l4xx_ll_sdmmc.c * @author MCD Application Team - * @brief SDMMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following + * @brief SDMMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following * functionalities of the SDMMC peripheral: * + Initialization/de-initialization functions * + I/O operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### SDMMC peripheral features ##### - ============================================================================== - [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2 + ============================================================================== + [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA devices. - + [..] The SDMMC features include the following: - (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support - for three different data bus modes: 1-bit (default), 4-bit and 8-bit - (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) - (+) Full compliance with SD Memory Card Specifications Version 2.0 - (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two - different data bus modes: 1-bit (default) and 4-bit - (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol - Rev1.1) - (+) Data transfer up to 48 MHz for the 8 bit mode - (+) Data and command output enable signals to control external bidirectional drivers. - - + (+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support + for three different databus modes: 1-bit (default), 4-bit and 8-bit. + (+) Full compatibility with previous versions of MultiMediaCards (backward compatibility). + (+) Full compliance with SD memory card specifications version 4.1. + (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and + UHS-II mode not supported). + (+) Full compliance with SDIO card specification version 4.0. Card support + for two different databus modes: 1-bit (default) and 4-bit. + (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and + UHS-II mode not supported). + (+) Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed). + (+) Data and command output enable signals to control external bidirectional drivers + ##### How to use this driver ##### ============================================================================== [..] - This driver is a considered as a driver of service for external devices drivers + This driver is a considered as a driver of service for external devices drivers that interfaces with the SDMMC peripheral. - According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs + According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs is used in the device's driver to perform SDMMC operations and functionalities. - + This driver is almost transparent for the final user, it is only used to implement other functionalities of the external device. - + [..] (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the @@ -50,32 +51,37 @@ The SDMMC peripheral uses two clock signals: (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) (++) APB2 bus clock (PCLK2) - + -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) for STM32L496xG and STM32L4A6xG Frequency(PCLK2) >= (3 / 4 x Frequency(SDMMC_CK)) otherwise - + (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC peripheral. - (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) + (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) function and disable it using the function SDMMC_PowerState_OFF(SDMMCx). - + (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros. - - (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) - and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. - - (+) When using the DMA mode - (++) Configure the DMA in the MSP layer of the external device - (++) Active the needed channel Request - (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro - __SDMMC_DMA_DISABLE(). - - (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDMMC_SendCommand(SDMMCx), + + (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) + and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. + + (+) When using the DMA mode + (++) On STM32L4Rx/STM32L4Sxx devices + (+++) Configure the IDMA mode (Single buffer or double) + (+++) Configure the buffer address + (+++) Configure Data Path State Machine + (++) On other devices + (+++) Configure the DMA in the MSP layer of the external device + (+++) Active the needed channel Request + (+++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro + __SDMMC_DMA_DISABLE(). + + (+) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDMMC_SendCommand(SDMMCx), SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has - to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according + to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according to the selected command to be sent. The parameters that should be filled are: (++) Command Argument @@ -83,16 +89,16 @@ (++) Command Response type (++) Command Wait (++) CPSM Status (Enable or Disable). - + -@@- To check if the command is well received, read the SDMMC_CMDRESP register using the SDMMC_GetCommandResponse(). The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the SDMMC_GetResponse() function. - - (+) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), + + (+) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions. - + *** Read Operations *** ======================= [..] @@ -105,14 +111,14 @@ (++) Data Transfer direction: should be from card (To SDMMC) (++) Data Transfer mode (++) DPSM Status (Enable or Disable) - + (#) Configure the SDMMC resources to receive the data from the card according to selected transfer mode (Refer to Step 8, 9 and 10). - + (#) Send the selected Read command (refer to step 11). - + (#) Use the SDMMC flags/interrupts to check the transfer status. - + *** Write Operations *** ======================== [..] @@ -125,53 +131,37 @@ (++) Data Transfer direction: should be to card (To CARD) (++) Data Transfer mode (++) DPSM Status (Enable or Disable) - - (#) Configure the SDMMC resources to send the data to the card according to + + (#) Configure the SDMMC resources to send the data to the card according to selected transfer mode. - + (#) Send the selected Write command. - + (#) Use the SDMMC flags/interrupts to check the transfer status. - + *** Command management operations *** ===================================== [..] - (#) The commands used for Read/Write/Erase operations are managed in - separate functions. + (#) The commands used for Read/Write/Erase operations are managed in + separate functions. Each function allows to send the needed command with the related argument, then check the response. By the same approach, you could implement a command and check the response. - + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -187,7 +177,7 @@ * @{ */ -#if defined (HAL_SD_MODULE_ENABLED) +#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -207,15 +197,15 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ * @{ */ -/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization/de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ @@ -224,14 +214,16 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ * @brief Initializes the SDMMC according to the specified * parameters in the SDMMC_InitTypeDef and create the associated handle. * @param SDMMCx: Pointer to SDMMC register base - * @param Init: SDMMC initialization structure + * @param Init: SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) { + uint32_t tmpreg = 0; + /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); - assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ @@ -239,23 +231,20 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); - + /* Set SDMMC configuration parameters */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + tmpreg |= Init.ClockBypass; +#endif + tmpreg |= (Init.ClockEdge |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv + ); + /* Write to SDMMC CLKCR */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ - Init.ClockDiv); -#else - MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ - Init.ClockBypass |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ - Init.ClockDiv); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); return HAL_OK; } @@ -265,15 +254,15 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) * @} */ -/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### I/O operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the SDMMC data + This subsection provides a set of functions allowing to manage the SDMMC data transfers. @endverbatim @@ -281,25 +270,25 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) */ /** - * @brief Read data (word) from Rx FIFO in blocking mode (polling) + * @brief Read data (word) from Rx FIFO in blocking mode (polling) * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) { - /* Read data from Rx FIFO */ + /* Read data from Rx FIFO */ return (SDMMCx->FIFO); } /** - * @brief Write data (word) to Tx FIFO in blocking mode (polling) + * @brief Write data (word) to Tx FIFO in blocking mode (polling) * @param SDMMCx: Pointer to SDMMC register base * @param pWriteData: pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) -{ - /* Write data to FIFO */ +{ + /* Write data to FIFO */ SDMMCx->FIFO = *pWriteData; return HAL_OK; @@ -309,15 +298,15 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) * @} */ -/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions - * @brief management functions +/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the SDMMC data + This subsection provides a set of functions allowing to control the SDMMC data transfers. @endverbatim @@ -325,41 +314,43 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) */ /** - * @brief Set SDMMC Power state to ON. + * @brief Set SDMMC Power state to ON. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) -{ - /* Set power state to ON */ +{ + /* Set power state to ON */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; - #else SDMMCx->POWER = SDMMC_POWER_PWRCTRL; - #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - return HAL_OK; + + /* 1ms: required power up waiting time before starting the SD initialization + sequence */ + HAL_Delay(2); + + return HAL_OK; } #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** - * @brief Set SDMMC Power state to Power-Cycle. + * @brief Set SDMMC Power state to Power-Cycle. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx) -{ - /* Set power state to Power Cycle*/ +{ + /* Set power state to Power Cycle*/ SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1; - - return HAL_OK; + + return HAL_OK; } #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** - * @brief Set SDMMC Power state to OFF. + * @brief Set SDMMC Power state to OFF. * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ @@ -368,23 +359,21 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) /* Set power state to OFF */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL); - #else SDMMCx->POWER = (uint32_t)0x00000000; - #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - + return HAL_OK; } /** - * @brief Get SDMMC Power state. + * @brief Get SDMMC Power state. * @param SDMMCx: Pointer to SDMMC register base - * @retval Power status of the controller. The returned value can be one of the + * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF * - 0x02: Power UP - * - 0x03: Power ON + * - 0x03: Power ON */ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) { @@ -393,14 +382,16 @@ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) /** * @brief Configure the SDMMC command path according to the specified parameters in - * SDMMC_CmdInitTypeDef structure and send the command + * SDMMC_CmdInitTypeDef structure and send the command * @param SDMMCx: Pointer to SDMMC register base - * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains + * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) { + uint32_t tmpreg = 0; + /* Check the parameters */ assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex)); assert_param(IS_SDMMC_RESPONSE(Command->Response)); @@ -411,12 +402,14 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef SDMMCx->ARG = Command->Argument; /* Set SDMMC command parameters */ + tmpreg |= (uint32_t)(Command->CmdIndex |\ + Command->Response |\ + Command->WaitForInterrupt |\ + Command->CPSM); + /* Write to SDMMC CMD register */ - MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, Command->CmdIndex |\ - Command->Response |\ - Command->WaitForInterrupt |\ - Command->CPSM); - + MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); + return HAL_OK; } @@ -433,38 +426,40 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) /** * @brief Return the response received from the card for the last command - * @param SDMMCx: Pointer to SDMMC register base - * @param Response: Specifies the SDMMC response register. + * @param SDMMCx: Pointer to SDMMC register base + * @param Response: Specifies the SDMMC response register. * This parameter can be one of the following values: * @arg SDMMC_RESP1: Response Register 1 * @arg SDMMC_RESP2: Response Register 2 * @arg SDMMC_RESP3: Response Register 3 - * @arg SDMMC_RESP4: Response Register 4 + * @arg SDMMC_RESP4: Response Register 4 * @retval The Corresponding response register value */ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) { - __IO uint32_t tmp = 0; + uint32_t tmp; /* Check the parameters */ assert_param(IS_SDMMC_RESP(Response)); - + /* Get the response */ - tmp = (uint32_t)&(SDMMCx->RESP1) + Response; - + tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; + return (*(__IO uint32_t *) tmp); -} +} /** - * @brief Configure the SDMMC data path according to the specified + * @brief Configure the SDMMC data path according to the specified * parameters in the SDMMC_DataInitTypeDef. - * @param SDMMCx: Pointer to SDMMC register base - * @param Data : pointer to a SDMMC_DataInitTypeDef structure + * @param SDMMCx: Pointer to SDMMC register base + * @param Data : pointer to a SDMMC_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) { + uint32_t tmpreg = 0; + /* Check the parameters */ assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength)); assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); @@ -479,11 +474,13 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* SDMMCx->DLEN = Data->DataLength; /* Set the SDMMC data configuration parameters */ + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + Data->TransferDir |\ + Data->TransferMode |\ + Data->DPSM); + /* Write to SDMMC DCTRL */ - MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\ - Data->TransferDir |\ - Data->TransferMode |\ - Data->DPSM); + MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); return HAL_OK; @@ -501,7 +498,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) /** * @brief Get the FIFO data - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval Data received */ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) @@ -511,7 +508,7 @@ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) /** * @brief Sets one of the two options of inserting read wait interval. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. * This parameter can be: * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK @@ -525,8 +522,8 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM /* Set SDMMC read wait mode */ MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); - - return HAL_OK; + + return HAL_OK; } /** @@ -534,13 +531,13 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM */ -/** @defgroup HAL_SDMMC_LL_Group4 Command management functions - * @brief Data transfers functions +/** @defgroup HAL_SDMMC_LL_Group4 Command management functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### Commands management functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to manage the needed commands. @@ -550,22 +547,22 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM /** * @brief Send the Data Block Lenght command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)BlockSize; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); @@ -574,22 +571,22 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) /** * @brief Send the Read Single Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); @@ -598,22 +595,22 @@ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) /** * @brief Send the Read Multi Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); @@ -622,22 +619,22 @@ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) /** * @brief Send the Write Single Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); @@ -646,22 +643,22 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) /** * @brief Send the Write Multi Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); @@ -670,22 +667,22 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) /** * @brief Send the Start Address Erase command for SD and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)StartAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); @@ -694,22 +691,22 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) /** * @brief Send the End Address Erase command for SD and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)EndAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); @@ -718,22 +715,22 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) /** * @brief Send the Start Address Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)StartAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); @@ -742,22 +739,22 @@ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) /** * @brief Send the End Address Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ + uint32_t errorstate; + + /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)EndAdd; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); @@ -766,22 +763,22 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) /** * @brief Send the Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = 0; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); @@ -790,47 +787,57 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Stop Transfer command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD12 STOP_TRANSMISSION */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDSTOP_ENABLE(SDMMCx); + __SDMMC_CMDTRANS_DISABLE(SDMMCx); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDSTOP_DISABLE(SDMMCx); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + return errorstate; } /** * @brief Send the Select Deselect command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param addr: Address of the card to be selected + * @param SDMMCx: Pointer to SDMMC register base + * @param addr: Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ sdmmc_cmdinit.Argument = (uint32_t)Addr; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); @@ -839,21 +846,21 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) /** * @brief Send the Go Idle State command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - sdmmc_cmdinit.Argument = 0; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdError(SDMMCx); @@ -862,14 +869,14 @@ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Operating Condition command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD8 to verify SD card interface operating condition */ /* Argument: - [31:12]: Reserved (shall be set to '0') - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) @@ -880,8 +887,8 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp7(SDMMCx); @@ -889,25 +896,25 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) } /** - * @brief Send the Application command to verify that that the next command + * @brief Send the Application command to verify that that the next command * is an application specific com-mand rather than a standard command * and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param Argument: Command Argument + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + sdmmc_cmdinit.Argument = (uint32_t)Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ /* If there is a HAL_ERROR, it is a MMC card, else it is a SD card: SD card 2.0 (voltage range mismatch) @@ -918,17 +925,17 @@ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) } /** - * @brief Send the command asking the accessed card to send its operating + * @brief Send the command asking the accessed card to send its operating * condition register (OCR) - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) sdmmc_cmdinit.Argument = Argument; #else @@ -938,8 +945,8 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); @@ -955,15 +962,15 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); @@ -978,16 +985,16 @@ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD51 SD_APP_SEND_SCR */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); @@ -1002,16 +1009,16 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD2 ALL_SEND_CID */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); @@ -1027,16 +1034,16 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD9 SEND_CSD */ sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); @@ -1045,23 +1052,23 @@ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the Send CSD command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param pRCA: Card RCA + * @param SDMMCx: Pointer to SDMMC register base + * @param pRCA: Card RCA * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + /* Send CMD3 SD_CMD_SET_REL_ADDR */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); @@ -1077,15 +1084,15 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); @@ -1094,21 +1101,21 @@ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the Status register command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - sdmmc_cmdinit.Argument = 0; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); @@ -1116,24 +1123,24 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) } /** - * @brief Sends host capacity support information and activates the card's + * @brief Sends host capacity support information and activates the card's * initialization process. Send SDMMC_CMD_SEND_OP_COND command - * @param SDIOx: Pointer to SDIO register base + * @param SDMMCx: Pointer to SDMMC register base * @parame Argument: Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); @@ -1142,22 +1149,24 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand - * @param SDIOx: Pointer to SDIO register base + * @param SDMMCx: Pointer to SDMMC register base * @parame Argument: Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - - sdmmc_cmdinit.Argument = Argument; + uint32_t errorstate; + + /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ + /* CMD Response: R1 */ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); @@ -1166,7 +1175,7 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** - * @brief Send the command asking the accessed card to send its operating + * @brief Send the command asking the accessed card to send its operating * condition register (OCR) * @param None * @retval HAL status @@ -1174,32 +1183,56 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; - + uint32_t errorstate; + sdmmc_cmdinit.Argument = 0x00000000; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT); return errorstate; } -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +/** + * @brief Send the Send EXT_CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); + + return errorstate; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ -/* Private function ----------------------------------------------------------*/ +/* Private function ----------------------------------------------------------*/ /** @addtogroup SD_Private_Functions * @{ */ - + /** * @brief Checks for error conditions for CMD0. * @param hsd: SD handle @@ -1209,74 +1242,82 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); - + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); - + /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - + return SDMMC_ERROR_NONE; } /** * @brief Checks for error conditions for R1 response. * @param hsd: SD handle - * @param SD_CMD: The sent command index + * @param SD_CMD: The sent command index * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) { uint32_t response_r1; - uint32_t flags; - - flags = SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT; + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ - register uint32_t count = Timeout * (SystemCoreClock / 8 /1000); - + register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, flags)); - + sta_reg = SDMMCx->STA; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +#else + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - + return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - + return SDMMC_ERROR_CMD_CRC_FAIL; } - + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + /* Check response received is of desired command */ if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) { return SDMMC_ERROR_CMD_CRC_FAIL; } - - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - + /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - + if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) { return SDMMC_ERROR_NONE; @@ -1366,29 +1407,31 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ */ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); - + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); - + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - + return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - + return SDMMC_ERROR_CMD_CRC_FAIL; } else @@ -1408,31 +1451,33 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) */ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) { + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); - + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); - + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - + return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else - { + { /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } - + return SDMMC_ERROR_NONE; } @@ -1440,56 +1485,62 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) * @brief Checks for error conditions for R6 (RCA) response. * @param hsd: SD handle * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative - * address RCA + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) { uint32_t response_r1; - + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); - + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); - + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - + return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - + return SDMMC_ERROR_CMD_CRC_FAIL; } - + else + { + /* Nothing to do */ + } + /* Check response received is of desired command */ if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) { return SDMMC_ERROR_CMD_CRC_FAIL; } - + /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - + /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - + if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) { *pRCA = (uint16_t) (response_r1 >> 16); - + return SDMMC_ERROR_NONE; } else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) @@ -1513,54 +1564,56 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ */ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) { + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); - + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - + return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - + return SDMMC_ERROR_CMD_CRC_FAIL; } + else + { + /* Nothing to do */ + } if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); } - + return SDMMC_ERROR_NONE; - + } /** * @} */ -/** - * @} - */ - -#endif /* (HAL_SD_MODULE_ENABLED) */ +#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h index 41996af8e0..c28cbaf8b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h @@ -2,40 +2,24 @@ ****************************************************************************** * @file stm32l4xx_ll_sdmmc.h * @author MCD Application Team - * @brief Header file of low layer SDMMC HAL module. + * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SDMMC_H -#define __STM32L4xx_LL_SDMMC_H +#ifndef STM32L4xx_LL_SDMMC_H +#define STM32L4xx_LL_SDMMC_H #ifdef __cplusplus extern "C" { @@ -52,15 +36,15 @@ /** @addtogroup SDMMC_LL * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types * @{ */ - -/** - * @brief SDMMC Configuration Structure definition + +/** + * @brief SDMMC Configuration Structure definition */ typedef struct { @@ -84,33 +68,33 @@ typedef struct This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_Transceiver */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -}SDMMC_InitTypeDef; - -/** - * @brief SDMMC Command Control structure +}SDMMC_InitTypeDef; + + +/** + * @brief SDMMC Command Control structure */ -typedef struct +typedef struct { uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register. */ - uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and + uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and Max_Data = 64 */ uint32_t Response; /*!< Specifies the SDMMC response type. This parameter can be a value of @ref SDMMC_LL_Response_Type */ - uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is + uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ @@ -120,25 +104,25 @@ typedef struct }SDMMC_CmdInitTypeDef; -/** - * @brief SDMMC Data Control structure +/** + * @brief SDMMC Data Control structure */ typedef struct { uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ - + uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ - + uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ - + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ - + uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_DPSM_State */ @@ -147,7 +131,7 @@ typedef struct /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants * @{ @@ -160,12 +144,12 @@ typedef struct #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ @@ -177,7 +161,7 @@ typedef struct #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ -#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out +#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ @@ -189,20 +173,20 @@ typedef struct #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ -/** - * @brief SDMMC Commands Index +/** + * @brief SDMMC Commands Index */ #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -214,17 +198,17 @@ typedef struct #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ @@ -234,40 +218,40 @@ typedef struct #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather +#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card +#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ -/** +/** * @brief Following commands are SD Card Specific commands. - * SDMMC_APP_CMD should be sent before sending these commands. + * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ -/** +/** * @brief Following commands are SD Card Specific security commands. - * SDMMC_CMD_APP_CMD should be sent before sending these commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) @@ -281,8 +265,8 @@ typedef struct #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) -/** - * @brief Masks for errors Card Status R1 (OCR Register) +/** + * @brief Masks for errors Card Status R1 (OCR Register) */ #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) @@ -305,8 +289,8 @@ typedef struct #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) -/** - * @brief Masks for R6 Response +/** + * @brief Masks for R6 Response */ #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) @@ -316,8 +300,10 @@ typedef struct #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) +#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -343,7 +329,7 @@ typedef struct #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) -/** +/** * @brief Command Class supported */ #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) @@ -359,7 +345,7 @@ typedef struct #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ - ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) + ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) /** * @} */ @@ -369,13 +355,13 @@ typedef struct * @{ */ #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) -#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS +#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ - ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) + ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) /** * @} - */ + */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving @@ -385,7 +371,7 @@ typedef struct #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ - ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) + ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) /** * @} */ @@ -398,12 +384,33 @@ typedef struct #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ - ((WIDE) == SDMMC_BUS_WIDE_4B) || \ - ((WIDE) == SDMMC_BUS_WIDE_8B)) + ((WIDE) == SDMMC_BUS_WIDE_4B) || \ + ((WIDE) == SDMMC_BUS_WIDE_8B)) /** * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SDMMC_LL_Speed_Mode + * @{ + */ +#define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) +#define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) +#define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) +#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) +#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) + +#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ + ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ + ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ + ((MODE) == SDMMC_SPEED_MODE_DDR)) + +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control * @{ */ @@ -411,24 +418,23 @@ typedef struct #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ - ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) + ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) /** * @} */ - + /** @defgroup SDMMC_LL_Clock_Division Clock Division * @{ */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ -#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400) +#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) #else -#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) +#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} - */ - + */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @defgroup SDMMC_LL_Transceiver Transceiver @@ -447,7 +453,7 @@ typedef struct /** @defgroup SDMMC_LL_Command_Index Command Index * @{ */ -#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) +#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) /** * @} */ @@ -460,8 +466,8 @@ typedef struct #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ - ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ - ((RESPONSE) == SDMMC_RESPONSE_LONG)) + ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ + ((RESPONSE) == SDMMC_RESPONSE_LONG)) /** * @} */ @@ -470,12 +476,12 @@ typedef struct * @{ */ #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) -#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT +#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ - ((WAIT) == SDMMC_WAIT_IT) || \ - ((WAIT) == SDMMC_WAIT_PEND)) + ((WAIT) == SDMMC_WAIT_IT) || \ + ((WAIT) == SDMMC_WAIT_PEND)) /** * @} */ @@ -487,10 +493,10 @@ typedef struct #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ - ((CPSM) == SDMMC_CPSM_ENABLE)) + ((CPSM) == SDMMC_CPSM_ENABLE)) /** * @} - */ + */ /** @defgroup SDMMC_LL_Response_Registers Response Register * @{ @@ -501,15 +507,15 @@ typedef struct #define SDMMC_RESP4 ((uint32_t)0x0000000CU) #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ - ((RESP) == SDMMC_RESP2) || \ - ((RESP) == SDMMC_RESP3) || \ - ((RESP) == SDMMC_RESP4)) + ((RESP) == SDMMC_RESP2) || \ + ((RESP) == SDMMC_RESP3) || \ + ((RESP) == SDMMC_RESP4)) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode * @{ */ -#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) +#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) @@ -518,14 +524,11 @@ typedef struct * @} */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ /** @defgroup SDMMC_LL_Data_Length Data Lenght * @{ */ -#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) /** * @} */ @@ -544,26 +547,26 @@ typedef struct #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) + ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) /** * @} */ @@ -575,7 +578,7 @@ typedef struct #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ - ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) + ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) /** * @} */ @@ -591,7 +594,7 @@ typedef struct #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ - ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) + ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} */ @@ -603,11 +606,11 @@ typedef struct #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ - ((DPSM) == SDMMC_DPSM_ENABLE)) + ((DPSM) == SDMMC_DPSM_ENABLE)) /** * @} */ - + /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode * @{ */ @@ -618,47 +621,56 @@ typedef struct ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) /** * @} - */ + */ /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources * @{ */ -#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE -#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE -#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE -#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE -#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE -#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE -#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE -#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE -#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE -#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE -#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE -#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE -#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE -#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE -#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE -#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE -#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE -#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE -#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE -#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE -#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE -#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE +#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE +#endif +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) +#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE +#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE +#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE +#else +#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE +#endif +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) +#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE +#endif +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE #else -#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE -#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE -#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE -#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE +#endif +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE +#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE +#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE +#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE +#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} - */ + */ /** @defgroup SDMMC_LL_Flags Flags * @{ @@ -672,33 +684,40 @@ typedef struct #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD +#endif #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT +#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT +#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT +#else +#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT +#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT +#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT +#endif #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE -#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD -#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT -#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT -#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END +#else +#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL +#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL +#endif +#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC -#else -#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT -#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT -#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT -#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL -#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -738,12 +757,12 @@ typedef struct /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros * @{ */ - + /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions * @brief SDMMC_LL registers bit address in the alias region * @{ @@ -754,7 +773,9 @@ typedef struct #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ SDMMC_CLKCR_WIDBUS |\ - SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) + SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ + SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ + SDMMC_CLKCR_SELCLKRX)) #else #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ @@ -779,17 +800,23 @@ typedef struct #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */ +/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 110MHz*/ +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x8A) + +/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 110MHz*/ +#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x3) + +/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 110MHz*/ +#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2) /* SDMMC Data Transfer Frequency (25MHz max) */ -#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */ +#define SDMMC_TRANSFER_CLK_DIV SDMMC_NSpeed_CLK_DIV #else /* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ /* SDMMC Data Transfer Frequency (25MHz max) */ -#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @@ -800,174 +827,178 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ - + #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief Enable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None - */ + */ #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) /** * @brief Disable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None */ #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) /** * @brief Enable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None - */ + */ #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) + /** * @brief Disable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None */ #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ - + /** * @brief Enable the SDMMC device interrupt. - * @param __INSTANCE__: Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @retval None */ #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) /** * @brief Disable the SDMMC device interrupt. - * @param __INSTANCE__: Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @retval None */ #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) /** - * @brief Checks whether the specified SDMMC flag is set or not. - * @param __INSTANCE__: Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to check. + * @brief Checks whether the specified SDMMC flag is set or not. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_CMDACT: Command transfer in progress - * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full - * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure * @arg SDMMC_FLAG_IDMATE: IDMA transfer error * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete - * @arg SDMMC_FLAG_TXACT: Data transmit in progress - * @arg SDMMC_FLAG_RXACT: Data receive in progress - * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO * @retval The new state of SDMMC_FLAG (SET or RESET). */ -#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) +#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) /** * @brief Clears the SDMMC pending flags. - * @param __INSTANCE__: Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to clear. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __FLAG__: specifies the flag to clear. * This parameter can be one or a combination of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion @@ -980,61 +1011,62 @@ typedef struct /** * @brief Checks whether the specified SDMMC interrupt has occurred or not. - * @param __INSTANCE__: Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @retval The new state of SDMMC_IT (SET or RESET). */ #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clears the SDMMC's interrupt pending bits. - * @param __INSTANCE__: Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt @@ -1046,94 +1078,111 @@ typedef struct /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ + */ #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) /** * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ + */ #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ + */ #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) /** * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ + */ #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) /** * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ -#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) + */ +#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) /** * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ -#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) + */ +#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) /** * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ + */ #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) -#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) +#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) #else -#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) +#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__: Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ + */ #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) -#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) +#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) #else -#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) +#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** * @brief Enable the CMDTRANS mode. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ -#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) + */ +#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) /** * @brief Disable the CMDTRANS mode. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None - */ -#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) + */ +#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) + +/** + * @brief Enable the CMDSTOP mode. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) + +/** + * @brief Disable the CMDSTOP mode. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} */ /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SDMMC_LL_Exported_Functions * @{ */ - + /* Initialization/de-initialization functions **********************************/ /** @addtogroup HAL_SDMMC_LL_Group1 * @{ @@ -1142,7 +1191,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); /** * @} */ - + /* I/O operation functions *****************************************************/ /** @addtogroup HAL_SDMMC_LL_Group2 * @{ @@ -1152,7 +1201,7 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); /** * @} */ - + /* Peripheral Control functions ************************************************/ /** @addtogroup HAL_SDMMC_LL_Group3 * @{ @@ -1201,34 +1250,44 @@ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ - -/** - * @} - */ - -/** - * @} - */ /** * @} */ +/** + * @} + */ + +/** + * @} + */ + + /** + * @} + */ + +/** + * @} + */ #endif /* SDMMC1 */ #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_LL_SDMMC_H */ +#endif /* STM32L4xx_LL_SDMMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c index 99e28de235..7da4b70555 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -196,7 +180,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h index 108715f153..2fa03b8c8b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SPI_H -#define __STM32L4xx_LL_SPI_H +#ifndef STM32L4xx_LL_SPI_H +#define STM32L4xx_LL_SPI_H #ifdef __cplusplus extern "C" { @@ -397,7 +381,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } /** @@ -738,7 +722,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } /** @@ -902,7 +886,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } /** @@ -921,7 +905,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } /** @@ -932,7 +916,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } /** @@ -943,7 +927,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } /** @@ -954,7 +938,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } /** @@ -965,7 +949,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } /** @@ -983,7 +967,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } /** @@ -994,7 +978,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } /** @@ -1048,11 +1032,10 @@ __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) { - __IO uint32_t tmpreg; - tmpreg = SPIx->SR; - (void) tmpreg; - tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); - (void) tmpreg; + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); } /** @@ -1170,7 +1153,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } /** @@ -1181,7 +1164,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } /** @@ -1192,7 +1175,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } /** @@ -1233,7 +1216,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } /** @@ -1266,7 +1249,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) { - return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } /** @@ -1373,16 +1356,13 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) */ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) { - *((__IO uint8_t *)&SPIx->DR) = TxData; -} - -#if __GNUC__ -# define MAY_ALIAS __attribute__ ((__may_alias__)) +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; #else -# define MAY_ALIAS + *((__IO uint8_t *)&SPIx->DR) = TxData; #endif - -typedef __IO uint16_t MAY_ALIAS uint16_io_t; +} /** * @brief Write 16-Bits in the data register @@ -1393,7 +1373,12 @@ typedef __IO uint16_t MAY_ALIAS uint16_io_t; */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { - *((uint16_io_t*)&SPIx->DR) = TxData; +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif } /** @@ -1430,6 +1415,6 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); } #endif -#endif /* __STM32L4xx_LL_SPI_H */ +#endif /* STM32L4xx_LL_SPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c index 083b96f141..458b7a5bf4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -47,7 +31,7 @@ * @{ */ -#if defined (SWPMI1) +#if defined(SWPMI1) /** @addtogroup SWPMI_LL * @{ @@ -61,7 +45,7 @@ * @{ */ -#define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63)) +#define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63U)) #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \ || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) @@ -96,13 +80,22 @@ */ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) { + ErrorStatus status = SUCCESS; + /* Check the parameter */ assert_param(IS_SWPMI_INSTANCE(SWPMIx)); - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1); + if (SWPMIx == SWPMI1) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1); + } + else + { + status = ERROR; + } - return SUCCESS; + return status; } /** @@ -119,7 +112,7 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_SWPMI_INSTANCE(SWPMIx)); assert_param(IS_LL_SWPMI_BITRATE_VALUE(SWPMI_InitStruct->BitRatePrescaler)); @@ -128,7 +121,7 @@ ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_Ini assert_param(IS_LL_SWPMI_VOLTAGE_CLASS(SWPMI_InitStruct->VoltageClass)); /* SWPMI needs to be in deactivated state, in order to be able to configure some bits */ - if (LL_SWPMI_IsActivated(SWPMIx) == 0) + if (LL_SWPMI_IsActivated(SWPMIx) == 0U) { /* Configure the BRR register (Bitrate) */ LL_SWPMI_SetBitRatePrescaler(SWPMIx, SWPMI_InitStruct->BitRatePrescaler); @@ -177,7 +170,7 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct) * @} */ -#endif /* defined (SWPMI1) */ +#endif /* SWPMI1 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h index 4193ed5c22..a1a8522e74 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SWPMI_H -#define __STM32L4xx_LL_SWPMI_H +#ifndef STM32L4xx_LL_SWPMI_H +#define STM32L4xx_LL_SWPMI_H #ifdef __cplusplus extern "C" { @@ -48,7 +32,7 @@ extern "C" { * @{ */ -#if defined (SWPMI1) +#if defined(SWPMI1) /** @defgroup SWPMI_LL SWPMI * @{ @@ -84,7 +68,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. - This parameter must be a number between Min_Data=0 and Max_Data=63. + This parameter must be a number between Min_Data=0 and Max_Data=63U. The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER @@ -366,7 +350,7 @@ __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)); + return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); } /** @@ -397,7 +381,7 @@ __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx) * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler * @param SWPMIx SWPMI Instance - * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63 + * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63U * @retval None */ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler) @@ -409,7 +393,7 @@ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_ * @brief Get Bitrate prescaler * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler * @param SWPMIx SWPMI Instance - * @retval A number between Min_Data=0 and Max_Data=63 + * @retval A number between Min_Data=0 and Max_Data=63U */ __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) { @@ -459,7 +443,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); } /** @@ -470,7 +454,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); } /** @@ -481,7 +465,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); } /** @@ -492,7 +476,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); } /** @@ -503,7 +487,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); } /** @@ -515,7 +499,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); } /** @@ -527,7 +511,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); } /** @@ -539,7 +523,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); } /** @@ -551,7 +535,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); } /** @@ -562,7 +546,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); } /** @@ -573,7 +557,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)); + return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); } /** @@ -867,7 +851,7 @@ __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); } /** @@ -878,7 +862,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); } /** @@ -889,7 +873,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); } /** @@ -900,7 +884,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); } /** @@ -911,7 +895,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); } /** @@ -922,7 +906,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); } /** @@ -933,7 +917,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); } /** @@ -944,7 +928,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); } /** @@ -955,7 +939,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)); + return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); } /** @@ -996,7 +980,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)); + return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); } /** @@ -1029,7 +1013,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) { - return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)); + return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); } /** @@ -1044,7 +1028,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) */ __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) { - register uint32_t data_reg_addr = 0; + uint32_t data_reg_addr; if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) { @@ -1154,7 +1138,7 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); * @} */ -#endif /* defined (SWPMI1) */ +#endif /* SWPMI1 */ /** * @} @@ -1164,6 +1148,6 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); } #endif -#endif /* __STM32L4xx_LL_SWPMI_H */ +#endif /* STM32L4xx_LL_SWPMI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h index e1ed494005..e0bf66b496 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h @@ -19,36 +19,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_SYSTEM_H -#define __STM32L4xx_LL_SYSTEM_H +#ifndef STM32L4xx_LL_SYSTEM_H +#define STM32L4xx_LL_SYSTEM_H #ifdef __cplusplus extern "C" { @@ -1639,6 +1623,6 @@ __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) } #endif -#endif /* __STM32L4xx_LL_SYSTEM_H */ +#endif /* STM32L4xx_LL_SYSTEM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c index 4ae0d28f2a..d790867528 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -42,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32L4xx_LL_Driver * @{ @@ -62,135 +46,135 @@ * @{ */ #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ - || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ - || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ - || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ - || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ - || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ @@ -338,7 +322,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) */ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); @@ -528,8 +512,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct */ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; + uint32_t tmpccmr1; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); @@ -619,10 +603,10 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI */ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { - uint32_t tmpcr2 = 0U; - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpsmcr = 0U; + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); @@ -784,7 +768,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT */ /** @addtogroup TIM_LL_Private_Functions TIM Private Functions - * @brief Private functions + * @brief Private functions * @{ */ /** @@ -797,9 +781,9 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT */ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -876,9 +860,9 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -955,9 +939,9 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1034,9 +1018,9 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1104,8 +1088,8 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr3 = 0U; - uint32_t tmpccer = 0U; + uint32_t tmpccmr3; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(TIMx)); @@ -1165,8 +1149,8 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni */ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { - uint32_t tmpccmr3 = 0U; - uint32_t tmpccer = 0U; + uint32_t tmpccmr3; + uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(TIMx)); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h index ab0dd4e6d6..815a2a1169 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -127,14 +111,13 @@ static const uint8_t SHIFT_TAB_OISx[] = * @} */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Constants TIM Private Constants * @{ */ /* Defines used for the bit position in the register and perform offsets */ -#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source) +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) /* Generic bit definitions for TIMx_OR2 register */ #define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */ @@ -192,7 +175,7 @@ static const uint8_t SHIFT_TAB_OISx[] = /** Legacy definitions for compatibility purpose @cond 0 -*/ + */ #if defined(DFSDM1_Channel0) #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E @@ -223,14 +206,14 @@ static const uint8_t SHIFT_TAB_OISx[] = * @retval none */ #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ -(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) /** @brief Calculate the deadtime sampling period(in ps). * @param __TIMCLK__ timer input clock frequency (in Hz). @@ -241,9 +224,9 @@ static const uint8_t SHIFT_TAB_OISx[] = * @retval none */ #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ - (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ - ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ - ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) /** * @} */ @@ -726,7 +709,7 @@ typedef struct #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!TIMx_CCRy else active.*/ #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ @@ -782,7 +765,7 @@ typedef struct /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler * @{ */ -#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ +#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ @@ -1058,7 +1041,9 @@ typedef struct #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ +#if defined(DFSDM1_Channel0) #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ +#endif /* DFSDM1_Channel0 */ /** * @} */ @@ -1066,7 +1051,7 @@ typedef struct /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY * @{ */ -#define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ +#define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ /** * @} @@ -1093,12 +1078,12 @@ typedef struct #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ -#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ +#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ /** * @} */ @@ -1170,7 +1155,7 @@ typedef struct #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L412xx) || defined (STM32L422xx) ||defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ @@ -1186,8 +1171,11 @@ typedef struct */ #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */ #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ +#if defined (STM32L412xx) || defined (STM32L422xx) +#else #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ +#endif /** * @} */ @@ -1298,7 +1286,7 @@ typedef struct /** Legacy definitions for compatibility purpose @cond 0 -*/ + */ #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK /** @endcond @@ -1322,7 +1310,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in TIM register. @@ -1330,7 +1318,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -1348,7 +1336,7 @@ typedef struct * @retval UIF status bit */ #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ - (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) /** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. @@ -1362,11 +1350,11 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ - 0U) + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) /** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. @@ -1376,7 +1364,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1387,7 +1375,7 @@ typedef struct * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ - (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. @@ -1398,8 +1386,8 @@ typedef struct * @retval Compare value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ -((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). @@ -1411,8 +1399,8 @@ typedef struct * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @brief HELPER macro retrieving the ratio of the input capture prescaler @@ -1425,7 +1413,7 @@ typedef struct * @retval Input capture prescaler ratio (1, 2, 4 or 8) */ #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ - ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) /** @@ -1475,7 +1463,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } /** @@ -1508,7 +1496,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } /** @@ -1578,7 +1566,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction + * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode @@ -1593,7 +1581,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) { - MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); } /** @@ -1646,7 +1634,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } /** @@ -2013,7 +2001,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) { - return (READ_BIT(TIMx->CCER, Channels) == (Channels)); + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } /** @@ -2059,7 +2047,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2104,7 +2092,7 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2143,7 +2131,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2303,7 +2291,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2329,7 +2317,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2355,9 +2343,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; - return (READ_BIT(*pReg, bitfield) == bitfield); + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** @@ -2381,7 +2369,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2406,7 +2394,7 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2431,9 +2419,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; - return (READ_BIT(*pReg, bitfield) == bitfield); + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** @@ -2460,7 +2448,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2487,7 +2475,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2516,9 +2504,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; - return (READ_BIT(*pReg, bitfield) == bitfield); + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** @@ -2615,7 +2603,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) { - WRITE_REG(TIMx->CCR5, CompareValue); + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); } /** @@ -2706,7 +2694,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_REG(TIMx->CCR5)); + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } /** @@ -2730,7 +2718,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels * @param TIMx Timer instance - * @param GroupCH5 This parameter can be one of the following values: + * @param GroupCH5 This parameter can be a combination of the following values: * @arg @ref LL_TIM_GROUPCH5_NONE * @arg @ref LL_TIM_GROUPCH5_OC1REFC * @arg @ref LL_TIM_GROUPCH5_OC2REFC @@ -2739,7 +2727,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) { - MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); } /** @@ -2787,7 +2775,7 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2815,7 +2803,7 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2839,7 +2827,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2865,7 +2853,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2890,7 +2878,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2928,7 +2916,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2965,7 +2953,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3062,7 +3050,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } /** @@ -3173,7 +3161,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } /** @@ -3353,7 +3341,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } /** @@ -3477,7 +3465,8 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 * @retval None */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, + uint32_t BreakFilter) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); } @@ -3598,7 +3587,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } /** @@ -3641,7 +3630,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } /** @@ -3669,8 +3658,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); - SET_BIT(*pReg , Source); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + SET_BIT(*pReg, Source); } /** @@ -3698,7 +3687,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -3728,8 +3717,8 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); - MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE))); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** * @} @@ -3764,12 +3753,12 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 * @param DMABurstLength This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS @@ -3793,7 +3782,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 */ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) { - MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); } /** @@ -4036,7 +4025,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } /** @@ -4058,7 +4047,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } /** @@ -4080,7 +4069,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } /** @@ -4102,7 +4091,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } /** @@ -4124,7 +4113,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } /** @@ -4146,7 +4135,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } /** @@ -4168,7 +4157,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } /** @@ -4190,7 +4179,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } /** @@ -4212,7 +4201,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } /** @@ -4234,7 +4223,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } /** @@ -4256,7 +4245,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } /** @@ -4278,7 +4267,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } /** @@ -4300,7 +4289,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } /** @@ -4322,7 +4311,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } /** @@ -4344,7 +4333,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } /** @@ -4366,7 +4355,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); } /** @@ -4406,7 +4395,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } /** @@ -4439,7 +4428,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } /** @@ -4472,7 +4461,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } /** @@ -4505,7 +4494,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } /** @@ -4538,7 +4527,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } /** @@ -4571,7 +4560,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } /** @@ -4604,7 +4593,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } /** @@ -4637,7 +4626,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } /** @@ -4677,7 +4666,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } /** @@ -4710,7 +4699,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } /** @@ -4743,7 +4732,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } /** @@ -4776,7 +4765,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } /** @@ -4809,7 +4798,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } /** @@ -4842,7 +4831,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } /** @@ -4875,7 +4864,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c index a49c43007c..deadefcd20 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -38,11 +22,11 @@ #include "stm32l4xx_ll_usart.h" #include "stm32l4xx_ll_rcc.h" #include "stm32l4xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32L4xx_LL_Driver * @{ @@ -65,7 +49,6 @@ * @} */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ @@ -73,68 +56,70 @@ #if defined(USART_PRESC_PRESCALER) #define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) -#endif +#endif /* USART_PRESC_PRESCALER */ /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U) #else #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) -#endif +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ -#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \ - && ((__VALUE__) <= 0x0000FFFFU)) +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} @@ -223,10 +208,10 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * @brief Initialize USART registers according to the specified * parameters in USART_InitStruct. * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance - * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * that contains the configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are initialized according to USART_InitStruct content @@ -241,7 +226,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini assert_param(IS_UART_INSTANCE(USARTx)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue)); -#endif +#endif /* USART_PRESC_PRESCALER */ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); @@ -315,9 +300,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini } /* Configure the USART Baud Rate : -#if defined(USART_PRESC_PRESCALER) + #if defined(USART_PRESC_PRESCALER) - prescaler value is required -#endif + #endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -329,21 +314,24 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini periphclk, #if defined(USART_PRESC_PRESCALER) USART_InitStruct->PrescalerValue, -#endif +#endif /* USART_PRESC_PRESCALER */ USART_InitStruct->OverSampling, USART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR(USARTx->BRR)); - } + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + /* Check BRR is lower than or equal to 0xFFFF */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); + } #if defined(USART_PRESC_PRESCALER) + /*---------------------------- USART PRESC Configuration ----------------------- * Configure USARTx PRESC (Prescaler) with parameters: * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value. */ LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue); -#endif +#endif /* USART_PRESC_PRESCALER */ } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -352,8 +340,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /** * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure - * whose fields will be set to default values. + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. * @retval None */ @@ -362,7 +350,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) /* Set USART_InitStruct fields to default values */ #if defined(USART_PRESC_PRESCALER) USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; -#endif +#endif /* USART_PRESC_PRESCALER */ USART_InitStruct->BaudRate = 9600U; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; @@ -376,9 +364,9 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * @brief Initialize USART Clock related settings according to the * specified parameters in the USART_ClockInitStruct. * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content @@ -439,8 +427,8 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef /** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure - * whose fields will be set to default values. + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. * @retval None */ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h index da5cd195ff..74906566e8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_USART_H -#define __STM32L4xx_LL_USART_H +#ifndef STM32L4xx_LL_USART_H +#define STM32L4xx_LL_USART_H #ifdef __cplusplus extern "C" { @@ -61,25 +45,25 @@ extern "C" { * @{ */ /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ -static const uint16_t USART_PRESCALER_TAB[] = +static const uint32_t USART_PRESCALER_TAB[] = { - (uint16_t)1, - (uint16_t)2, - (uint16_t)4, - (uint16_t)6, - (uint16_t)8, - (uint16_t)10, - (uint16_t)12, - (uint16_t)16, - (uint16_t)32, - (uint16_t)64, - (uint16_t)128, - (uint16_t)256 + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL }; /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /* Private constants ---------------------------------------------------------*/ /** @defgroup USART_LL_Private_Constants USART Private Constants @@ -115,8 +99,8 @@ typedef struct This parameter can be a value of @ref USART_LL_EC_PRESCALER. This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ +#endif /* USART_PRESC_PRESCALER */ -#endif uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ @@ -202,23 +186,23 @@ typedef struct */ #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #if defined(USART_CR1_FIFOEN) #define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ #if defined(USART_CR2_SLVEN) #define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ -#endif +#endif /* USART_CR2_SLVEN */ #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ /** @@ -238,13 +222,13 @@ typedef struct #define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ #else #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ #if defined(USART_CR1_FIFOEN) #define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ #else #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ @@ -252,7 +236,7 @@ typedef struct #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ #if defined(USART_CR2_SLVEN) #define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ -#endif +#endif /* USART_CR2_SLVEN */ #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ @@ -265,14 +249,14 @@ typedef struct #if defined(USART_CR1_FIFOEN) #define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ #define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) #define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ #define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -286,13 +270,13 @@ typedef struct #define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ #else #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ #else #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ @@ -300,20 +284,20 @@ typedef struct #if defined(USART_CR1_FIFOEN) #define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ #define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ #if defined(USART_CR1_FIFOEN) #define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) #define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -331,8 +315,8 @@ typedef struct /** * @} */ -#endif +#endif /* USART_CR1_FIFOEN */ /** @defgroup USART_LL_EC_DIRECTION Communication Direction * @{ */ @@ -440,8 +424,8 @@ typedef struct /** * @} */ -#endif +#endif /* USART_PRESC_PRESCALER */ /** @defgroup USART_LL_EC_STOPBITS Stop Bits * @{ */ @@ -630,16 +614,17 @@ typedef struct * @arg @ref LL_USART_PRESCALER_DIV64 * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 - * @param __PRESCALER__ Prescaler value @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ #if defined(USART_PRESC_PRESCALER) -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) #else -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) -#endif +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#endif /* USART_PRESC_PRESCALER */ /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -659,16 +644,16 @@ typedef struct * @arg @ref LL_USART_PRESCALER_DIV64 * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 - * @param __PRESCALER__ Prescaler value @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ #if defined(USART_PRESC_PRESCALER) -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) #else -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) -#endif +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#endif /* USART_PRESC_PRESCALER */ /** * @} @@ -721,11 +706,10 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /** * @brief FIFO Mode Enable * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -762,7 +746,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } /** @@ -868,10 +852,10 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that @@ -911,9 +895,46 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } +#if defined(USART_CR3_UCESM) +/** + * @brief USART Clock enabled in STOP Mode + * @note When this function is called, USART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief USART clock disabled in STOP Mode + * @note When this function is called, USART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if USART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); +} + +#endif /* USART_CR3_UCESM */ /** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @rmtoll CR1 RE LL_USART_EnableDirectionRx @@ -1114,7 +1135,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } /** @@ -1267,7 +1288,6 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, } #if defined(USART_PRESC_PRESCALER) - /** * @brief Configure Clock source prescaler for baudrate generator and oversampling * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -1291,7 +1311,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, */ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); } /** @@ -1318,8 +1338,8 @@ __STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); } -#endif +#endif /* USART_PRESC_PRESCALER */ /** * @brief Enable Clock output on SCLK pin * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not @@ -1356,7 +1376,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); } /** @@ -1601,7 +1621,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); } /** @@ -1669,7 +1689,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); } /** @@ -1848,7 +1868,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); } /** @@ -1881,7 +1901,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } /** @@ -1949,23 +1969,32 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * @retval None */ #if defined(USART_PRESC_PRESCALER) -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, uint32_t BaudRate) #else __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate) -#endif +#endif /* USART_PRESC_PRESCALER */ { - register uint32_t usartdiv = 0x0U; - register uint32_t brrtemp = 0x0U; + uint32_t usartdiv; + register uint32_t brrtemp; +#if defined(USART_PRESC_PRESCALER) + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) +#else if (OverSampling == LL_USART_OVERSAMPLING_8) +#endif /* USART_PRESC_PRESCALER */ { #if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, PrescalerValue, BaudRate)); + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); #else usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); -#endif +#endif /* USART_PRESC_PRESCALER */ brrtemp = usartdiv & 0xFFF0U; brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); USARTx->BRR = brrtemp; @@ -1973,10 +2002,10 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph else { #if defined(USART_PRESC_PRESCALER) - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, PrescalerValue, BaudRate)); + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); #else USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); -#endif +#endif /* USART_PRESC_PRESCALER */ } } @@ -2009,29 +2038,34 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @retval Baud Rate */ #if defined(USART_PRESC_PRESCALER) -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) #else __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) -#endif +#endif /* USART_PRESC_PRESCALER */ { - register uint32_t usartdiv = 0x0U; + register uint32_t usartdiv; register uint32_t brrresult = 0x0U; #if defined(USART_PRESC_PRESCALER) - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[PrescalerValue])); -#endif + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); +#endif /* USART_PRESC_PRESCALER */ usartdiv = USARTx->BRR; - if (OverSampling == LL_USART_OVERSAMPLING_8) + if (usartdiv == 0U) { - if ((usartdiv & 0xFFF7U) != 0U) + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; #if defined(USART_PRESC_PRESCALER) brrresult = (periphclkpresc * 2U) / usartdiv; #else brrresult = (PeriphClk * 2U) / usartdiv; -#endif +#endif /* USART_PRESC_PRESCALER */ } } else @@ -2042,7 +2076,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe brrresult = periphclkpresc / usartdiv; #else brrresult = PeriphClk / usartdiv; -#endif +#endif /* USART_PRESC_PRESCALER */ } } return (brrresult); @@ -2138,7 +2172,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); } /** @@ -2184,7 +2218,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); + MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2245,7 +2279,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); } /** @@ -2284,7 +2318,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); } /** @@ -2331,7 +2365,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR */ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); + MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2360,7 +2394,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); + MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); } /** @@ -2421,7 +2455,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } /** @@ -2429,7 +2463,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) */ #if defined(USART_CR2_SLVEN) - /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature * @{ */ @@ -2441,7 +2474,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR2, USART_CR2_SLVEN); } @@ -2454,7 +2487,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); } @@ -2467,9 +2500,9 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); } /** @@ -2482,7 +2515,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); } @@ -2496,7 +2529,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval None */ -__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx) +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); } @@ -2509,16 +2542,16 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef* USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)); + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); } /** * @} */ -#endif +#endif /* USART_CR2_SLVEN */ /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature * @{ */ @@ -2590,7 +2623,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); } /** @@ -2691,7 +2724,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } /** @@ -3018,7 +3051,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } /** @@ -3029,18 +3062,18 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } /** * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll ISR NF LL_USART_IsActiveFlag_NE + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE * @param USARTx USART Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } /** @@ -3051,7 +3084,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } /** @@ -3062,11 +3095,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE @@ -3080,10 +3112,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } -#else +#else /** * @brief Check if the USART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE @@ -3092,10 +3124,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the USART Transmission Complete Flag is set or not * @rmtoll ISR TC LL_USART_IsActiveFlag_TC @@ -3104,11 +3136,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF @@ -3122,10 +3153,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } -#else +#else /** * @brief Check if the USART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE @@ -3134,10 +3165,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the USART LIN Break Detection Flag is set or not * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3148,7 +3179,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); } /** @@ -3161,7 +3192,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } /** @@ -3174,7 +3205,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } /** @@ -3185,7 +3216,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); } /** @@ -3198,11 +3229,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); } #if defined(USART_CR2_SLVEN) - /** * @brief Check if the SPI Slave Underrun error flag is set or not * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not @@ -3213,10 +3243,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)); + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR2_SLVEN */ /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not @@ -3227,7 +3257,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); } /** @@ -3240,7 +3270,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); } /** @@ -3251,7 +3281,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } /** @@ -3262,7 +3292,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } /** @@ -3273,7 +3303,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } /** @@ -3284,7 +3314,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } /** @@ -3297,7 +3327,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } /** @@ -3308,7 +3338,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } /** @@ -3319,11 +3349,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the USART TX FIFO Empty Flag is set or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3334,7 +3363,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } /** @@ -3347,12 +3376,11 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not @@ -3362,12 +3390,11 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the USART TX FIFO Threshold Flag is set or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3378,7 +3405,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } /** @@ -3391,10 +3418,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_USART_ClearFlag_PE @@ -3418,14 +3445,14 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) } /** - * @brief Clear Noise detected Flag - * @rmtoll ICR NCF LL_USART_ClearFlag_NE + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE * @param USARTx USART Instance * @retval None */ __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) { - WRITE_REG(USARTx->ICR, USART_ICR_NCF); + WRITE_REG(USARTx->ICR, USART_ICR_NECF); } /** @@ -3451,7 +3478,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Clear TX FIFO Empty Flag * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3464,8 +3490,8 @@ __STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) { WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_USART_ClearFlag_TC @@ -3478,7 +3504,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) } #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag @@ -3490,7 +3515,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) { WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); } -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @brief Clear LIN Break Detection Flag @@ -3543,7 +3568,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR2_SLVEN) - /** * @brief Clear SPI Slave Underrun Flag * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not @@ -3556,8 +3580,8 @@ __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) { WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); } -#endif +#endif /* USART_CR2_SLVEN */ /** * @brief Clear Character Match Flag * @rmtoll ICR CMCF LL_USART_ClearFlag_CM @@ -3602,7 +3626,6 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE @@ -3618,8 +3641,8 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } -#else +#else /** * @brief Enable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE @@ -3630,8 +3653,8 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Enable Transmission Complete Interrupt * @rmtoll CR1 TCIE LL_USART_EnableIT_TC @@ -3644,7 +3667,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF @@ -3660,8 +3682,8 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } -#else +#else /** * @brief Enable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE @@ -3672,8 +3694,8 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_TXEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Enable Parity Error Interrupt * @rmtoll CR1 PEIE LL_USART_EnableIT_PE @@ -3721,7 +3743,6 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Empty Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3745,8 +3766,8 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Enable LIN Break Detection Interrupt * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3802,7 +3823,6 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Enable TX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3815,10 +3835,9 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); } -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt @@ -3832,10 +3851,9 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) - /** * @brief Enable RX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -3848,8 +3866,8 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE @@ -3862,7 +3880,6 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE @@ -3878,8 +3895,8 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } -#else +#else /** * @brief Disable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE @@ -3890,8 +3907,8 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable Transmission Complete Interrupt * @rmtoll CR1 TCIE LL_USART_DisableIT_TC @@ -3904,7 +3921,6 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF @@ -3920,8 +3936,8 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } -#else +#else /** * @brief Disable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE @@ -3932,8 +3948,8 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable Parity Error Interrupt * @rmtoll CR1 PEIE LL_USART_DisableIT_PE @@ -3981,7 +3997,6 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Empty Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4007,8 +4022,8 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Disable LIN Break Detection Interrupt * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -4064,7 +4079,6 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) } #if defined(USART_CR1_FIFOEN) - /** * @brief Disable TX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4077,8 +4091,8 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); } -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -4093,10 +4107,9 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) - /** * @brief Disable RX FIFO Threshold Interrupt * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4109,8 +4122,8 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE @@ -4119,11 +4132,10 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE @@ -4137,10 +4149,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } -#else +#else /** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE @@ -4149,10 +4161,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC @@ -4161,11 +4173,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /* Legacy define */ #define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF @@ -4179,10 +4190,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } -#else +#else /** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE @@ -4191,10 +4202,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE @@ -4203,7 +4214,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } /** @@ -4214,7 +4225,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } /** @@ -4225,7 +4236,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); } /** @@ -4238,11 +4249,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4253,7 +4263,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } /** @@ -4266,10 +4276,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -4280,7 +4290,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); } /** @@ -4291,7 +4301,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } /** @@ -4304,7 +4314,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } /** @@ -4317,11 +4327,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } #if defined(USART_CR1_FIFOEN) - /** * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4332,12 +4341,11 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ #if defined(USART_TCBGT_SUPPORT) - /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. @@ -4349,12 +4357,11 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_TCBGT_SUPPORT */ #if defined(USART_CR1_FIFOEN) - /** * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not @@ -4365,10 +4372,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_CR1_FIFOEN */ /** * @} */ @@ -4407,7 +4414,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } /** @@ -4440,7 +4447,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } /** @@ -4473,7 +4480,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) */ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) { - return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } /** @@ -4488,7 +4495,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx */ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) { - register uint32_t data_reg_addr = 0U; + register uint32_t data_reg_addr; if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { @@ -4520,7 +4527,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) { - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** @@ -4555,7 +4562,7 @@ __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value */ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) { - USARTx->TDR = Value & 0x1FFU; + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); } /** @@ -4576,7 +4583,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu */ __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) { - SET_BIT(USARTx->RQR, USART_RQR_ABRRQ); + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); } /** @@ -4587,7 +4594,7 @@ __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) { - SET_BIT(USARTx->RQR, USART_RQR_SBKRQ); + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); } /** @@ -4598,7 +4605,7 @@ __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->RQR, USART_RQR_MMRQ); + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); } /** @@ -4617,7 +4624,7 @@ __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) { - SET_BIT(USARTx->RQR, USART_RQR_RXFRQ); + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } /** @@ -4628,15 +4635,13 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) @else * @brief Request a Transmit data flush @endif - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @param USARTx USART Instance * @retval None */ __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) { - SET_BIT(USARTx->RQR, USART_RQR_TXFRQ); + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); } /** @@ -4675,6 +4680,6 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS } #endif -#endif /* __STM32L4xx_LL_USART_H */ +#endif /* STM32L4xx_LL_USART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c index 092c9828e3..0d62ac914b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c @@ -3,21 +3,21 @@ * @file stm32l4xx_ll_usb.c * @author MCD Application Team * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization/de-initialization functions * + I/O operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @@ -26,54 +26,26 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" -/** @defgroup USB_LL USB Low Layer - * @brief Low layer module for USB_FS and USB_OTG_FS drivers - * @{ - */ -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /** @addtogroup STM32L4xx_LL_USB_DRIVER * @{ */ - - +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB) || defined (USB_OTG_FS) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -81,65 +53,159 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ #if defined (USB_OTG_FS) -/** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions - * @{ - */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); -/** - * @} - */ -#endif /* USB_OTG_FS */ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions * @{ */ -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== - ##### Initialization/de-initialization functions ##### + ##### Initialization/de-initialization functions ##### =============================================================================== - [..] This section provides functions allowing to: - + @endverbatim * @{ */ -/*============================================================================== - USB OTG FS peripheral available on STM32L475xx, STM32L476xx, STM32L485xx and - STM32L486xx devices -==============================================================================*/ -#if defined (USB_OTG_FS) + /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); + HAL_StatusTypeDef ret; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select and set Host mode */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); - - /* Deactivate the power down*/ - USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - return HAL_OK; } /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -148,11 +214,10 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) return HAL_OK; } - /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -160,396 +225,423 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; return HAL_OK; } - + /** * @brief USB_SetCurrentMode : Set functional mode - * @param USBx: Selected device - * @param mode: current core mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_HOST_MODE: Host mode + * @arg USB_DRD_MODE: Dual Role Device mode * @retval HAL status */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode) { - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if ( mode == USB_HOST_MODE) + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; } - else if ( mode == USB_DEVICE_MODE) + else if (mode == USB_DEVICE_MODE) { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } - HAL_Delay(50); - + else + { + return HAL_ERROR; + } + HAL_Delay(50U); + return HAL_OK; } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { - uint32_t index = 0; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - - if (cfg.vbus_sensing_enable == 0) + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) { /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable*/ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; } - + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; + USBx_PCGCCTL = 0U; /* Device mode configuration */ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - - /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); + + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; - - for (index = 0; index < cfg.dev_endpoints; index++) + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) { - if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) { - USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } } else { - USBx_INEP(index)->DIEPCTL = 0; + USBx_INEP(i)->DIEPCTL = 0U; } - - USBx_INEP(index)->DIEPTSIZ = 0; - USBx_INEP(index)->DIEPINT = 0xFF; + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; } - - for (index = 0; index < cfg.dev_endpoints; index++) + + for (i = 0U; i < cfg.dev_endpoints; i++) { - if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) { - USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } } else { - USBx_OUTEP(index)->DOEPCTL = 0; + USBx_OUTEP(i)->DOEPCTL = 0U; } - - USBx_OUTEP(index)->DOEPTSIZ = 0; - USBx_OUTEP(index)->DOEPINT = 0xFF; + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } - + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - if (cfg.dma_enable == 1) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); - - index= USBx_DEVICE->DTHRCTL; - } - + /* Disable all interrupts. */ - USBx->GINTMSK = 0; - + USBx->GINTMSK = 0U; + /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; + USBx->GINTSTS = 0xBFFFFFFFU; /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; - if(cfg.Sof_enable) + if (cfg.Sof_enable != 0U) { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - if (cfg.vbus_sensing_enable == ENABLE) + if (cfg.vbus_sensing_enable == 1U) { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); } - - return HAL_OK; -} + return ret; +} /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx: Selected device - * @param num: FIFO number + * @param USBx Selected device + * @param num FIFO number * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - + uint32_t count = 0U; + + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - + return HAL_OK; } - /** * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { uint32_t count = 0; - + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - + do { - if (++count > 200000) + if (++count > 200000U) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - + return HAL_OK; } /** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. - * @param USBx: Selected device - * @param speed: device speed + * @param USBx Selected device + * @param speed device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { + uint32_t USBx_BASE = (uint32_t)USBx; + USBx_DEVICE->DCFG |= speed; return HAL_OK; } /** - * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx: Selected device - * @retval speed : device speed + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode + * @arg PCD_SPEED_FULL: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { - uint8_t speed = 0; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { - speed = USB_OTG_SPEED_HIGH; + speed = USBD_FS_SPEED; } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) + else { - speed = USB_OTG_SPEED_FULL; + speed = 0xFU; } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - speed = USB_OTG_SPEED_LOW; - } - + return speed; } /** * @brief Activate and configure an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - // MBED PATCH - USBx_INEP(ep->num)->DIEPCTL = ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } } else { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - // MBED PATCH - USBx_OUTEP(ep->num)->DOEPCTL = ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); - } + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } } return HAL_OK; } + /** * @brief Activate and configure a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - static __IO uint32_t debug = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) { - // MBED PATCH - USBx_INEP(ep->num)->DIEPCTL = ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) { - // MBED PATCH - USBx_OUTEP(ep->num)->DOEPCTL = ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); } return HAL_OK; } + /** * @brief De-activate and de-initialize an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); } else { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); } + return HAL_OK; } /** * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + /* Read DEPCTLn register */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); } + return HAL_OK; } /** * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - uint16_t pktcnt = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else { @@ -558,139 +650,41 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe * short_packet pktcnt = N + (short_packet * exist ? 1 : 0) */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + if (ep->type == EP_TYPE_ISOC) { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); - } + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } } - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - // Added for MBED PR #3062 - atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num); - } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - if (ep->type == EP_TYPE_ISOC) + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len == 0) - { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } } else { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } else { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } - } - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len); } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if(ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - } - - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - // Added for MBED PR #3062 - atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num)); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -698,705 +692,702 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD * pktcnt = N * xfersize = N * maxpacket */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0) + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len == 0U) { - ep->xfer_len = ep->maxpacket; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } } - - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } -// MBED PATCH /** - * @brief USB_EPStoptXfer : stop transfer on this endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status - * @note IN endpoints must have NAK enabled before calling this function - * @note OUT endpoints must have global out NAK enabled before calling this - * function. Furthermore, the RX fifo must be empty or the status - * HAL_BUSY will be returned. */ -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - HAL_StatusTypeDef ret = HAL_OK; - uint32_t count = 0U; - uint32_t epint, fifoemptymsk; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; /* IN endpoint */ if (ep->is_in == 1U) { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } /* EP enable, IN data in FIFO */ - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - /* Disable this endpoint */ - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; - count = 0; - do - { - if (++count > 200000U) - { - return HAL_TIMEOUT; - } - } - while ((USBx_INEP(ep->num)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); - } + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - /* Clear transfer complete interrupt */ - epint = USB_ReadDevInEPInterrupt(USBx, ep->num); - if((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { - CLEAR_IN_EP_INTR(ep->num, USB_OTG_DIEPINT_XFRC); + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); } - - /* Mask fifo empty interrupt */ - fifoemptymsk = 0x1U << ep->num; - atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); } else /* OUT endpoint */ { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len > 0U) { - /* Disable this endpoint */ - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; - count = 0; - do - { - if (++count > 200000U) - { - return HAL_TIMEOUT; - } - if ((USBx->GINTSTS & USB_OTG_GINTSTS_RXFLVL) == USB_OTG_GINTSTS_RXFLVL) - { - /* Although not mentioned in the Reference Manual, it appears that the - * rx fifo must be empty for an OUT endpoint to be disabled. Typically - * this will happen when setting the global OUT nak (required by Reference - * Manual) as this requires processing the rx fifo. This is not guaranteed - * though, as a setup packet can arrive even while global OUT nak is set. - * - * During testing this event was observed and prevented endpoint disabling - * from completing until the rx fifo was empty. To address this problem - * return HAL_BUSY if the rx fifo is not empty to give higher level code - * a chance to clear the fifo and retry the operation. - * - */ - return HAL_BUSY; - } - } - while ((USBx_OUTEP(ep->num)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + ep->xfer_len = ep->maxpacket; } - /* Clear interrupt */ - epint = USB_ReadDevOutEPInterrupt(USBx, ep->num); - if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) - { - CLEAR_OUT_EP_INTR(ep->num, USB_OTG_DOEPINT_XFRC); - } - } - return ret; -} + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); -/** - * @brief USB_EPSetNak : stop transfer and nak all tokens on this endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetNak(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) -{ - uint32_t count = 0; - if (ep->is_in == 1U) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - count = 0; - do - { - if (++count > 200000U) - { - return HAL_TIMEOUT; - } - } - while ((USBx_INEP(ep->num)->DIEPCTL & USB_OTG_DIEPCTL_NAKSTS) != USB_OTG_DIEPCTL_NAKSTS); - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - count = 0; - do - { - if (++count > 200000U) - { - return HAL_TIMEOUT; - } - } - while ((USBx_OUTEP(ep->num)->DOEPCTL & USB_OTG_DOEPCTL_NAKSTS) != USB_OTG_DOEPCTL_NAKSTS); + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); } + return HAL_OK; } /** - * @brief USB_EPSetNak : resume transfer and stop naking on this endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearNak(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) -{ - uint32_t count = 0; - if (ep->is_in == 1U) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_CNAK; - count = 0; - do - { - if (++count > 200000U) - { - return HAL_TIMEOUT; - } - } - while ((USBx_INEP(ep->num)->DIEPCTL & USB_OTG_DIEPCTL_NAKSTS) == USB_OTG_DIEPCTL_NAKSTS); - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_CNAK; - count = 0; - do - { - if (++count > 200000U) - { - return HAL_TIMEOUT; - } - } - while ((USBx_OUTEP(ep->num)->DOEPCTL & USB_OTG_DOEPCTL_NAKSTS) == USB_OTG_DOEPCTL_NAKSTS); - } - return HAL_OK; -} -// MBED PATCH - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel - * @param USBx: Selected device - * @param src: pointer to source buffer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to write - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - uint32_t count32b= 0 , index= 0; - count32b = (len + 3) / 4; - for (index = 0; index < count32b; index++, src += 4) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; } + return HAL_OK; } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx: Selected device - * @param src: source pointer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to read - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { - uint32_t index=0; - uint32_t count32b = (len + 3) / 4; - - for ( index = 0; index < count32b; index++, dest += 4 ) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; } - return ((void *)dest); + + return ((void *)pDest); } /** * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; } else { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; } + return HAL_OK; } - /** * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { - if (ep->is_in == 1) + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } } else { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } } return HAL_OK; } /** - * @brief USB_StopDevice : Stop the USB device mode - * @param USBx: Selected device + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) { - uint32_t index; - + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + /* Clear Pending interrupt */ - for (index = 0; index < 15 ; index++) + for (i = 0U; i < 15U; i++) { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - + /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; - + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); - + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + return HAL_OK; } -/** - * @brief USB_SetDevAddress : Stop the USB device mode - * @param USBx: Selected device - * @param address: new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) -{ - USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; - - return HAL_OK; -} - /** * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + HAL_Delay(3U); + + return HAL_OK; } /** * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + HAL_Delay(3U); + + return HAL_OK; } /** * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { - uint32_t tmpreg = 0; - + uint32_t tmpreg; + tmpreg = USBx->GINTSTS; tmpreg &= USBx->GINTMSK; - return tmpreg; + + return tmpreg; } /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; + tmpreg = USBx_DEVICE->DAINT; tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xffff0000) >> 16); + + return ((tmpreg & 0xffff0000U) >> 16); } /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; + tmpreg = USBx_DEVICE->DAINT; tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xFFFF)); + + return ((tmpreg & 0xFFFFU)); } /** * @brief Returns Device OUT EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { + uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; - tmpreg = USBx_OUTEP(epnum)->DOEPINT; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; tmpreg &= USBx_DEVICE->DOEPMSK; + return tmpreg; } /** * @brief Returns Device IN EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { - uint32_t tmpreg = 0, msk = 0, emp = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; + msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - tmpreg = USBx_INEP(epnum)->DIEPINT & msk; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + return tmpreg; } /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx: Selected device - * @param interrupt: interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) { - USBx->GINTSTS |= interrupt; + USBx->GINTSTS |= interrupt; } /** * @brief Returns USB core mode - * @param USBx: Selected device + * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host + * 0 : Host * 1 : Device */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { - return ((USBx->GINTSTS ) & 0x1); + return ((USBx->GINTSTS) & 0x1U); } - /** * @brief Activate EP0 for Setup transactions - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) { - USBx_INEP(0)->DIEPCTL |= 3; + USBx_INEP(0U)->DIEPCTL |= 3U; } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; } - /** * @brief Prepare the EP0 to start the first control setup - * @param USBx: Selected device - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup: pointer to setup packet + * @param USBx Selected device + * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) { - /* Prevent unused argument(s) compilation warning */ UNUSED(psetup); + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - return HAL_OK; -} - -/** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t index = 0; - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) + if (gSNPSiD > USB_OTG_CORE_ID_300A) { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; - } - else - { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } } - /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - /* Clear all pending HC Interrupts */ - for (index = 0; index < cfg.Host_channels; index++) - { - USBx_HC(index)->HCINT = 0xFFFFFFFF; - USBx_HC(index)->HCINTMSK = 0; - } - - /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); - - HAL_Delay(200); - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; - - /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - return HAL_OK; } /** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the - * HCFG register on the PHY type and set the right frame interval - * @param USBx: Selected device - * @param freq: clock frequency - * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - - if (freq == HCFG_48_MHZ) + uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { - USBx_HOST->HFIR = (uint32_t)48000; + if (++count > 200000U) + { + return HAL_TIMEOUT; + } } - else if (freq == HCFG_6_MHZ) + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do { - USBx_HOST->HFIR = (uint32_t)6000; - } - return HAL_OK; + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + + /* Make sure the FIFOs are flushed. */ + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Enable VBUS driving */ + (void)USB_DriveVbus(USBx, 1U); + + HAL_Delay(200U); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xFFFFFFFFU; + + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + /* Enable the common interrupts */ + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return HAL_OK; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = 48000U; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = 6000U; + } + else + { + /* ... */ + } + + return HAL_OK; } /** * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL status - * @note (1)The application must wait at least 10 ms + * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0 = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + return HAL_OK; } /** * @brief USB_DriveVbus : activate or de-activate vbus - * @param state: VBUS state + * @param state VBUS state * This parameter can be one of these values: - * 0 : VBUS Active + * 0 : VBUS Active * 1 : VBUS Inactive * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) { - __IO uint32_t hprt0 = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + hprt0 = USBx_HPRT0; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); } - return HAL_OK; + return HAL_OK; } /** * @brief Return Host Core speed - * @param USBx: Selected device + * @param USBx Selected device * @retval speed : Host speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode */ -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) { - __IO uint32_t hprt0 = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); } /** * @brief Return Host Current Frame number - * @param USBx: Selected device + * @param USBx Selected device * @retval current frame number */ -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } /** * @brief Initialize a host channel - * @param USBx: Selected device - * @param ch_num : Channel number + * @param USBx Selected device + * @param ch_num Channel number * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number + * @param epnum Endpoint number * This parameter can be a value from 1 to 15 - * @param dev_address: Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed: Current device speed + * @param speed Current device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type + * @param ep_type Endpoint Type * This parameter can be one of these values: * @arg EP_TYPE_CTRL: Control type * @arg EP_TYPE_ISOC: Isochronous type * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size + * @param mps Max Packet Size * This parameter can be a value from 0 to32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -1404,374 +1395,397 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ep_type, uint16_t mps) { - + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; + /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + /* Enable channel interrupts required for this transfer. */ - switch (ep_type) + switch (ep_type) { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - break; - - case EP_TYPE_INTR: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - case EP_TYPE_ISOC: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; - } - - /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); - - /* Make sure host channel interrupts are enabled. */ - USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - - /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); - - if (ep_type == EP_TYPE_INTR) - { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; } - return HAL_OK; + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if (speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + + if (ep_type == EP_TYPE_INTR) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + } + + return ret; } /** * @brief Start a transfer over a host channel - * @param USBx: Selected device - * @param hc: pointer to host channel structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used + * @param USBx Selected device + * @param hc pointer to host channel structure * @retval HAL state */ -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#endif /* __CC_ARM */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc) { - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; - uint32_t tmpreg = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; + /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) + if (hc->xfer_len > 0U) { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } } else { - num_packets = 1; + num_packets = 1U; } - if (hc->ep_is_in) + if (hc->ep_is_in != 0U) { - hc->xfer_len = num_packets * hc->max_packet; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; } - + /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; + tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - - if (dma == 0) /* Slave mode */ - { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) { - switch(hc->ep_type) + switch (hc->ep_type) { /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (hc->xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); - // Added for MBED PR #3432 - hc->xfer_count = hc->xfer_len; + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len); } - } - + return HAL_OK; } /** * @brief Read all host channel interrupts status - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) { - return ((USBx_HOST->HAINT) & 0xFFFF); + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); } /** * @brief Halt a host channel - * @param USBx: Selected device - * @param hc_num: Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { - uint32_t count = 0; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->HNPTXSTS & 0xFFFF) == 0) + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do { - if (++count > 1000) + if (++count > 1000U) { break; } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do { - if (++count > 1000) + if (++count > 1000U) { break; } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } - + return HAL_OK; } /** * @brief Initiate Do Ping protocol - * @param USBx: Selected device - * @param hc_num: Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { - uint8_t num_packets = 1; - uint32_t tmpreg = 0; - - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; } /** * @brief Stop Host Core - * @param USBx: Selected device + * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { - uint8_t index; - uint32_t count = 0; - uint32_t value = 0; - - USB_DisableGlobalInt(USBx); - - /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); - + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; + uint32_t value; + uint32_t i; + + + (void)USB_DisableGlobalInt(USBx); + + /* Flush FIFO */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + /* Flush out any leftover queued requests. */ - for (index = 0; index <= 15; index++) + for (i = 0U; i <= 15U; i++) { - value = USBx_HC(index)->HCCHAR; + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; + USBx_HC(i)->HCCHAR = value; } - + /* Halt all channels to put them into a known state. */ - for (index = 0; index <= 15; index++) + for (i = 0U; i <= 15U; i++) { - value = USBx_HC(index)->HCCHAR ; + value = USBx_HC(i)->HCCHAR; value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; + value |= USB_OTG_HCCHAR_CHENA; value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; - - USBx_HC(index)->HCCHAR = value; - do + USBx_HC(i)->HCCHAR = value; + + do { - if (++count > 1000) + if (++count > 1000U) { break; } } - while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); - return HAL_OK; + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; } /** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { /* active Remote wakeup signalling */ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; } + return HAL_OK; } /** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) { + uint32_t USBx_BASE = (uint32_t)USBx; + /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + return HAL_OK; } +#endif /* defined (USB_OTG_FS) */ -#endif /* USB_OTG_FS */ - -/*============================================================================== - USB Device FS peripheral available on STM32L432xx, STM32L433xx, STM32L442xx) - and STM32L443xx devices -==============================================================================*/ #if defined (USB) /** * @brief Initializes the USB Core @@ -1782,15 +1796,15 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(cfg); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; } @@ -1802,15 +1816,17 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { - uint32_t winterruptmask = 0; - + uint16_t winterruptmask; + /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + /* Set interrupt mask */ USBx->CNTR |= winterruptmask; - + return HAL_OK; } @@ -1822,15 +1838,17 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { - uint32_t winterruptmask = 0; - + uint16_t winterruptmask; + /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + /* Clear interrupt mask */ USBx->CNTR &= ~winterruptmask; - + return HAL_OK; } @@ -1842,29 +1860,28 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) * @arg USB_DEVICE_MODE: Peripheral mode mode * @retval HAL status */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(mode); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return HAL_OK; } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit : Initializes the USB controller registers * for device mode * @param USBx : Selected device * @param cfg : pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) +HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); @@ -1872,16 +1889,40 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) /* Init Device */ /*CNTR_FRES = 1*/ USBx->CNTR = USB_CNTR_FRES; - + /*CNTR_FRES = 0*/ USBx->CNTR = 0; - + /*Clear pending interrupts*/ USBx->ISTR = 0; - + /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - + + /* Enable USB Device Interrupt mask */ + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed :Initializes the device speed + * depending on the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(speed); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; } @@ -1893,17 +1934,17 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(num); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; } @@ -1914,14 +1955,14 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) */ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - return HAL_OK; } @@ -1933,36 +1974,57 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { + HAL_StatusTypeDef ret = HAL_OK; + uint16_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; + /* initialize Endpoint */ switch (ep->type) { - case EP_TYPE_CTRL: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL); - break; - case EP_TYPE_BULK: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK); - break; - case EP_TYPE_INTR: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT); - break; - case EP_TYPE_ISOC: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS); - break; - default: + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; break; - } - + + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; + break; + } + + PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX); + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0) + + if (ep->doublebuffer == 0U) { - if (ep->is_in) + if (ep->is_in != 0U) { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } } else { @@ -1978,36 +2040,46 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) /*Double Buffer*/ else { - /*Set the endpoint as double buffered*/ + /* Set the endpoint as double buffered */ PCD_SET_EP_DBUF(USBx, ep->num); - /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in==0) + /* Set buffer address for double buffered mode */ + PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in == 0U) { - /* Clear the data toggle bits for the endpoint IN/OUT*/ + /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ + + /* Reset value of the data toggle bits for the endpoint out */ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { - /* Clear the data toggle bits for the endpoint IN/OUT*/ + /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); PCD_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - - return HAL_OK; + + return ret; } /** @@ -2018,13 +2090,13 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { - if (ep->is_in) + if (ep->is_in != 0U) { PCD_CLEAR_TX_DTOG(USBx, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { @@ -2035,16 +2107,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /*Double Buffer*/ else - { - if (ep->is_in==0) + { + if (ep->is_in == 0U) { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - + /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -2059,7 +2131,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } } - + return HAL_OK; } @@ -2069,36 +2141,36 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) * @param ep: pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t dma) +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - uint16_t pmabuffer = 0; - uint32_t len = ep->xfer_len; - + uint16_t pmabuffer; + uint32_t len; + /* IN endpoint */ - if (ep->is_in == 1) + if (ep->is_in == 1U) { /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { - len=ep->maxpacket; - ep->xfer_len-=len; + len = ep->maxpacket; + ep->xfer_len -= len; } else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) { - USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); + len = ep->xfer_len; + ep->xfer_len = 0U; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + { + USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); PCD_SET_EP_TX_CNT(USBx, ep->num, len); } else { /* Write the data to the USB endpoint */ - if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX) + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); @@ -2110,10 +2182,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } - + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); } else /* OUT endpoint */ @@ -2121,17 +2193,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t /* Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { - len=ep->maxpacket; - ep->xfer_len-=len; + len = ep->maxpacket; + ep->xfer_len -= len; } else { - len=ep->xfer_len; - ep->xfer_len =0; + len = ep->xfer_len; + ep->xfer_len = 0U; } - + /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); @@ -2139,17 +2211,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t else { /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); } - + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } - + return HAL_OK; } /** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param src : pointer to source buffer @@ -2159,22 +2231,20 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t */ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(src); UNUSED(ch_ep_num); UNUSED(len); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return HAL_OK; } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel * @param USBx : Selected device * @param dest : destination pointer @@ -2183,43 +2253,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep */ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(dest); UNUSED(len); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return ((void *)NULL); } /** * @brief USB_EPSetStall : set a stall condition over an EP * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param ep: pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->num == 0) + if (ep->is_in != 0U) { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); } else { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL); - } + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); } + return HAL_OK; } @@ -2231,16 +2292,27 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->is_in) + if (ep->doublebuffer == 0U) { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } } + return HAL_OK; } @@ -2253,13 +2325,13 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ USBx->CNTR = USB_CNTR_FRES; - + /* clear interrupt status register */ USBx->ISTR = 0; - + /* switch-off device */ USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - + return HAL_OK; } @@ -2270,14 +2342,14 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) { - if(address == 0) + if (address == 0U) { - /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; + /* set device address and enable function */ + USBx->DADDR = USB_DADDR_EF; } - + return HAL_OK; } @@ -2286,11 +2358,11 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) * @param USBx : Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - USB->BCDR |= USB_BCDR_DPPU; - + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + USBx->BCDR |= USB_BCDR_DPPU; + return HAL_OK; } @@ -2299,11 +2371,11 @@ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) { - /* Disable DP Pull-Down bit*/ - USB->BCDR &= ~(USB_BCDR_DPPU); - + /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ + USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); + return HAL_OK; } @@ -2312,10 +2384,10 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) { - uint32_t tmpreg = 0; - + uint32_t tmpreg; + tmpreg = USBx->ISTR; return tmpreg; } @@ -2325,16 +2397,14 @@ uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - return (0); } @@ -2343,16 +2413,14 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) * @param USBx : Selected device * @retval HAL status */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - return (0); } @@ -2363,17 +2431,15 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(epnum); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return (0); } @@ -2384,74 +2450,68 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(epnum); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return (0); } /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) +void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(interrupt); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ } /** * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param psetup : pointer to setup packet + * @param USBx Selected device + * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma ,uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); UNUSED(psetup); - UNUSED(dma); - + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ return HAL_OK; } /** * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { USBx->CNTR |= USB_CNTR_RESUME; - + return HAL_OK; } /** * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) @@ -2461,114 +2521,91 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. - * @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; - uint16_t temp1, temp2; + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp1, temp2; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); + uint8_t *pBuf = pbUsrBuf; - for (i = n; i != 0; i--) + pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pbUsrBuf++; + temp1 = (uint16_t) * pBuf; + pBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8)); + *pdwVal = (uint16_t)temp2; + pdwVal++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + + pBuf++; } } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. -* @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx: USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; + uint32_t n = (uint32_t)wNBytes >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; + temp = *pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + pBuf++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + } + + if ((wNBytes % 2U) != 0U) + { + temp = *pdwVal; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); } } -#endif /* USB */ -/** - * @} - */ +#endif /* defined (USB) */ + /** * @} */ -#if defined (USB_OTG_FS) -/** @addtogroup USB_LL_Private_Functions - * @{ - */ -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - /* Wait for AHB master IDLE state. */ - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - - /* Core Soft Reset */ - count = 0; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; -} /** * @} */ -#endif /* USB_OTG_FS */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +#endif /* defined (USB) || defined (USB_OTG_FS) */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ -/** - * @} - */ /** * @} */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h index 8c02253cb0..b8a3eec722 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h @@ -2,619 +2,651 @@ ****************************************************************************** * @file stm32l4xx_ll_usb.h * @author MCD Application Team - * @brief Header file of USB Core HAL module. + * @brief Header file of USB Low Layer HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_USB_H -#define __STM32L4xx_LL_USB_H +#ifndef STM32L4xx_LL_USB_H +#define STM32L4xx_LL_USB_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" -/** @addtogroup STM32L4xx_HAL +#if defined (USB) || defined (USB_OTG_FS) +/** @addtogroup STM32L4xx_HAL_Driver * @{ */ -/** @addtogroup USB_Core +/** @addtogroup USB_LL * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USB Mode definition - */ -typedef enum -{ - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 - -}USB_ModeTypeDef; +/* Exported types ------------------------------------------------------------*/ +/** + * @brief USB Mode definition + */ #if defined (USB_OTG_FS) -/** - * @brief URB States definition - */ -typedef enum { + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ URB_IDLE = 0, URB_DONE, URB_NOTREADY, URB_NYET, URB_ERROR, URB_STALL - -}USB_OTG_URBStateTypeDef; +} USB_OTG_URBStateTypeDef; -/** - * @brief Host channel States definition - */ -typedef enum { +/** + * @brief Host channel States definition + */ +typedef enum +{ HC_IDLE = 0, HC_XFRC, HC_HALTED, HC_NAK, HC_NYET, HC_STALL, - HC_XACTERR, - HC_BBLERR, + HC_XACTERR, + HC_BBLERR, HC_DATATGLERR - -}USB_OTG_HCStateTypeDef; +} USB_OTG_HCStateTypeDef; -/** - * @brief PCD Initialization Structure definition +/** + * @brief USB OTG Initialization Structure definition */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS_ */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed_ */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - -}USB_OTG_CfgTypeDef; + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY_ */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +} USB_OTG_CfgTypeDef; typedef struct { - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ - - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t even_odd_frame; /*!< IFrame parity - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ -}USB_OTG_EPTypeDef; + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type_ */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +} USB_OTG_EPTypeDef; typedef struct { - uint8_t dev_addr ; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + uint8_t dev_addr ; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - - uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ - - uint16_t max_packet; /*!< Endpoint Max packet size. - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t data_pid; /*!< Initial data PID. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - - uint32_t xfer_len; /*!< Current transfer length. */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - - uint8_t toggle_in; /*!< IN transfer current toggle flag. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t toggle_out; /*!< OUT transfer current toggle flag - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - - uint32_t ErrCnt; /*!< Host channel error count.*/ - - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ - -}USB_OTG_HCTypeDef; -#endif /* USB_OTG_FS */ + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type_ */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count.*/ + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_FS) */ #if defined (USB) -/** - * @brief USB Initialization Structure definition + +typedef enum +{ + USB_DEVICE_MODE = 0 +} USB_ModeTypeDef; + +/** + * @brief USB Initialization Structure definition */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ + + uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; typedef struct { - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type */ - - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ - - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral - This parameter is added to ensure compatibility across USB peripherals */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + This parameter can be 0 or 1 */ + + uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral + This parameter is added to ensure compatibility across USB peripherals */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_EPTypeDef; -#endif /* USB */ +#endif /* defined (USB) */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ + #if defined (USB_OTG_FS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + /** @defgroup USB_Core_Mode_ USB Core Mode * @{ */ -#define USB_OTG_MODE_DEVICE 0 -#define USB_OTG_MODE_HOST 1 -#define USB_OTG_MODE_DRD 2 +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U /** * @} */ -/** @defgroup USB_Core_Speed_ USB Core Speed - * @{ - */ -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_LOW 2 -#define USB_OTG_SPEED_FULL 3 -/** - * @} - */ - -/** @defgroup USB_Core_PHY_ USB Core PHY - * @{ - */ -#define USB_OTG_EMBEDDED_PHY 1 -/** - * @} - */ - -/** @defgroup USB_Core_MPS_ USB Core MPS +/** @defgroup USB_LL Device Speed * @{ */ -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 +#define USBD_FS_SPEED 2U +#define USBH_FS_SPEED 1U /** * @} */ -/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) -/** - * @} - */ - -/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval - * @{ - */ -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 +#define USB_OTG_SPEED_FULL 3U /** * @} */ -/** @defgroup USB_EP0_MPS_ USB EP0 MPS +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U /** * @} */ -/** @defgroup USB_EP_Speed_ USB EP Speed +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value * @{ */ -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ /** * @} */ -/** @defgroup USB_EP_Type_ USB EP Type +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ -/** @defgroup USB_STS_Defines_ USB STS Defines +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency * @{ */ -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) /** * @} */ -/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval * @{ - */ -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U /** * @} */ - -/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines - * @{ - */ -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 -/** - * @} - */ - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) - -#endif /* USB_OTG_FS */ - -#if defined (USB) /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U /** * @} - */ + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ /** @defgroup USB_LL_EP_Type USB Low Layer EP Type * @{ */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U /** * @} - */ + */ -#define BTABLE_ADDRESS (0x000) -#endif /* USB */ +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_FS_SPEED 2U +/** + * @} + */ + +#define BTABLE_ADDRESS 0x000U +#define PMA_ACCESS 1U +#endif /* defined (USB) */ +#if defined (USB_OTG_FS) +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) */ +#if defined (USB) +#define EP_ADDR_MSK 0x7U +#endif /* defined (USB) */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ #if defined (USB_OTG_FS) #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - + #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) -#endif /* USB_OTG_FS */ +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ #if defined (USB_OTG_FS) -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); // MBED PATCH -HAL_StatusTypeDef USB_EPSetNak(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); // MBED PATCH -HAL_StatusTypeDef USB_EPClearNak(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); // MBED PATCH -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup); uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq); +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc); +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -#endif /* USB_OTG_FS */ +#endif /* defined (USB_OTG_FS) */ #if defined (USB) -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); -HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ); +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep ,uint8_t dma); +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void * USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx); +void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt); +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -#endif /* USB */ +#endif /* defined (USB) */ /** * @} - */ + */ /** * @} */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ + #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_LL_USB_H */ +#endif /* STM32L4xx_LL_USB_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c index dff9d0b8ff..0f1999b45d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -37,13 +21,11 @@ #include "stm32l4xx_ll_rcc.h" #include "stm32l4xx_ll_system.h" #include "stm32l4xx_ll_pwr.h" - -// Removed from MBED PR #3410 -//#ifdef USE_FULL_ASSERT -//#include "stm32_assert.h" -//#else -//#define assert_param(expr) ((void)0U) -//#endif /* USE_FULL_ASSERT */ +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32L4xx_LL_Driver * @{ @@ -134,7 +116,7 @@ || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ || ((__VALUE__) == LL_RCC_PLLM_DIV_8)) -#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \ || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \ @@ -204,20 +186,22 @@ void LL_Init1msTick(uint32_t HCLKFrequency) void LL_mDelay(uint32_t Delay) { __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + uint32_t tmpDelay = Delay; + /* Add this code to indicate that local variable is not used */ ((void)tmp); /* Add a period to guaranty minimum wait */ - if(Delay < LL_MAX_DELAY) + if(tmpDelay < LL_MAX_DELAY) { - Delay++; + tmpDelay++; } - while (Delay) + while (tmpDelay != 0U) { if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) { - Delay--; + tmpDelay--; } } } @@ -236,7 +220,7 @@ void LL_mDelay(uint32_t Delay) [..] System, AHB and APB buses clocks configuration - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others. @endverbatim @internal @@ -317,16 +301,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U, msi_range = 0U; + uint32_t pllfreq, msi_range; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; + uint32_t hpre = 0U; /* Set default value */ #endif /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) { /* Get the current MSI range */ - if(LL_RCC_MSI_IsEnabledRangeSelect()) + if(LL_RCC_MSI_IsEnabledRangeSelect() != 0U) { msi_range = LL_RCC_MSI_GetRange(); switch (msi_range) @@ -442,10 +426,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; + ErrorStatus status; + uint32_t pllfreq; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; + uint32_t hpre = 0U; /* Set default value */ #endif /* Check if one of the PLL is enabled */ @@ -523,10 +507,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; + ErrorStatus status; + uint32_t pllfreq; #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; + uint32_t hpre = 0U; /* Set default value */ #endif /* Check the parameters */ @@ -748,7 +732,7 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) { - uint32_t pllfreq = 0U; + uint32_t pllfreq; /* Check the parameters */ assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); @@ -757,7 +741,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL /* Check different PLL parameters according to RM */ /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */ - pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1)); + pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U)); assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/ @@ -765,7 +749,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); /* - PLLR: ensure that max frequency at 120000000 Hz is reached */ - pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1) * 2); + pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U); assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); return pllfreq; @@ -788,12 +772,14 @@ static ErrorStatus UTILS_PLL_IsBusy(void) status = ERROR; } +#if defined(RCC_PLLSAI1_SUPPORT) /* Check if PLLSAI1 is busy*/ if(LL_RCC_PLLSAI1_IsReady() != 0U) { /* PLLSAI1 configuration cannot be modified */ status = ERROR; } +#endif /*RCC_PLLSAI1_SUPPORT*/ #if defined(RCC_PLLSAI2_SUPPORT) /* Check if PLLSAI2 is busy*/ @@ -819,7 +805,7 @@ static ErrorStatus UTILS_PLL_IsBusy(void) static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; - uint32_t hclk_frequency = 0U; + uint32_t hclk_frequency; assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); @@ -858,7 +844,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); } - + /* Decreasing the number of wait states because of lower CPU frequency */ if(SystemCoreClock > hclk_frequency) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h index 01a32c8ab8..1ecb7d5278 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h @@ -18,29 +18,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h index 01ba7d0987..2fde58cb8a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h @@ -6,36 +6,20 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_WWDG_H -#define __STM32L4xx_LL_WWDG_H +#ifndef STM32L4xx_LL_WWDG_H +#define STM32L4xx_LL_WWDG_H #ifdef __cplusplus extern "C" { @@ -49,30 +33,25 @@ extern "C" { */ #if defined (WWDG) - /** @defgroup WWDG_LL WWDG * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ - /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants * @{ */ - /** @defgroup WWDG_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions * @{ */ -#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI /** * @} */ @@ -80,10 +59,10 @@ extern "C" { /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER * @{ */ -#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ /** * @} */ @@ -119,7 +98,6 @@ extern "C" { * @} */ - /** * @} */ @@ -155,7 +133,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) */ __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) { - return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); + return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } /** @@ -182,7 +160,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) */ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) { - return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T)); + return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } /** @@ -215,7 +193,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale */ __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) { - return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); + return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } /** @@ -247,7 +225,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) */ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) { - return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W)); + return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } /** @@ -268,7 +246,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) */ __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) { - return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); + return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } /** @@ -310,7 +288,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) */ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) { - return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); + return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } /** @@ -335,6 +313,6 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) } #endif -#endif /* __STM32L4xx_LL_WWDG_H */ +#endif /* STM32L4xx_LL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c index f8719f6b4d..ebc0a81f61 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c @@ -66,29 +66,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -187,11 +171,6 @@ * @{ */ -// Removed from MBED PR #4740 -/*+ MBED */ -#if 0 -/*- MBED */ - /** * @brief Setup the microcontroller system. * @param None @@ -228,14 +207,11 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#include "nvic_addr.h" // MBED + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED #endif } -/*+ MBED */ -#endif -/*- MBED */ - /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.h similarity index 56% rename from targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h rename to targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.h index 4bbc092679..70c38997b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/system_stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -103,8 +87,6 @@ extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index bb1bc5e4de..88f406bfdd 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -189,13 +189,13 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) if (irq == RxIrq) { __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); // Check if TxIrq is disabled too - if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) { + if (LL_LPUART_IsEnabledIT_TXE(huart->Instance) == 0) { all_disabled = 1; } } else { // TxIrq __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); // Check if RxIrq is disabled too - if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) { + if (LL_LPUART_IsEnabledIT_RXNE(huart->Instance) == 0) { all_disabled = 1; } } diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index f9a159e5f0..a1d7052daf 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -180,6 +180,8 @@ void lp_ticker_init(void) #if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT) /* EXTI lines are not configured by default */ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); +#endif +#if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE) __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); #endif @@ -279,8 +281,8 @@ void lp_ticker_set_interrupt(timestamp_t timestamp) * not less than few ticks away (LP_TIMER_SAFE_GUARD). So let's make sure it' * s at least current tick + LP_TIMER_SAFE_GUARD */ for(uint8_t i = 0; i < LP_TIMER_SAFE_GUARD; i++) { - if (LP_TIMER_WRAP(last_read_counter + i) == timestamp) { - timestamp = LP_TIMER_WRAP(timestamp + LP_TIMER_SAFE_GUARD); + if (LP_TIMER_WRAP((last_read_counter + i)) == timestamp) { + timestamp = LP_TIMER_WRAP((timestamp + LP_TIMER_SAFE_GUARD)); } } /* Then check if this target timestamp is not in the past, or close to wrap-around diff --git a/targets/targets.json b/targets/targets.json index 2b7e402991..c18fcf0f2c 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3413,7 +3413,11 @@ "NUCLEO_L432KC": { "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"], + "extra_labels_add": [ + "STM32L4", + "STM32L432xC", + "STM32L432KC" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -3426,7 +3430,9 @@ } }, "macros_add": [ - "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED" + "STM32L432xx", + "MBED_TICKLESS", + "EXTRA_IDLE_STACK_REQUIRED" ], "overrides": { "lpticker_delay_ticks": 0 }, "detect_code": ["0770"], @@ -3445,9 +3451,16 @@ }, "NUCLEO_L433RC_P": { "inherits": ["FAMILY_STM32"], - "supported_form_factors": ["ARDUINO", "MORPHO"], + "supported_form_factors": [ + "ARDUINO", + "MORPHO" + ], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"], + "extra_labels_add": [ + "STM32L4", + "STM32L433xC", + "STM32L433RC" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -3460,7 +3473,9 @@ } }, "macros_add": [ - "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED" + "STM32L433xx", + "MBED_TICKLESS", + "EXTRA_IDLE_STACK_REQUIRED" ], "overrides": { "lpticker_delay_ticks": 0 }, "detect_code": ["0779"], @@ -3500,7 +3515,7 @@ "MPU" ], "device_has_remove": ["LPTICKER"], - "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "MBED_SPLIT_HEAP"], + "macros_add": ["STM32L443xx", "MBEDTLS_CONFIG_HW_SUPPORT", "MBED_SPLIT_HEAP"], "device_name": "STM32L443RC", "detect_code": ["0458"], "bootloader_supported": true @@ -3524,6 +3539,7 @@ "overrides": { "lpticker_delay_ticks": 0 }, "detect_code": ["0765"], "macros_add": [ + "STM32L476xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED", "USBHOST_OTHER", @@ -3555,7 +3571,10 @@ } }, "detect_code": ["0766"], - "macros_add": ["USBHOST_OTHER"], + "macros_add": [ + "STM32L476xx", + "USBHOST_OTHER" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -3572,7 +3591,11 @@ "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"], + "extra_labels_add": [ + "STM32L4", + "STM32L486RG", + "STM32L486xG" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -3587,9 +3610,9 @@ "overrides": { "lpticker_delay_ticks": 0 }, "detect_code": ["0827"], "macros_add": [ + "STM32L486xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED", - "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT", "MBED_SPLIT_HEAP" ], @@ -3625,6 +3648,7 @@ "overrides": { "lpuart_clock_source": "USE_LPUART_CLK_HSI" }, "detect_code": ["0460"], "macros_add": [ + "STM32L486xx", "MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570", "MBED_SPLIT_HEAP" @@ -4179,10 +4203,17 @@ } }, "DISCO_L475VG_IOT01A": { - "components_add": ["QSPIF", "FLASHIAP"], + "components_add": [ + "QSPIF", + "FLASHIAP" + ], "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"], + "extra_labels_add": [ + "STM32L4", + "STM32L475xG", + "STM32L475VG" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -4198,9 +4229,9 @@ "supported_form_factors": ["ARDUINO"], "detect_code": ["0764"], "macros_add": [ + "STM32L475xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED", - "USBHOST_OTHER", "MBED_SPLIT_HEAP" ], "device_has_add": [ @@ -4210,7 +4241,6 @@ "TRNG", "FLASH", "QSPI", - "USBDEVICE", "MPU" ], "release_versions": ["2", "5"], @@ -4233,7 +4263,7 @@ } }, "detect_code": ["0468"], - "macros_add": ["USBHOST_OTHER", "MBED_SPLIT_HEAP"], + "macros_add": ["STM32L475xx", "USBHOST_OTHER", "MBED_SPLIT_HEAP"], "device_has_add": [ "ANALOGOUT", "CAN", @@ -4251,7 +4281,11 @@ "components_add": ["QSPIF", "FLASHIAP"], "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"], + "extra_labels_add": [ + "STM32L4", + "STM32L476xG", + "STM32L476VG" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -4266,9 +4300,9 @@ "overrides": { "lpticker_delay_ticks": 0 }, "detect_code": ["0820"], "macros_add": [ + "STM32L476xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED", - "USBHOST_OTHER", "MBED_SPLIT_HEAP" ], "device_has_add": [ @@ -4278,7 +4312,6 @@ "TRNG", "FLASH", "QSPI", - "USBDEVICE", "MPU" ], "release_versions": ["2", "5"], @@ -4304,6 +4337,7 @@ "overrides": { "lpticker_delay_ticks": 0 }, "detect_code": ["1500"], "macros_add": [ + "STM32L476xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED", "USBHOST_OTHER", @@ -4422,6 +4456,7 @@ "MPU" ], "macros_add": [ + "STM32L471xx", "MBED_SPLIT_HEAP" ], "release_versions": ["2", "5"], @@ -7780,8 +7815,14 @@ "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "STMOD", "PMOD"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"], - "components_add": ["QSPIF"], + "extra_labels_add": [ + "STM32L4", + "STM32L496AG", + "STM32L496xG" + ], + "components_add": [ + "QSPIF" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -7794,6 +7835,7 @@ } }, "macros_add": [ + "STM32L496xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED" ], @@ -7807,7 +7849,6 @@ "TRNG", "FLASH", "MPU", - "USBDEVICE", "QSPI" ], "release_versions": ["2", "5"], @@ -7818,7 +7859,11 @@ "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L496ZG", "STM32L496xG"], + "extra_labels_add": [ + "STM32L4", + "STM32L496ZG", + "STM32L496xG" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -7831,6 +7876,7 @@ } }, "macros_add": [ + "STM32L496xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED" ], @@ -7843,7 +7889,6 @@ "SERIAL_ASYNCH", "TRNG", "FLASH", - "USBDEVICE", "MPU" ], "release_versions": ["2", "5"], @@ -7858,7 +7903,11 @@ "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], "core": "Cortex-M4F", - "extra_labels_add": ["STM32L4", "STM32L4R5ZI", "STM32L4R5xI"], + "extra_labels_add": [ + "STM32L4", + "STM32L4R5ZI", + "STM32L4R5xI" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -7871,6 +7920,7 @@ } }, "macros_add": [ + "STM32L4R5xx", "MBED_TICKLESS", "EXTRA_IDLE_STACK_REQUIRED" ], @@ -7883,7 +7933,6 @@ "SERIAL_ASYNCH", "TRNG", "FLASH", - "USBDEVICE", "MPU" ], "release_versions": ["2", "5"], @@ -7896,9 +7945,16 @@ }, "DISCO_L4R9I": { "inherits": [ "FAMILY_STM32" ], - "supported_form_factors": [ "ARDUINO", "STMOD", "PMOD" ], + "supported_form_factors": [ + "ARDUINO", + "STMOD", + "PMOD" + ], "core": "Cortex-M4F", - "extra_labels_add": [ "STM32L4", "STM32L4R9xI" ], + "extra_labels_add": [ + "STM32L4", + "STM32L4R9xI" + ], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",