From 95f6826196be0869295a2983e79e623b7045aec0 Mon Sep 17 00:00:00 2001 From: Bogdan Marinescu Date: Thu, 5 Sep 2013 18:31:17 +0300 Subject: [PATCH] Refactor code for LPC810/LPC812 There were lots of overlaps in the code for LPC810 and LPC812, including duplicated source files. This commit adds a TARGET_LPC81X_COMMON folder in both HAL and CMSIS, this folder keeps common code for the targets. --- .../cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h | 687 ------------------ .../TOOLCHAIN_ARM_MICRO/LPC810.sct | 0 .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s | 0 .../TARGET_LPC810/system_LPC8xx.c | 0 .../TOOLCHAIN_ARM_MICRO/LPC812.sct | 0 .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s | 0 .../{ => TARGET_LPC812}/system_LPC8xx.c | 0 .../TARGET_LPC81X_COMMON}/LPC8xx.h | 0 .../TOOLCHAIN_ARM_MICRO/sys.cpp | 0 .../TARGET_LPC81X_COMMON}/cmsis.h | 0 .../TARGET_LPC81X_COMMON}/cmsis_nvic.c | 0 .../TARGET_LPC81X_COMMON}/cmsis_nvic.h | 0 .../TARGET_LPC81X_COMMON}/system_LPC8xx.h | 0 .../TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp | 31 - .../cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h | 13 - .../TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c | 30 - .../TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h | 26 - .../TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h | 62 -- .../TARGET_LPC81X/PeripheralNames.h | 30 - .../hal/TARGET_NXP/TARGET_LPC81X/PortNames.h | 30 - .../TARGET_LPC810/PinNames.h | 0 .../{ => TARGET_LPC812}/PinNames.h | 0 .../TARGET_LPC81X_COMMON}/PeripheralNames.h | 0 .../TARGET_LPC81X_COMMON}/PortNames.h | 0 .../TARGET_LPC81X_COMMON}/device.h | 0 .../TARGET_LPC81X_COMMON}/gpio_api.c | 0 .../TARGET_LPC81X_COMMON}/gpio_irq_api.c | 0 .../TARGET_LPC81X_COMMON}/gpio_object.h | 0 .../TARGET_LPC81X_COMMON}/i2c_api.c | 0 .../TARGET_LPC81X_COMMON}/objects.h | 0 .../TARGET_LPC81X_COMMON}/pinmap.c | 0 .../TARGET_LPC81X_COMMON}/serial_api.c | 0 .../TARGET_LPC81X_COMMON}/spi_api.c | 0 .../TARGET_LPC81X_COMMON}/us_ticker.c | 0 .../hal/TARGET_NXP/TARGET_LPC81X/device.h | 57 -- .../hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c | 69 -- .../TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c | 127 ---- .../TARGET_NXP/TARGET_LPC81X/gpio_object.h | 48 -- .../hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c | 242 ------ .../hal/TARGET_NXP/TARGET_LPC81X/objects.h | 52 -- .../hal/TARGET_NXP/TARGET_LPC81X/pinmap.c | 50 -- .../hal/TARGET_NXP/TARGET_LPC81X/serial_api.c | 280 ------- .../hal/TARGET_NXP/TARGET_LPC81X/spi_api.c | 210 ------ .../hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c | 93 --- workspace_tools/targets.py | 4 +- 45 files changed, 2 insertions(+), 2139 deletions(-) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h rename libraries/mbed/targets/cmsis/TARGET_NXP/{ => TARGET_LPC81X}/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{ => TARGET_LPC81X}/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{ => TARGET_LPC81X}/TARGET_LPC810/system_LPC8xx.c (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/{ => TARGET_LPC812}/TOOLCHAIN_ARM_MICRO/LPC812.sct (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/{ => TARGET_LPC812}/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/{ => TARGET_LPC812}/system_LPC8xx.c (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/LPC8xx.h (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/TOOLCHAIN_ARM_MICRO/sys.cpp (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/cmsis.h (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/cmsis_nvic.c (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/cmsis_nvic.h (100%) rename libraries/mbed/targets/cmsis/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/system_LPC8xx.h (100%) delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h delete mode 100644 libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PeripheralNames.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PortNames.h rename libraries/mbed/targets/hal/TARGET_NXP/{ => TARGET_LPC81X}/TARGET_LPC810/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/{ => TARGET_LPC812}/PinNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/PeripheralNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/PortNames.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/device.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/gpio_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/gpio_irq_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/gpio_object.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/i2c_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/objects.h (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/pinmap.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/serial_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/spi_api.c (100%) rename libraries/mbed/targets/hal/TARGET_NXP/{TARGET_LPC810 => TARGET_LPC81X/TARGET_LPC81X_COMMON}/us_ticker.c (100%) delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/pinmap.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c delete mode 100644 libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h deleted file mode 100644 index 4dcffe4496..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h +++ /dev/null @@ -1,687 +0,0 @@ -/**************************************************************************** - * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $ - * Project: NXP LPC8xx software example - * - * Description: - * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for - * NXP LPC800 Device Series - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' - * relevant copyright in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. -****************************************************************************/ -#ifndef __LPC8xx_H__ -#define __LPC8xx_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup LPC8xx_Definitions LPC8xx Definitions - This file defines all structures and symbols for LPC8xx: - - Registers and bitfields - - peripheral base address - - PIO definitions - @{ -*/ - - -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions - Configuration of the Cortex-M0+ Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** LPC8xx Specific Interrupt Numbers ********************************************************/ - SPI0_IRQn = 0, /*!< SPI0 */ - SPI1_IRQn = 1, /*!< SPI1 */ - Reserved0_IRQn = 2, /*!< Reserved Interrupt */ - UART0_IRQn = 3, /*!< USART0 */ - UART1_IRQn = 4, /*!< USART1 */ - UART2_IRQn = 5, /*!< USART2 */ - Reserved1_IRQn = 6, /*!< Reserved Interrupt */ - Reserved2_IRQn = 7, /*!< Reserved Interrupt */ - I2C_IRQn = 8, /*!< I2C */ - SCT_IRQn = 9, /*!< SCT */ - MRT_IRQn = 10, /*!< MRT */ - CMP_IRQn = 11, /*!< CMP */ - WDT_IRQn = 12, /*!< WDT */ - BOD_IRQn = 13, /*!< BOD */ - Reserved3_IRQn = 14, /*!< Reserved Interrupt */ - WKT_IRQn = 15, /*!< WKT Interrupt */ - Reserved4_IRQn = 16, /*!< Reserved Interrupt */ - Reserved5_IRQn = 17, /*!< Reserved Interrupt */ - Reserved6_IRQn = 18, /*!< Reserved Interrupt */ - Reserved7_IRQn = 19, /*!< Reserved Interrupt */ - Reserved8_IRQn = 20, /*!< Reserved Interrupt */ - Reserved9_IRQn = 21, /*!< Reserved Interrupt */ - Reserved10_IRQn = 22, /*!< Reserved Interrupt */ - Reserved11_IRQn = 23, /*!< Reserved Interrupt */ - PININT0_IRQn = 24, /*!< External Interrupt 0 */ - PININT1_IRQn = 25, /*!< External Interrupt 1 */ - PININT2_IRQn = 26, /*!< External Interrupt 2 */ - PININT3_IRQn = 27, /*!< External Interrupt 3 */ - PININT4_IRQn = 28, /*!< External Interrupt 4 */ - PININT5_IRQn = 29, /*!< External Interrupt 5 */ - PININT6_IRQn = 30, /*!< External Interrupt 6 */ - PININT7_IRQn = 31, /*!< External Interrupt 7 */ -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*@}*/ /* end of group LPC8xx_CMSIS */ - - -#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ -#include "system_LPC8xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block - @{ -*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ - __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ - __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ - __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ - uint32_t RESERVED0[4]; - - __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ - __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ - uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ - __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ - uint32_t RESERVED3[10]; - - __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ - __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ - __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ - uint32_t RESERVED5[4]; - __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ - uint32_t RESERVED6[18]; - - __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ - __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ - __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ - uint32_t RESERVED7; - __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ - __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ - uint32_t RESERVED8[1]; - __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ - __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ - uint32_t RESERVED9[12]; - __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */ - __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ - __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ - uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - uint32_t RESERVED11[27]; - __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ - __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ - __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ - uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ -} LPC_SYSCON_TypeDef; -/*@}*/ /* end of group LPC8xx_SYSCON */ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ - __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ - __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ - __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ - __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */ - __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */ - __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ - __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ - __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */ - __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */ - __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */ - __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ -} LPC_IOCON_TypeDef; -/*@}*/ /* end of group LPC8xx_IOCON */ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL) - */ -typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ - __I uint32_t RESERVED2; - __I uint32_t FMSW0; -} LPC_FLASHCTRL_TypeDef; -/*@}*/ /* end of group LPC8xx_FLASHCTRL */ - - -/*------------- Power Management Unit (PMU) --------------------------*/ -/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit - @{ -*/ -typedef struct -{ - __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ - __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ - __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ - __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ - __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ - __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ -} LPC_PMU_TypeDef; -/*@}*/ /* end of group LPC8xx_PMU */ - - -/*------------- Switch Matrix Port --------------------------*/ -/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port - @{ -*/ -typedef struct -{ - union { - __IO uint32_t PINASSIGN[9]; - struct { - __IO uint32_t PINASSIGN0; - __IO uint32_t PINASSIGN1; - __IO uint32_t PINASSIGN2; - __IO uint32_t PINASSIGN3; - __IO uint32_t PINASSIGN4; - __IO uint32_t PINASSIGN5; - __IO uint32_t PINASSIGN6; - __IO uint32_t PINASSIGN7; - __IO uint32_t PINASSIGN8; - }; - }; - __I uint32_t RESERVED0[103]; - __IO uint32_t PINENABLE0; -} LPC_SWM_TypeDef; -/*@}*/ /* end of group LPC8xx_SWM */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */ - __I uint16_t RESERVED0[2039]; - __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */ - uint32_t RESERVED1[1006]; - __IO uint32_t DIR0; /* 0x2000 */ - uint32_t RESERVED2[31]; - __IO uint32_t MASK0; /* 0x2080 */ - uint32_t RESERVED3[31]; - __IO uint32_t PIN0; /* 0x2100 */ - uint32_t RESERVED4[31]; - __IO uint32_t MPIN0; /* 0x2180 */ - uint32_t RESERVED5[31]; - __IO uint32_t SET0; /* 0x2200 */ - uint32_t RESERVED6[31]; - __O uint32_t CLR0; /* 0x2280 */ - uint32_t RESERVED7[31]; - __O uint32_t NOT0; /* 0x2300 */ - -} LPC_GPIO_PORT_TypeDef; - - -// ------------------------------------------------------------------------------------------------ -// ----- PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT) - */ - -typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ - __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ - __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ - __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ -} LPC_PIN_INT_TypeDef; - - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -/** @addtogroup LPC8xx_CRC - @{ -*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - __O uint32_t WR_DATA_DWORD; - __O uint16_t WR_DATA_WORD; - uint16_t RESERVED_WORD; - __O uint8_t WR_DATA_BYTE; - uint8_t RESERVED_BYTE[3]; - }; -} LPC_CRC_TypeDef; -/*@}*/ /* end of group LPC8xx_CRC */ - -/*------------- Comparator (CMP) --------------------------------------------------*/ -/** @addtogroup LPC8xx_CMP LPC8xx Comparator - @{ -*/ -typedef struct { /*!< (@ 0x40024000) CMP Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ - __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ -} LPC_CMP_TypeDef; -/*@}*/ /* end of group LPC8xx_CMP */ - - -/*------------- Wakeup Timer (WKT) --------------------------------------------------*/ -/** @addtogroup LPC8xx_WKT - @{ -*/ -typedef struct { /*!< (@ 0x40028000) WKT Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */ - uint32_t Reserved[2]; - __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */ -} LPC_WKT_TypeDef; -/*@}*/ /* end of group LPC8xx_WKT */ - - -/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ -typedef struct { -__IO uint32_t INTVAL; -__IO uint32_t TIMER; -__IO uint32_t CTRL; -__IO uint32_t STAT; -} MRT_Channel_cfg_Type; - -typedef struct { - MRT_Channel_cfg_Type Channel[4]; - uint32_t Reserved0[1]; - __IO uint32_t IDLE_CH; - __IO uint32_t IRQ_FLAG; -} LPC_MRT_TypeDef; - - -/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ -/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter - @{ -*/ -/** - * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART) - */ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t CTRL; - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; /* 0x10 */ - __I uint32_t RXDATA; - __I uint32_t RXDATA_STAT; - __IO uint32_t TXDATA; - __IO uint32_t BRG; /* 0x20 */ - __IO uint32_t INTSTAT; -} LPC_USART_TypeDef; - -/*@}*/ /* end of group LPC8xx_USART */ - - -/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/ -/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port - @{ -*/ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t DLY; - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; /* 0x10 */ - __I uint32_t RXDAT; - __IO uint32_t TXDATCTL; - __IO uint32_t TXDAT; - __IO uint32_t TXCTRL; /* 0x20 */ - __IO uint32_t DIV; - __I uint32_t INTSTAT; -} LPC_SPI_TypeDef; -/*@}*/ /* end of group LPC8xx_SPI */ - - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -/** @addtogroup LPC8xx_I2C I2C-Bus Interface - @{ -*/ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; - __IO uint32_t TIMEOUT; /* 0x10 */ - __IO uint32_t DIV; - __IO uint32_t INTSTAT; - uint32_t Reserved0[1]; - __IO uint32_t MSTCTL; /* 0x20 */ - __IO uint32_t MSTTIME; - __IO uint32_t MSTDAT; - uint32_t Reserved1[5]; - __IO uint32_t SLVCTL; /* 0x40 */ - __IO uint32_t SLVDAT; - __IO uint32_t SLVADR0; - __IO uint32_t SLVADR1; - __IO uint32_t SLVADR2; /* 0x50 */ - __IO uint32_t SLVADR3; - __IO uint32_t SLVQUAL0; - uint32_t Reserved2[9]; - __I uint32_t MONRXDAT; /* 0x80 */ -} LPC_I2C_TypeDef; - -/*@}*/ /* end of group LPC8xx_I2C */ - -/** - * @brief State Configurable Timer (SCT) (SCT) - */ - -/** - * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) - */ - -#define CONFIG_SCT_nEV (6) /* Number of events */ -#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */ -#define CONFIG_SCT_nOU (4) /* Number of outputs */ - -typedef struct -{ - __IO uint32_t CONFIG; /* 0x000 Configuration Register */ - union { - __IO uint32_t CTRL_U; /* 0x004 Control Register */ - struct { - __IO uint16_t CTRL_L; /* 0x004 low control register */ - __IO uint16_t CTRL_H; /* 0x006 high control register */ - }; - }; - __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ - __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ - __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ - __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ - __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ - __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ - __IO uint16_t START_L; /* 0x014 start register for counter L */ - __IO uint16_t START_H; /* 0x016 start register for counter H */ - uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ - union { - __IO uint32_t COUNT_U; /* 0x040 counter register */ - struct { - __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ - __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ - }; - }; - __IO uint16_t STATE_L; /* 0x044 state register for counter L */ - __IO uint16_t STATE_H; /* 0x046 state register for counter H */ - __I uint32_t INPUT; /* 0x048 input register */ - __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ - __IO uint32_t OUTPUT; /* 0x050 output register */ - __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ - __IO uint32_t RES; /* 0x058 conflict resolution register */ - uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */ - __IO uint32_t EVEN; /* 0x0F0 event enable register */ - __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ - __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ - __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ - - union { - __IO union { /* 0x100-... Match / Capture value */ - uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCH[i].L Access to L value */ - uint16_t H; /* SCTMATCH[i].H Access to H value */ - }; - } MATCH[CONFIG_SCT_nRG]; - __I union { - uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAP[i].L Access to H value */ - uint16_t H; /* SCTCAP[i].H Access to H value */ - }; - } CAP[CONFIG_SCT_nRG]; - }; - - - uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ - - union { - __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ - __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ - }; - uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ - union { - __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ - __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ - }; - - uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ - - - union { - __IO union { /* 0x200-... Match Reload / Capture Control value */ - uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCHREL[i].L Access to L value */ - uint16_t H; /* SCTMATCHREL[i].H Access to H value */ - }; - } MATCHREL[CONFIG_SCT_nRG]; - __IO union { - uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ - uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ - }; - } CAPCTRL[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ - - union { - __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ - __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ - }; - uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ - union { - __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ - __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ - }; - uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ - - __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ - uint32_t STATE; /* Event State Register */ - uint32_t CTRL; /* Event Control Register */ - } EVENT[CONFIG_SCT_nEV]; - - uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ - - __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ - uint32_t SET; /* Output n Set Register */ - uint32_t CLR; /* Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - - uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ - - __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ - -} LPC_SCT_TypeDef; -/*@}*/ /* end of group LPC8xx_SCT */ - - -/*------------- Watchdog Timer (WWDT) -----------------------------------------*/ -/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer - @{ -*/ -typedef struct -{ - __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ - __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ - __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ - uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */ - __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ - __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ -} LPC_WWDT_TypeDef; -/*@}*/ /* end of group LPC8xx_WDT */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_ROM_BASE (0x1FFF0000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000) - -#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000) -#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000) -#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000) -#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000) -#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000) -#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000) - -/* AHB peripherals */ -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000) - -#define LPC_GPIO_PORT_BASE (0xA0000000) -#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) -#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE ) - - -#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE ) -#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE ) - -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE ) -#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE ) -#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE ) -#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE ) -#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE ) - -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE ) - -#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE ) -#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE ) - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC8xx_H__ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.c rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/LPC812.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/LPC812.sct rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.c rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/LPC8xx.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/LPC8xx.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/LPC8xx.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/TOOLCHAIN_ARM_MICRO/sys.cpp similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/sys.cpp rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/TOOLCHAIN_ARM_MICRO/sys.cpp diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/system_LPC8xx.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.h rename to libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/system_LPC8xx.h diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp deleted file mode 100644 index 2f1024ace8..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - stackheap - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * Setup a fixed single stack/heap memory model, - * between the top of the RW/ZI region and the stackpointer - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -extern char Image$$RW_IRAM1$$ZI$$Limit[]; - -extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { - uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; - uint32_t sp_limit = __current_sp(); - - zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned - - struct __initial_stackheap r; - r.heap_base = zi_limit; - r.heap_limit = sp_limit; - return r; -} - -#ifdef __cplusplus -} -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h deleted file mode 100644 index 12302cc3ad..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC8xx specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC8xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c deleted file mode 100644 index 6b8912505b..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic for LPC11U24 - * Copyright (c) 2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ -#include "cmsis_nvic.h" - -#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h deleted file mode 100644 index 6acdca9efd..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h deleted file mode 100644 index f559e944c6..0000000000 --- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.h - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC8xx_H -#define __SYSTEM_LPC8xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC8xx_H */ diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PeripheralNames.h deleted file mode 100644 index 988c1cb898..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PeripheralNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PortNames.h deleted file mode 100644 index bbd5b31103..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PortNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/PinNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/PeripheralNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/PeripheralNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/PortNames.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PortNames.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/PortNames.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/device.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/device.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/gpio_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/gpio_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/gpio_irq_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/gpio_irq_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/gpio_object.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/gpio_object.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/i2c_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/i2c_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/objects.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/objects.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/objects.h rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/objects.h diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/pinmap.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/pinmap.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/pinmap.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/pinmap.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/serial_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/serial_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/serial_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/spi_api.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/spi_api.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/spi_api.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/us_ticker.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC81X_COMMON/us_ticker.c diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h deleted file mode 100644 index ddb923bb83..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 0 -#define DEVICE_PORTOUT 0 -#define DEVICE_PORTINOUT 0 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 0 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 0 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c deleted file mode 100644 index 62754bc3b5..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c +++ /dev/null @@ -1,69 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" - -static int gpio_enabled = 0; -static void gpio_enable(void) { - gpio_enabled = 1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */ - LPC_SYSCON->PRESETCTRL &= ~(0x1<<10); - LPC_SYSCON->PRESETCTRL |= (0x1<<10); -} - -uint32_t gpio_set(PinName pin) { - int f = 0; - - if (!gpio_enabled) - gpio_enable(); - - pin_function(pin, f); - - return (1 << ((int)pin & 0x1F)); -} - -void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) { - if(pin == NC) return; - - obj->pin = pin; - obj->mask = gpio_set(pin); - - obj->reg_set = &LPC_GPIO_PORT->SET0; - obj->reg_clr = &LPC_GPIO_PORT->CLR0; - obj->reg_in = &LPC_GPIO_PORT->PIN0; - obj->reg_dir = &LPC_GPIO_PORT->DIR0; - - gpio_dir(obj, direction); - switch (direction) { - case PIN_OUTPUT: pin_mode(pin, PullNone); break; - case PIN_INPUT : pin_mode(pin, PullDown); break; - } -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - switch (direction) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c deleted file mode 100644 index c90c31a3da..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c +++ /dev/null @@ -1,127 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "error.h" - -#define CHANNEL_NUM 8 -#define LPC_GPIO_X LPC_PIN_INT -#define PININT_IRQ PININT0_IRQn - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -static inline void handle_interrupt_in(uint32_t channel) { - uint32_t ch_bit = (1 << channel); - // Return immediately if: - // * The interrupt was already served - // * There is no user handler - // * It is a level interrupt, not an edge interrupt - if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || - (channel_ids[channel] == 0 ) || - (LPC_GPIO_X->ISEL & ch_bit ) ) return; - - if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); - LPC_GPIO_X->RISE = ch_bit; - } - if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); - } - LPC_GPIO_X->IST = ch_bit; -} - -void gpio_irq0(void) {handle_interrupt_in(0);} -void gpio_irq1(void) {handle_interrupt_in(1);} -void gpio_irq2(void) {handle_interrupt_in(2);} -void gpio_irq3(void) {handle_interrupt_in(3);} -void gpio_irq4(void) {handle_interrupt_in(4);} -void gpio_irq5(void) {handle_interrupt_in(5);} -void gpio_irq6(void) {handle_interrupt_in(6);} -void gpio_irq7(void) {handle_interrupt_in(7);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) return -1; - - irq_handler = handler; - - int found_free_channel = 0; - int i = 0; - for (i=0; ich = i; - found_free_channel = 1; - break; - } - } - if (!found_free_channel) return -1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - LPC_SYSCON->PINTSEL[obj->ch] = pin; - - // Interrupt Wake-Up Enable - LPC_SYSCON->STARTERP0 |= 1 << obj->ch; - - void (*channels_irq)(void) = NULL; - switch (obj->ch) { - case 0: channels_irq = &gpio_irq0; break; - case 1: channels_irq = &gpio_irq1; break; - case 2: channels_irq = &gpio_irq2; break; - case 3: channels_irq = &gpio_irq3; break; - case 4: channels_irq = &gpio_irq4; break; - case 5: channels_irq = &gpio_irq5; break; - case 6: channels_irq = &gpio_irq6; break; - case 7: channels_irq = &gpio_irq7; break; - } - NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; - LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - unsigned int ch_bit = (1 << obj->ch); - - // Clear interrupt - if (!(LPC_GPIO_X->ISEL & ch_bit)) - LPC_GPIO_X->IST = ch_bit; - - // Edge trigger - LPC_GPIO_X->ISEL &= ~ch_bit; - if (event == IRQ_RISE) { - if (enable) { - LPC_GPIO_X->IENR |= ch_bit; - } else { - LPC_GPIO_X->IENR &= ~ch_bit; - } - } else { - if (enable) { - LPC_GPIO_X->IENF |= ch_bit; - } else { - LPC_GPIO_X->IENF &= ~ch_bit; - } - } -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h deleted file mode 100644 index 8f8d5eb595..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c deleted file mode 100644 index f6424724c8..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c +++ /dev/null @@ -1,242 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -static const SWM_Map SWM_I2C_SDA[] = { - {7, 24}, -}; - -static const SWM_Map SWM_I2C_SCL[] = { - {8, 0}, -}; - -static uint8_t repeated_start = 0; - -#define I2C_DAT(x) (x->i2c->MSTDAT) -#define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07)) - -static inline int i2c_status(i2c_t *obj) { - return I2C_STAT(obj); -} - -// Wait until the Serial Interrupt (SI) is set -static int i2c_wait_SI(i2c_t *obj) { - int timeout = 0; - while (!(obj->i2c->STAT & (1 << 0))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} - -static inline void i2c_interface_enable(i2c_t *obj) { - obj->i2c->CFG |= (1 << 0); -} - -static inline void i2c_power_enable(i2c_t *obj) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5); - LPC_SYSCON->PRESETCTRL &= ~(0x1<<6); - LPC_SYSCON->PRESETCTRL |= (0x1<<6); -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - obj->i2c = (LPC_I2C_TypeDef *)LPC_I2C; - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_I2C_SDA[0]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (sda << swm->offset); - - swm = &SWM_I2C_SCL[0]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (scl << swm->offset); - - // enable power - i2c_power_enable(obj); - // set default frequency at 100k - i2c_frequency(obj, 100000); - i2c_interface_enable(obj); -} - -inline int i2c_start(i2c_t *obj) { - int status = 0; - if (repeated_start) { - obj->i2c->MSTCTL = (1 << 1) | (1 << 0); - repeated_start = 0; - } else { - obj->i2c->MSTCTL = (1 << 1); - } - return status; -} - -inline int i2c_stop(i2c_t *obj) { - int timeout = 0; - - obj->i2c->MSTCTL = (1 << 2) | (1 << 0); - while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) { - timeout ++; - if (timeout > 100000) return 1; - } - - return 0; -} - - -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { - // write the data - I2C_DAT(obj) = value; - - if (!addr) - obj->i2c->MSTCTL = (1 << 0); - - // wait and return status - i2c_wait_SI(obj); - return i2c_status(obj); -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - // wait for it to arrive - i2c_wait_SI(obj); - if (!last) - obj->i2c->MSTCTL = (1 << 0); - - // return the data - return (I2C_DAT(obj) & 0xFF); -} - -void i2c_frequency(i2c_t *obj, int hz) { - // No peripheral clock divider on the M0 - uint32_t PCLK = SystemCoreClock; - - uint32_t clkdiv = PCLK / (hz * 4) - 1; - - obj->i2c->DIV = clkdiv; - obj->i2c->MSTTIME = 0; -} - -// The I2C does a read or a write as a whole operation -// There are two types of error conditions it can encounter -// 1) it can not obtain the bus -// 2) it gets error responses at part of the transmission -// -// We tackle them as follows: -// 1) we retry until we get the bus. we could have a "timeout" if we can not get it -// which basically turns it in to a 2) -// 2) on error, we use the standard error mechanisms to report/debug -// -// Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically -// check for that - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count, status; - - i2c_start(obj); - - status = i2c_do_write(obj, (address | 0x01), 1); - if (status != 0x01) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - int value = i2c_do_read(obj, 0); - status = i2c_status(obj); - if (status != 0x00) { - i2c_stop(obj); - return count; - } - data[count] = (char) value; - } - - // read in last byte - int value = i2c_do_read(obj, 1); - status = i2c_status(obj); - if (status != 0x01) { - i2c_stop(obj); - return length - 1; - } - - data[count] = (char) value; - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } else { - repeated_start = 1; - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i, status; - - i2c_start(obj); - - status = i2c_do_write(obj, (address & 0xFE), 1); - if (status != 0x02) { - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - for (i=0; iPIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 , - &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 , - &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 , - &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11, - &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14, - &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17, -}; - -void pin_function(PinName pin, int function) { - -} - -void pin_mode(PinName pin, PinMode mode) { - if (pin == (uint32_t)NC) { return; } - - if ((pin == 10) || (pin == 11)) { - // True open-drain pins can be configured for different I2C-bus speeds - return; - } - - __IO uint32_t *reg = IOCON_REGISTERS[pin]; - - if (mode == OpenDrain) { - *reg |= (1 << 10); - } else { - uint32_t tmp = *reg; - tmp &= ~(0x3 << 3); - tmp |= (mode & 0x3) << 3; - *reg = tmp; - } -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c deleted file mode 100644 index 9a98f82e87..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c +++ /dev/null @@ -1,280 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 3 - -static const SWM_Map SWM_UART_TX[] = { - {0, 0}, - {1, 8}, - {2, 16}, -}; - -static const SWM_Map SWM_UART_RX[] = { - {0, 8}, - {1, 16}, - {2, 24}, -}; - -// bit flags for used UARTs -static unsigned char uart_used = 0; -static int get_available_uart(void) { - int i; - for (i=0; i<3; i++) { - if ((uart_used & (1 << i)) == 0) - return i; - } - return -1; -} - -#define UART_EN (0x01<<0) - -#define CTS_DELTA (0x01<<5) -#define RXBRK (0x01<<10) -#define DELTA_RXBRK (0x01<<11) - -#define RXRDY (0x01<<0) -#define TXRDY (0x01<<2) - -#define TXBRKEN (0x01<<1) - -static uint32_t UARTSysClk; - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - int is_stdio_uart = 0; - - int uart_n = get_available_uart(); - if (uart_n == -1) { - error("No available UART"); - } - obj->index = uart_n; - obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n)); - uart_used |= (1 << uart_n); - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_UART_TX[uart_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset); - - swm = &SWM_UART_RX[uart_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset); - - /* uart clock divided by 1 */ - LPC_SYSCON->UARTCLKDIV = 1; - - /* disable uart interrupts */ - NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); - - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n)); - - /* Peripheral reset control to UART, a "1" bring it out of reset. */ - LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n)); - LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n)); - - UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV; - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - /* Clear all status bits. */ - obj->uart->STAT = CTS_DELTA | DELTA_RXBRK; - - /* enable uart interrupts */ - NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); - - /* Enable UART interrupt */ - // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK; - - /* Enable UART */ - obj->uart->CFG |= UART_EN; - - is_stdio_uart = ((tx == USBTX) && (rx == USBRX)); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - uart_used &= ~(1 << obj->index); - serial_irq_ids[obj->index] = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - /* Integer divider: - BRG = UARTSysClk/(Baudrate * 16) - 1 - - Frational divider: - FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1) - - where - FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1) - - (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB - register is 0xFF. - (2) In ADD register value, depending on the value of UartSysClk, - baudrate, BRG register value, and SUB register value, be careful - about the order of multiplier and divider and make sure any - multiplier doesn't exceed 32-bit boundary and any divider doesn't get - down below one(integer 0). - (3) ADD should be always less than SUB. - */ - obj->uart->BRG = UARTSysClk / 16 / baudrate - 1; - - LPC_SYSCON->UARTFRGDIV = 0xFF; - LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) / - (baudrate * (obj->uart->BRG + 1)) - ) - (LPC_SYSCON->UARTFRGDIV + 1); - -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - // 0: 1 stop bits, 1: 2 stop bits - if (stop_bits != 1 && stop_bits != 2) { - error("Invalid stop bits specified"); - } - stop_bits -= 1; - - // 0: 7 data bits ... 2: 9 data bits - if (data_bits < 7 || data_bits > 9) { - error("Invalid number of bits (%d) in serial format, should be 7..9", data_bits); - } - data_bits -= 7; - - int paritysel; - switch (parity) { - case ParityNone: paritysel = 0; break; - case ParityEven: paritysel = 2; break; - case ParityOdd : paritysel = 3; break; - default: - error("Invalid serial parity setting"); - return; - } - - obj->uart->CFG = (data_bits << 2) - | (paritysel << 4) - | (stop_bits << 6); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t iir, uint32_t index) { - // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling - SerialIrq irq_type; - switch (iir) { - case 1: irq_type = TxIrq; break; - case 2: irq_type = RxIrq; break; - default: return; - } - - if (serial_irq_ids[index] != 0) - irq_handler(serial_irq_ids[index], irq_type); -} - -void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);} -void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);} -void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; - case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; - case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; - } - - if (enable) { - obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2)); - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2)); - all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0; - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - return obj->uart->RXDATA; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - obj->uart->TXDATA = c; -} - -int serial_readable(serial_t *obj) { - return obj->uart->STAT & RXRDY; -} - -int serial_writable(serial_t *obj) { - return obj->uart->STAT & TXRDY; -} - -void serial_clear(serial_t *obj) { - // [TODO] -} - -void serial_pinout_tx(PinName tx) { - -} - -void serial_break_set(serial_t *obj) { - obj->uart->CTRL |= TXBRKEN; -} - -void serial_break_clear(serial_t *obj) { - obj->uart->CTRL &= ~TXBRKEN; -} - diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c deleted file mode 100644 index 0a5d9797fd..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c +++ /dev/null @@ -1,210 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "error.h" - -static const SWM_Map SWM_SPI_SSEL[] = { - {4, 16}, - {5, 16}, -}; - -static const SWM_Map SWM_SPI_SCLK[] = { - {3, 24}, - {4, 24}, -}; - -static const SWM_Map SWM_SPI_MOSI[] = { - {4, 0}, - {5, 0}, -}; - -static const SWM_Map SWM_SPI_MISO[] = { - {4, 8}, - {5, 16}, -}; - -// bit flags for used SPIs -static unsigned char spi_used = 0; -static int get_available_spi(void) { - int i; - for (i=0; i<2; i++) { - if ((spi_used & (1 << i)) == 0) - return i; - } - return -1; -} - -static inline int ssp_disable(spi_t *obj); -static inline int ssp_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - int spi_n = get_available_spi(); - if (spi_n == -1) { - error("No available SPI"); - } - obj->spi_n = spi_n; - spi_used |= (1 << spi_n); - - obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE); - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_SPI_SCLK[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset); - - swm = &SWM_SPI_MOSI[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset); - - swm = &SWM_SPI_MISO[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset); - - swm = &SWM_SPI_SSEL[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset); - - // clear interrupts - obj->spi->INTENCLR = 0x3f; - - // enable power and clocking - switch (obj->spi_n) { - case 0: - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11); - LPC_SYSCON->PRESETCTRL &= ~(0x1<<0); - LPC_SYSCON->PRESETCTRL |= (0x1<<0); - break; - case 1: - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - LPC_SYSCON->PRESETCTRL &= ~(0x1<<1); - LPC_SYSCON->PRESETCTRL |= (0x1<<1); - break; - } - - // set default format and frequency - if (ssel == NC) { - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - } else { - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } - spi_frequency(obj, 1000000); - - // enable the ssp channel - ssp_enable(obj); -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - ssp_disable(obj); - - if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) { - error("SPI format error"); - } - - - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - - // set it up - int DSS = bits - 1; // DSS (data select size) - int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity - int SPH = (phase) ? 1 : 0; // SPH - clock out phase - - uint32_t tmp = obj->spi->CFG; - tmp &= ~((1 << 2) | (1 << 4) | (1 << 5)); - tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2); - obj->spi->CFG = tmp; - - // select frame length - tmp = obj->spi->TXDATCTL; - tmp &= ~(0xf << 24); - tmp |= (DSS << 24); - obj->spi->TXDATCTL = tmp; - - ssp_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - ssp_disable(obj); - - uint32_t PCLK = SystemCoreClock; - - obj->spi->DIV = PCLK/hz - 1; - obj->spi->DLY = 0; - ssp_enable(obj); -} - -static inline int ssp_disable(spi_t *obj) { - return obj->spi->CFG &= ~(1 << 0); -} - -static inline int ssp_enable(spi_t *obj) { - return obj->spi->CFG |= (1 << 0); -} - -static inline int ssp_readable(spi_t *obj) { - return obj->spi->STAT & (1 << 0); -} - -static inline int ssp_writeable(spi_t *obj) { - return obj->spi->STAT & (1 << 1); -} - -static inline void ssp_write(spi_t *obj, int value) { - while (!ssp_writeable(obj)); - // end of transfer - obj->spi->TXDATCTL |= (1 << 20); - obj->spi->TXDAT = value; -} - -static inline int ssp_read(spi_t *obj) { - while (!ssp_readable(obj)); - return obj->spi->RXDAT; -} - -static inline int ssp_busy(spi_t *obj) { - // TODO - return 0; -} - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -}; - -int spi_slave_read(spi_t *obj) { - return obj->spi->RXDAT; -} - -void spi_slave_write(spi_t *obj, int value) { - while (ssp_writeable(obj) == 0) ; - obj->spi->TXDAT = value; -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c deleted file mode 100644 index cf03fc931a..0000000000 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c +++ /dev/null @@ -1,93 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -#define US_TICKER_TIMER_IRQn SCT_IRQn - -int us_ticker_inited = 0; - -void us_ticker_init(void) { - if (us_ticker_inited) return; - us_ticker_inited = 1; - - // Enable the SCT clock - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); - - // Clear peripheral reset the SCT: - LPC_SYSCON->PRESETCTRL |= (1 << 8); - - // Unified counter (32 bits) - LPC_SCT->CONFIG |= 1; - - // halt and clear the counter - LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3); - - // System Clock (12)MHz -> us_ticker (1)MHz - LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5); - - // unhalt the counter: - // - clearing bit 2 of the CTRL register - LPC_SCT->CTRL_L &= ~(1 << 2); - - NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -uint32_t us_ticker_read() { - if (!us_ticker_inited) - us_ticker_init(); - - return LPC_SCT->COUNT_U; -} - -void us_ticker_set_interrupt(unsigned int timestamp) { - // halt the counter: - // - setting bit 2 of the CTRL register - LPC_SCT->CTRL_L |= (1 << 2); - - // set timestamp in compare register - LPC_SCT->MATCH[0].U = timestamp; - - // unhalt the counter: - // - clearing bit 2 of the CTRL register - LPC_SCT->CTRL_L &= ~(1 << 2); - - // if events are not enabled, enable them - if (!(LPC_SCT->EVEN & 0x01)) { - - // comb mode = match only - LPC_SCT->EVENT[0].CTRL = (1 << 12); - - // ref manual: - // In simple applications that do not - // use states, write 0x01 to this - // register to enable an event - LPC_SCT->EVENT[0].STATE |= 0x1; - - // enable events - LPC_SCT->EVEN |= 0x1; - } -} - -void us_ticker_disable_interrupt(void) { - LPC_SCT->EVEN &= ~1; -} - -void us_ticker_clear_interrupt(void) { - LPC_SCT->EVFLAG = 1; -} diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 20cf2d598e..888f40b9c0 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -127,7 +127,7 @@ class LPC812(Target): self.core = "Cortex-M0+" - self.extra_labels = ['NXP', 'LPC81X'] + self.extra_labels = ['NXP', 'LPC81X', 'LPC81X_COMMON'] self.supported_toolchains = ["uARM"] @@ -140,7 +140,7 @@ class LPC810(Target): self.core = "Cortex-M0+" - self.extra_labels = ['NXP', 'LPC810'] + self.extra_labels = ['NXP', 'LPC81X', 'LPC81X_COMMON'] self.supported_toolchains = ["uARM"]