mirror of https://github.com/ARMmbed/mbed-os.git
Change LPC54608 to LPC546XX to include support for LPC54608/18/28
Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>pull/5268/head
Mahadevan Mahesh
adbridge
parent
fc41c055f9
commit
95b6acd095
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@ -45,11 +45,11 @@
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!ClocksProfile
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product: Clocks v1.0
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processor: LPC54608J512
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package_id: LPC54608J512ET180
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processor: LPC54618J512
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package_id: LPC54618J512ET180
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mcu_data: ksdk2_0
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processor_version: 0.0.0
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board: LPCXpresso54608
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board: LPCXpresso54618
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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#include "fsl_power.h"
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@ -1,7 +1,7 @@
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/*
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** ###################################################################
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** Processors: LPC54608J512BD208
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** LPC54608J512ET180
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** Processors: LPC54618J512BD208
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** LPC54618J512ET180
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**
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** Compilers: Keil ARM C/C++ Compiler
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** GNU C Compiler
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@ -13,7 +13,7 @@
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** Build: b170214
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for LPC54608
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** CMSIS Peripheral Access Layer for LPC54618
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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@ -56,16 +56,16 @@
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*/
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/*!
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* @file LPC54608.h
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* @file LPC54618.h
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* @version 1.1
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* @date 2016-11-25
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* @brief CMSIS Peripheral Access Layer for LPC54608
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* @brief CMSIS Peripheral Access Layer for LPC54618
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*
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* CMSIS Peripheral Access Layer for LPC54608
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* CMSIS Peripheral Access Layer for LPC54618
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*/
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#ifndef _LPC54608_H_
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#define _LPC54608_H_ /**< Symbol preventing repeated inclusion */
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#ifndef _LPC54618_H_
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#define _LPC54618_H_ /**< Symbol preventing repeated inclusion */
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/** Memory map major version (memory maps with equal major version number are
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* compatible) */
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@ -181,7 +181,7 @@ typedef enum IRQn {
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#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
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#include "core_cm4.h" /* Core Peripheral Access Layer */
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#include "system_LPC54608.h" /* Device specific configuration file */
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#include "system_LPC54618.h" /* Device specific configuration file */
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/*!
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* @}
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@ -713,7 +713,8 @@ typedef struct {
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/** CAN - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[16];
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uint8_t RESERVED_0[12];
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__IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
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__IO uint32_t TEST; /**< Test Register, offset: 0x10 */
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uint8_t RESERVED_1[4];
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__IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
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@ -779,6 +780,23 @@ typedef struct {
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* @{
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*/
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/*! @name DBTP - Data Bit Timing Prescaler Register */
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#define CAN_DBTP_DSJW_MASK (0xFU)
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#define CAN_DBTP_DSJW_SHIFT (0U)
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#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
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#define CAN_DBTP_DTSEG2_MASK (0xF0U)
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#define CAN_DBTP_DTSEG2_SHIFT (4U)
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#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
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#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
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#define CAN_DBTP_DTSEG1_SHIFT (8U)
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#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
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#define CAN_DBTP_DBRP_MASK (0x1F0000U)
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#define CAN_DBTP_DBRP_SHIFT (16U)
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#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
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#define CAN_DBTP_TDC_MASK (0x800000U)
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#define CAN_DBTP_TDC_SHIFT (23U)
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#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
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/*! @name TEST - Test Register */
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#define CAN_TEST_LBCK_MASK (0x10U)
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#define CAN_TEST_LBCK_SHIFT (4U)
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@ -815,6 +833,12 @@ typedef struct {
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#define CAN_CCCR_TEST_MASK (0x80U)
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#define CAN_CCCR_TEST_SHIFT (7U)
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#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
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#define CAN_CCCR_FDOE_MASK (0x100U)
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#define CAN_CCCR_FDOE_SHIFT (8U)
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#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
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#define CAN_CCCR_BRSE_MASK (0x200U)
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#define CAN_CCCR_BRSE_SHIFT (9U)
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#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
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#define CAN_CCCR_PXHD_MASK (0x1000U)
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#define CAN_CCCR_PXHD_SHIFT (12U)
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#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
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@ -824,6 +848,9 @@ typedef struct {
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#define CAN_CCCR_TXP_MASK (0x4000U)
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#define CAN_CCCR_TXP_SHIFT (14U)
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#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
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#define CAN_CCCR_NISO_MASK (0x8000U)
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#define CAN_CCCR_NISO_SHIFT (15U)
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#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
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/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
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#define CAN_NBTP_NTSEG2_MASK (0x7FU)
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@ -898,6 +925,18 @@ typedef struct {
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#define CAN_PSR_BO_MASK (0x80U)
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#define CAN_PSR_BO_SHIFT (7U)
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#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
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#define CAN_PSR_DLEC_MASK (0x700U)
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#define CAN_PSR_DLEC_SHIFT (8U)
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#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
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#define CAN_PSR_RESI_MASK (0x800U)
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#define CAN_PSR_RESI_SHIFT (11U)
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#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
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#define CAN_PSR_RBRS_MASK (0x1000U)
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#define CAN_PSR_RBRS_SHIFT (12U)
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#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
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#define CAN_PSR_RFDF_MASK (0x2000U)
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#define CAN_PSR_RFDF_SHIFT (13U)
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#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
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#define CAN_PSR_PXE_MASK (0x4000U)
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#define CAN_PSR_PXE_SHIFT (14U)
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#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
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@ -12367,5 +12406,5 @@ typedef struct {
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*/ /* end of group SDK_Compatibility_Symbols */
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#endif /* _LPC54608_H_ */
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#endif /* _LPC54618_H_ */
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@ -46,8 +46,8 @@
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** ###################################################################
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*/
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#ifndef _LPC54608_FEATURES_H_
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#define _LPC54608_FEATURES_H_
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#ifndef _LPC54618_FEATURES_H_
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#define _LPC54618_FEATURES_H_
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/* SOC module features */
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@ -133,7 +133,7 @@
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/* CAN module features */
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/* @brief Support CANFD or not */
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#define FSL_FEATURE_CAN_SUPPORT_CANFD (0)
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#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
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/* DMA module features */
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@ -227,5 +227,5 @@
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/* @brief Base address of the USB dedicated RAM */
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#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
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#endif /* _LPC54608_FEATURES_H_ */
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#endif /* _LPC54618_FEATURES_H_ */
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@ -1,8 +1,8 @@
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#! armcc -E
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/*
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** ###################################################################
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** Processors: LPC54608J512BD208
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** LPC54608J512ET180
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** Processors: LPC54618J512BD208
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** LPC54618J512ET180
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**
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** Compiler: Keil ARM C/C++ Compiler
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** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
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@ -1,7 +1,7 @@
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;/*****************************************************************************
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; * @file: startup_LPC54608.s
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; * @file: startup_LPC54618.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
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; * LPC54608
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; * LPC54618
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; * @version: 1.1
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; * @date: 2016-11-25
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; *
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@ -1,61 +1,28 @@
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/*
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** ###################################################################
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** Processors: LPC54608J512
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** Processors: LPC54618J512
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**
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** Compiler: GNU C Compiler
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** Reference manual: LPC54608 Series Reference Manual, Rev. 0 , 06/2017
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** Reference manual: LPC54618 Series Reference Manual, Rev. 0 , 06/2017
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** Version: rev. 1.0, 2017-6-06
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** Build: b161214
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**
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** Abstract:
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** Linker file for the GNU C Compiler
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**
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** Copyright (c) 2016 Freescale Semiconductor, Inc.
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** Copyright (c) 2016 - 2017 , NXP
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** All rights reserved.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** 1. Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** 2. Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Copyright (c) 2016 NXP Semiconductors, Inc.
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of NXP Semiconductors, Inc. nor the names of its
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** 3. Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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@ -97,8 +64,6 @@ MEMORY
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m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000
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m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000
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m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00002000
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}
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/* Define output sections */
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@ -1,54 +1,25 @@
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/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_LPC54608.S */
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/* @file: startup_LPC54618.S */
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/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
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/* LPC54608 */
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/* LPC54618 */
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/* @version: 1.0 */
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/* @date: 2017-6-6 */
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/* @build: b161214 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
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/* Copyright (c) 2016 - 2017 , NXP */
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/* */
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/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
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/* Copyright 2016-2017 NXP */
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/* Redistribution and use in source and binary forms, with or without modification, */
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/* are permitted provided that the following conditions are met: */
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/* */
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/* o Redistributions of source code must retain the above copyright notice, this list */
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/* 1. Redistributions of source code must retain the above copyright notice, this list */
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/* of conditions and the following disclaimer. */
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/* */
|
||||
/* o Redistributions in binary form must reproduce the above copyright notice, this */
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/* 2. Redistributions in binary form must reproduce the above copyright notice, this */
|
||||
/* list of conditions and the following disclaimer in the documentation and/or */
|
||||
/* other materials provided with the distribution. */
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/* */
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/* o Neither the name of copyright holder nor the names of its */
|
||||
/* contributors may be used to endorse or promote products derived from this */
|
||||
/* software without specific prior written permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
|
||||
/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
|
||||
/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
|
||||
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
|
||||
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
|
||||
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
|
||||
/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
|
||||
/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
|
||||
/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/* Copyright (c) 2016 , NXP Semiconductors, Inc. */
|
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/* All rights reserved. */
|
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/* */
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||||
/* Redistribution and use in source and binary forms, with or without modification, */
|
||||
/* are permitted provided that the following conditions are met: */
|
||||
/* */
|
||||
/* o Redistributions of source code must retain the above copyright notice, this list */
|
||||
/* of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* o Redistributions in binary form must reproduce the above copyright notice, this */
|
||||
/* list of conditions and the following disclaimer in the documentation and/or */
|
||||
/* other materials provided with the distribution. */
|
||||
/* */
|
||||
/* o Neither the name of NXP Semiconductors, Inc. nor the names of its */
|
||||
/* 3. Neither the name of the copyright holder nor the names of its */
|
||||
/* contributors may be used to endorse or promote products derived from this */
|
||||
/* software without specific prior written permission. */
|
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/* */
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@ -1,7 +1,7 @@
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/*
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** ###################################################################
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** Processors: LPC54608J512BD208
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** LPC54608J512ET180
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** Processors: LPC54618J512BD208
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** LPC54618J512ET180
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**
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** Compiler: IAR ANSI C/C++ Compiler for ARM
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** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
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@ -1,7 +1,7 @@
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;/*****************************************************************************
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; * @file: startup_LPC54608.s
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; * @file: startup_LPC54618.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File
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; * LPC54608
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; * LPC54618
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; * @version: 1.1
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; * @date: 2016-11-25
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; *----------------------------------------------------------------------------
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@ -36,14 +36,14 @@
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*
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* The CPU macro should be declared in the project or makefile.
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*/
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#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180))
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#if (defined(CPU_LPC54618J512BD208) || defined(CPU_LPC54618J512ET180))
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#define LPC54608_SERIES
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#define LPC54618_SERIES
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/* CMSIS-style register definitions */
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#include "LPC54608.h"
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#include "LPC54618.h"
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/* CPU specific feature definitions */
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#include "LPC54608_features.h"
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#include "LPC54618_features.h"
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#else
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#error "No valid CPU defined!"
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@ -1,7 +1,7 @@
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/*
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** ###################################################################
|
||||
** Processors: LPC54608J512BD208
|
||||
** LPC54608J512ET180
|
||||
** Processors: LPC54618J512BD208
|
||||
** LPC54618J512ET180
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** GNU C Compiler
|
||||
|
|
@ -58,10 +58,10 @@
|
|||
*/
|
||||
|
||||
/*!
|
||||
* @file LPC54608
|
||||
* @file LPC54618
|
||||
* @version 1.1
|
||||
* @date 2016-11-25
|
||||
* @brief Device specific configuration file for LPC54608 (implementation file)
|
||||
* @brief Device specific configuration file for LPC54618 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC54608J512BD208
|
||||
** LPC54608J512ET180
|
||||
** Processors: LPC54618J512BD208
|
||||
** LPC54618J512ET180
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** GNU C Compiler
|
||||
|
|
@ -58,18 +58,18 @@
|
|||
*/
|
||||
|
||||
/*!
|
||||
* @file LPC54608
|
||||
* @file LPC54618
|
||||
* @version 1.1
|
||||
* @date 2016-11-25
|
||||
* @brief Device specific configuration file for LPC54608 (header file)
|
||||
* @brief Device specific configuration file for LPC54618 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_LPC54608_H_
|
||||
#define _SYSTEM_LPC54608_H_ /**< Symbol preventing repeated inclusion */
|
||||
#ifndef _SYSTEM_LPC54618_H_
|
||||
#define _SYSTEM_LPC54618_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -118,4 +118,4 @@ void SystemCoreClockUpdate (void);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_LPC54608_H_ */
|
||||
#endif /* _SYSTEM_LPC54618_H_ */
|
||||
|
|
@ -984,8 +984,13 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
|
|||
return m;
|
||||
}
|
||||
|
||||
/* Set PLL output based on desired output rate */
|
||||
static pll_error_t CLOCK_GetPllConfig(
|
||||
/*
|
||||
* Set PLL output based on desired output rate.
|
||||
* In this function, the it calculates the PLL setting for output frequency from input clock
|
||||
* frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
|
||||
* the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
|
||||
*/
|
||||
static pll_error_t CLOCK_GetPllConfigInternal(
|
||||
uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
|
||||
{
|
||||
uint32_t nDivOutHz, fccoHz, multFccoDiv;
|
||||
|
|
@ -1098,6 +1103,64 @@ static pll_error_t CLOCK_GetPllConfig(
|
|||
return kStatus_PLL_Success;
|
||||
}
|
||||
|
||||
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
|
||||
/* Alloct the static buffer for cache. */
|
||||
pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
|
||||
uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
|
||||
uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
|
||||
uint32_t gPllSetupCacheIdx = 0U;
|
||||
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
|
||||
|
||||
/*
|
||||
* Calculate the PLL setting values from input clock freq to output freq.
|
||||
*/
|
||||
static pll_error_t CLOCK_GetPllConfig(
|
||||
uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
|
||||
{
|
||||
pll_error_t retErr;
|
||||
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
|
||||
{
|
||||
if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) )
|
||||
{
|
||||
/* Hit the target in cache buffer. */
|
||||
pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl;
|
||||
pSetup->pllndec = gPllSetupCacheStruct[i].pllndec;
|
||||
pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec;
|
||||
pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec;
|
||||
retErr = kStatus_PLL_Success;
|
||||
}
|
||||
}
|
||||
|
||||
if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
|
||||
{
|
||||
return retErr;
|
||||
}
|
||||
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
|
||||
|
||||
/* No cache or did not hit the cache. */
|
||||
retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup);
|
||||
|
||||
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
|
||||
if (kStatus_PLL_Success == retErr)
|
||||
{
|
||||
/* Cache the most recent calulation result into buffer. */
|
||||
gFinHzCache[gPllSetupCacheIdx] = finHz;
|
||||
gFoutHzCache[gPllSetupCacheIdx] = foutHz;
|
||||
|
||||
gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl;
|
||||
gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec;
|
||||
gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec;
|
||||
gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec;
|
||||
/* Update the index for next available buffer. */
|
||||
gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
|
||||
}
|
||||
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
|
||||
|
||||
return retErr;
|
||||
}
|
||||
|
||||
/* Update SYSTEM PLL rate variable */
|
||||
static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
|
||||
|
|
@ -59,6 +59,18 @@
|
|||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
|
||||
#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
|
||||
*
|
||||
* Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
|
||||
* would cache the recent calulation and accelerate the execution to get the
|
||||
* right settings.
|
||||
*/
|
||||
#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
|
||||
#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
|
||||
#endif
|
||||
|
||||
/*! @brief Clock ip name array for ROM. */
|
||||
#define ADC_CLOCKS \
|
||||
{ \
|
||||
|
|
@ -656,7 +668,7 @@ typedef enum _clock_attach_id
|
|||
kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
|
||||
kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
|
||||
kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
|
||||
kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
|
||||
kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
|
||||
kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
|
||||
|
||||
kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
|
||||
|
|
@ -575,7 +575,7 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui
|
|||
i2s_dma_handle_t *i2sHandle = privateHandle->handle;
|
||||
I2S_Type *base = privateHandle->base;
|
||||
|
||||
if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle))
|
||||
if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -1,6 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright (c) 2016, NXP
|
||||
* Copyright (c) 2013-2016, NXP Semiconductors.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
|
|
@ -230,15 +230,6 @@ void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
|
|||
*/
|
||||
void POWER_SetVoltageForFreq(uint32_t freq);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
|
||||
*
|
||||
* @param freq - The desired frequency at which the part would like to operate,
|
||||
* note that the voltage and flash wait states should be set before changing frequency
|
||||
* @return none
|
||||
*/
|
||||
void POWER_SetVoltageForFreq(uint32_t freq);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to return the library version.
|
||||
*
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue