diff --git a/Jenkinsfile b/Jenkinsfile index 846827c2a0..c938dd0a24 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,31 +1,2 @@ - -// List of targets to compile -def targets = [ - //"LPC1768", - //"NUCLEO_F401RE", - //"NRF51822", - "K64F" - ] - -// Map toolchains to compiler labels on Jenkins -def toolchains = [ - ARM: "armcc", - //IAR: "iar_arm", - GCC_ARM: "arm-none-eabi-gcc" - ] - -// mbed.getCurrentBranch returns either local branch name or reference to pull request -def currentBranch = mbed.getCurrentBranch() - -// Create a map of predefined build steps -def parallelSteps = mbed.createParalleSteps("mbed-os", targets, toolchains) - -// Run build steps parallel, map as paramater -mbed.compile(parallelSteps) - -def testApps = [ - "mbed-os-cliapp" - ] - -// buildTestApps accepts array of test application names and a mbed-os branch or PR reference as parameters -mbed.buildTestApps(testApps, "${currentBranch}") +// This is internal file to run tests in internal Jenkins +mbed.run_job() diff --git a/TESTS/mbed_hal/common_tickers/main.cpp b/TESTS/mbed_hal/common_tickers/main.cpp index f91eb3e5c1..7ba9c1f3de 100644 --- a/TESTS/mbed_hal/common_tickers/main.cpp +++ b/TESTS/mbed_hal/common_tickers/main.cpp @@ -36,7 +36,7 @@ #define TICKER_100_TICKS 100 -#define MAX_FUNC_EXEC_TIME_US 20 +#define MAX_FUNC_EXEC_TIME_US 30 #define DELTA_FUNC_EXEC_TIME_US 5 #define NUM_OF_CALLS 1000 diff --git a/TESTS/netsocket/dns/asynchronous_dns_cache.cpp b/TESTS/netsocket/dns/asynchronous_dns_cache.cpp index 70283cbae9..3a25296a3c 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_cache.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_cache.cpp @@ -56,8 +56,9 @@ void ASYNCHRONOUS_DNS_CACHE() int delay_ms = (ticker_us - started_us) / 1000; static int delay_first = delay_ms / 2; + printf("Delays: first: %i, delay_ms: %i\n", delay_first, delay_ms); // Check that cached accesses are at least twice as fast as the first one - TEST_ASSERT_FALSE(i != 0 && delay_ms > delay_first); + TEST_ASSERT_TRUE(i == 0 || delay_ms <= delay_first); printf("DNS: query \"%s\" => \"%s\", time %i ms\n", dns_test_hosts[0], data.addr.get_ip_address(), delay_ms); diff --git a/TESTS/netsocket/dns/dns_tests.h b/TESTS/netsocket/dns/dns_tests.h index f393560011..7bfe53f71c 100644 --- a/TESTS/netsocket/dns/dns_tests.h +++ b/TESTS/netsocket/dns/dns_tests.h @@ -59,6 +59,7 @@ extern const char dns_test_hosts_second[MBED_CONF_APP_DNS_TEST_HOSTS_NUM][DNS_TE NetworkInterface *get_interface(); void hostbyname_cb(void *data, nsapi_error_t result, SocketAddress *address); void do_asynchronous_gethostbyname(const char hosts[][DNS_TEST_HOST_LEN], unsigned int op_count, int *exp_ok, int *exp_no_mem, int *exp_dns_failure, int *exp_timeout); +void do_gethostbyname(const char hosts[][DNS_TEST_HOST_LEN], unsigned int op_count, int *exp_ok, int *exp_no_mem, int *exp_dns_failure, int *exp_timeout); /* * Test cases @@ -73,5 +74,8 @@ void ASYNCHRONOUS_DNS_EXTERNAL_EVENT_QUEUE(); void ASYNCHRONOUS_DNS_INVALID_HOST(); void ASYNCHRONOUS_DNS_TIMEOUTS(); void ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT(); - +void SYNCHRONOUS_DNS(); +void SYNCHRONOUS_DNS_MULTIPLE(); +void SYNCHRONOUS_DNS_CACHE(); +void SYNCHRONOUS_DNS_INVALID(); #endif diff --git a/TESTS/netsocket/dns/main.cpp b/TESTS/netsocket/dns/main.cpp index 768790105a..15b956bb4c 100644 --- a/TESTS/netsocket/dns/main.cpp +++ b/TESTS/netsocket/dns/main.cpp @@ -107,6 +107,39 @@ void do_asynchronous_gethostbyname(const char hosts[][DNS_TEST_HOST_LEN], unsign delete[] data; } +void do_gethostbyname(const char hosts[][DNS_TEST_HOST_LEN], unsigned int op_count, int *exp_ok, int *exp_no_mem, int *exp_dns_failure, int *exp_timeout) +{ + // Verify that there is enough hosts in the host list + TEST_ASSERT(op_count <= MBED_CONF_APP_DNS_TEST_HOSTS_NUM) + + // Reset counters + (*exp_ok) = 0; + (*exp_no_mem) = 0; + (*exp_dns_failure) = 0; + (*exp_timeout) = 0; + + for (unsigned int i = 0; i < op_count; i++) { + SocketAddress address; + nsapi_error_t err = net->gethostbyname(hosts[i], &address); + + TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_NO_MEMORY || err == NSAPI_ERROR_DNS_FAILURE || err == NSAPI_ERROR_TIMEOUT); + if (err == NSAPI_ERROR_OK) { + (*exp_ok)++; + printf("DNS: query \"%s\" => \"%s\"\n", + hosts[i], address.get_ip_address()); + } else if (err == NSAPI_ERROR_DNS_FAILURE) { + (*exp_dns_failure)++; + printf("DNS: query \"%s\" => DNS failure\n", hosts[i]); + } else if (err == NSAPI_ERROR_TIMEOUT) { + (*exp_timeout)++; + printf("DNS: query \"%s\" => timeout\n", hosts[i]); + } else if (err == NSAPI_ERROR_NO_MEMORY) { + (*exp_no_mem)++; + printf("DNS: query \"%s\" => no memory\n", hosts[i]); + } + } +} + NetworkInterface *get_interface() { return net; @@ -145,6 +178,10 @@ Case cases[] = { #ifdef MBED_EXTENDED_TESTS Case("ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT", ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT), #endif + Case("SYNCHRONOUS_DNS", SYNCHRONOUS_DNS), + Case("SYNCHRONOUS_DNS_MULTIPLE", SYNCHRONOUS_DNS_MULTIPLE), + Case("SYNCHRONOUS_DNS_CACHE", SYNCHRONOUS_DNS_CACHE), + Case("SYNCHRONOUS_DNS_INVALID", SYNCHRONOUS_DNS_INVALID), }; Specification specification(test_setup, cases); diff --git a/TESTS/netsocket/dns/synchronous_dns.cpp b/TESTS/netsocket/dns/synchronous_dns.cpp new file mode 100644 index 0000000000..a6be9e004d --- /dev/null +++ b/TESTS/netsocket/dns/synchronous_dns.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "dns_tests.h" + +using namespace utest::v1; + +namespace { +int result_ok; +int result_no_mem; +int result_dns_failure; +int result_exp_timeout; +} + +void SYNCHRONOUS_DNS() +{ + do_gethostbyname(dns_test_hosts, 1, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); + + TEST_ASSERT(result_ok == 1); + TEST_ASSERT(result_no_mem == 0); + TEST_ASSERT(result_dns_failure == 0); + TEST_ASSERT(result_exp_timeout == 0); +} diff --git a/TESTS/netsocket/dns/synchronous_dns_cache.cpp b/TESTS/netsocket/dns/synchronous_dns_cache.cpp new file mode 100644 index 0000000000..5a18d8dd76 --- /dev/null +++ b/TESTS/netsocket/dns/synchronous_dns_cache.cpp @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "dns_tests.h" + +using namespace utest::v1; + +namespace { +int ticker_us = 0; +} + +static void test_dns_query_ticker(void) +{ + ticker_us += 100; +} + +void SYNCHRONOUS_DNS_CACHE() +{ + rtos::Semaphore semaphore; + + Ticker ticker; + ticker.attach_us(&test_dns_query_ticker, 100); + + for (unsigned int i = 0; i < 5; i++) { + SocketAddress address; + int started_us = ticker_us; + nsapi_error_t err = get_interface()->gethostbyname(dns_test_hosts_second[0], &address); + + int delay_ms = (ticker_us - started_us) / 1000; + + static int delay_first = delay_ms / 2; + // Check that cached accesses are at least twice as fast as the first one + TEST_ASSERT_TRUE(i == 0 || delay_ms <= delay_first); + + printf("DNS: query \"%s\" => \"%s\", time %i ms\n", + dns_test_hosts_second[0], address.get_ip_address(), delay_ms); + } +} diff --git a/TESTS/netsocket/dns/synchronous_dns_invalid.cpp b/TESTS/netsocket/dns/synchronous_dns_invalid.cpp new file mode 100644 index 0000000000..7623f24753 --- /dev/null +++ b/TESTS/netsocket/dns/synchronous_dns_invalid.cpp @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "dns_tests.h" + + +using namespace utest::v1; + +namespace { +int result_ok; +int result_no_mem; +int result_dns_failure; +int result_exp_timeout; +} + +void SYNCHRONOUS_DNS_INVALID() +{ + //Ensure that there are no addressess in cache + do_gethostbyname(dns_test_hosts_second, MBED_CONF_NSAPI_DNS_CACHE_SIZE, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); + + char dns_test_hosts_new[MBED_CONF_APP_DNS_TEST_HOSTS_NUM][DNS_TEST_HOST_LEN]; + memcpy(dns_test_hosts_new, dns_test_hosts, sizeof(dns_test_hosts_new)); + + int expected_failures = 0; + int expected_successes = 0; + + for (int i = 0; i < MBED_CONF_APP_DNS_TEST_HOSTS_NUM; i++) { + if ((i % 2) == 0) { + expected_failures++; + strcat(&(dns_test_hosts_new[i][0]), "_invalid"); + } else { + expected_successes++; + } + } + + do_gethostbyname(dns_test_hosts_new, MBED_CONF_APP_DNS_TEST_HOSTS_NUM, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); + + TEST_ASSERT(result_ok == expected_successes); + TEST_ASSERT(result_no_mem == 0); + TEST_ASSERT(result_dns_failure == expected_failures); + TEST_ASSERT(result_exp_timeout == 0); +} diff --git a/TESTS/netsocket/dns/synchronous_dns_multiple.cpp b/TESTS/netsocket/dns/synchronous_dns_multiple.cpp new file mode 100644 index 0000000000..28dcb513f8 --- /dev/null +++ b/TESTS/netsocket/dns/synchronous_dns_multiple.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "dns_tests.h" + +using namespace utest::v1; + +namespace { +int result_ok; +int result_no_mem; +int result_dns_failure; +int result_exp_timeout; +} + +void SYNCHRONOUS_DNS_MULTIPLE() +{ + do_gethostbyname(dns_test_hosts, MBED_CONF_APP_DNS_TEST_HOSTS_NUM, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); + + TEST_ASSERT(result_ok == MBED_CONF_APP_DNS_TEST_HOSTS_NUM); + TEST_ASSERT(result_no_mem == 0); + TEST_ASSERT(result_dns_failure == 0); + TEST_ASSERT(result_exp_timeout == 0); +} diff --git a/TESTS/network/emac/emac_test_initialize.cpp b/TESTS/network/emac/emac_test_initialize.cpp index 568cc577d6..05cf08b7c5 100644 --- a/TESTS/network/emac/emac_test_initialize.cpp +++ b/TESTS/network/emac/emac_test_initialize.cpp @@ -102,7 +102,7 @@ void test_emac_initialize() #endif // Power up the interface and emac driver - network_interface->connect(); + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, network_interface->connect()); worker_loop_link_up_wait(); } diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp index c9aba478ef..3f118d31fb 100644 --- a/TESTS/network/emac/main.cpp +++ b/TESTS/network/emac/main.cpp @@ -55,7 +55,7 @@ using namespace utest::v1; // Test setup utest::v1::status_t test_setup(const size_t number_of_cases) { #if !MBED_CONF_APP_ECHO_SERVER - GREENTEA_SETUP(600, "default_auto"); + GREENTEA_SETUP(1200, "default_auto"); #endif return verbose_test_setup_handler(number_of_cases); } diff --git a/drivers/CAN.cpp b/drivers/CAN.cpp index 2c0a53442f..e3a0d42854 100644 --- a/drivers/CAN.cpp +++ b/drivers/CAN.cpp @@ -17,7 +17,6 @@ #if DEVICE_CAN -#include "cmsis.h" #include "platform/mbed_power_mgmt.h" namespace mbed { diff --git a/drivers/TimerEvent.cpp b/drivers/TimerEvent.cpp index ddf495f681..9c5174dc72 100644 --- a/drivers/TimerEvent.cpp +++ b/drivers/TimerEvent.cpp @@ -14,7 +14,6 @@ * limitations under the License. */ #include "drivers/TimerEvent.h" -#include "cmsis.h" #include #include "hal/ticker_api.h" diff --git a/events/Event.h b/events/Event.h index 6032856cdc..3f66d4f72c 100644 --- a/events/Event.h +++ b/events/Event.h @@ -2055,6 +2055,7 @@ private: } public: +#if !defined(DOXYGEN_ONLY) /** Create an event * @param q Event queue to dispatch on * @param f Function to execute when the event is dispatched @@ -4063,7 +4064,7 @@ Event EventQueue::event(mbed::Callback(this, cb, c0, c1, c2, c3, c4); } - +#endif } #endif diff --git a/events/EventQueue.h b/events/EventQueue.h index 3232327119..b06b595fa7 100644 --- a/events/EventQueue.h +++ b/events/EventQueue.h @@ -183,6 +183,9 @@ public: */ void chain(EventQueue *target); + + + #if defined(DOXYGEN_ONLY) /** Calls an event on the queue * * The specified callback will be executed in the context of the event @@ -192,11 +195,412 @@ public: * events out of irq contexts. * * @param f Function to execute in the context of the dispatch loop + * @param args Arguments to pass to the callback * @return A unique id that represents the posted event and can * be passed to cancel, or an id of 0 if there is not * enough memory to allocate the event. * Returned id will remain valid until event has finished * executing. + * + * @code + * #include "mbed.h" + * + * int main() { + * // creates a queue with the default size + * EventQueue queue; + * + * // events are simple callbacks + * queue.call(printf, "called immediately\n"); + * + * // the dispatch method executes events + * queue.dispatch(); + * } + * @endcode + */ + template + int call(F f, Args ...args); + + /** Calls an event on the queue + * + * The specified callback is executed in the context of the event + * queue's dispatch loop. + * + * The call function is IRQ safe and can act as a mechanism for moving + * events out of IRQ contexts. + * + * @param obj Object to call with the member function + * @param method Member function to execute in the context of the dispatch loop + * @param args Arguments to pass to the callback + * @return A unique ID that represents the posted event and can + * be passed to cancel, or an ID of 0 if there is not + * enough memory to allocate the event. + * Returned ID remains valid until event has finished + * executing. + * + * @code + * #include "mbed.h" + * + * class EventHandler { + * int _id; + * public: + * EventHandler(int id) : _id(id) { } + * + * void handler(int c) { + * printf("ID: %d Param: %d\r\n", _id, c); + * } + * }; + * + * int main() { + * // creates a queue with the default size + * EventQueue queue; + * + * // Create EventHandler object with state + * EventHandler handler_cb(1); + * + * // events are simple callbacks, call object method + * // with provided parameter + * queue.call(&handler_cb, &EventHandler::handler, 2); + * + * // the dispath method executes events + * queue.dispatch(); + * } + * @endcode + */ + template + int call(T *obj, R (T::*method)(Args ...args), Args ...args); + + /** Calls an event on the queue after a specified delay + * + * The specified callback is executed in the context of the event + * queue's dispatch loop. + * + * The call_in function is IRQ safe and can act as a mechanism for moving + * events out of IRQ contexts. + * + * @param ms Time to delay in milliseconds + * @param args Arguments to pass to the callback + * @return A unique ID that represents the posted event and can + * be passed to cancel, or an ID of 0 if there is not + * enough memory to allocate the event. + * + * @code + * #include "mbed.h" + * + * int main() { + * // creates a queue with the default size + * EventQueue queue; + * + * // events are simple callbacks + * queue.call_in(2000, printf, "called in 2 seconds\n"); + * + * // the dispatch methods executes events + * queue.dispatch(); + * } + * @endcode + */ + template + int call_in(int ms, Args ...args); + + /** Calls an event on the queue after a specified delay + * + * The specified callback is executed in the context of the event + * queue's dispatch loop. + * + * The call_in function is IRQ safe and can act as a mechanism for moving + * events out of IRQ contexts. + * + * @param ms Time to delay in milliseconds + * @param obj Object to call with the member function + * @param method Member function to execute in the context of the dispatch loop + * @param args Arguments to pass to the callback + * @return A unique ID that represents the posted event and can + * be passed to cancel, or an ID of 0 if there is not + * enough memory to allocate the event. + * + * @code + * #include "mbed.h" + * + * class EventHandler { + * int _id; + * public: + * EventHandler(int id) : _id(id) { } + * + * void handler(int c) { + * printf("ID: %d Param: %d\r\n", _id, c); + * } + * }; + * + * int main() { + * // creates a queue with the default size + * EventQueue queue; + * + * // Create EventHandler object with state + * EventHandler handler_cb(3); + * + * // events are simple callbacks, call object method in 2 seconds + * // with provided parameter + * queue.call_in(2000, &handler_cb, &EventHandler::handler, 4); + * + * // the dispatch method executes events + * queue.dispatch(); + * } + * @endcode + */ + template + int call_in(int ms, T *obj, R (T::*method)(Args ...args), Args ...args); + + /** Calls an event on the queue periodically + * + * @note The first call_every event occurs after the specified delay. + * To create a periodic event that fires immediately, @see Event. + * + * The specified callback is executed in the context of the event + * queue's dispatch loop. + * + * The call_every function is IRQ safe and can act as a mechanism for + * moving events out of IRQ contexts. + * + * @param ms Period of the event in milliseconds + * @param f Function to execute in the context of the dispatch loop + * @param args Arguments to pass to the callback + * @return A unique ID that represents the posted event and can + * be passed to cancel, or an ID of 0 if there is not + * enough memory to allocate the event. + * + * @code + * #include "mbed.h" + * + * class EventHandler { + * int _id; + * public: + * EventHandler(int id) : _id(id) { } + * + * void handler(int c) { + * printf("ID: %d Param: %d\r\n", _id, c); + * } + * }; + * + * int main() { + * // creates a queue with the default size + * EventQueue queue; + * + * // events are simple callbacks, call every 2 seconds + * queue.call_every(2000, printf, "Calling every 2 seconds\n"); + * + * // the dispatch method executes events + * queue.dispatch(); + * } + * @endcode + */ + template + int call_every(int ms, F f, Args ...args); + + /** Calls an event on the queue periodically + * + * @note The first call_every event occurs after the specified delay. + * To create a periodic event that fires immediately, @see Event. + * + * The specified callback is executed in the context of the event + * queue's dispatch loop. + * + * The call_every function is IRQ safe and can act as a mechanism for + * moving events out of IRQ contexts. + * + * @param ms Period of the event in milliseconds + * @param obj Object to call with the member function + * @param method Member function to execute in the context of the dispatch loop + * @param args Arguments to pass to the callback + * + * @code + * #include "mbed.h" + * + * class EventHandler { + * int _id; + * public: + * EventHandler(int id) : _id(id) { } + * + * void handler(int c) { + * printf("ID: %d Param: %d\r\n", _id, c); + * } + * }; + * + * int main() { + * // creates a queue with the default size + * EventQueue queue; + * + * // Create EventHandler object with state + * EventHandler handler_cb(5); + * + * // events are simple callbacks, call object method every 2 seconds + * // with provided parameter + * queue.call_every(2000, &handler_cb, &EventHandler::handler, 6); + * + * // the dispatch method executes events + * queue.dispatch(); + * } + * @endcode + */ + template + int call_every(int ms, T *obj, R (T::*method)(Args ...args), Args ...args); + + /** Creates an event bound to the event queue + * + * Constructs an event bound to the specified event queue. The specified + * callback acts as the target for the event and is executed in the + * context of the event queue's dispatch loop once posted. + * + * @param func Function to execute when the event is dispatched + * @param args Arguments to pass to the callback + * @return Event that dispatches on the specific queue + * + * @code + * #include "mbed.h" + * + * void handler(int c) { + * printf("Param: %d\r\n", c); + * } + * + * int main() + * { + * EventQueue queue; + * + * // Create event with parameter + * Event e = queue.event(handler, 1); + * e(); + * + * // Create event and post parameter later + * Event e2 = queue.event(handler); + * + * // Post the event with paramter 8 + * e.post(8); + * + * // The dispatch method executes events + * queue.dispatch(); + * + * e2.post(2); + * + * queue.dispatch(); + * } + * @endcode + */ + template + Event event(R (*func)(BoundArgs...), Args ...args); + + /** Creates an event bound to the event queue + * + * Constructs an event bound to the specified event queue. The specified + * callback acts as the target for the event and is executed in the + * context of the event queue's dispatch loop once posted. + * + * @param obj Object to call with the member function + * @param method Member function to execute in the context of the dispatch loop + * @param context_args Arguments to pass to the callback + * @return Event that dispatches on the specific queue + * + * @code + * #include "mbed.h" + * + * class EventHandler { + * int _id; + * + * public: + * EventHandler(int id) : _id(id) { } + * + * void handler(int c) { + * printf("ID: %d Param: %d\r\n", _id, c); + * } + * }; + * + * int main() + * { + * EventQueue queue; + * + * EventHandler handler_cb(10); + * + * // Create event on the eventqueue with a method callback + * Event e = queue.event(&handler_cb, &EventHandler::handler); + * + * // Post the event with paramter 8 + * e.post(11); + * + * // The dispatch method executes events + * queue.dispatch(); + * } + * @endcode + */ + template + Event event(T *obj, R (T::*method)(BoundArgs..., Args...), ContextArgs ...context_args); + + /** Creates an event bound to the event queue + * + * Constructs an event bound to the specified event queue. The specified + * callback acts as the target for the event and is executed in the + * context of the event queue's dispatch loop once posted. + * + * @param cb Callback object + * @param context_args Arguments to pass to the callback + * @return Event that dispatches on the specific queue + * + * @code + * #include "mbed.h" + * + * void handler(int c) { + * printf("Param: %d\r\n", c); + * } + * + * int main() + * { + * EventQueue queue; + * // Create callback object acting as a function + * // pointer to handler + * Callback cb(handler); + * + * // Pass the callback object to the eventqueue + * Event e = queue.event(cb); + * + * // Post the event with parameter 8 + * e.post(9); + * + * // The dispatch method executes events + * q.dispatch(); + * } + * @endcode + */ + template + Event event(mbed::Callback cb, ContextArgs ...context_args); + + #else + + /** Calls an event on the queue + * + * The specified callback is executed in the context of the event + * queue's dispatch loop. + * + * The call function is IRQ safe and can act as a mechanism for moving + * events out of IRQ contexts. + * + * @param f Function to execute in the context of the dispatch loop + * @return A unique ID that represents the posted event and can + * be passed to cancel, or an ID of 0 if there is not + * enough memory to allocate the event. + * Returned ID remains valid until event has finished + * executing. + * + * @code + * #include "mbed.h" + * + * int main() + * { + * EventQueue queue; + * + * Callback cb(handler); + * + * // Create event on the eventqueue with a separate callback object + * Event e = queue.event(cb); + * e.post(1); + * queue.dispatch(); + * } + * @endcode */ template int call(F f) @@ -211,6 +615,7 @@ public: return equeue_post(&_equeue, &EventQueue::function_call, e); } + /** Calls an event on the queue * @see EventQueue::call * @param f Function to execute in the context of the dispatch loop @@ -490,8 +895,8 @@ public: * The call_in function is irq safe and can act as a mechanism for moving * events out of irq contexts. * - * @param f Function to execute in the context of the dispatch loop * @param ms Time to delay in milliseconds + * @param f Function to execute in the context of the dispatch loop * @return A unique id that represents the posted event and can * be passed to cancel, or an id of 0 if there is not * enough memory to allocate the event. @@ -2395,6 +2800,7 @@ public: */ template Event event(mbed::Callback cb, C0 c0, C1 c1, C2 c2, C3 c3, C4 c4); + #endif protected: template diff --git a/features/cellular/framework/AT/AT_CellularNetwork.cpp b/features/cellular/framework/AT/AT_CellularNetwork.cpp index 22dc766b1d..491031bacf 100644 --- a/features/cellular/framework/AT/AT_CellularNetwork.cpp +++ b/features/cellular/framework/AT/AT_CellularNetwork.cpp @@ -1265,7 +1265,7 @@ nsapi_error_t AT_CellularNetwork::get_operator_names(operator_names_list &op_nam { _at.lock(); - _at.cmd_start("AT+COPN?"); + _at.cmd_start("AT+COPN"); _at.cmd_stop(); _at.resp_start("+COPN:"); diff --git a/features/frameworks/greentea-client/greentea-client/test_env.h b/features/frameworks/greentea-client/greentea-client/test_env.h index 6aa2617c57..672874d29a 100644 --- a/features/frameworks/greentea-client/greentea-client/test_env.h +++ b/features/frameworks/greentea-client/greentea-client/test_env.h @@ -33,8 +33,12 @@ /** * Auxilary macros */ +#ifndef NL #define NL "\n" +#endif +#ifndef RCNL #define RCNL "\r\n" +#endif /** * Auxilary macros to keep mbed-drivers compatibility with utest before greentea-client diff --git a/features/frameworks/greentea-client/source/greentea_metrics.cpp b/features/frameworks/greentea-client/source/greentea_metrics.cpp index dd9f37dac7..0789effa24 100644 --- a/features/frameworks/greentea-client/source/greentea_metrics.cpp +++ b/features/frameworks/greentea-client/source/greentea_metrics.cpp @@ -87,7 +87,11 @@ MBED_UNUSED static void send_stack_info() // Print info for all other threads uint32_t thread_n = osThreadGetCount(); - osThreadId_t *threads = new osThreadId_t[thread_n]; + osThreadId_t *threads = new (std::nothrow) osThreadId_t[thread_n]; + // Don't fail on lack of memory + if (!threads) { + goto end; + } thread_n = osThreadEnumerate(threads, thread_n); for(size_t i = 0; i < thread_n; i++) { @@ -97,6 +101,7 @@ MBED_UNUSED static void send_stack_info() delete[] threads; +end: mutex->unlock(); } diff --git a/features/unsupported/tests/mbed/env/test_env.h b/features/unsupported/tests/mbed/env/test_env.h index bfb2c44d2d..6a390dc551 100644 --- a/features/unsupported/tests/mbed/env/test_env.h +++ b/features/unsupported/tests/mbed/env/test_env.h @@ -4,8 +4,12 @@ #include #include "mbed.h" +#ifndef NL #define NL "\n" +#endif +#ifndef RCNL #define RCNL "\r\n" +#endif // Const strings used in test_end extern const char* TEST_ENV_START; diff --git a/platform/mbed_stats.c b/platform/mbed_stats.c index 11d870b7d1..81b1a6a3ce 100644 --- a/platform/mbed_stats.c +++ b/platform/mbed_stats.c @@ -41,7 +41,10 @@ void mbed_stats_stack_get(mbed_stats_stack_t *stats) osThreadId_t *threads; threads = malloc(sizeof(osThreadId_t) * thread_n); - MBED_ASSERT(threads != NULL); + // Don't fail on lack of memory + if (!threads) { + return; + } osKernelLock(); thread_n = osThreadEnumerate(threads, thread_n); @@ -69,7 +72,10 @@ size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count) osThreadId_t *threads; threads = malloc(sizeof(osThreadId_t) * count); - MBED_ASSERT(threads != NULL); + // Don't fail on lack of memory + if (!threads) { + return 0; + } osKernelLock(); count = osThreadEnumerate(threads, count); diff --git a/platform/mbed_version.h b/platform/mbed_version.h index 3ca5b7cd32..7d5b7823a6 100644 --- a/platform/mbed_version.h +++ b/platform/mbed_version.h @@ -43,7 +43,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_PATCH_VERSION 5 +#define MBED_PATCH_VERSION 7 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch)) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralNames.h new file mode 100644 index 0000000000..65d2b635b8 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralNames.h @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, + ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, + ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, + ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, + ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, + ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, + ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, + ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, + ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, + ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, + ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, + ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, + ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, + ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, + ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralPins.c new file mode 100644 index 0000000000..c2bb8f627e --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PeripheralPins.c @@ -0,0 +1,242 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTA17, ADC1_SE17, 0}, + {PTB0 , ADC0_SE8 , 0}, + {PTB1 , ADC0_SE9 , 0}, + {PTB2 , ADC0_SE12, 0}, + {PTB3 , ADC0_SE13, 0}, + {PTB6 , ADC1_SE12, 0}, + {PTB7 , ADC1_SE13, 0}, + {PTB10, ADC1_SE14, 0}, + {PTB11, ADC1_SE15, 0}, + {PTC0 , ADC0_SE14, 0}, + {PTC1 , ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10, ADC1_SE6b, 0}, + {PTC11, ADC1_SE7b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTE0, ADC1_SE4a, 0}, + {PTE1, ADC1_SE5a, 0}, + {PTE2, ADC1_SE6a, 0}, + {PTE3, ADC1_SE7a, 0}, + //{PTE24, ADC0_SE17, 0}, //I2C pull up + //{PTE25, ADC0_SE18, 0}, //I2C pull up + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE25, I2C_0, 5}, + {PTB1 , I2C_0, 2}, + {PTB3 , I2C_0, 2}, + {PTC11, I2C_1, 2}, + {PTA13, I2C_2, 5}, + {PTD3 , I2C_0, 7}, + {PTE0 , I2C_1, 6}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE24, I2C_0, 5}, + {PTB0 , I2C_0, 2}, + {PTB2 , I2C_0, 2}, + {PTC10, I2C_1, 2}, + {PTA12, I2C_2, 5}, + {PTA14, I2C_2, 5}, + {PTD2 , I2C_0, 7}, + {PTE1 , I2C_1, 6}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC17, UART_3, 3}, + {PTD7 , UART_0, 3}, + {PTD3 , UART_2, 3}, + {PTC4 , UART_1, 3}, + {PTC15, UART_4, 3}, + {PTB11, UART_3, 3}, + {PTA14, UART_0, 3}, + {PTE24, UART_4, 3}, + {PTE4 , UART_3, 3}, + {PTE0, UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTE1 , UART_1, 3}, + {PTE5 , UART_3, 3}, + {PTE25, UART_4, 3}, + {PTA15, UART_0, 3}, + {PTC16, UART_3, 3}, + {PTB10, UART_3, 3}, + {PTC3 , UART_1, 3}, + {PTC14, UART_4, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PTB13, UART_3, 2}, + {PTE2 , UART_1, 3}, + {PTE6 , UART_3, 3}, + {PTE26, UART_4, 3}, + {PTA0 , UART_0, 2}, + {PTA16, UART_0, 3}, + {PTB3 , UART_0, 3}, + {PTB9 , UART_3, 3}, + {PTC2 , UART_1, 3}, + {PTC13, UART_4, 3}, + {PTC19, UART_3, 3}, + {PTD1 , UART_2, 3}, + {PTD5 , UART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PTB12, UART_3, 2}, + {PTE3 , UART_1, 3}, + {PTE7 , UART_3, 3}, + {PTE27, UART_4, 3}, + {PTA17, UART_0, 3}, + {PTB8 , UART_3, 3}, + {PTC1 , UART_1, 3}, + {PTC12, UART_4, 3}, + {PTC18, UART_3, 3}, + {PTD0 , UART_2, 3}, + {PTD4 , UART_0, 3}, + {PTA3 , UART_0, 2}, + {PTB2 , UART_0, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTD1 , SPI_0, 2}, + {PTE2 , SPI_1, 2}, + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTB21, SPI_2, 2}, + {PTC5 , SPI_0, 2}, + {PTD5 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2 , SPI_0, 2}, + {PTE1 , SPI_1, 2}, + {PTE3 , SPI_1, 7}, + {PTA16, SPI_0, 2}, + {PTB16, SPI_1, 2}, + {PTB22, SPI_2, 2}, + {PTC6 , SPI_0, 2}, + {PTD6 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3 , SPI_0, 2}, + {PTE1 , SPI_1, 7}, + {PTE3 , SPI_1, 2}, + {PTA17, SPI_0, 2}, + {PTB17, SPI_1, 2}, + {PTB23, SPI_2, 2}, + {PTC7 , SPI_0, 2}, + {PTD7 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0 , SPI_0, 2}, + {PTE4 , SPI_1, 2}, + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTB20, SPI_2, 2}, + {PTC4 , SPI_0, 2}, + {PTD4 , SPI_1, 7}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0 , PWM_6 , 3}, + {PTA1 , PWM_7 , 3}, + {PTA2 , PWM_8 , 3}, + {PTA3 , PWM_1 , 3}, + {PTA4 , PWM_2 , 3}, + {PTA5 , PWM_3 , 3}, + {PTA6 , PWM_4 , 3}, + {PTA7 , PWM_5 , 3}, + {PTA8 , PWM_9 , 3}, + {PTA9 , PWM_10, 3}, + {PTA10, PWM_17, 3}, + {PTA11, PWM_18, 3}, + {PTA12, PWM_9 , 3}, + {PTA13, PWM_10, 3}, + + {PTB0 , PWM_9 , 3}, + {PTB1 , PWM_10, 3}, + {PTB18, PWM_17, 3}, + {PTB19, PWM_18, 3}, + + {PTC1 , PWM_1 , 4}, + {PTC2 , PWM_2 , 4}, + {PTC3 , PWM_3 , 4}, + {PTC4 , PWM_4 , 4}, + {PTC5 , PWM_3 , 7}, + {PTC8 , PWM_29, 3}, + {PTC9 , PWM_30, 3}, + {PTC10, PWM_31, 3}, + {PTC11, PWM_32, 3}, + + {PTD0 , PWM_25, 4}, + {PTD1 , PWM_26, 4}, + {PTD2 , PWM_27, 4}, + {PTD3 , PWM_28, 4}, + {PTD4 , PWM_5 , 4}, + {PTD5 , PWM_6 , 4}, + {PTD6 , PWM_7 , 4}, + {PTD4 , PWM_5 , 4}, + {PTD7 , PWM_8 , 4}, + + {PTE5 , PWM_25, 6}, + {PTE6 , PWM_26, 6}, + + {NC , NC , 0} +}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PinNames.h new file mode 100644 index 0000000000..af4b262b3e --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/PinNames.h @@ -0,0 +1,318 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define DAC0_OUT 0xFEFE /* DAC does not have Pin Name in RM */ +#define NOT_CONNECTED (int)0xFFFFFFFF +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), + PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), + PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), + PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTA22 = (0 << GPIO_PORT_SHIFT | 22), + PTA23 = (0 << GPIO_PORT_SHIFT | 23), + PTA24 = (0 << GPIO_PORT_SHIFT | 24), + PTA25 = (0 << GPIO_PORT_SHIFT | 25), + PTA26 = (0 << GPIO_PORT_SHIFT | 26), + PTA27 = (0 << GPIO_PORT_SHIFT | 27), + PTA28 = (0 << GPIO_PORT_SHIFT | 28), + PTA29 = (0 << GPIO_PORT_SHIFT | 29), + PTA30 = (0 << GPIO_PORT_SHIFT | 30), + PTA31 = (0 << GPIO_PORT_SHIFT | 31), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), + PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), + PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), + PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), + PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), + PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB12 = (1 << GPIO_PORT_SHIFT | 12), + PTB13 = (1 << GPIO_PORT_SHIFT | 13), + PTB14 = (1 << GPIO_PORT_SHIFT | 14), + PTB15 = (1 << GPIO_PORT_SHIFT | 15), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTB24 = (1 << GPIO_PORT_SHIFT | 24), + PTB25 = (1 << GPIO_PORT_SHIFT | 25), + PTB26 = (1 << GPIO_PORT_SHIFT | 26), + PTB27 = (1 << GPIO_PORT_SHIFT | 27), + PTB28 = (1 << GPIO_PORT_SHIFT | 28), + PTB29 = (1 << GPIO_PORT_SHIFT | 29), + PTB30 = (1 << GPIO_PORT_SHIFT | 30), + PTB31 = (1 << GPIO_PORT_SHIFT | 31), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTC20 = (2 << GPIO_PORT_SHIFT | 20), + PTC21 = (2 << GPIO_PORT_SHIFT | 21), + PTC22 = (2 << GPIO_PORT_SHIFT | 22), + PTC23 = (2 << GPIO_PORT_SHIFT | 23), + PTC24 = (2 << GPIO_PORT_SHIFT | 24), + PTC25 = (2 << GPIO_PORT_SHIFT | 25), + PTC26 = (2 << GPIO_PORT_SHIFT | 26), + PTC27 = (2 << GPIO_PORT_SHIFT | 27), + PTC28 = (2 << GPIO_PORT_SHIFT | 28), + PTC29 = (2 << GPIO_PORT_SHIFT | 29), + PTC30 = (2 << GPIO_PORT_SHIFT | 30), + PTC31 = (2 << GPIO_PORT_SHIFT | 31), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), + PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), + PTD10 = (3 << GPIO_PORT_SHIFT | 10), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTD15 = (3 << GPIO_PORT_SHIFT | 15), + PTD16 = (3 << GPIO_PORT_SHIFT | 16), + PTD17 = (3 << GPIO_PORT_SHIFT | 17), + PTD18 = (3 << GPIO_PORT_SHIFT | 18), + PTD19 = (3 << GPIO_PORT_SHIFT | 19), + PTD20 = (3 << GPIO_PORT_SHIFT | 20), + PTD21 = (3 << GPIO_PORT_SHIFT | 21), + PTD22 = (3 << GPIO_PORT_SHIFT | 22), + PTD23 = (3 << GPIO_PORT_SHIFT | 23), + PTD24 = (3 << GPIO_PORT_SHIFT | 24), + PTD25 = (3 << GPIO_PORT_SHIFT | 25), + PTD26 = (3 << GPIO_PORT_SHIFT | 26), + PTD27 = (3 << GPIO_PORT_SHIFT | 27), + PTD28 = (3 << GPIO_PORT_SHIFT | 28), + PTD29 = (3 << GPIO_PORT_SHIFT | 29), + PTD30 = (3 << GPIO_PORT_SHIFT | 30), + PTD31 = (3 << GPIO_PORT_SHIFT | 31), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), + PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), + PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), + PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), + PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), + PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), + PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), + PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE14 = (4 << GPIO_PORT_SHIFT | 14), + PTE15 = (4 << GPIO_PORT_SHIFT | 15), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE26 = (4 << GPIO_PORT_SHIFT | 26), + PTE27 = (4 << GPIO_PORT_SHIFT | 27), + PTE28 = (4 << GPIO_PORT_SHIFT | 28), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + // Analog + A0 = PTB6, + A1 = PTB7, + A2 = DAC0_OUT, + //A3 = DAC1_OUT, + + // General Pin Input Output (GPIO) + GPIO0 = PTC1, + GPIO1 = PTC5, + GPIO2 = PTD6, + GPIO3 = PTC9, + GPIO4 = PTC3, + GPIO5 = PTC6, + GPIO6 = NOT_CONNECTED, + + // Pulse Width Modulation (PWM) + PWM0 = GPIO2, + PWM1 = GPIO3, + PWM2 = GPIO0, + PWM3 = GPIO1, + + // LEDs + LED0 = GPIO0, + LED1 = GPIO1, + LED2 = GPIO2, + + LED_RED = LED0, + LED_GREEN = LED1, + LED_BLUE = LED2, + + // USB bridge and SWD UART connected UART pins + USBTX = PTC15, + USBRX = PTC14, + + // UART pins + UART0_RX = PTD8, + UART0_TX = PTD9, + UART0_CTS = PTD11, + UART0_RTS = PTD10, + + UART1_RX = USBRX, + UART1_TX = USBTX, + UART1_CTS = PTC13, + UART1_RTS = PTC12, + + UART2_RX = PTC16, + UART2_TX = PTC17, + UART2_CTS = PTC19, + UART2_RTS = PTC18, + + // I2C pins + I2C0_SCL = PTC10, + I2C0_SDA = PTC11, + + I2C1_SCL = PTB2, + I2C1_SDA = PTB3, + + I2C2_SCL = NOT_CONNECTED, + I2C2_SDA = NOT_CONNECTED, + + // SPI pins + SPI0_SCK = PTB11, + SPI0_MOSI = PTB16, + SPI0_MISO = PTB17, + SPI0_SS0 = PTB10, + SPI0_SS1 = PTB9, + SPI0_SS2 = PTB8, + + SPI1_SCK = PTB21, + SPI1_MOSI = PTB22, + SPI1_MISO = PTB23, + SPI1_SS0 = PTB20, + SPI1_SS1 = PTB19, + SPI1_SS2 = PTB18, + + SPI2_SCK = PTD1, + SPI2_MOSI = PTD2, + SPI2_MISO = PTD3, + SPI2_SS0 = PTD0, + SPI2_SS1 = PTD4, + SPI2_SS2 = PTD5, + + SPI3_SCK = NOT_CONNECTED, + SPI3_MOSI = NOT_CONNECTED, + SPI3_MISO = NOT_CONNECTED, + SPI3_SS0 = NOT_CONNECTED, + SPI3_SS1 = NOT_CONNECTED, + SPI3_SS2 = NOT_CONNECTED, + + // SWD UART + SWD_TGT_TX = UART1_TX, + SWD_TGT_RX = UART1_RX, + SWD_TGT_CTS = UART1_CTS, + SWD_TGT_RTS = UART1_RTS, + + // Generics + SERIAL_TX = UART0_TX, + SERIAL_RX = UART0_RX, + I2C_SCL = I2C0_SCL, + I2C_SDA = I2C0_SDA, + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_SS0, + PWM_OUT = PWM0, + + // Not connected + NC = NOT_CONNECTED +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.c new file mode 100644 index 0000000000..7e2d7e7c51 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.c @@ -0,0 +1,234 @@ +/********************************************************************** + * + * Filename: crc.c + * + * Description: Slow and fast implementations of the CRC standards. + * + * Notes: The parameters for each supported CRC standard are + * defined in the header file crc.h. The implementations + * here should stand up to further additions to that list. + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#include "crc.h" + + +/* + * Derive parameters from the standard-specific parameters in crc.h. + */ +#define WIDTH (8 * sizeof(crc)) +#define TOPBIT (1 << (WIDTH - 1)) + +#if (REFLECT_DATA == TRUE) +#undef REFLECT_DATA +#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8)) +#else +#undef REFLECT_DATA +#define REFLECT_DATA(X) (X) +#endif + +#if (REFLECT_REMAINDER == TRUE) +#undef REFLECT_REMAINDER +#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH)) +#else +#undef REFLECT_REMAINDER +#define REFLECT_REMAINDER(X) (X) +#endif + + +/********************************************************************* + * + * Function: reflect() + * + * Description: Reorder the bits of a binary sequence, by reflecting + * them about the middle position. + * + * Notes: No checking is done that nBits <= 32. + * + * Returns: The reflection of the original data. + * + *********************************************************************/ +static unsigned long +reflect(unsigned long data, unsigned char nBits) +{ + unsigned long reflection = 0x00000000; + unsigned char bit; + + /* + * Reflect the data about the center bit. + */ + for (bit = 0; bit < nBits; ++bit) + { + /* + * If the LSB bit is set, set the reflection of it. + */ + if (data & 0x01) + { + reflection |= (1 << ((nBits - 1) - bit)); + } + + data = (data >> 1); + } + + return (reflection); + +} /* reflect() */ + + +/********************************************************************* + * + * Function: crcSlow() + * + * Description: Compute the CRC of a given message. + * + * Notes: + * + * Returns: The CRC of the message. + * + *********************************************************************/ +crc +crcSlow(unsigned char const message[], int nBytes) +{ + crc remainder = INITIAL_REMAINDER; + int byte; + unsigned char bit; + + + /* + * Perform modulo-2 division, a byte at a time. + */ + for (byte = 0; byte < nBytes; ++byte) + { + /* + * Bring the next byte into the remainder. + */ + remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8)); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) + { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) + { + remainder = (remainder << 1) ^ POLYNOMIAL; + } + else + { + remainder = (remainder << 1); + } + } + } + + /* + * The final remainder is the CRC result. + */ + return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); + +} /* crcSlow() */ + + +crc crcTable[256]; + + +/********************************************************************* + * + * Function: crcInit() + * + * Description: Populate the partial CRC lookup table. + * + * Notes: This function must be rerun any time the CRC standard + * is changed. If desired, it can be run "offline" and + * the table results stored in an embedded system's ROM. + * + * Returns: None defined. + * + *********************************************************************/ +void +crcInit(void) +{ + crc remainder; + int dividend; + unsigned char bit; + + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) + { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (WIDTH - 8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) + { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) + { + remainder = (remainder << 1) ^ POLYNOMIAL; + } + else + { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + crcTable[dividend] = remainder; + } + +} /* crcInit() */ + + +/********************************************************************* + * + * Function: crcFast() + * + * Description: Compute the CRC of a given message. + * + * Notes: crcInit() must be called first. + * + * Returns: The CRC of the message. + * + *********************************************************************/ +crc +crcFast(unsigned char const message[], int nBytes) +{ + crc remainder = INITIAL_REMAINDER; + unsigned char data; + int byte; + + + /* + * Divide the message by the polynomial, a byte at a time. + */ + for (byte = 0; byte < nBytes; ++byte) + { + data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8)); + remainder = crcTable[data] ^ (remainder << 8); + } + + /* + * The final remainder is the CRC. + */ + return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); + +} /* crcFast() */ + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.h new file mode 100644 index 0000000000..fae66ae4bc --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/crc.h @@ -0,0 +1,77 @@ +/********************************************************************** + * + * Filename: crc.h + * + * Description: A header file describing the various CRC standards. + * + * Notes: + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#ifndef _crc_h +#define _crc_h + + +#define FALSE 0 +#define TRUE !FALSE + +/* + * Select the CRC standard from the list that follows. + */ +#define CRC16 + + +#if defined(CRC_CCITT) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-CCITT" +#define POLYNOMIAL 0x1021 +#define INITIAL_REMAINDER 0xFFFF +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA FALSE +#define REFLECT_REMAINDER FALSE +#define CHECK_VALUE 0x29B1 + +#elif defined(CRC16) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-16" +#define POLYNOMIAL 0x8005 +#define INITIAL_REMAINDER 0x0000 +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xBB3D + +#elif defined(CRC32) + +typedef unsigned long crc; + +#define CRC_NAME "CRC-32" +#define POLYNOMIAL 0x04C11DB7 +#define INITIAL_REMAINDER 0xFFFFFFFF +#define FINAL_XOR_VALUE 0xFFFFFFFF +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xCBF43926 + +#else + +#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." + +#endif + + +void crcInit(void); +crc crcSlow(unsigned char const message[], int nBytes); +crc crcFast(unsigned char const message[], int nBytes); + + +#endif /* _crc_h */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/device.h new file mode 100644 index 0000000000..29a4e7a0b1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.c new file mode 100644 index 0000000000..9ceaef0a1a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 120MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 7U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 120000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC, false); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.h new file mode 100644 index 0000000000..050c3ab79b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 50000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.c new file mode 100644 index 0000000000..7faf4e87c6 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.c @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_phy.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0xFFFFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) +{ + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; + uint32_t instance = ENET_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI(base, srcClock_Hz, false); + + /* Initialization after PHY stars to work. */ + while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) + { + PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + counter --; + } + + if (!counter) + { + return kStatus_Fail; + } + + /* Reset PHY. */ + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + + return result; +} + +status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr) +{ + status_t result = kStatus_Success; + uint32_t bssReg; + uint32_t counter = PHY_TIMEOUT_COUNT; + + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, + (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter --) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { + if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) + { + break; + } + } + + if (!counter) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + assert(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in the basic control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + assert(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); + if (result == kStatus_Success) + { + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = kPHY_FullDuplex; + } + else + { + /* Half duplex. */ + *duplex = kPHY_HalfDuplex; + } + + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = kPHY_Speed100M; + } + else + { /* 10M speed. */ + *speed = kPHY_Speed10M; + } + } + + return result; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.h new file mode 100644 index 0000000000..5512477d10 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/fsl_phy.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the PHY status. */ +enum _phy_status +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); + +/*! + * @brief Initiates auto negotiation. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @retval kStatus_Success PHY auto negotiation success + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c new file mode 100644 index 0000000000..3c62ed7ca4 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c @@ -0,0 +1,80 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" + +#define CRC16 +#include "crc.h" +#include "fsl_clock_config.h" + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} + +// Provide ethernet devices with a semi-unique MAC address from the UUID +void mbed_mac_address(char *mac) +{ + uint16_t MAC[3]; // 3 16 bits words for the MAC + + // get UID via SIM_UID macros defined in the K64F MCU CMSIS header file + uint32_t UID[4]; + UID[0] = SIM->UIDH; + UID[1] = SIM->UIDMH; + UID[2] = SIM->UIDML; + UID[3] = SIM->UIDL; + + // generate three CRC16's using different slices of the UUID + MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word + MAC[1] = crcSlow((const uint8_t *)UID, 12); + MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word + + // The network stack expects an array of 6 bytes + // so we copy, and shift and copy from the half-word array to the byte array + mac[0] = MAC[0] >> 8; + mac[1] = MAC[0]; + mac[2] = MAC[1] >> 8; + mac[3] = MAC[1]; + mac[4] = MAC[2] >> 8; + mac[5] = MAC[2]; + + // We want to force bits [1:0] of the most significant byte [0] + // to be "10" + // http://en.wikipedia.org/wiki/MAC_address + + mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered" + mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast + +} + + + diff --git a/targets/TARGET_Freescale/mbed_rtx.h b/targets/TARGET_Freescale/mbed_rtx.h index 3602d0436f..507c042e2e 100644 --- a/targets/TARGET_Freescale/mbed_rtx.h +++ b/targets/TARGET_Freescale/mbed_rtx.h @@ -89,6 +89,12 @@ #define INITIAL_SP (0x20030000UL) #endif +#elif defined(TARGET_SDT64B) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20030000UL) +#endif + #elif defined(TARGET_KW24D) #ifndef INITIAL_SP diff --git a/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PeripheralNames.h b/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PeripheralNames.h new file mode 100644 index 0000000000..9d4d4a687b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PeripheralNames.h @@ -0,0 +1,90 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1, + UART_2 = MXC_BASE_UART2, + UART_3 = MXC_BASE_UART3, + STDIO_UART = UART_1 +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2CM0, + I2C_1 = MXC_BASE_I2CM1, + I2C_2 = MXC_BASE_I2CM2 +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPIM0, + SPI_1 = MXC_BASE_SPIM1, + SPI_2 = MXC_BASE_SPIM2 +} SPIName; + +typedef enum { + PWM_0 = MXC_BASE_PT0, + PWM_1 = MXC_BASE_PT1, + PWM_2 = MXC_BASE_PT2, + PWM_3 = MXC_BASE_PT3, + PWM_4 = MXC_BASE_PT4, + PWM_5 = MXC_BASE_PT5, + PWM_6 = MXC_BASE_PT6, + PWM_7 = MXC_BASE_PT7, + PWM_8 = MXC_BASE_PT8, + PWM_9 = MXC_BASE_PT9, + PWM_10 = MXC_BASE_PT10, + PWM_11 = MXC_BASE_PT11, + PWM_12 = MXC_BASE_PT12, + PWM_13 = MXC_BASE_PT13, + PWM_14 = MXC_BASE_PT14, + PWM_15 = MXC_BASE_PT15 +} PWMName; + +typedef enum { + ADC = MXC_BASE_ADC +} ADCName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PinNames.h new file mode 100644 index 0000000000..94884dd909 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32620C/TARGET_SDT32620B/PinNames.h @@ -0,0 +1,198 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, + PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL +} PinDirection; + +#define PORT_SHIFT 12 +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) + +#define NOT_CONNECTED (int)0xFFFFFFFF + +typedef enum { + P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, + P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, + P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, + P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, + P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, + P5_0 = (5 << PORT_SHIFT), P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, + P6_0 = (6 << PORT_SHIFT), + + // Analog input pins + AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, AIN_10, AIN_11, + + // Analog + A0 = AIN_0, + A1 = AIN_1, + A2 = AIN_2, + A3 = AIN_3, + + // General Pin Input Output (GPIO) + GPIO0 = P1_4, + GPIO1 = P1_5, + GPIO2 = P4_0, + GPIO3 = P4_1, + GPIO4 = P4_2, + GPIO5 = P4_3, + GPIO6 = P5_6, + + //Purse Width Modulation (PWM) + PWM0 = GPIO2, + PWM1 = GPIO3, + PWM2 = GPIO0, + PWM3 = GPIO1, + + // LEDs + LED0 = GPIO0, + LED1 = GPIO1, + LED2 = GPIO2, + LED3 = NOT_CONNECTED, + LED4 = NOT_CONNECTED, + + LED_RED = LED0, + LED_GREEN = LED1, + LED_BLUE = LED2, + + // USB bridge and SWD UART connected UART pins + USBTX = P2_1, + USBRX = P2_0, + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + + // UART pins + UART0_RX = P0_0, + UART0_TX = P0_1, + UART0_CTS = P0_2, + UART0_RTS = P0_3, + + UART1_RX = P2_0, + UART1_TX = P2_1, + UART1_CTS = P2_2, + UART1_RTS = P2_3, + + UART2_RX = P3_0, + UART2_TX = P3_1, + UART2_CTS = P3_2, + UART2_RTS = P3_3, + + // I2C pins + I2C0_SCL = P1_7, + I2C0_SDA = P1_6, + + I2C1_SCL = P3_5, + I2C1_SDA = P3_4, + + I2C2_SCL = P6_0, + I2C2_SDA = P5_7, + + // SPI pins + SPI0_SCK = P0_4, + SPI0_MOSI = P0_5, + SPI0_MISO = P0_6, + SPI0_SS0 = P0_7, + SPI0_SS1 = P4_4, + SPI0_SS2 = P4_5, + + SPI1_SCK = P1_0, + SPI1_MOSI = P1_1, + SPI1_MISO = P1_2, + SPI1_SS0 = P1_3, + SPI1_SS1 = P3_6, + SPI1_SS2 = P3_7, + + SPI2_SCK = P2_4, + SPI2_MOSI = P2_5, + SPI2_MISO = P2_6, + SPI2_SS0 = P2_7, + SPI2_SS1 = P4_6, + SPI2_SS2 = P4_7, + + SPI3_SCK = P5_0, + SPI3_MOSI = P5_1, + SPI3_MISO = P5_2, + SPI3_SS0 = P5_3, + SPI3_SS1 = P5_4, + SPI3_SS2 = P5_5, + + // SWD UART + SWD_TGT_TX = UART1_TX, + SWD_TGT_RX = UART1_RX, + SWD_TGT_CTS = UART1_CTS, + SWD_TGT_RTS = UART1_RTS, + + // Generics + SERIAL_TX = UART0_TX, + SERIAL_RX = UART0_RX, + I2C_SCL = I2C0_SCL, + I2C_SDA = I2C0_SDA, + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_SS0, + PWM_OUT = PWM0, + + // Not connected + NC = NOT_CONNECTED +} PinName; + +typedef enum { + PullUp, + PullDown, + OpenDrain, + PullNone, + PullDefault = PullUp +} PinMode; + +typedef enum { + LED_ON = 0, + LED_OFF = 1 +} LedStates; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PeripheralNames.h b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PeripheralNames.h new file mode 100644 index 0000000000..4686ef9c91 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PeripheralNames.h @@ -0,0 +1,88 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1, + UART_2 = MXC_BASE_UART2, + STDIO_UART = UART_1 +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2CM0, + I2C_1 = MXC_BASE_I2CM1 +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPIM0, + SPI_1 = MXC_BASE_SPIM1, + SPI_2 = MXC_BASE_SPIM2 +} SPIName; + +typedef enum { + PWM_0 = MXC_BASE_PT0, + PWM_1 = MXC_BASE_PT1, + PWM_2 = MXC_BASE_PT2, + PWM_3 = MXC_BASE_PT3, + PWM_4 = MXC_BASE_PT4, + PWM_5 = MXC_BASE_PT5, + PWM_6 = MXC_BASE_PT6, + PWM_7 = MXC_BASE_PT7, + PWM_8 = MXC_BASE_PT8, + PWM_9 = MXC_BASE_PT9, + PWM_10 = MXC_BASE_PT10, + PWM_11 = MXC_BASE_PT11, + PWM_12 = MXC_BASE_PT12, + PWM_13 = MXC_BASE_PT13, + PWM_14 = MXC_BASE_PT14, + PWM_15 = MXC_BASE_PT15 +} PWMName; + +typedef enum { + ADC = MXC_BASE_ADC +} ADCName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PinNames.h new file mode 100644 index 0000000000..8183adb469 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_SDT32625B/PinNames.h @@ -0,0 +1,196 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = 0, /* MXC_V_GPIO_OUT_MODE_HIGH_Z,*/ + PIN_OUTPUT = 1 /* MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE */ +} PinDirection; + +#define PORT_SHIFT 12 +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) + +#define NOT_CONNECTED (int)0xFFFFFFFF + +typedef enum { + P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, + P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, + P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, + P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, + P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, + + // Analog input pins + AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, + + // Analog + A0 = AIN_0, + A1 = AIN_1, + A2 = AIN_2, + A3 = AIN_3, + + // General Pin Input Output (GPIO) + GPIO0 = P1_4, + GPIO1 = P1_5, + GPIO2 = P4_0, + GPIO3 = P4_1, + GPIO4 = P4_2, + GPIO5 = P4_3, + GPIO6 = NOT_CONNECTED, + + //Purse Width Modulation (PWM) + PWM0 = GPIO2, + PWM1 = GPIO3, + PWM2 = GPIO0, + PWM3 = GPIO1, + + // LEDs + LED0 = GPIO0, + LED1 = GPIO1, + LED2 = GPIO2, + LED3 = NOT_CONNECTED, + LED4 = NOT_CONNECTED, + + LED_RED = LED0, + LED_GREEN = LED1, + LED_BLUE = LED2, + + // USB bridge and SWD UART connected UART pins + USBTX = P2_1, + USBRX = P2_0, + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + + // UART pins + UART0_RX = P0_0, + UART0_TX = P0_1, + UART0_CTS = P0_2, + UART0_RTS = P0_3, + + UART1_RX = P2_0, + UART1_TX = P2_1, + UART1_CTS = P2_2, + UART1_RTS = P2_3, + + UART2_RX = P3_0, + UART2_TX = P3_1, + UART2_CTS = P3_2, + UART2_RTS = P3_3, + + // I2C pins + I2C0_SCL = P1_7, + I2C0_SDA = P1_6, + + I2C1_SCL = P3_5, + I2C1_SDA = P3_4, + + I2C2_SCL = NOT_CONNECTED, + I2C2_SDA = NOT_CONNECTED, + + // SPI pins + SPI0_SCK = P0_4, + SPI0_MOSI = P0_5, + SPI0_MISO = P0_6, + SPI0_SS0 = P0_7, + SPI0_SS1 = P4_4, + SPI0_SS2 = P4_5, + + SPI1_SCK = P1_0, + SPI1_MOSI = P1_1, + SPI1_MISO = P1_2, + SPI1_SS0 = P1_3, + SPI1_SS1 = P3_6, + SPI1_SS2 = P3_7, + + SPI2_SCK = P2_4, + SPI2_MOSI = P2_5, + SPI2_MISO = P2_6, + SPI2_SS0 = P2_7, + SPI2_SS1 = P4_6, + SPI2_SS2 = P4_7, + + SPI3_SCK = NOT_CONNECTED, + SPI3_MOSI = NOT_CONNECTED, + SPI3_MISO = NOT_CONNECTED, + SPI3_SS0 = NOT_CONNECTED, + SPI3_SS1 = NOT_CONNECTED, + SPI3_SS2 = NOT_CONNECTED, + + // SWD UART + SWD_TGT_TX = UART1_TX, + SWD_TGT_RX = UART1_RX, + SWD_TGT_CTS = UART1_CTS, + SWD_TGT_RTS = UART1_RTS, + + // Generics + SERIAL_TX = UART0_TX, + SERIAL_RX = UART0_RX, + I2C_SCL = I2C0_SCL, + I2C_SDA = I2C0_SDA, + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_SS0, + PWM_OUT = PWM0, + + // Not connected + NC = NOT_CONNECTED +} PinName; + +typedef enum { + PullUp, + PullDown, + OpenDrain, + PullNone, + PullDefault = PullUp +} PinMode; + +typedef enum { + LED_ON = 0, + LED_OFF = 1 +} LedStates; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/PinNames.h new file mode 100644 index 0000000000..46005eaf52 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/PinNames.h @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2013 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define NOT_CONNECTED (int)0xFFFFFFFF +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + + // Analog + A0 = P0_1, + A1 = P0_2, + A2 = P0_3, + A3 = P0_4, + + // General Pin Input Output (GPIO) + GPIO0 = P0_5, + GPIO1 = P0_7, + GPIO2 = P0_12, + GPIO3 = NOT_CONNECTED, + GPIO4 = NOT_CONNECTED, + GPIO5 = NOT_CONNECTED, + GPIO6 = NOT_CONNECTED, + + //Purse Width Modulation (PWM) + PWM0 = GPIO2, + PWM1 = GPIO3, + PWM2 = GPIO0, + PWM3 = GPIO1, + + // LEDs + LED0 = GPIO0, + LED1 = GPIO1, + LED2 = GPIO2, + + LED_RED = LED0, + LED_GREEN = LED1, + LED_BLUE = LED2, + + // USB bridge and SWD UART connected UART pins + USBTX = P0_9, + USBRX = P0_11, + + // UART pins + UART0_RX = NOT_CONNECTED, + UART0_TX = NOT_CONNECTED, + UART0_CTS = NOT_CONNECTED, + UART0_RTS = NOT_CONNECTED, + + UART1_RX = P0_11, + UART1_TX = P0_9, + UART1_CTS = P0_10, + UART1_RTS = P0_8, + + RX_PIN_NUMBER = p11, + TX_PIN_NUMBER = p9, + CTS_PIN_NUMBER = p10, + RTS_PIN_NUMBER = p8, + + + UART2_RX = NOT_CONNECTED, + UART2_TX = NOT_CONNECTED, + UART2_CTS = NOT_CONNECTED, + UART2_RTS = NOT_CONNECTED, + + // I2C pins + I2C0_SCL = P0_20, + I2C0_SDA = P0_19, + + I2C1_SCL = P0_30, + I2C1_SDA = P0_29, + + I2C2_SCL = NOT_CONNECTED, + I2C2_SDA = NOT_CONNECTED, + + // SPI pins + SPI0_SCK = P0_18, + SPI0_MOSI = P0_15, + SPI0_MISO = P0_16, + SPI0_SS0 = P0_17, + SPI0_SS1 = P0_14, + SPI0_SS2 = P0_13, + + SPI1_SCK = P0_25, + SPI1_MOSI = P0_23, + SPI1_MISO = P0_24, + SPI1_SS0 = P0_22, + SPI1_SS1 = P0_21, + SPI1_SS2 = P0_28, + + SPI2_SCK = NOT_CONNECTED, + SPI2_MOSI = NOT_CONNECTED, + SPI2_MISO = NOT_CONNECTED, + SPI2_SS0 = NOT_CONNECTED, + SPI2_SS1 = NOT_CONNECTED, + SPI2_SS2 = NOT_CONNECTED, + + SPI3_SCK = NOT_CONNECTED, + SPI3_MOSI = NOT_CONNECTED, + SPI3_MISO = NOT_CONNECTED, + SPI3_SS0 = NOT_CONNECTED, + SPI3_SS1 = NOT_CONNECTED, + SPI3_SS2 = NOT_CONNECTED, + + // SWD UART + SWD_TGT_TX = UART1_TX, + SWD_TGT_RX = UART1_RX, + SWD_TGT_CTS = UART1_CTS, + SWD_TGT_RTS = UART1_RTS, + + // Generics + SERIAL_TX = UART1_TX, + SERIAL_RX = UART1_RX, + I2C_SCL = I2C0_SCL, + I2C_SDA = I2C0_SDA, + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_SS0, + PWM_OUT = PWM0, + + // Not connected + NC = NOT_CONNECTED +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/device.h new file mode 100644 index 0000000000..2427e752ea --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_SDT51822B/device.h @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/PinNames.h new file mode 100644 index 0000000000..3d0c4461c9 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/PinNames.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2016 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define NOT_CONNECTED (int)0xFFFFFFFF +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + P0_31 = p31, + + RX_PIN_NUMBER = p8, + TX_PIN_NUMBER = p6, + CTS_PIN_NUMBER = p7, + RTS_PIN_NUMBER = p5, + + // mBed interface Pins + STDIO_UART_TX = TX_PIN_NUMBER, + STDIO_UART_RX = RX_PIN_NUMBER, + STDIO_UART_CTS = CTS_PIN_NUMBER, + STDIO_UART_RTS = RTS_PIN_NUMBER, + + // Analog + A0 = P0_2, + A1 = P0_3, + A2 = P0_4, + A3 = P0_28, + + // General Pin Input Output (GPIO) + GPIO0 = P0_9, + GPIO1 = P0_10, + GPIO2 = P0_17, + GPIO3 = P0_29, + GPIO4 = NOT_CONNECTED, + GPIO5 = NOT_CONNECTED, + GPIO6 = NOT_CONNECTED, + + //Purse Width Modulation (PWM) + PWM0 = GPIO2, + PWM1 = GPIO3, + PWM2 = GPIO0, + PWM3 = GPIO1, + + // LEDs + LED0 = GPIO0, + LED1 = GPIO1, + LED2 = GPIO2, + + LED_RED = LED0, + LED_GREEN = LED1, + LED_BLUE = LED2, + + // USB bridge and SWD UART connected UART pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + // UART pins + UART0_RX = NOT_CONNECTED, + UART0_TX = NOT_CONNECTED, + UART0_CTS = NOT_CONNECTED, + UART0_RTS = NOT_CONNECTED, + + UART1_RX = P0_8, + UART1_TX = P0_6, + UART1_CTS = P0_7, + UART1_RTS = P0_5, + + UART2_RX = NOT_CONNECTED, + UART2_TX = NOT_CONNECTED, + UART2_CTS = NOT_CONNECTED, + UART2_RTS = NOT_CONNECTED, + + // I2C pins + I2C0_SCL = P0_27, + I2C0_SDA = P0_26, + + I2C1_SCL = P0_31, + I2C1_SDA = P0_30, + + I2C2_SCL = NOT_CONNECTED, + I2C2_SDA = NOT_CONNECTED, + + // SPI pins + SPI0_SCK = P0_14, + SPI0_MOSI = P0_12, + SPI0_MISO = P0_13, + SPI0_SS0 = P0_11, + SPI0_SS1 = P0_15, + SPI0_SS2 = P0_16, + + SPI1_SCK = P0_25, + SPI1_MOSI = P0_23, + SPI1_MISO = P0_24, + SPI1_SS0 = P0_22, + SPI1_SS1 = P0_19, + SPI1_SS2 = P0_20, + + SPI2_SCK = NOT_CONNECTED, + SPI2_MOSI = NOT_CONNECTED, + SPI2_MISO = NOT_CONNECTED, + SPI2_SS0 = NOT_CONNECTED, + SPI2_SS1 = NOT_CONNECTED, + SPI2_SS2 = NOT_CONNECTED, + + SPI3_SCK = NOT_CONNECTED, + SPI3_MOSI = NOT_CONNECTED, + SPI3_MISO = NOT_CONNECTED, + SPI3_SS0 = NOT_CONNECTED, + SPI3_SS1 = NOT_CONNECTED, + SPI3_SS2 = NOT_CONNECTED, + + // SWD UART + SWD_TGT_TX = UART1_TX, + SWD_TGT_RX = UART1_RX, + SWD_TGT_CTS = UART1_CTS, + SWD_TGT_RTS = UART1_RTS, + + // Generics + SERIAL_TX = UART1_TX, + SERIAL_RX = UART1_RX, + I2C_SCL = I2C0_SCL, + I2C_SDA = I2C0_SDA, + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_SS0, + PWM_OUT = PWM0, + + // Not connected + NC = NOT_CONNECTED +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/device.h new file mode 100644 index 0000000000..2427e752ea --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_SDT52832B/device.h @@ -0,0 +1,38 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h index 451c125b35..af3f0de8c6 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h @@ -8557,9 +8557,7 @@ // <1=> NRF_CLOCK_LF_SRC_XTAL // <2=> NRF_CLOCK_LF_SRC_SYNTH -#ifndef NRF_SDH_CLOCK_LF_SRC -#define NRF_SDH_CLOCK_LF_SRC 1 -#endif +#include "nrf5x_lf_clk_helper.h" // NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. #ifndef NRF_SDH_CLOCK_LF_RC_CTIV diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h index 201402a18e..c342fae1f0 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h @@ -8556,9 +8556,7 @@ // <1=> NRF_CLOCK_LF_SRC_XTAL // <2=> NRF_CLOCK_LF_SRC_SYNTH -#ifndef NRF_SDH_CLOCK_LF_SRC -#define NRF_SDH_CLOCK_LF_SRC 1 -#endif +#include "nrf5x_lf_clk_helper.h" // NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. #ifndef NRF_SDH_CLOCK_LF_RC_CTIV diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/pwmout_api.c index 57dd7a28af..3db9cf58e0 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/pwmout_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/pwmout_api.c @@ -57,6 +57,9 @@ #define MAX_PWM_PERIOD_MS (MAX_PWM_PERIOD_US / 1000) #define MAX_PWM_PERIOD_S ((float) MAX_PWM_PERIOD_US / 1000000.0f) +/* Sequence bit that denotes the polarity of the pwm waveform. */ +#define SEQ_POLARITY_BIT (0x8000) + /* Allocate PWM instances. */ static nrf_drv_pwm_t nordic_nrf5_pwm_instance[] = { #if PWM0_ENABLED @@ -98,9 +101,6 @@ static void nordic_pwm_init(pwmout_t *obj) .step_mode = NRF_PWM_STEP_AUTO, }; - /* Make sure PWM instance is not running before making changes. */ - nrf_drv_pwm_uninit(&nordic_nrf5_pwm_instance[obj->instance]); - /* Initialize instance with new configuration. */ ret_code_t result = nrf_drv_pwm_init(&nordic_nrf5_pwm_instance[obj->instance], &config, @@ -114,6 +114,9 @@ static void nordic_pwm_restart(pwmout_t *obj) { MBED_ASSERT(obj); + /* Uninitialize PWM instace */ + nrf_drv_pwm_uninit(&nordic_nrf5_pwm_instance[obj->instance]); + /* (Re)initialize PWM instance. */ nordic_pwm_init(obj); @@ -140,7 +143,7 @@ void pwmout_init(pwmout_t *obj, PinName pin) /* Get hardware instance from pinmap. */ int instance = pin_instance_pwm(pin); - MBED_ASSERT(instance < (int)(sizeof(nordic_nrf5_pwm_instance) / sizeof(nrf_drv_pwm_t))); + MBED_ASSERT(instance < (int) (sizeof(nordic_nrf5_pwm_instance) / sizeof(nrf_drv_pwm_t))); /* Populate PWM object with default values. */ obj->instance = instance; @@ -153,6 +156,9 @@ void pwmout_init(pwmout_t *obj, PinName pin) obj->sequence.repeats = 0; obj->sequence.end_delay = 0; + /* Set active low logic. */ + obj->pulse |= SEQ_POLARITY_BIT; + /* Initialize PWM instance. */ nordic_pwm_init(obj); } @@ -184,17 +190,20 @@ void pwmout_write(pwmout_t *obj, float percent) /* Find counts based on period. */ uint16_t pulse = obj->period * percent; + /* Clear sequence, but keep the polarity bit */ + obj->pulse &= SEQ_POLARITY_BIT; + /* Ensure we don't overcount. */ - obj->pulse = (pulse > MAX_PWM_COUNTERTOP) ? MAX_PWM_COUNTERTOP : pulse; + obj->pulse |= (pulse > MAX_PWM_COUNTERTOP) ? MAX_PWM_COUNTERTOP : pulse; /* Store actual percentage passed as parameter to avoid floating point rounding errors. */ obj->percent = percent; /* Set new duty-cycle. */ ret_code_t result = nrf_drv_pwm_simple_playback(&nordic_nrf5_pwm_instance[obj->instance], - &obj->sequence, - 1, - NRF_DRV_PWM_FLAG_LOOP); + &obj->sequence, + 1, + NRF_DRV_PWM_FLAG_LOOP); MBED_ASSERT(result == NRF_SUCCESS); } @@ -266,10 +275,11 @@ void pwmout_period_us(pwmout_t *obj, int period) } /* Scale new count based on stored duty-cycle and new period. */ - uint32_t pulse = (period * obj->pulse) / obj->period; + uint32_t pulse = (period * (obj->pulse & ~SEQ_POLARITY_BIT)) / obj->period; /* Store new values in object. */ - obj->pulse = pulse; + obj->pulse &= SEQ_POLARITY_BIT; + obj->pulse |= pulse; obj->period = period; obj->percent = (float) pulse / (float) period; @@ -287,8 +297,9 @@ void pwmout_pulsewidth(pwmout_t *obj, float pulse) DEBUG_PRINTF("pwmout_pulsewidt: %f\r\n", pulse); /* Cap pulsewidth to period before setting it. */ - if ((pulse * 1000000) > (float) obj->pulse) { - obj->pulse = obj->period; + if ((pulse * 1000000) > (float) (obj->pulse & ~SEQ_POLARITY_BIT)) { + obj->pulse &= SEQ_POLARITY_BIT; + obj->pulse |= obj->period; pwmout_pulsewidth_us(obj, obj->pulse); } else { pwmout_pulsewidth_us(obj, pulse * 1000000); @@ -306,7 +317,8 @@ void pwmout_pulsewidth_ms(pwmout_t *obj, int pulse) /* Cap pulsewidth to period before setting it. */ if ((pulse * 1000) > (int) obj->period) { - obj->pulse = obj->period; + obj->pulse &= SEQ_POLARITY_BIT; + obj->pulse |= obj->period; pwmout_pulsewidth_us(obj, obj->pulse); } else { pwmout_pulsewidth_us(obj, pulse * 1000); @@ -328,7 +340,8 @@ void pwmout_pulsewidth_us(pwmout_t *obj, int pulse) } /* Store new values in object. */ - obj->pulse = pulse; + obj->pulse &= SEQ_POLARITY_BIT; + obj->pulse |= pulse; obj->percent = (float) pulse / (float) obj->period; /* Restart instance with new values. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_FULL/mbed_lib.json b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_FULL/mbed_lib.json index 6fdffbe148..bb625ad33f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_FULL/mbed_lib.json +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_FULL/mbed_lib.json @@ -4,9 +4,6 @@ "SOFTDEVICE_PRESENT=1", "S132", "BLE_STACK_SUPPORT_REQD", - "NRF_SDH_CLOCK_LF_SRC=1", - "NRF_SDH_CLOCK_LF_RC_CTIV=0", - "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0", "NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7", "NRF_SD_BLE_API_VERSION=5", "NRF_SDH_ENABLED=1", diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_OTA/mbed_lib.json b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_OTA/mbed_lib.json index 6fdffbe148..bb625ad33f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_OTA/mbed_lib.json +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132_OTA/mbed_lib.json @@ -4,9 +4,6 @@ "SOFTDEVICE_PRESENT=1", "S132", "BLE_STACK_SUPPORT_REQD", - "NRF_SDH_CLOCK_LF_SRC=1", - "NRF_SDH_CLOCK_LF_RC_CTIV=0", - "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0", "NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7", "NRF_SD_BLE_API_VERSION=5", "NRF_SDH_ENABLED=1", diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_FULL/mbed_lib.json b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_FULL/mbed_lib.json index 0d1c884510..7189ece9f9 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_FULL/mbed_lib.json +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_FULL/mbed_lib.json @@ -4,9 +4,6 @@ "SOFTDEVICE_PRESENT=1", "S140", "BLE_STACK_SUPPORT_REQD", - "NRF_SDH_CLOCK_LF_SRC=1", - "NRF_SDH_CLOCK_LF_RC_CTIV=0", - "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0", "NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7", "NRF_SD_BLE_API_VERSION=5", "NRF_SDH_ENABLED=1", diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_OTA/mbed_lib.json b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_OTA/mbed_lib.json index 0d1c884510..7189ece9f9 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_OTA/mbed_lib.json +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S140_OTA/mbed_lib.json @@ -4,9 +4,6 @@ "SOFTDEVICE_PRESENT=1", "S140", "BLE_STACK_SUPPORT_REQD", - "NRF_SDH_CLOCK_LF_SRC=1", - "NRF_SDH_CLOCK_LF_RC_CTIV=0", - "NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0", "NRF_SDH_CLOCK_LF_XTAL_ACCURACY=7", "NRF_SD_BLE_API_VERSION=5", "NRF_SDH_ENABLED=1", diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/nrf5x_lf_clk_helper.h b/targets/TARGET_NORDIC/TARGET_NRF5x/nrf5x_lf_clk_helper.h index 08744be767..fb0d5cccbb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/nrf5x_lf_clk_helper.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/nrf5x_lf_clk_helper.h @@ -43,6 +43,18 @@ #warning No configuration for LF clock source. Xtal source will be used as a default configuration. #endif +#define DEFAULT_LFCLK_CONF_ACCURACY NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM + +#ifdef NRF52 + #define MAX_LFCLK_CONF_RC_CTIV 32 +#else + #define MAX_LFCLK_CONF_RC_CTIV 64 +#endif + +#define MAX_LFCLK_CONF_RC_TEMP_CTIV 33 + +#define DEFAULT_LFCLK_CONF_RC_CTIV 16 // Check temperature every 16 * 250ms. +#define DEFAULT_LFCLK_CONF_RC_TEMP_CTIV 1 // Only calibrate if temperature has changed. #define NRF_LF_SRC_XTAL 2 @@ -50,10 +62,38 @@ #define NRF_LF_SRC_RC 4 #if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH + #define NRF_SDH_CLOCK_LF_SRC NRF_CLOCK_LF_SRC_SYNTH + #define NRF_SDH_CLOCK_LF_RC_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. + #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Synth) #elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_XTAL + #define NRF_SDH_CLOCK_LF_SRC NRF_CLOCK_LF_SRC_XTAL + #define NRF_SDH_CLOCK_LF_RC_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. + #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Xtal) #elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC + #define NRF_SDH_CLOCK_LF_SRC NRF_CLOCK_LF_SRC_RC + + #ifdef MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL + #define NRF_SDH_CLOCK_LF_RC_CTIV MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL + #else + #define NRF_SDH_CLOCK_LF_RC_CTIV DEFAULT_LFCLK_CONF_RC_CTIV + #endif + + #ifdef MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG + #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG + #else + #define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV DEFAULT_LFCLK_CONF_RC_TEMP_CTIV + #endif + + #if (NRF_SDH_CLOCK_LF_RC_CTIV < 1) || (NRF_SDH_CLOCK_LF_RC_CTIV > MAX_LFCLK_CONF_RC_CTIV) + #error Calibration timer interval out of range! + #endif + + #if (NRF_SDH_CLOCK_LF_RC_TEMP_CTIV < 0 ) || (NRF_SDH_CLOCK_LF_RC_TEMP_CTIV > 33) + #error Number/mode of LF RC calibration intervals out of range! + #endif + #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_RC) #else #error Bad LFCLK configuration. Declare proper source through mbed configuration. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c index 5795639d87..710d813813 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/spi_api.c @@ -107,15 +107,9 @@ static inline int spi_readable(spi_t * obj) int spi_master_write(spi_t *obj, int value) { - lpspi_transfer_t masterXfer; uint32_t rx_data; - masterXfer.txData = (uint8_t *)&value; - masterXfer.rxData = NULL; - masterXfer.dataSize = 1; - masterXfer.configFlags = kLPSPI_MasterPcs0 | kLPSPI_MasterPcsContinuous | kLPSPI_SlaveByteSwap; - - LPSPI_MasterTransferBlocking(spi_address[obj->instance], &masterXfer); + LPSPI_WriteData(spi_address[obj->instance], value); // wait rx buffer full while (!spi_readable(obj)); diff --git a/targets/TARGET_Realtek/mbed_rtx.h b/targets/TARGET_Realtek/mbed_rtx.h index 1da2503cd2..934726af56 100644 --- a/targets/TARGET_Realtek/mbed_rtx.h +++ b/targets/TARGET_Realtek/mbed_rtx.h @@ -1,3 +1,4 @@ + /* mbed Microcontroller Library * Copyright (c) 2013-2016 Realtek Semiconductor Corp. * @@ -40,4 +41,4 @@ #endif #endif -#endif +#endif \ No newline at end of file diff --git a/targets/targets.json b/targets/targets.json index 4c5eb65846..6af8758ddf 100755 --- a/targets/targets.json +++ b/targets/targets.json @@ -639,6 +639,12 @@ "network-default-interface-type": "ETHERNET" } }, + "SDT64B": { + "inherits": ["K64F"], + "extra_labels_add": ["K64F"], + "extra_labels_remove": ["FRDM"], + "detect_code": ["3105"] + }, "EV_COG_AD4050LZ": { "inherits": ["Target"], "core": "Cortex-M4F", @@ -2320,14 +2326,14 @@ }, "MOTE_L152RC": { "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO"], "core": "Cortex-M3", - "default_toolchain": "uARM", + "default_toolchain": "ARM", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "extra_labels_add": ["STM32L1", "STM32L152RC"], - "overrides": {"lse_available": 0}, "detect_code": ["4100"], - "device_has_add": ["ANALOGOUT"], - "default_lib": "small", - "release_versions": ["2"], + "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "FLASH"], + "release_versions": ["2", "5"], "device_name": "STM32L152RC" }, "DISCO_F401VC": { @@ -3048,6 +3054,16 @@ "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"], "release_versions": ["2", "5"] }, + "SDT32620B": { + "inherits": ["Target"], + "core": "Cortex-M4F", + "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32620","TARGET_REV=0x4332","OPEN_DRAIN_LEDS"], + "detect_code": ["3101"], + "extra_labels": ["Maxim", "MAX32620C"], + "supported_toolchains": ["GCC_ARM", "IAR", "ARM"], + "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"], + "release_versions": ["2", "5"] + }, "MAX32625_BASE": { "inherits": ["Target"], "core": "Cortex-M4F", @@ -3071,6 +3087,11 @@ "MAX32625MBED": { "inherits": ["MAX32625_NO_BOOT"] }, + "SDT32625B": { + "inherits": ["MAX32625_BASE"], + "extra_labels_add": ["MAX32625_NO_BOOT"], + "detect_code": ["3102"] + }, "MAX32625PICO": { "inherits": ["MAX32625_BOOT"], "extra_labels_add": ["MAX32625PICO_BASE"] @@ -3835,6 +3856,13 @@ "release_versions": ["2", "5"], "device_name": "nRF51822_xxAA" }, + "SDT51822B": { + "inherits": ["MCU_NRF51_32K_UNIFIED"], + "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "detect_code": ["3103"], + "release_versions": ["2", "5"], + "device_name": "nRF51822_xxAA" + }, "NRF51_DONGLE": { "inherits": ["MCU_NRF51_32K_UNIFIED"], "progen": {"target": "nrf51-dongle"}, @@ -3917,6 +3945,12 @@ "release_versions": ["5"], "device_name": "nRF52832_xxAA" }, + "SDT52832B": { + "inherits": ["MCU_NRF52832"], + "release_versions": ["5"], + "detect_code": ["3104"], + "device_name": "nRF52832_xxAA" + }, "UBLOX_EVA_NINA": { "inherits": ["MCU_NRF52832"], "release_versions": ["5"], diff --git a/tools/export/embitz/__init__.py b/tools/export/embitz/__init__.py index 9cdd1f03a4..067168b2f1 100644 --- a/tools/export/embitz/__init__.py +++ b/tools/export/embitz/__init__.py @@ -64,17 +64,13 @@ class EmBitz(Exporter): l, _ = splitext(basename(lib)) libraries.append(l[3:]) - - if self.resources.linker_script is None: - self.resources.linker_script = '' - ctx = { 'name': self.project_name, 'target': self.target, 'toolchain': self.toolchain.name, 'source_files': source_files, 'include_paths': self.resources.inc_dirs, - 'script_file': self.resources.linker_script, + 'script_file': self.resources.linker_script or '', 'library_paths': self.resources.lib_dirs, 'libraries': libraries, 'symbols': self.toolchain.get_symbols(),